L6280

L6280 THREE CHANNELS MULTIPOWER DRIVER SYSTEM ADVANCE DATA PROGRAMMABLE CONFIGURATION (CHANNELS 1 AND 2) OUTPUT CURRENT UP TO 1A (CHANNELS 1 AND 2) 1 SENSE PER CHANNEL OUTPUT CURRENT CHANNEL 3 UP TO 3A DIRECT INTERFACE TO MICROPROCESSOR C-MOS COMPATIBLE INPUT INTERNAL DC-DC CONVERTER FOR LOGIC SUPPLY (+5V) POWER FAIL WATCHDOG MANAGEMENT THERMAL PROTECTION VERY LOW DISSIPATED POWER (SUITABLE FOR USE IN BATTERY SUPPLIED APPLICATIONS) DESCRIPTION The L6280 is a multipower driver system for motor and solenoid control applicatios that connects directly to a microprocessor bus. Realized in Multipower BCD technology -- which combines isolated DMOS transistors, CMOS & bipolar circuits on the BLOCK DIAGRAM MULTIPOWER BCD TECHNOLOGY PLCC44 ORDERING NUMBER: L6280 same chip -- it integrates two 1A motor drivers (channels 1 & 2) a 3A solenoid driver (channel 3) and a 5V switchmode power supply. All of the drivers in the L6280 are controlled by a microprocessor which loads commands and reads diagnostic information, treating the device as a peripheral. Channels 1 and 2 feature a programmable output DMOS transistor configuration that can be set during the initialization phase. Thanks to very low dissipation of its DMOS power stages the L6280 needs no heatsink and is packaged in a 44-lead PLCC package. January 1992 1/26 This is advanced information on a new product now in development or undergoing evaluation. Details are subject to change without notice. L6280 PIN CONNECTION (top view) ABSOLUTE MAXIMUM RATINGS Symbol VS VSS V13 VDHS VO VOD Vsense VI ILSD Logic Supply Voltage Pin 13 Input Voltage (Note B) High Side Out Transistor Driving Voltage (Note B,C) Output Voltage. CH1; CH2: Unipolar Motor Drive (Note D) CH3 Differential Output Voltage CH1; CH2; Full Bridge Configuration (Note E) Sensing Voltage Logic Input Voltage Low Side Driver Input Current CH1; CH2 DC Operation Peak (Note F) CH3 DC Operation Peak (Note G) High Side Driver Onput Current CH1; CH2 DC Operation Peak (Note F) CH3 DC Operation Peak (Note G) SMPS Output Current (Continuous) (Peak; TON < 5ms) Reset Output Open Drain Input Current Total Power Dissipation atTamb = 70°C (Note H) Storage an Junction Temperature Range Parameter Power Supply Voltage (Note A) Value 35 7 60 18 60 60 60 -1 to 2 -0.3 to VSS +0.3 0.7 2 3 4.4 1 2 3 4.4 1 2 16 1.6 -40 to 150 Unit V V V V V V V V V A A A A A A A A A A mA W °C IHSD ISSOUT IRES Ptot Tstg; Tj Notes: A) D0 = D1 = D2 = D3 =0; B) V13 = VS + VDHS ; C) At 20V > VDHS > 17V the input current at pin 13 must be < 30mA; D) D0 = 1; D1 = D2 = D3 = 0; E) D1 = 1; D0 = X; D2 = D3 = 0; F) The pulse width must be < 5ms and the Duty Cycle must be < 10% G) The pulse width must be VPF -0.3 Min. Typ. Max. 2 48 1.35 -10 VSS 10 0.8 13 7.5 5.25 7.5 800 96 Unit mA V V µA V µA V V mA V mA mA KHz KHz KHz KHz KHz °C ms ms Ω Ω Ω Ω Ω ns V V µs V mA A V V V V V SENSE Vref DAC tC VDHS IDHS ISS (OUT) max VDLS VSSF VFHSD (1;2) VFLSD (1AB;2AB) VFHSD 4/26 L6280 ELECTRICAL CHARACTERISTICS (continued) Symbol VFLSD tCW tWPW tSU tDH tWC Notes: 1) When driving a unipolar stepper motor the Power Supply Voltage must be lower than 24V. 2) A lower Supply Voltage than the Power Fail threshold disables the Step Down Power Supply (see Fig.2) 3) The minimum output current equals the half of the peak-to-peak current ripple 4) tWD ≅ CWD x 1.5 /50 x 10 -6 (sec) 5) tD ≅ CD x 3.5 /50 x 10 -6 (sec) 6) tC≅ COSC x Rint. (sec); Rint. = 600Ω ± 30% Parameter Internal Clamp Diode Forward Volt. CH3 Chip Seletion to End of Write Write Pulse Width Data Set-up Time Data Hold-up Time Write Cycle Time Test Condition @ IDS = 1A (Fig. 5) (Fig. 6) (Fig. 6) (Fig. 6) (Fig. 6) (Fig. 6) Min. Typ. Max. 1.1 Unit V ns ns ns ns ms 700 700 700 0 2.7 Figure 1: Drain Lekage Current Equivalent Test Circuit . The Gate-to-Source Voltage VGS is below the Switch-Off Threshold. Figure 3: Typical Normalized RDS(ON) vs. Junction Temperature 5/26 L6280 Figure 2: Reset Output Behaviour versus Power Supply Voltage VS and/or Logic Supply Voltage VSS. Figure 4a:Sink Output DMOS RON Equivalent Test Circuit Figure 4b:Source Output DMOS RON Equivalent Test Circuit 6/26 L6280 Figure 5: Possible Hardware Configurations of Power Stage (CH1 and CH2) Figure 6: Write Cycle 7/26 L6280 SYSTEM DESCRIPTION (Refer to the Block Diagram) The L6280 is a single chip power microsystem which includes drives for three different loads, the associated control logic and a Switched Mode Power Supply (SMPS) at VSS = 5V ± 5%. The IC can be directly connected to a standard microprocessor because of its common I/O interface architecture. The L6280 can exchange information regarding the load driver and the control method via a 8 bit data bus. The block named microprocessor interface decodes the first four bits (A0....A3), which, depending on the content of the remaining four (D0.......D3) are used to enable the power DMOS, to activate the PWM loop, and finally to set the D/A output value. The power stage can be divided into 3 channels. Channels1 and 2 have 6 DMOS transistors each one (2high side drivers with Rdson =1Ω, 4 low side drivers with Rdson =2Ω). Depending on the application load, these driver transistors can be connected in different ways. The microprocessor, via software, must activate the proper control loop to optimize operation of different loads and output stage configurations. Because of this programmability in the control of the output configurations, a large variety of different loads can be driven by the same integrated circuit (see possible configuration for power stage on Figure 5) giving the greater system flexibility. Current levels up to 1A are possible from CH1 and CH2, limited primarily by the power dissipation of the IC. The third channel has a fixed configuration intended to drive a solenoid. DMOS transistors with 0.5Ω Rdson are used to provide 4A max load capability. All three channels have 3 bit current D/A resolution. Some auxiliary blocks of diagnostic and protection (e.g.: The power Fail/Reset and the watchdog) are provided to protect the system from microprocessor failure or power fail. Figure 7: SMPS Block Diagram Step Down Switchmode Power Supply (See Figure 7). The step down switchmode power supply contains a DMOS power stage with 1Ω Rdson (Q1), control circuitry, diagnostics and protection circuits; a regulated voltage (V SSout) is used to drive some of the internal circuit blocks and the external microprocessor and memories. Thanks to the DMOS output stage this regulator can deliver a continuous output power of 4W (5V; 0.8A) with an efficiency betler than 90% at a typical frequency of 80kHz. The regulation loop uses a classical pulse width modulation circuit that includes a sawtooth generator, an error amplifier, a voltage comparator and a PWM latch. A precision 5V reference is generated and trimmed on chip to guarantee a 5% tolerance. This reference is used as voltage reference for the SMPS and the reference for the DACs. The IC also provides an extra voltage (VS+VDHS) for the correct driving of the high side drivers. These transistors require a gate voltage higher than the supply voltage Vs to obtain the minimum ON resistance. Because of the v ery low current needed to drive DMOS transistors, this auxiliary voltage is easily obtained from a second winding on the inductor of the LC output network (see Application Information). An overcurrent protection circuit is included to turn OFF the power transistor when a current level of 1.2A is exceeded. The SMPS block also includes a voltage sensing circuit to generate a power ON reset signal for the microprocessor. This Power Fail circuit senses the input supply voltage and the output regulated voltage and sets the Reset-out pin to the high voltage only when both the sensed voltages are correct. Finally, the SMPS block is able to deliver fOSC/2 used in the actuation stage for the PWM control of the current (CH1; CH2 and CH3). 8/26 L6280 Pwm Current Control Loop The current control is achieved big a cycle of charge (TON) and discharge (TOFF) of the energy stored in each couple of windings of the driven motor (MA and MB). Fig. 8 shows the windings MA of an unipolar stepper motor during TON. FF1 is setted by the clock pulse and the transistor QA is ON. At the moment Q1is ON the current exponentially increases until RS x IP equals VREF. A reset pulse is produced, QA is switched OFF and Q2 is switched ON (Fig. 9). Since the magnetic flux 0MA = NA IP cannot suddenly change and since the coil tourus number in the discharge loop is doubled, the peak current IP modifies it self into IP/2. The OFF time is characteryzed by a slow recirculation of the current IP/2 that decreases until a new clock pulse sets a new TON configuration. To control the current in two separate windings MA and MB with just one sense resistor RS and one comparator, a special PWM control loop based on a ”time sharing” technique (Patented) is used (Fig. 10). In this configuration the chopping frequency, that defines the TON + TOFF period of each phase, is halved by FF3 that drives ON G1 and G2 alternately. During TOFF of one winding, for instance MA (and QA is OFF), its current does not flow throught the sensing resistor that can be used to monitor the current that flows through the second winding MB, allowed by the ON-status of QB. Fig. 11 shows a simplified timing before and during the phase change from AB to AB (CCW, full Figure 8 - TON Configuration: Motor Windings MA (A; A). step). It can be seen that before the time t1, IA and IB are alternately controlled in a chopping period Tch1 of 4 oscillator periods or two clock periods. The time sharing is 50% - 50% and the chopping frequency is typically of 20KHz (fosc = 80KHz). Afther the time t1, as soon as I A is sensed, a different time sharing is generated. In fact since a Reset pulse is last after one clock pulse, FF2 can drive FF3 to change for IB chopping only at the next clock pulse (Fig 10; Fig 11). This means that the chopping time becomes Tch2 = 6 oscillator pulses, the frequency decreases to 16.6KHz (fosc = 80 KHz) and the time sharing becomes of 67% - 33%. At the end of the phase change period tphc the time sharing comes back to 50% - 50% again. It can be noted that this behaviour allows a faster phase change and then a higher speed of the motor. The cost of that, is the increase of the TOFF of the unchanged phase B and then a small increase of the ripple of the current I B (see ∆IB1