L6374FP013TR

L6374 Industrial quad line driver Features ■ Four independent line drivers with 100 mA up to 35 V outputs ■ Input signals between - 7 V and + 35 V, with pre-setting threshold ■ Push-pull outputs with three state control and true zero current between Vs and ground ■ Current limiting on each output effective in the full "ground to Vs" output voltage range Description ■ Output voltage clamp to Vs and to ground ■ Overtemperature and undervoltage protections The L6374 is especially designed to be used as a line driver in industrial control systems based on the 24 V signal levels (IEC 61131, 24VDC). ■ Diagnostic for overtemperature, undervoltage and overcurrent Table 1. ■ Pre-setting delay for overcurrent diagnostic ■ High speed operation: up to 300 kHz with 35 V swing Figure 1. March 2008 SO-20 Device summary Order codes Package Packaging L6374FP SO-20 Tube L6374FPT SO-20 Tape and reel Block diagram Rev 3 1/19 www.st.com 19 Contents L6374 Contents 1 Maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 2 Pin connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 3 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 4 Thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 4.1 RthJP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 4.2 RthJA1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 4.3 RthJA2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 5 Overtemperature protection (OVT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 6 Undervoltage protection (UV) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 7 Diagnostic logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 8 Programmable delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 9 Analog inputs (I1,I2,I3,I4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 10 State / push-pull input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 11 The switching of the output stage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 12 Application note . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 13 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 14 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 2/19 L6374 1 Maximum ratings Maximum ratings Table 2. Absolute maximum ratings Symbol Pin VS 1 Vilog 12, 13 Value Unit Supply voltage (tW ≤ 10 ms) 50 V Supply voltage (DC) 40 V -0.3 to 7 V ±1 mA ±2 mA - 7 to 35 V ±100 mA ±1 A -0.3 to VS +0.3 V Setting pin forced current ±1 mA Setting pin forced voltage -0.3 to 5 V External voltage -0.3 to 35 V Externally forced current -10 to 10 mA Voltage on the delay capacitor, externally forced -0.3 to 4.5 V Top Ambient temperature, operating range -25 to 85 °C TJ Junction temperature, operating range (see overtemperature protection) -25 to 125 °C Storage temperature -55 to 150 °C Iilog Ii Vi Parameter Logic input voltage (DC) Logic input forced current, per pin 7, 8, Channel input current (forced) 9, 10 Channel input voltage Output current (forced, apart from inductive load) Iout Vout Iset 3, 4, Output current (forced, apart from inductive load) 17, same tW ≤ 10 ms 18 Output Voltage (forced, not resulting from an inductive kick) 11 Vset Vdiag 14 Idiag VC3 Tstg 2 13 Pin connections Figure 2. Pins connection (top view) 3/19 Electrical characteristics L6374 3 Electrical characteristics Table 3. Electrical characteristics Symbol Pin Parameter Test condition Min Typ Max Unit 10.8 35 V 9 10.8 V 450 650 mV 3 5 mA DC operation (VS = 24 V; TJ = -25 to 125 °C; unless otherwise specified) VS Vsh Supply voltage UV upperthreshold 1 Hys1 UV hysteresis Iqsc Quiescent current Outputs open Vref Input comparators reference voltage Reference pin floating 1.05 1.25 1.35 V 11 250 Sink/source current on reference pin Vref = 0 V -30 -20 -10 µA Iref Vref = 5 V 10 20 30 µA Comparator threshold with external bias VS = 9 to 12 V -0.2 2.0 V Vth VS = 12 to 35 V -0.2 5.0 V VREF externally biased -7 VREF -0.2 V Pin VREF floating -7 0.8 V VREF +0.2 35 V 2 35 V -7 35 V 0 < Vi < VS -1 1 µA Vi = -7 V -1 -0.5 -0.1 mA 100 200 350 mV Vil Vih Input low level 7, 8, 9, 10 Vi Input high level VREF externally biased Pin VREF floating Input voltage (operative range) Input bias current Ibias Hys2 Input comparators hysteresis See analog inputs sections Th OVT upper threshold 170 °C HT OVT hysteresis 20 °C Isc Current limit Vi = -7 to VS; Vout = 0 to VS; Internal voltage drop @ rated current Von 3, 4, 17, 18 Output 3-state leakage current Ilkg 200 300 mA Iout = ±100mA; sourced @ high output, sunk @ low output TJ = 125 °C 400 600 mV Same, TJ = 25 °C 250 400 mV -25 25 µA -0.2 0.8 V 2 5.5 V 25 µA 5 µA 500 mV Vout = 0 to VS Push-pull mode request Vin 12 Iin Idlkg Vdiag 4/19 14 3-state mode request Input current Vi = 0 V Diagnostic output leakage Diagnostic OFF; Vdiag = 24 V Diagnostic output voltage drop Idiag = 5 mA 110 10 200 L6374 Table 3. Symbol Electrical characteristics Electrical characteristics (continued) Pin Parameter Test condition Min Typ Max Unit AC operation (VS = 10.8 to 35 V; TJ = -25 to 125 °C; Iout = 100 mA; unless otherwise specified; see switching waveforms diagrams) tdr tdf 7 to 4 8 to 3 Delay time on rising edge 9 to181 0 to Delay time on falling edge 17 tr Rise time 3, 4, 17,18 tf Fall time Rl to ground 1000 1500 ns Rl to VS 500 1000 ns Rl to ground 500 1000 ns Rl to VS 1000 1500 ns Rl to ground 120 250 ns Rl to VS 120 250 ns Rl to ground 150 300 ns Rl to VS 150 300 ns 5/19 Thermal characteristics 4 Thermal characteristics Table 4. Symbol 4.1 L6374 Thermal data Parameter Value Unit RthJP Thermal resistance, junction to pin 17 °C/W RthJA1 Thermal resistance, junction to ambient (see thermal characteristics) 65 °C/W RthJA2 Thermal resistance, junction to ambient (see thermal characteristics) 80 °C/W RthJP The reference point is the knee on the four central pins, where the pins are upwardly bent and the soldering joint with the PCB footprint can be made. 4.2 RthJA1 If a dissipating surface, thick at least 35 µm, and with a surface similar or bigger than the one shown, is created making use of the printed circuit. Such heatsinking surface is considered on the bottom side of an horizontal PCB (worst case). 4.3 RthJA2 If the power dissipating pins (the four central ones), as well as the others, have a minimum thermal connection with the external world (very thin strips only) so that the dissipation takes place through still air and through the PCB itself. It is the same situation of point above, without any heatsinking surface created on purpose on the board. 6/19 L6374 Thermal characteristics Figure 3. Printed heatsink 7/19 Overtemperature protection (OVT) 5 L6374 Overtemperature protection (OVT) If the chip temperature exceeds Th (measured in a central position in the chip) the chip deactivates itself. The following actions are taken: ● all the output stages are forced in the "three state" condition, i.e. are disconnected from the output pins; only the clamping diodes at the outputs remain active; ● the signal Diag is activated (active low). Normal operation is resumed as soon as (typically after some seconds) the chip temperature monitored goes back below Th -HT. The different upper and lower thresholds with hysteretic behavior, assure that no intermittent conditions can be generated. 6 Undervoltage protection (UV) The supply voltage is expected to range from 11 V to 35 V, even if its reference value is considered to be 24 V. In this range the L6374 operates correctly. Below 10.8 V the overall system has to be considered not reliable. Consequently the supply voltage is monitored continuously and a signal, called UV, is internally generated and used. The signal is "on" as long as the supply voltage does not reach the upper internal threshold of the Vs comparator (called Vsh). The UV signal disappears above Vsh. Once the UV signal has been removed, the supply voltage must decrease below the lower threshold (i.e. below Vsh -Hys1) before it is turned on again. The hysteresis Hys1 is provided to prevent intermittent operation of the device at low supply voltages that may have a superimposed ripple around the average value. The UV signal inhibits the outputs, putting them in three-state, but has no effect on the creation of the reference voltages for the internal comparators, nor on the continuous operation of the charge-pump circuits. 8/19 L6374 7 Diagnostic logic Diagnostic logic The situations that are monitored and signalled with the Diag output pin are: 8 ● current limit (OVC) in action; there are 8 individual current limiting circuits, two per each output, i.e. one per every output transistor; they limit the current that can be either sourced or sunk from each output, to a typical value of 150 mA, equal for all of them; ● undervoltage protection (UV); ● overtemperature protection (OVP); The diagnostic signal is transmitted via an open drain output (for ease of wired-or connection of several such signals) and a low level represents the presence of at least one of the monitored conditions, mentioned above. Programmable delay The current limiting circuits can be requested to perform even in absence of a real fault condition, for a short period, if the load is of capacitive nature or if it is a filament lamp (that exhibits a very low resistance during the initial heating phase). To avoid the forwarding of misleading, short diagnostic pulses in coincidence with the intervention of the current limiting circuits when operating on capacitive loads, a delay of about 5 µs is inserted on the signal path, between the "OR" of the current limit signals and its use as external diagnostic. It takes about 1µs to charge (or discharge) by 24 V a capacitor of 5 nF with a current of 120 mA . To implement longer delays (from the intervention of one of the current limiting circuits to the activation of the diagnostic) an external capacitor can be connected between pin C3 and ground (pin C3 is otherwise left open). The delay shall then be determined by the ratio of about 10 pF/µs, using the value of the capacitance connected to the pin. 9 Analog inputs (I1,I2,I3,I4) The input stage of each channel is a high im-pedence comparator with built-in hysteresis (200 mV) for high noise immunity. Each comparator has one input connected to all the others and tied to a common pin Ref (Pin 11). If this pin is left floating an internal precise band gap voltage reference (1.25 V) is applied, otherwise these inputs can be externally programmed by connecting an external voltage source (from 0 to 5 V) and the current on this pin is internally limited to ±20 mA. The other input pin of each comparator can swing from -7 to 35 V. For this reason it has been implemented the structure shown in Figure 4 on page 10 and the device can also be used as line receiver. When the input voltage is negative, the current is internally limited by a 15 kΩ resistor as shown in Figure 4 on page 10. High and low input thresholds can be obtained by adding and subtracting half of the hysteresis to the voltage of pin Ref (see Figure 5 on page 10). 9/19 State / push-pull input 10 L6374 State / push-pull input The input 3st/Pp is instead intended for a digital incoming signal. It has an internal threshold set at 1.26 V; an internal bias circuit (10 mA typical) simulates a high level (three-state) if the pin is disconnected. Figure 4. Equivalent input circuit Figure 5. Input comparator threshold Vout Hys2 Hys2 2 2 Vs Vref 10/19 D94IN073 Vi L6374 11 The switching of the output stage The switching of the output stage The cross conduction of the two transistors of an output stage of the L6374 would be significantly noisy, because the transistors here can carry peak currents in excess of 100 mA, and even more in the few nanoseconds before the current limiting circuits are really effective. Consequently the device has been designed so as to avoid such cross conduction. At every switching transition, first of all the transistor in conduction is turned OFF. Then, after a safe interval of around 200 ns, the other transistor is turned on. When analyzing the switching cycle, and the associated switching times, it is useful to identify some subsequent phases: ● delay from the input pin to the output reaction; ● OFF transition in the output stage; ● dead time ● on transition in the output stage. Figure 6. VS = 35 V, 350 Ω connected to VS/2. Figure 6 helps understand such sequence. In fact, with a purely resistive load connected to Vs/2 no parasitic elements interfere significantly. The waveform can be significantly less easy to in terpret if the load has not the perfect symmetry of that case, as showed below. For instance, it is enough to connect the resistive load to ground, or to Vs – as Figure 7 and Figure 8 – show to hide some of the switching phases described. If the load is connected to ground, the waveform stays stuck to ground as long as the output stage is in high impedance; viceversa when the load is connected to Vs the waveform will linger close to the supply voltage as long as possible. If an output load made of an inductor and a resistor in series is used, the inductive kick at the beginning of every output transition generates the equivalent effect of an "anticipated" 11/19 The switching of the output stage L6374 switching when the inductor can discharge; while the switching looks "delayed" if the output transition tends to initiate a charging phase (see Figure 9). With a load almost free from parasitic elements, the waveforms resemble the ones of the purely resistive cases. With a real, more composite load, the effect of the inductive kick in comparison to the resistive load, would be more apparent. With a capacitor and a resistor in parallel as a load, another type of waveform can be seen (reported in Figure 10). As long as the output stage stays in the transient high impedance state, the output voltage will follow the classic exponential law of an RC relaxation. As soon as the other transistor is switched on and takes charge, the waveform is quickly forcibly brought to its steady state value. From the above it is possible to see how the switching times, inherently very fast, of the output stages, may be difficult to identify in a waveform if the output load is not accurately taken into consideration. Figure 11 show typical switching waveform for inputs and outputs. Figure 7. 12/19 VS = 35 V, 350 Ω connected to ground L6374 The switching of the output stage Figure 8. VS = 35 V, 350 Ω connected to VS Figure 9. VS = 35 V, 350 Ω and 1 mH connected to ground. 13/19 The switching of the output stage L6374 Figure 10. VS = 35 V, 350 Ω || 1 nF connected to ground. Figure 11. Switching waveforms. In 50% 50% tdr t tdf Out 90% 90% 10% 10% tr 14/19 tf D94IN074 t L6374 12 Application note Application note It is recommended not to leave the Ref pin (pin 11) floating: if not used with an external voltage reference, it is better to connect an external capacitor (of at least 10 nF) between this pin and ground. This capacitor filters the voltage reference against voltage spikes that can be generated by the commutation of the output stages. This is very common using capacitive loads: in fact, the initial transient of such loads behaves like a short circuit, so the current flowing through the outputs presents very high spikes. Moreover, if the device is used as a line receiver. (i.e. the input signals can go below ground) it is required not to leave the Ref pin (pin 11) floating: in this case, the pin can be connected to ground or to a fixed external voltage reference. 15/19 Package mechanical data 13 L6374 Package mechanical data In order to meet environmental requirements, ST offers these devices in ECOPACK® packages. These packages have a lead-free second level interconnect . The category of second level interconnect is marked on the package and on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. ECOPACK is an ST trademark. ECOPACK specifications are available at: www.st.com 16/19 L6374 Package mechanical data Table 5. SO-20 mechanical data mm inch Dim. Min Typ Max Min Typ Max A 2.35 2.65 0.093 0.104 A1 0.1 0.3 0.004 0.012 B 0.33 0.51 0.013 0.020 C 0.23 0.32 0.009 0.013 D 12.6 13 0.496 0.512 E 7.4 7.6 0.291 0.299 e 1.27 0.050 H 10 10.65 0.394 0.419 h 0.25 0.75 0.010 0.030 L 0.4 1.27 0.016 0.050 K 0° (min.)8° (max.) Figure 12. Package dimensions 17/19 Revision history 14 L6374 Revision history Table 6. 18/19 Document revision history Date Revision Changes August 2003 1 First Issue June 2004 2 Technical migration from ST-PRESS to EDOCS. 03-Mar-2008 3 Modified: Removed obsolete package DIP-20 L6374 Please Read Carefully: Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any time, without notice. All ST products are sold pursuant to ST’s terms and conditions of sale. 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