L6382D5

L6382D5 Power management unit for microcontrolled ballast Features ■ Integrated high-voltage start-up ■ 4 drivers for PFC, half-bridge & pre-heating MOSFETs ■ Fully integrated power management for all operating modes ■ 5V microcontroller compatible ■ Internal two point VCC regulator ■ Over-current protection with digital output signal ■ Cross-conduction protection (interlocking) ■ Under voltage lock-out ■ Integrated bootstrap diode Applications ■ Dimmable / non-dimmable ballast Figure 1. March 2007 SO-20 Description The L6382D5 is suitable for microcontrolled electronic ballasts embedding a PFC stage and a half-bridge stage. The L6382D5 includes 4 MOSFET driving stages (for the PFC, for the half bridge, for the preheating MOSFET) plus a power management unit (PMU) featuring also a reference able to supply the microcontroller in any condition. Besides increasing the application efficiency, the L6382D5 reduces the bill of materials because different tasks (regarding drivers and power management) are performed by a single IC, which improves the application reliability. Block diagram Rev 3 1/21 www.st.com 21 Contents L6382D5 Contents 1 Device description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 2 Pin settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 3 2.1 Pin connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 2.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 3.1 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 3.2 Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 4 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 5 Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 6 5.1 Power management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 5.2 START-UP mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 5.2.1 SAVE Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 5.2.2 OPERATING Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 5.2.3 Shut Down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Block description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 6.1 Supply section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 6.2 5V reference voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 6.3 Drivers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 6.4 Internal logic, over current protection (OCP) and interlocking function . . 16 7 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 8 Order codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 9 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 2/21 L6382D5 1 Device description Device description Designed in High-voltage BCD Off-line technology, the L6382D5 is provided with 4 inputs pin and a high voltage start-up generator conceived for applications managed by a microcontroller. It allows the designer to use the same ballast circuit for different lamp wattage/type by simply changing the µC software. The digital input pins - able to receive signals up to 400KHz - are connected to level shifters that provide the control signals to their relevant drivers; in particular the L6382D5 embeds one driver for the PFC pre-regulator stage, two drivers for the ballast half-bridge stage (High Voltage, including also the bootstrap function) and the last one to provide supplementary features like preheating of filaments supplied through isolated filaments in dimmable applications. A precise reference voltage (+5V ±2%) able to provide up to 30mA is available to supply the µC in operating mode. Instead, during start-up and save mode the current available at VREF is up to 10mA and it is provided by the internal high voltage start-up generator. The chip has been conceived with advanced power management logic to minimize power losses and increase the application reliability. In the half-bridge section, a patented integrated bootstrap section replaces the external bootstrap diode. The L6382D5 integrates also a function that regulates the IC supply voltage (without the need of any external charge pump) and optimizes the current consumption. Figure 2. Typical system block diagram 3/21 Pin settings L6382D5 2 Pin settings 2.1 Pin connection Figure 3. Pin connection (top view) PFI LSI HSI HEI PFG N.C. TPR GND LSG VCC 2.2 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 VREF CSI CSO HEG N.C. HVSU N.C. OUT HSG BOOT Pin description Table 1. Pin description Name Pin N° Description 1 PFI Digital input signal to control the PFC gate driver. This pin has to be connected to a 5V CMOS compatible signal. 2 LSI Digital input signal to control the half-bridge low side driver. This pin has to be connected to a 5V CMOS compatible signal. 3 HSI Digital input signal to control the half-bridge high side driver. This pin has to be connected to a 5V CMOS compatible signal. 4 HEI Digital input signal to control the HEG output. This pin has to be connected to a 5V CMOS compatible signal. 5 PFG PFC Driver Output. This pin must be connected to the PFC power MOSFET gate. A resistor connected between this pin and the power MOS gate can be used to reduce the peak current. An internal 10KΩ resistor toward ground avoids spurious and undesired MOSFET turn-on The totem pole output stage is able to drive the power MOS with a peak current of 120mA source and 250mA sink. 6 N.C. Not connected 7 TPR Input for two point regulator; by coupling the pin with a capacitor to a switching circuit, it is possible to implement a charge circuit for the Vcc. GND Chip ground. Current return for both the low-side gate-drive currents and the bias current of the IC. All of the ground connections of the bias components should be tied to a track going to this pin and kept separate from any pulsed current return. 8 4/21 L6382D5 Pin settings Table 1. Pin description (continued) Name Pin N° Description 9 LSG Low Side Driver Output. This pin must be connected to the gate of the halfbridge low side power MOSFET. A resistor connected between this pin and the power MOS gate can be used to reduce the peak current. An internal 20KΩ resistor toward ground avoids spurious and undesired MOSFET turn-on. The totem pole output stage is able to drive power with a peak current of 120mA source and 120mA sink. 10 Vcc Supply Voltage for the signal part of the IC and for the drivers. BOOT High-side gate-drive floating supply Voltage. The bootstrap capacitor connected between this pin and pin 13 (OUT) is fed by an internal synchronous bootstrap diode driven in phase with the low-side gate-drive. This patented structure normally replaces the external diode. 12 HSG High Side Driver Output. This pin must be connected to the gate of the half bridge high side power MOSFET . A resistor connected between this pin and the power MOS gate can be used to reduce the peak current. An internal 20KΩ resistor toward OUT pin avoids spurious and undesired MOSFET turn-on The totem pole output stage is able to drive the power MOS with a peak current of 120mA source and 120mA sink. 13 OUT High-side gate-drive floating ground. Current return for the high-side gate-drive current. Layout carefully the connection of this pin to avoid too large spikes below ground. 14 N.C. Not connected 11 High-voltage start-up. The current flowing into this pin charges the capacitor connected between pin Vcc and GND to start up the IC. Whilst the chip is in save mode, the generator is cycled on-off between turn-on and save mode voltages. When the chip works in operating mode the generator is shut down and it is re-enabled when the Vcc voltage falls below the UVLO threshold. According to the required VREF pin current, this pin can be connected to the rectified mains voltage either directly or through a resistor. 15 HVSU 16 N.C. High-voltage spacer. The pin is not connected internally to isolate the highvoltage pin and comply with safety regulations (creepage distance) on the PCB. 17 HEG Output for the HEI block; this driver can be used to drive the MOS employed in isolated filaments preheating. An internal 20KΩ resistor toward ground avoids spurious and undesired MOSFET turn-on. 18 CSO Output of current sense comparator, compatible with 5V CMOS logic; during operating mode, the pin is forced low whereas whenever the OC comparator is triggered (CSI> 0.55 typ.) the pin latches high. CSI Input of current sense comparator, it is enabled only during operating mode; when the pin voltage exceeds the internal threshold, the CSO pin is forced high and the half bridge drivers are disabled. It exits from this condition by either cycling the Vcc below the UVLO or with LGI=HGI=low simultaneously. VREF Voltage reference. During operating mode an internal generator provides an accurate voltage reference that can be used to supply up to 30mA to an external circuit. A small film capacitor (0.22µF min.), connected between this pin and GND is recommended to ensure the stability of the generator and to prevent noise from affecting the reference. 19 20 5/21 Maximum ratings L6382D5 3 Maximum ratings 3.1 Absolute maximum ratings Table 2. Absolute maximum ratings Symbol Pin VCC 10 IC supply voltage (ICC = 20mA) Self-limited VHVSU 15 High voltage start-up generator voltage range -0.3 to 600 V VBOOT 11 Floating supply voltage -1 to VHVSU+VCC V VOUT 13 Floating ground voltage -1 to 600 V ITPR(RMS) 7 Maximum TPR RMS current ±200 mA ITPR(PK) 7 Maximum TPR peak current ±600 mA VTPR 7 Maximum TPR voltage(1) 14 V 19 CSI input voltage -0.3 to 7 V Logic input voltage -0.3 to 7 V 15 to 400 KHz Operating frequency 15 to 600 KHz Storage Temperature -40 to +150 °C Ambient Temperature operating range -40 to +125 °C 1, 2, 3, 4 Parameter 9, 12, Operating frequency 17 5 Tstg Tj Value Unit 1. Excluding operating mode 3.2 Thermal data Table 3. Thermal data Symbol RthJA 6/21 Parameter Maximum thermal resistance junction-ambient Value Unit 120 °C/W L6382D5 4 Electrical characteristics Electrical characteristics Table 4. Electrical characteristcs (TJ = 25°C, VCC = 13V, CDRIVER = 1nF unless otherwise specified) Symbol Pin Parameter Test condition Min Typ Max Unit Supply voltage VccON 10 Turn-on voltage 13 14 15 V VccOFF 10 Turn-off voltage 8.5 9 9.5 V VccSM 10 Save mode voltage 12.75 13.8 14.85 V VSMhys 10 Save mode hysteresys 0.12 0.16 0.2 V VREF(OFF) 10 Reference turn-off 6 6.4 6.8 V IvccON 10 Start-up current 160 µA µA 10 Save Mode current consumption (1) 220 IvccSM 250 µA 2.1 mA 18 V Ivcc 10 Quiescent current in operating mode Vz 10 Internal Zener 190 VCC=13V; LGI = HGI = high; no load on VREF. 16.5 17 High voltage start-up VHVSU > 50V IMSS 15 Maximum current ILSS 15 Leakage current off VHVSU = 600V state 20 mA 40 µA Two point regulator (TPR) protection TPRst 10 Vcc Protection level Operating mode 14.0 14.5 15.0 V TPR(ON) 10 Vcc Turn-on level Operating mode; after the first falling edge on LSG 12.5 13 13.5 V TPR(OFF) 10 Vcc Turn-off level Operating mode; after the first falling edge on LSG 12.45 12.95 13.48 V 7 Output voltage on state ITPR = 200mA 2 V 7 Forward voltage drop Diode @ 600mA forward current. 2.3 V 7 Leakage current off VTPR = 13V state 5 µA 7/21 Electrical characteristics L6382D5 Table 4. Electrical characteristcs (TJ = 25°C, VCC = 13V, CDRIVER = 1nF unless otherwise specified) (continued) Symbol Pin Parameter Test condition Min Typ Max Unit LSG, HEG & PFG drivers VOH(LS) VOL(LS) 5, 9 17 5, 9 17 HIGH Output Voltage LOW Output Voltage Source Current Capability Sink Current Capability ILSG = IPFG = 10mA TFALL 9 V 0.5 V ILSG = IPFG = 10mA IHEG = 2.5mA LSG and PFG 120 mA HEG 50 mA LSG 120 mA HEG 70 PFG 250 5 TRISE 12.5 IHEG = 2.5mA 80 Rise time Cload = 1nF 300 17 60 5, 60 9 Fall time Cload = 1nF 110 17 RB ns 40 Propagation delay (input to output) TDELAY ns Pull down Resistor LSG; high to low and low to high 300 ns HEG; high to low and low to high 200 ns PFG; high to low 250 ns PFG; low to high 200 ns LSG 20 KΩ HEG 50 KΩ PFG 10 KΩ HSG driver (voltages referred to OUT) VOH(HS) 12 HIGH Output Voltage IHSG = 10 mA 12.5 V VOL(HS) 12 LOW Output Voltage IHSG = 10 mA 0.5 V 12 Sink Current Capability 120 mA 12 Source Current Capability 120 mA 12 Rise time TRISE 8/21 Cload = 1nF 115 ns L6382D5 Electrical characteristics Table 4. Electrical characteristcs (TJ = 25°C, VCC = 13V, CDRIVER = 1nF unless otherwise specified) (continued) Symbol Pin Parameter Test condition TFALL 12 Fall time Cload = 1nF TDELAY 12 Propagation delay (LGI to LSG) high to low and low to high RB 12 Pull down Resistor to OUT Min Typ Max 75 Unit ns 300 ns KΩ 20 High-side floating gate-driver supply ILKBOOT 11 VBOOT pin leakage current VBOOT = 580V 5 µA ILKOUT 13 OUT pin leakage current VOUT = 562V 5 µA Synchronous bootstrap diode onresistance VLVG = HIGH 150 Ω Forward Voltage Drop at 10 mA forward current 2.4 V Forward Current at 5V forward voltage drop 20 20 Reference voltage 15mA load. 4.9 20 Load regulation IRef = -3 to +30 mA -20 20 Voltage change 15mA load; Vcc = 9V to 15V 20 VREF latched protection RDS(on) mA VREF VREF IREF 20 VREF Clamp @3mA 20 Current Drive Capability 5.1 V 2 mV 15 mV 3.2 V 1.8 V -3 +30 mA -3 +10 mA 0.56 V 500 nA 200 ns VCC from 0 to VCCON during start-up; Vcc from VREF(OFF) to 0 during shut-down; VREF < 2V Save mode 5 1.2 Overcurrent buffer stage VCSI 19 Comparator Level ICSI 19 Input Bias Current Propagation delay 0.52 CSO turn off to LSG low 0.54 9/21 Electrical characteristics L6382D5 Table 4. Electrical characteristcs (TJ = 25°C, VCC = 13V, CDRIVER = 1nF unless otherwise specified) (continued) Symbol Pin Parameter Test condition 18 High output voltage I CSO = 200µA 18 Low output voltage I CSO = -150µA Min Typ Max Unit 0.5 V 135 µs VREF0.5V DIM Normal Mode Time Out TED 65 100 Vref enabling drivers 4.6 V Time enabling drivers 10 µs Logic input 1 to 4 Low Level Logic Input Voltage 1 to 4 High Level Logic Input Voltage LGI Pull down resistor 1.3 3.7 V V 100 KΩ 1. Specification over the -40°C to +125°C junction temperature range are ensured by design, characterization and statistical correlation. 10/21 L6382D5 Application information 5 Application information 5.1 Power management The L6382D5 has two stable states (save mode and operating mode) and two additional states that manage the Start-up and fault conditions: the Over Current Protection is a parallel asynchronous process enabled when in operating mode Figure 4. Following paragraphs will describe each mode and the condition necessary to shift between them. Figure 4. State diagram START-UP VCC>VCC(ON) VCC4.6V & TDE>10µs VCC