L6382D_07

L6382D Power management unit for microcontrolled ballast Features ■ ■ ■ ■ ■ ■ ■ ■ ■ Integrated high-voltage start-up 4 drivers for PFC, half-bridge & pre-heating MOSFETs 3.3V microcontroller compatible Fully integrate power management for all operating modes Internal two point VCC regulator Over-current protection with digital output signal Cross-conduction protection (interlocking) Under voltage lock-out Integrated bootstrap diode SO-20 Description The L6382D is suitable for microcontrolled electronic ballasts embedding a PFC stage and a half-bridge stage. The L6382D includes 4 MOSFET driving stages (for the PFC, for the half bridge, for the preheating MOSFET) plus a power management unit (PMU) featuring also a reference able to supply the microcontroller in any condition. Besides increasing the application efficiency, the L6382D reduces the bill of materials because different tasks (regarding drivers and power management) are performed by a single IC, which improves the application reliability. Applications ■ Dimmable / non-dimmable ballast Figure 1. Block diagram µ March 2007 Rev 6 1/22 www.st.com 22 Contents L6382D Contents 1 2 Device description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Pin settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 2.1 2.2 Pin connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 3 Maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 3.1 3.2 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 4 5 6 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Typical electrical performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 6.1 Power management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 6.1.1 6.1.2 6.1.3 6.1.4 START-UP mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 SAVE Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 OPERATING Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Shut down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 7 Block description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 7.1 7.2 7.3 7.4 Supply section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 3.3V reference voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Drivers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Internal logic, over current protection (OCP) and interlocking function . . 17 8 9 10 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Order codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 2/22 L6382D Device description 1 Device description Designed in High-voltage BCD Off-line technology, the L6382D is a PFC and ballast controller provided with 4 inputs pin and a high voltage start-up generator conceived for applications managed by a microcontroller providing the maximum flexibility. It allows the designer to use the same ballast circuit for different lamp wattage/type by simply changing the µC software. The digital input pins - able to receive signals up to 400KHz - are connected to level shifters that provide the control signals to their relevant drivers; in particular the L6382D embeds one driver for the PFC pre-regulator stage, two drivers for the ballast half-bridge stage (High Voltage, including also the bootstrap function) and the last one to provide supplementary features like preheating of filaments supplied through isolated windings in dimmable applications. A precise reference voltage (+3.3V ±1%) able to provide up to 30mA is available to supply the µC: this current is obtained thanks to the on-chip high voltage start-up generator that, moreover, keeps the consumption before start-up below 150µA. The chip has been designed with advanced power management logic to minimize power losses and increase the application reliability. In the half-bridge section, a patented integrated bootstrap section replaces the external bootstrap diode. The L6382D integrates also a function that regulates the IC supply voltage (without the need of any external charge pump) and optimizes the current consumption. Figure 2. Typical system block diagram 3/22 Pin settings L6382D 2 2.1 Pin settings Pin connection Figure 3. Pin connection (top view) PFI LSI HSI HEI PFG N.C. TPR GND LSG VCC 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 VREF CSI CSO HEG N.C. HVSU N.C. OUT HSG BOOT 2.2 Pin description Table 1. Pin description Name 1 2 3 4 Pin N° PFI LSI HSI HEI Description Digital input signal to control the PFC gate driver. This pin has to be connected to a TTL compatible signal. Digital input signal to control the half-bridge low side driver. This pin has to be connected to a TTL compatible signal. Digital input signal to control the half-bridge high side driver. This pin has to be connected to a TTL compatible signal. Digital input signal to control the HEG output. This pin has to be connected to a TTL compatible signal. PFC Driver Output. This pin is intended to be connected to the PFC power MOSFET gate. A resistor connected between this pin and the power MOS gate can be used to reduce the peak current. An internal 10KΩ resistor toward ground avoids spurious and undesired MOSFET turn-on. The totem pole output stage is able to drive the power MOS with a peak current of 120mA source and 250mA sink. Not connected Input for two point regulator; by coupling the pin with a capacitor to a switching circuit, it is possible to implement a charge circuit for the Vcc. Chip ground. Current return for both the low-side gate-drive currents and the bias current of the IC. All of the ground connections of the bias components should be tied to a trace going to this pin and kept separate from any pulsed current return. 5 PFG 6 7 N.C. TPR 8 GND 4/22 L6382D Table 1. Pin description Name Pin N° Description Pin settings 9 LSG Low Side Driver Output. This pin must be connected to the gate of the halfbridge low side power MOSFET. A resistor connected between this pin and the power MOS gate can be used to reduce the peak current. An internal 20KΩ resistor toward ground avoids spurious and undesired MOSFET turn-on. The totem pole output stage is able to drive power with a peak current of 120mA source and 120mA sink. Supply Voltage for the signal part of the IC and for the drivers. High-side gate-drive floating supply Voltage. The bootstrap capacitor connected between this pin and pin 13 (OUT) is fed by an internal synchronous bootstrap diode driven in phase with the low-side gate-drive. This patented structure normally replaces the external diode. High Side Driver Output. This pin must be connected to the gate of the half bridge high side power MOSFET . A resistor connected between this pin and the power MOS gate can be used to reduce the peak current. An internal 20KΩ resistor toward OUT pin avoids spurious and undesired MOSFET turn-on The totem pole output stage is able to drive the power MOS with a peak current of 120mA source and 120mA sink. High-side gate-drive floating ground. Current return for the high-side gate-drive current. Layout carefully the connection of this pin to avoid too large spikes below ground. Not connected High-voltage start-up. The current flowing into this pin charges the capacitor connected between pin Vcc and GND to start up the IC. Whilst the chip is in save mode, the generator is cycled on-off between turn-on and save mode voltages. When the chip works in operating mode the generator is shut down and it is re-enabled when the Vcc voltage falls below the UVLO threshold. According to the required VREF pin current, this pin can be connected to the rectified mains voltage either directly or through a resistor. High-voltage spacer. The pin is not connected internally to isolate the highvoltage pin and comply with safety regulations (creepage distance) on the PCB. Output for the HEI block; this driver can be used to drive the MOS employed in isolated filaments preheating. An internal 20KΩ resistor toward ground avoids spurious and undesired MOSFET turn-on. Output of current sense comparator, compatible with TTL logic signal; during operating mode, the pin is forced low whereas whenever the OC comparator is triggered (CSI> 0.5V typ.) the pin latches high. Input of current sense comparator, it is enabled only during operating mode; when the pin voltage exceeds the internal threshold, the CSO pin is forced high and the half bridge drivers are disabled. It exits from this condition by either cycling the Vcc below the UVLO or with LGI=HGI=low simultaneously. Voltage reference. During normal mode an internal generator provides an accurate voltage reference that can be used to supply up to 30mA (during operating mode) to an external circuit. A small film capacitor (0.22µF min.), connected between this pin and GND is recommended to ensure the stability of the generator and to prevent noise from affecting the reference. 10 Vcc 11 BOOT 12 HSG 13 14 OUT N.C. 15 HVSU 16 N.C. 17 HEG 18 CSO 19 CSI 20 VREF 5/22 Maximum ratings L6382D 3 3.1 Maximum ratings Absolute maximum ratings Table 2. Absolute maximum ratings Symbol VCC VHVSU VBOOT VOUT ITPR(RMS) ITPR(PK) VTPR Pin 10 15 11 13 7 7 7 19 1, 2, 3, 4 Parameter IC supply voltage (ICC = 20mA) High voltage start-up generator voltage range Floating supply voltage Floating ground voltage Maximum TPR RMS current Maximum TPR peak current Maximum TPR voltage(1) CSI input voltage Logic input voltage Value Self-limited -0.3 to 600 -1 to VHVSU+VCC -1 to 600 ±200 ±600 14 -0.3 to 7 -0.3 to 7 15 to 400 15 to 600 -40 to +150 -40 to +125 V V V mA mA V V V KHz KHz °C °C Unit 9, 12, Operating frequency 17 5 Tstg TJ Operating frequency Storage temperature Ambient temperature operating range 1. Excluding operating mode 3.2 Thermal data Table 3. Thermal data Symbol RthJA Parameter Maximum thermal resistance junction-ambient Value 120 Unit °C/W 6/22 L6382D Electrical characteristics 4 Electrical characteristics Table 4. Electrical characteristcs (TJ = 25°C, VCC = 13V, CDRIVER = 1nF unless otherwise specified) Symbol Pin Parameter Test condition Min Typ Max Unit Supply voltage VCCON VCCOFF VCCSM VSMhys VREF(OFF) IvccON IvccSM 10 10 10 10 10 10 10 Turn-on voltage Turn-off voltage Save mode voltage Save mode hysteresys Reference turn-off Start-up current Save Mode current consumption (1) Quiescent current in operating mode Internal Zener LGI = HGI = high; no load on VREF. 16.5 17 13 7.5 12.75 0.12 5.7 14 8.25 13.8 0.16 6 15 9.2 14.85 0.2 6.4 150 190 150 230 2 18 V V V V V µA µA µA mA V Ivcc Vz 10 10 High voltage start-up IMSS ILSS 15 15 Maximum current VHVSU > 50V 20 40 mA µA Leakage current off VHVSU = 600V state Two point regulator (TPR) protection TPRst 10 Vcc Protection level Vcc Turn-on level Operating mode Operating mode; after the first falling edge on LSG Operating mode; after the first falling edge on LSG ITPR = 200mA @ 600mA forward current. 14.0 14.5 15.0 V TPR(ON) 10 12.5 13 13.5 V TPR(OFF) 10 Vcc Turn-off level Output voltage on state Forward voltage drop Diode 12.45 12.95 13.48 V 7 7 7 2 2.3 5 V V µA Leakage current off VTPR = 13V state 7/22 Electrical characteristics Table 4. Electrical characteristcs (TJ = 25°C, VCC = 13V, CDRIVER = 1nF unless otherwise specified) (continued) Symbol Pin Parameter Test condition Min Typ L6382D Max Unit LSG, HEG & PFG drivers VOH(LS) 5, 9 17 5, 9 17 HIGH Output Voltage LOW Output Voltage Source Current Capability ILSG = IPFG = 10mA 12.5 IHEG = 2.5mA ILSG=IPFG=10mA 0.5 IHEG = 2.5mA LSG and PFG HEG LSG Sink Current Capability HEG PFG LSG TRISE Rise time HEG PFG LSG TFALL Fall time HEG PFG LSG; high to low and low to high TDELAY Propagation delay (input to output) HEG; high to low and low to high PFG; high to low PFG; low to high LSG RB Pull down Resistor HEG PFG HSG driver (voltages referred to OUT) VOH(HS) VOL(HS) 12 12 12 12 TRISE TFALL 12 12 HIGH Output Voltage LOW Output Voltage Sink Current Capability Source Current Capability Rise time Fall time Cload = 1nF Cload = 1nF IHSG = 10 mA IHSG = 10 mA 120 120 115 75 12.5 0.5 V V mA mA ns ns 20 50 10 120 50 120 70 250 115 300 60 75 110 40 300 200 250 200 ns ns ns ns ns ns ns ns ns ns KΩ KΩ KΩ mA mA mA V V VOL(LS) 8/22 L6382D Electrical characteristics Table 4. Electrical characteristcs (TJ = 25°C, VCC = 13V, CDRIVER = 1nF unless otherwise specified) (continued) Symbol TDELAY RB Pin 12 12 Parameter Propagation delay (LGI to LSG) Pull down Resistor Test condition high to low and low to high to OUT 20 Min Typ Max 300 Unit ns KΩ High-side floating gate-driver supply ILKBOOT ILKOUT 11 13 VBOOT pin leakage current OUT pin leakage current Synchronous bootstrap diode onresistance Forward Voltage Drop Forward Current VREF VREF 20 20 20 20 Reference voltage Load regulation Voltage change VREF latched protection VREF Clamp @3mA VCC from 0 to VCCON during start-up;Vcc from VREF(OFF) to 0 during shut-down; Vref