L6386ED013TR

L6386E High-voltage high and low side driver Features ■ ■ ■ High voltage rail up to 600V dV/dt immunity ±50V/nsec in full temperature range Driver current capability: – 400mA source, – 650mA sink Switching times 50/30 nsec rise/fall with 1nF load CMOS/TTL Schmitt trigger inputs with hysteresis and pull down Under voltage lock out on lower and upper driving section Integrated bootstrap diode Outputs in phase with inputs DIP-14 SO-14 Description The L6386E is an high-voltage device, manufactured with the BCD "OFF-LINE" technology. It has a Driver structure that enables to drive independent referenced Channel Power MOS or IGBT. The High Side (Floating) Section is enabled to work with voltage Rail up to 600V. The Logic Inputs are CMOS/TTL compatible for ease of interfacing with controlling devices. ■ ■ ■ ■ ■ Figure 1. Block diagram BOOTSTRAP DRIVER 14 VCC 4 UV DETECTION UV DETECTION H.V. R R HIN 3 LEVEL SHIFTER LOGIC S VCC HVG DRIVER 13 OUT 12 LVG LVG DRIVER LIN 1 VREF 9 PGND 8 5 DIAG TO LOAD HVG Vboot CBOOT SD 2 SGND 7 October 2007 Rev 1 + 6 CIN D97IN520D 1/18 www.st.com 18 Contents L6386E Contents 1 Electrical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 1.1 1.2 1.3 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Recommended operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 2 3 Pin connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 3.1 3.2 3.3 AC operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 DC operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 4 Bootstrap driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 4.1 CBOOT selection and charging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 5 6 7 8 Typical characteristic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Order codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 2/18 L6386E Electrical data 1 1.1 Electrical data Absolute maximum ratings Table 1. Symbol Vout Vcc Vboot Vhvg Vlvg Vi Vdiag Vcin dVout/dt Ptot Tj Tstg Output voltage Supply voltage Floating supply voltage High side gate output voltage Low side gate output voltage Logic input voltage Open drain forced voltage Comparator input voltage Allowed output slew rate Total power dissipation (TJ = 85 °C) Junction temperature Storage temperature Absolute maximum ratings Parameter Value -3 to Vboot - 18 - 0.3 to +18 -1 to 618 - 1 to Vboot -0.3 to Vcc +0.3 -0.3 to Vcc +0.3 -0.3 to Vcc +0.3 -0.3 to Vcc +0.3 50 750 150 -50 to 150 Unit V V V V V V V V V/ns mW °C °C Note: ESD immunity for pins 12, 13 and 14 is guaranteed up to 900V (Human Body Model) 1.2 Thermal data Table 2. Symbol Rth(JA) Thermal data Parameter Thermal Resistance Junction to ambient SO-14 165 DIP-14 100 Unit °C/W 1.3 Recommended operating conditions Table 3. Symbol Vout VBS (2) fsw Vcc TJ Recommended operating conditions Pin 12 14 Parameter Output voltage Floating supply voltage Switching frequency 4 Supply voltage Junction temperature -45 HVG,LVG load CL = 1nF Test condition Min (1) (1) Typ Max 580 17 400 17 125 Unit V V kHz V °C 1. If the condition Vboot - Vout < 18V is guaranteed, Vout can range from -3 to 580V 2. VBS = Vboot - Vout 3/18 Pin connection L6386E 2 Pin connection Figure 2. Pin connection (Top view) LIN SD HIN VCC DIAG CIN SGND 1 2 3 4 5 6 7 D97IN521A 14 13 12 11 10 9 8 Vboot HVG OUT N.C. N.C. LVG PGND Table 4. N° 1 2 3 4 5 6 7 8 9 10, 11 12 13 14 Pin description Pin LIN SD(1) HIN VCC DIAG CIN SGND PGND LVG (1) N.C. OUT HVG (1) Type I I I Low side driver logic input Shut down logic input High side driver logic input Low voltage supply O I Open drain diagnostic output Comparator input Ground Power ground O Low side driver output Not connected O O High side driver floating driver High side driver output Bootstrapped supply voltage Function Vboot 1. The circuit guarantees 0.3V maximum on the pin (@ Isink = 10mA), with VCC >3V. This allows to omit the "bleeder" resistor connected between the gate and the source of the external MOSFET normally used to hold the pin low; the gate driver assures low impedance also in SD condition. 4/18 L6386E Electrical characteristics 3 3.1 Electrical characteristics AC operation Table 5. Symbol ton toff tsd tr tf AC operation electrical characteristcs (VCC = 15V; TJ = 25°C) Pin Parameter Test condition Min Typ 110 Vout = 0V 110 105 CL = 1000pF CL = 1000pF 50 30 Max 150 150 150 ns ns Unit ns ns High/low side driver turn-on 1,3 vs propagation delay 9,13 High/low side driver turn-off propagation delay 2 vs 9,13 9, 13 Fall time Shut down to high/low side propagation delay Rise time 3.2 DC operation Table 6. Symbol DC operation electrical characteristcs (VCC = 15V; TJ = 25°C) Pin Parameter Test condition Min Typ Max Unit Low supply voltage section Vcc Vccth1 Vccth2 Vcchys Iqccu Iqcc 4 Supply voltage Vcc UV turn on threshold Vcc UV turn off threshold Vcc UV hysteresis Undervoltage quiescent supply current Quiescent current Vcc ≤ 11V Vcc = 15V 11.5 9.5 12 10 2 200 250 320 17 12.5 10.5 V V V V µA µA Bootstrapped supply section Vboot Vbth1 Vbth2 Vbhys Iqboot Ilk Rdson 14 Bootstrap supply voltage Vboot UV turn on threshold Vboot UV turn off threshold Vboot UV hysteresis Vboot quiescent current High voltage leakage current Bootstrap driver on resistance (1) HVG ON Vhvg = Vout = Vboot = 600V Vcc ≥12.5V; Vin = 0V 125 10.7 9.5 11.9 9.9 2 200 10 17 12.9 10.7 V V V V µA µA Ω 5/18 Electrical characteristics Table 6. Symbol L6386E DC operation electrical characteristcs (continued)(VCC = 15V; TJ = 25°C) Pin Parameter Test condition Min Typ Max Unit Driving buffers section Iso Isi 9, 13 9, 13 High/low side source short circuit current High/low side sink short circuit current VIN = Vih (tp < 10µs) VIN = Vil (tp < 10µs) 300 500 400 650 mA mA Logic inputs Vil Vih Iih Iil Low level logic threshold voltage 1,2, High level logic threshold 3 voltage High level logic input current Low level logic input current VIN = 15V VIN = 0V 3.6 50 70 1 1.5 V V µA µA Sense comparator Vio Iio Vol Vref 6 2 Input offset voltage Input bias current Open drain low level output voltage Comparator reference voltage Vcin ≥ 0.5 Iod = -2.5mA 0.46 0.5 -10 0.2 0.8 0.54 10 mV µA V V 1. RDS(on) is tested in the following way: ( V CC – V CBOOT1 ) – ( V CC – V CBOOT2 ) R DSON = -----------------------------------------------------------------------------------------------------I 1 ( V CC ,V CBOOT1 ) – I 2 ( V CC ,V CBOOT2 ) where I1 is pin 8 current when VCBOOT = VCBOOT1, I2 when VCBOOT = VCBOOT2 6/18 L6386E Electrical characteristics 3.3 Timing diagram Figure 3. Input/output timing diagram HIN LIN SD HOUT LOUT VREF VCIN DIAG Note: SD active condition is latched until next negative IN edge. D97IN522A 7/18 Bootstrap driver L6386E 4 Bootstrap driver A bootstrap circuitry is needed to supply the high voltage section. This function is normally accomplished by a high voltage fast recovery diode (Figure 4 a). In the L6386E a patented integrated structure replaces the external diode. It is realized by a high voltage DMOS, driven synchronously with the low side driver (LVG), with in series a diode, as shown in Figure 4 b. An internal charge pump (Figure 4 b) provides the DMOS driving voltage. The diode connected in series to the DMOS has been added to avoid undesirable turn on of it. 4.1 CBOOT selection and charging To choose the proper CBOOT value the external MOS can be seen as an equivalent capacitor. This capacitor CEXT is related to the MOS total gate charge: Q gate C EXT = -------------V gate The ratio between the capacitors CEXT and CBOOT is proportional to the cyclical voltage loss. It has to be: CBOOT>>>CEXT e.g.: if Qgate is 30nC and Vgate is 10V, CEXT is 3nF. With CBOOT = 100nF the drop would be 300mV. If HVG has to be supplied for a long time, the CBOOT selection has to take into account also the leakage losses. e.g.: HVG steady state consumption is lower than 200µA, so if HVG TON is 5ms, CBOOT has to supply 1µC to CEXT. This charge on a 1µF capacitor means a voltage drop of 1V. The internal bootstrap driver gives great advantages: the external fast recovery diode can be avoided (it usually has great leakage current). This structure can work only if VOUT is close to GND (or lower) and in the meanwhile the LVG is on. The charging time (Tcharge ) of the CBOOT is the time in which both conditions are fulfilled and it has to be long enough to charge the capacitor. The bootstrap driver introduces a voltage drop due to the DMOS RDSON (typical value: 125 Ω). At low frequency this drop can be neglected. Anyway increasing the frequency it must be taken in to account. The following equation is useful to compute the drop on the bootstrap DMOS: Q gate V drop = I ch arg e R dson → V drop = ------------------ R dson T ch arg e where Qgate is the gate charge of the external power MOS, Rdson is the on resistance of the bootstrap DMOS, and Tcharge is the charging time of the bootstrap capacitor. 8/18 L6386E Bootstrap driver For example: using a power MOS with a total gate charge of 30nC the drop on the bootstrap DMOS is about 1V, if the Tcharge is 5µs. In fact: 30nC V drop = -------------- ⋅ 125 Ω ∼ 0.8V 5µs Vdrop has to be taken into account when the voltage drop on CBOOT is calculated: if this drop is too high, or the circuit topology doesn’t allow a sufficient charging time, an external diode can be used. Figure 4. Bootstrap driver DBOOT VS VBOOT H.V. HVG VS VBOOT H.V. HVG CBOOT VOUT TO LOAD CBOOT VOUT TO LOAD LVG LVG a b D99IN1056 9/18 Typical characteristic L6386E 5 Typical characteristic Figure 5. Typical rise and fall times vs load capacitance D99IN1054 Figure 6. Iq (µA) 104 Quiescent current vs supply voltage D99IN1057 time (nsec) 250 200 Tr 150 Tf 100 50 0 103 102 10 0 1 2 3 4 5 C (nF) For both high and low side buffers @25˚C Tamb 0 2 4 6 8 10 12 14 16 VS(V) Figure 7. Turn on time vs temperature Figure 8. VBOOT UV turn on threshold vs temperature 250 15 @ Vcc = 15V 200 14 13 Vbth1 (V) 12 11 10 9 8 Typ. @ Vcc = 15V Ton (ns) 150 Typ. 100 50 0 -45 -25 0 25 50 Tj (°C) 75 100 125 7 -45 -25 0 25 50 Tj (°C) 75 100 125 Figure 9. Turn Off time vs temperature Figure 10. VBOOT UV turn off threshold vs temperature 15 250 @ Vcc = 15V 200 14 Vbth2 (V) 13 12 11 10 9 8 Typ. @ Vcc = 15V Toff (ns) 150 Typ. 100 50 0 -45 -25 0 25 50 Tj (°C) 75 100 125 7 -45 -25 0 25 50 Tj (°C) 75 100 125 10/18 L6386E Figure 11. Shutdown time vs temperature 250 Typical characteristic Figure 12. VBOOT UV Hysteresis 3 @ Vcc = 15V 200 150 100 50 0 -45 -25 0 25 50 Tj (°C) 75 100 125 Typ. @ Vcc = 15V 2.5 Vbhys (V) Typ. tsd (ns0 2 1.5 1 -45 -25 0 25 50 Tj (°C) 75 100 125 Figure 13. VCC UV turn on threshold vs temperature 15 14 Vccth1(V) 13 12 11 10 9 -45 -25 0 25 50 Tj (°C) 75 100 125 Typ. Figure 14. Output source current vs temperature 1000 @ Vcc = 15V 800 current (mA) 600 Typ. 400 200 0 -45 -25 0 25 50 Tj (°C) 75 100 125 Figure 15. VCC UV turn off threshold vs temperature 12 11 10 Typ. 9 8 7 -45 Figure 16. Output sink current vs temperature 1000 @ Vcc = 15V 800 current (mA) 600 400 200 0 -45 Typ. Vccth2(V) -25 0 25 50 75 100 125 -25 0 Tj (°C) 25 50 Tj (°C) 75 100 125 11/18 Typical characteristic L6386E Figure 17. VCC UV hysteresis vs 7temperature 3 2.5 Vcchys (V) Typ. 2 1.5 1 -45 -25 0 25 50 Tj (°C) 75 100 125 12/18 L6386E Package mechanical data 6 Package mechanical data In order to meet environmental requirements, ST offers these devices in ECOPACK® packages. These packages have a Lead-free second level interconnect . The category of second level interconnect is marked on the package and on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. ECOPACK is an ST trademark. ECOPACK specifications are available at: www.st.com 13/18 Package mechanical data Figure 18. DIP-14 mechanical data and package dimensions mm MIN. a1 B b b1 D E e e3 F I L Z 1.27 3.3 2.54 0.050 8.5 2.54 15.24 7.1 5.1 0.130 0.51 1.39 0.5 0.25 20 0.335 0.100 0.600 0.280 0.201 1.65 TYP. MAX. MIN. 0.020 0.055 0.020 0.010 0.787 0.065 inch TYP. MAX. L6386E DIM. OUTLINE AND MECHANICAL DATA DIP14 0.100 14/18 L6386E Package mechanical data Figure 19. SO-14 mechanical data and package dimensions mm DIM. MIN. A A1 A2 B C D (1) E e H h L k ddd 5.8 0.25 0.40 1.35 0.10 1.10 0.33 0.19 8.55 3.80 1.27 6.20 0.50 1.27 0.228 0.01 0.016 TYP. MAX. 1.75 0.30 1.65 0.51 0.25 8.75 4.0 MIN. 0.053 0.004 0.043 0.013 0.007 0.337 0.150 0.050 0.244 0.02 0.050 TYP. MAX. 0.069 0.012 0.065 0.020 0.01 0.344 0.157 inch OUTLINE AND MECHANICAL DATA 0˚ (min.), 8˚ (max.) 0.10 0.004 (1) “D” dimension does not include mold flash, protusions or gate burrs. Mold flash, protusions or gate burrs shall not exceed 0.15mm per side. SO14 0016019 D 15/18 Order codes L6386E 7 Order codes Table 7. Order codes Part number L6386E L6386ED L6386ED013TR Package DIP-8 SO-8 SO-8 Packaging Tube Tube Tape and reel 16/18 L6386E Revision history 8 Revision history Table 8. Date 11-Oct-2007 Document revision history Revision 1 First release Changes 17/18 L6386E Please Read Carefully: Information in this document is provided solely in connection with ST products. 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