L6388

L6388 HIGH-VOLTAGE HIGH AND LOW SIDE DRIVER 1 FEATURES Figure 1. Package ■ HIGH VOLTAGE RAIL UP TO 600 V ■ dV/dt IMMUNITY ± 50 V/nsec IN FULL TEMPERATURE RANGE ■ DRIVER CURRENT CAPABILITY:400 mA SOURCE,650 mA SINK ■ SWITCHING TIMES 70/40 nsec RISE/FALL WITH 1nF LOAD SO8 Table 1. Order Codes 3.3V, 5V, 15V CMOS/TTL INPUTS COMPARATORS WITH HYSTERESYS AND PULL DOWN ■ INTERNAL BOOTSTRAP DIODE ■ OUTPUTS IN PHASE WITH INPUTS ■ DEAD TIME AND INTERLOCKING FUNCTION DESCRIPTION ) s ( ct Package L6388 DIP8 L6388D SO8 SO8 in Tape & Reel o r P It has a Driver structure that enables to drive independent referenced N Channel Power MOS or IGBT. The Upper (Floating) Section is enabled to work with voltage Rail up to 600V. e t le The Logic Inputs are CMOS/TTL compatible for ease of interfacing with controlling devices. u d o BOOTSTRAP DRIVER VCC 3 t e l o r P e bs HIN O LIN UV DETECTION 8 UV DETECTION LOGIC 2 SHOOT THROUGH PREVENTION R R LEVEL SHIFTER Vboot H.V. HVG DRIVER Cboot HVG 7 S OUT VCC 1 LVG DRIVER May 2005 c u d ) s t( o s b O - The L6388 is an high-voltage device, manufactured with the BCD"OFF-LINE" technology. Figure 2. Block Diagram Part Number L6388D013TR ■ 2 DIP8 6 TO LOAD 5 LVG 4 GND Rev. 2 1/11 L6388 Table 2. Absolute Maximum Rating Symbol Parameter Value Unit Vout Output Voltage -3 to Vboot - 18 V Vcc Supply Voltage - 0.3 to +18 V Vboot Floating Supply Voltage - 1 to 618 V Vhvg High Side Gate Output Voltage - 1 to Vboot V Vlvg Low Side Gate Output Voltage -0.3 to Vcc +0.3 V Logic Input Voltage -0.3 to Vcc +0.3 V Allowed Output Slew Rate 50 V/ns Total Power Dissipation (Tj = 85°C) 750 mW Tj Junction Temperature 150 °C Tstg Storage Temperature -50 to 150 °C Vi dVout/dt Ptot Note: ESD immunity for pins 6, 7 and 8 is guaranteed up to 900V (Human Body Model) Figure 3. Pin Connection (Top view) LIN 1 8 Vboot HIN 2 7 HVG VCC 3 6 GND 4 5 Table 3. Pin Description ) s ( ct N. Name Type 1 LIN I Low Side Driver Logic Input 2 HIN I High Side Driver Logic Input 3 Vcc I Low Voltage Power Supply 4 GND 6 bs 7 O 8 LVG Function Ground LVG (*) O Low Side Driver Output OUT O High Side Driver Floating Reference HVG (*) O High Side Driver Output Vboot o r P u d o r P e t e l o 5 so b O - D97IN517A e t le OUT c u d ) s t( Bootstrap Supply Voltage (*) The circuit guarantees 0.3V maximum on the pin (@ Isink = 10mA). This allows to omit the "bleeder" resistor connected between the gate and the source of the external MOSFET normally used to hold the pin low. Table 4. Thermal Data Symbol Rth j-amb 2/11 Parameter Thermal Resistance Junction to Ambient SO8 Minidip Unit 150 100 °C/W L6388 Table 5. Recommended Operating Conditions Symbol Pin Parameter Vout 6 Output Voltage VBS (*) 8 Floating Supply Voltage Test Condition Switching Frequency fsw 3 Vcc Min. Typ. Max. Unit Note 1 580 V Note 1 17 V 400 kHz 17 V 125 °C Max. Unit HVG,LVG load CL = 1nF Supply Voltage Junction Temperature Tj -45 Note 1: If the condition Vboot - Vout < 18V is guaranteed, Vout can range from -3 to 580V (*): VBS = Vboot - Vout Table 6. Electrical Characteristics (Vcc = 15V; Tj = 25°C) Symbol Pin Parameter Test Condition Min. Typ. AC OPERATION ton 1 vs 5 High/Low Side Driver Turn-On 2 vs 7 Propagation Delay Vout = 0V toff High/Low Side Driver Turn-Off Propagation Delay Vout = 0V tr 7,5 Rise Time CL = 1000pF tf 7,5 Fall Time CL = 1000pF DT 7,5 Dead Time DC OPERATION Low Supply Voltage Section 3 Vccth1 Vcc UV Turn On Threshold (t s) Vccth2 Vcc UV Turn Off Threshold Vcchys Vcc UV Hysteresis Iqccu Rdson t e l o 300 ns 220 ns 70 100 ns 40 80 ns 220 320 420 ns 9.1 9.6 10.1 V 7.9 8.3 8.8 V r P e t le o s b O - od 160 0.9 V Undervoltage Quiescent Supply Current Vcc ≤ 9V 250 330 µA Quiescent Current Vcc = 15V 350 450 µA o r P e Iqcc c u d uc 225 ) s t( Bootstrap Driver on Resistance (**) Vcc Ω 125 Bootstrapped Supply Voltage Section s b O VBSth1 VBSth2 8 VBShys VBS UV Turn On Threshold 8.5 9.5 10.5 V VBS UV Turn Off Threshold 7.2 8.2 9.2 V VBS UV Hysteresis 0.9 V IQBS VBS Quiescent Current HVG ON 250 µA ILK High Voltage Leakage Current Vhvg = Vout = Vboot = 600V 10 µA High/Low Side Driver Iso Isi 5,7 Source Short Circuit Current VIN = Vih (tp < 10µs) 300 400 mA Sink Short Circuit Current VIN = Vil (tp < 10µs) 500 650 mA 3/11 L6388 Table 6. Electrical Characteristics (continued) (Vcc = 15V; Tj = 25°C) Symbol Pin Parameter Test Condition Min. Typ. Max. Unit 1.1 V Logic Inputs 1, 2 Vil Low Level Logic Input Voltage Vih High Level Logic Input Voltage Iih High Level Logic Input Current VIN = 15V Iil Low Level Logic Input Current VIN = 0V 1.8 V 20 70 µA µA -1 ( V CC – V CBOOT1 ) – ( V CC – V CBOOT2 ) (**) RDSON is tested in the following way: R DSON = -------------------------------------------------------------------------------------------------------------I 1 ( V CC, V CCBOOT1 ) – I 2 ( V CC, V CCBOOT2 ) where I1 is pin 8 current when VCBOOT = VCBOOT1, I2 when VCBOOT = VCBOOT2. Figure 4. Dead Time Waveforms Definitions H IN DT LVG DT o s b O DT HVG ) s ( ct e t le o r P Interlocking function c u d LIN Figure 5. Propagation Delay Waveform Definitions r P e LIN t e l o s b O HIN u d o 50% 50% > DT > DT 50% 50% ton 90% LVG 10% ton 90% HVG 4/11 50% 10% toff toff ) s t( L6388 3 INPUT LOGIC Input logic is provided with an interlocking circuitry which avoids the two outputs (LVG, HVG) to be active at the same time when both the logic input pins (LIN, HIN) are at a high logic level. In addition, to prevent cross conduction of the external MOSFETs, after each output is turned-off the other output cannot be turned-on before a certain amount of time (DT) (see Figure 4). Figure 6. Typical Rise and Fall Times vs. Load Capacitance time (nsec) D99IN1054 Figure 7. Quiescent Current vs. Supply Voltage Iq (µA) 104 250 D99IN1055 200 Tr 103 150 Tf 100 102 50 0 c u d 10 0 1 2 3 4 5 C (nF) For both high and low side buffers @25˚C Tamb 0 2 4 6 e t le 3.1 BOOTSTRAP DRIVER o r P 8 10 12 ) s t( 14 16 VS(V) A bootstrap circuitry is needed to supply the high voltage section. This function is normally accomplished by a high voltage fast recovery diode (fig. 8a). In the L6388 a patented integrated structure replaces the external diode. It is realized by a high voltage DMOS, driven synchronously with the low side driver (LVG), with in series a diode, as shown in fig. 8b o s b O - An internal charge pump (fig. 8b) provides the DMOS driving voltage . ) s ( ct The diode connected in series to the DMOS has been added to avoid undesirable turn on of it. 3.2 CBOOT selection and charging u d o To choose the proper CBOOT value the external MOS can be seen as an equivalent capacitor. This capacitor CEXT is related to the MOS total gate charge : r P e t e l o Q gate C EXT = --------------V gate The ratio between the capacitors CEXT and CBOOT is proportional to the cyclical voltage loss . It has to be: s b O CBOOT>>>CEXT e.g.: if Qgate is 30nC and Vgate is 10V, CEXT is 3nF. With CBOOT = 100nF the drop would be 300mV. If HVG has to be supplied for a long time, the CBOOT selection has to take into account also the leakage losses. e.g.: HVG steady state consumption is lower than 200µA, so if HVG TON is 5ms, CBOOT has to supply 1µC to CEXT. This charge on a 1µF capacitor means a voltage drop of 1V. The internal bootstrap driver gives great advantages: the external fast recovery diode can be avoided (it usually has great leakage current). This structure can work only if VOUT is close to GND (or lower) and in the meanwhile the LVG is on. The charging time (Tcharge) of the CBOOT is the time in which both conditions are fulfilled and it 5/11 L6388 has to be long enough to charge the capacitor. The bootstrap driver introduces a voltage drop due to the DMOS RDSON (typical value: 125 Ohm). At low frequency this drop can be neglected. Anyway increasing the frequency it must be taken in to account. The following equation is useful to compute the drop on the bootstrap DMOS: Q gate V drop = I ch arg e R dson → V drop = -------------------- R dson T ch arg e where Qgate is the gate charge of the external power MOS, Rdson is the on resistance of the bootstrap DMOS, and Tcharge is the charging time of the bootstrap capacitor. For example: using a power MOS with a total gate charge of 30nC the drop on the bootstrap DMOS is about 1V, if the Tcharge is 5µs. In fact: 30nC V drop = --------------- ⋅ 125Ω ∼ 0.8V 5µs Vdrop has to be taken into account when the voltage drop on CBOOT is calculated: if this drop is too high, or the circuit topology doesn't allow a sufficient charging time, an external diode can be used. Figure 8. Bootstrap Driver. c u d DBOOT VS VBOOT e t le H.V. so HVG (t s) LVG o r P e t e l o c u d b O - o r P CBOOT VOUT TO LOAD a VBOOT VS H.V. bs HVG O CBOOT VOUT TO LOAD LVG b 6/11 ) s t( L6388 Figure 9. VBOOT UV Turn On Threshold vs. Temperature Figure 12. VCC UV Turn Off Threshold vs. Temperature 11 13 @ Vcc = 15V 12 10 Typ. 10 Vccth2(V) VBSth1(V) 11 9 8 7 9 Typ. 8 7 6 6 5 -45 -25 0 25 50 Tj (˚C) 75 100 -45 125 25 75 100 c u d 1000 @ Vcc = 15V 13 50 125 o r P 800 current (mA) 12 11 10 9 ) s t( Figure 13. Output Source Current vs. Temperature 14 VBSth2(V) 0 Tj (˚C) Figure 10. VBOOT UV Turn Off Threshold vs. Temperature e t le 600 @ Vcc = 15V Typ. o s b O 400 200 8 Typ. 7 6 -45 -25 0 25 (s) t c u 50 75 100 13 d o r P e 11 0 25 50 Tj (˚C) 75 100 125 @ Vcc = 15V 800 10 9 -25 1000 current (mA) s b O -45 Figure 14. Output Sink Current vs. Temperature t e l o 12 0 125 Figure 11. VCC UV Turn On Threshold vs. Temperature Vccth1(V) -25 Typ. 600 Typ. 400 200 8 0 7 -45 -25 0 25 50 Tj (˚C) 75 100 125 -45 -25 0 25 50 Tj (˚C) 75 100 125 7/11 L6388 Figure 15. DIP8 Mechanical Data & Package Dimensions mm inch DIM. MIN. A TYP. MAX. MIN. 3.32 TYP. MAX. 0.131 a1 0.51 B 1.15 1.65 0.045 0.065 b 0.356 0.55 0.014 0.022 b1 0.204 0.304 0.008 0.012 0.020 D E 10.92 7.95 9.75 0.430 0.313 0.384 e 2.54 0.100 e3 7.62 0.300 e4 7.62 0.300 F 6.6 0.260 I 5.08 0.200 L 3.18 Z 3.81 0.125 1.52 r P e s b O 8/11 o r P DIP-8 e t le o s b O - 0.060 u d o c u d 0.150 ) s ( ct t e l o OUTLINE AND MECHANICAL DATA ) s t( L6388 Figure 16. SO8 Mechanical Data & Package Dimensions mm inch DIM. MIN. TYP. MAX. MIN. TYP. MAX. A 1.35 1.75 0.053 0.069 A1 0.10 0.25 0.004 0.010 A2 1.10 1.65 0.043 0.065 B 0.33 0.51 0.013 0.020 C 0.19 0.25 0.007 0.010 D (1) 4.80 5.00 0.189 0.197 E 3.80 4.00 0.15 0.157 e 1.27 0.050 H 5.80 6.20 0.228 0.244 h 0.25 0.50 0.010 0.020 L 0.40 1.27 0.016 0.050 k OUTLINE AND MECHANICAL DATA ddd 0˚ (min.), 8˚ (max.) c u d 0.10 0.004 Note: (1) Dimensions D does not include mold flash, protrusions or gate burrs. Mold flash, potrusions or gate burrs shall not exceed 0.15mm (.006inch) in total (both side). ) s ( ct ) s t( o r P SO-8 e t le o s b O - u d o r P e t e l o s b O 0016023 C 9/11 L6388 Table 7. Revision History Date Revision Description of Changes January 2005 1 First Issue May 2005 2 Changed from Preliminary Data to Final c u d e t le ) s ( ct u d o r P e t e l o s b O 10/11 o s b O - o r P ) s t( L6388 c u d e t le ) s ( ct ) s t( o r P o s b O - u d o r P e t e l o Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. s b O The ST logo is a registered trademark of STMicroelectronics. All other names are the property of their respective owners © 2005 STMicroelectronics - All rights reserved STMicroelectronics group of companies Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States of America www.st.com 11/11