L6388ED

L6388E High voltage high and low-side driver Datasheet - production data Description DIP-8 SO-8 Features  High voltage rail up to 600 V  dV/dt immunity ± 50 V/nsec in full temperature range  Driver current capability: – 400 mA source – 650 mA sink The L6388E is a high voltage gate driver, manufactured with the BCD ™ “offline” technology, and able to drive a half-bridge of power MOSFET/IGBT devices. The high-side (floating) section is enabled to work with voltage rail up to 600 V. Both device outputs can sink and source 650 mA and 400 mA respectively and cannot be simultaneously driven high thanks to an integrated interlocking function. Further prevention from outputs cross conduction is guaranteed by the deadtime function.  Switching times 70/40 nsec rise/fall with 1 nF load The L6388E device has two input and two output pins, and guarantees the outputs switch in phase with inputs. The logic inputs are CMOS/TTL compatible (3.3 V, 5 V and 15 V) to ease the interfacing with controlling devices.  3.3 V, 5 V, 15 V CMOS/TTL input comparators with hysteresis and pull-down The bootstrap diode is integrated in the driver allowing a more compact and reliable solution.  Internal bootstrap diode  Deadtime and interlocking function The L6388E device features the UVLO protection on both supply voltages (VCC and VBOOT) ensuring greater protection against voltage drops on the supply lines. Applications The device is available in a DIP-8 tube and SO-8 tube, and tape and reel packaging options.  Outputs in phase with inputs  Home appliances  Industrial applications and drives  Motor drivers – DC, AC, PMDC and PMAC motors  Induction heating  HVAC  Factory automation  Lighting applications  Power supply systems October 2015 This is information on a product in full production. DocID13991 Rev 5 1/18 www.st.com Contents L6388E Contents 1 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 2 Electrical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 2.1 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 2.2 Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 2.3 Recommended operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 3 Pin connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 4 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 4.1 AC operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 4.2 DC operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 5 Waveform definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 6 Input logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 7 Bootstrap driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 CBOOT selection and charging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 8 Typical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 9 Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 9.1 DIP-8 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 9.2 SO-8 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 10 Order codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 11 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 2/18 DocID13991 Rev 5 L6388E Block diagram 1 Block diagram Figure 1. Block diagram #005453"1
%3*7&3 7$$  67 %&5&$5*0/  67 %&5&$5*0/ -0(*$ )*/ -*/  4)005 5)306() 13&7&/5*0/ )7 )7( %3*7&3 3 3 -&7&4)*'5&3 7#005 $#005 )7(  4 065 7$$  -7( %3*7&3  50
-0"%  -7(  (/% ". DocID13991 Rev 5 3/18 18 Electrical data L6388E 2 Electrical data 2.1 Absolute maximum ratings Table 1. Absolute maximum ratings Value Symbol Unit Min. Max. VOUT Output voltage VBOOT -18 VBOOT V VCC Supply voltage - 0.3 18 V Floating supply voltage - 0.3 618 V VBOOT Vhvg High-side gate output voltage VOUT -0.3 VBOOT V Vlvg Low-side gate output voltage -0.3 VCC +0.3 V Logic input voltage -0.3 VCC +0.3 V 50 V/ns Vi dVOUT/dt Allowed output slew rate Total power dissipation (TJ = 85 °C) 750 750 mW Tj Junction temperature 150 150 °C Ts Storage temperature -50 150 °C ESD Human body model Ptot 2.2 Parameter 2 kV Thermal data Table 2. Thermal data Symbol Rth(JA) 2.3 Parameter Thermal resistance junction to ambient SO-8 DIP-8 Unit 150 100 °C/W Recommended operating conditions Table 3. Recommended operating conditions Symbol Pin VOUT 6 VBS(2) 8 TJ 3 Test condition Min. Max. Unit (1) 580 V Floating supply voltage (1) 17 V 400 kHz 17 V 125 °C HVG, LVG load CL = 1 nF Supply voltage Junction temperature -45 1. If the condition VBOOT - VOUT < 18 V is guaranteed, VOUT can range from -3 to 580 V. 2. VBS = VBOOT - VOUT. 4/18 Typ. Output voltage Switching frequency fsw VCC Parameter DocID13991 Rev 5 L6388E 3 Pin connection Pin connection Figure 2.Pin connection (top view) -*/   7#005 )*/   )7( 7$$   065 (/%   -7( %*/"W Table 4. Pin description No. Pin Type 1 LIN I Low-side driver logic input 2 HIN I High-side driver logic input 3 VCC P Low-voltage power supply 4 GND P Ground O Low-side driver output 5 LVG (1) Function 6 OUT P High-side driver floating reference 7 HVG(1) O High-side driver output 8 VBOOT P Bootstrap supply voltage 1. The circuit guarantees 0.3 V maximum on the pin (at Isink = 10 mA). This allows the omission of the “bleeder” resistor connected between the gate and the source of the external MOSFET normally used to hold the pin low. DocID13991 Rev 5 5/18 18 Electrical characteristics L6388E 4 Electrical characteristics 4.1 AC operation Table 5. AC operation electrical characteristics (VCC = 15 V; TJ = 25 °C) Symbol ton toff Pin Parameter Test condition High/low-side driver turn-on 1 vs. 5 propagation delay 2 vs. 7 High/low-side driver turn-off propagation delay Min. Typ. Max. Unit VOUT = 0 V 225 300 ns VOUT = 0 V 160 220 ns tr 5, 7 Rise time CL = 1000 pF 70 100 ns tf 5, 7 Fall time CL = 1000 pF 40 80 ns DT 5, 7 Deadtime 220 320 420 ns Min. Typ. Max. Unit 4.2 DC operation Table 6. DC operation electrical characteristics Symbol Pin Parameter Test condition Low supply voltage section VCCth1 VCC UV turn-on threshold 9.1 9.6 10.1 V VCCth2 VCC UV turn-off threshold 7.9 8.3 8.8 V VCC UV hysteresis 0.9 VCChys IQCCU 3 IQCC Undervoltage quiescent supply current VCC  9 V 250 330 A Quiescent current VCC = 15 V 350 450 A VCC  12.5 V 125 Bootstrap driver on RDS(on) V resistance(1)  Bootstrapped supply voltage section VBSth1 VBS UV turn-on threshold 8.5 9.5 10.5 V VBSth2 VBS UV turn-off threshold 7.2 8.2 9.2 V VBS UV hysteresis 0.9 VBShys 8 IQBS VBS quiescent current High voltage leakage current ILK V HVG ON 250 A Vhvg = VOUT = VBOOT = 600 V 10 A High/low-side driver Iso Isi 6/18 5, 7 Source short-circuit current VIN = Vih (tp < 10 s) 300 400 mA Sink short-circuit current VIN = Vil (tp < 10 s) 500 650 mA DocID13991 Rev 5 L6388E Electrical characteristics Table 6. DC operation electrical characteristics (continued) Symbol Pin Parameter Test condition Min. Typ. Max. Unit 1.1 V Logic inputs Vil Vih Iih Iil Low logic level input voltage 1, 2 High logic level input voltage 1.8 High logic level input current VIN = 15 V Low logic level input current VIN = 0 V V 20 -1 70 A A 1. RDS(on) is tested in the following way:  V CC – V BOOT1  –  V CC – V BOOT2  R DSON = ----------------------------------------------------------------------------------------------I 1  V CC ,V BOOT1  – I 2  V CC ,V BOOT2  where: I1 is pin 8 current when VBOOT = VBOOT1, I2 when VBOOT = VBOOT2. DocID13991 Rev 5 7/18 18 Waveform definitions 5 L6388E Waveform definitions Figure 3. Deadtime time waveform definition H IN DT DT LVG DT HVG Figure 4. Propagation delay waveform definition 8/18 DocID13991 Rev 5 Interlocking function LIN L6388E 6 Input logic Input logic Input logic is provided with an interlocking circuitry which avoids the two outputs (LVG, HVG) being active at the same time when both the logic input pins (LIN, HIN) are at a high logic level. In addition, to prevent cross conduction of the external MOSFETs, after each output is turned off, the other output cannot be turned on before a certain amount of time (DT) (see Figure 3). 7 Bootstrap driver A bootstrap circuitry is needed to supply the high voltage section. This function is normally accomplished by a high voltage fast recovery diode (Figure 5 a). In the L6388E device, a patented integrated structure replaces the external diode. It is realized by a high voltage DMOS, driven synchronously with the low-side driver (LVG), with a diode in series, as shown in Figure 5 b. An internal charge pump (Figure 5 b) provides the DMOS driving voltage. The diode connected in series to the DMOS has been added to avoid an undesirable turn-on. CBOOT selection and charging To choose the proper CBOOT value, the external MOSFET can be seen as an equivalent capacitor. This capacitor CEXT is related to the MOSFET total gate charge: Equation 1 Q gate C EXT = --------------V gate The ratio between the capacitors CEXT and CBOOT is proportional to the cyclical voltage loss. It must be: CBOOT>>>CEXT E.g.: if Qgate is 30 nC and Vgate is 10 V, CEXT is 3 nF. With CBOOT = 100 nF the drop is 300 mV. If HVG must be supplied for a long period, the CBOOT selection must also take the leakage losses into account. E.g.: HVG steady-state consumption is typical 250 A, so, if HVG TON is 5 ms, CBOOT must supply 1.25 C to CEXT. This charge on a 1 F capacitor means a voltage drop of 1.25 V. The internal bootstrap driver offers important advantages: the external fast recovery diode can be avoided (it usually has a high leakage current). This structure can work only if VOUT is close to GND (or lower) and, at the same time, the LVG is on. The charging time (Tcharge) of the CBOOT is the time in which both conditions are fulfilled and it must be long enough to charge the capacitor. The bootstrap driver introduces a voltage drop due to the DMOS RDS(on) (typical value: 125 ). This drop can be neglected at low switching frequency, but it should be taken into account when operating at high switching frequency. DocID13991 Rev 5 9/18 18 Bootstrap driver L6388E The following equation is useful to compute the drop on the bootstrap DMOS: Equation 2 Q gate V drop = I ch arg e R dson  V drop = -------------------R dson T ch arg e where Qgate is the gate charge of the external power MOSFET, RDS(on) is the on-resistance of the bootstrap DMOS, and Tcharge is the charging time of the bootstrap capacitor. For example: using a power MOSFET with a total gate charge of 30 nC, the drop on the bootstrap DMOS is about 1 V, if the Tcharge is 5 s. In fact: Equation 3 30nC V drop = ---------------  125  0.8V 5s Vdrop should be taken into account when the voltage drop on CBOOT is calculated: if this drop is too high, or the circuit topology doesn’t allow a sufficient charging time, an external diode can be used. Figure 5. Bootstrap driver DBOOT VS VBOOT H.V. HVG CBOOT VOUT TO LOAD LVG a VBOOT VS H.V. HVG CBOOT VOUT TO LOAD LVG b 10/18 DocID13991 Rev 5 L6388E Typical characteristics Figure 6. Typical rise and fall times vs. load capacitance time (nsec) D99IN1054 250 Figure 7. Quiescent current vs. supply voltage Iq (μA) 104 D99IN1055 200 Tr 103 150 Tf 100 102 50 10 0 0 1 2 3 4 5 C (nF) For both high and low side buffers @25˚C Tamb Figure 8. VBOOT UV turn-on threshold vs. temperature 2 0 4 6 8 10 12 14 16 VS(V) Figure 9. VCC UV turn-off threshold vs. temperature 11 13 @ Vcc = 15V 12 10 10 Typ. Vccth2(V) VBSth1(V) 11 9 8 7 9 Typ. 8 7 6 6 5 -45 -25 0 25 50 Tj (˚C) 75 100 -45 125 0 25 50 75 100 125 Figure 11. Output source current vs. temperature 1000 14 @ Vcc = 15V @ Vcc = 15V 13 800 current (mA) 12 11 10 9 600 Typ. 400 200 8 7 -25 Tj (˚C) Figure 10. VBOOT UV turn-off threshold vs. temperature VBSth2(V) 8 Typical characteristics Typ. 0 6 -45 -25 0 25 50 75 100 125 DocID13991 Rev 5 -45 -25 0 25 50 Tj (˚C) 75 100 125 11/18 18 Typical characteristics L6388E Figure 12. VCC UV turn-on threshold vs. temperature Figure 13. Output sink current vs. temperature 13 1000 @ Vcc = 15V 800 11 current (mA) Vccth1(V) 12 10 9 Typ. Typ. 400 200 8 0 7 -45 12/18 600 -25 0 25 50 Tj (˚C) 75 100 125 DocID13991 Rev 5 -45 -25 0 25 50 Tj (˚C) 75 100 125 L6388E 9 Package information Package information In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK® packages, depending on their level of environmental compliance. ECOPACK specifications, grade definitions and product status are available at: www.st.com. ECOPACK is an ST trademark. 9.1 DIP-8 package information Figure 14. DIP-8 package outline $0Y DocID13991 Rev 5 13/18 18 Package information L6388E Table 7. DIP-8 package mechanical data Dimensions (mm) Symbol Min. A Typ. 3.32 a1 0.51 B 1.15 1.65 b 0.356 0.55 b1 0.204 0.304 D E 10.92 7.95 9.75 e 2.54 e3 7.62 e4 7.62 F 6.6 I 5.08 L 3.18 Z 14/18 Max. 3.81 1.52 DocID13991 Rev 5 L6388E 9.2 Package information SO-8 package information Figure 15. SO-8 package outline $0Y Table 8. SO-8 package mechanical data Dimensions (mm) Symbol Min. Typ. A Max. 1.75 A1 0.10 0.25 A2 1.25 b 0.28 0.48 c 0.17 0.23 D 4.80 4.90 5.00 E 5.80 6.00 6.20 E1 3.80 3.90 4.00 e 1.27 h 0.25 0.50 L 0.40 1.27 L1 k 1.04 0° 8° ccc 0.10 DocID13991 Rev 5 15/18 18 Order codes 10 L6388E Order codes Table 9. Order codes 16/18 Part number Package Packaging L6388E DIP-8 Tube L6388ED SO-8 Tube L6388ED013TR SO-8 Tape and reel DocID13991 Rev 5 L6388E 11 Revision history Revision history Table 10. Document revision history Date Revision 11-Oct-2007 1 First release 29-Feb-2012 2 Updated Table 2, Table 7 and Section 6.1. DIP-8 mechanical data and package dimensions have been updated. SO-8 mechanical data and package dimensions have been updated. 31-Jan-2013 3 Update note in Section 2.1. 4 Added Section : Applications on page 1. Updated Section : Description on page 1 (replaced by new description). Updated Table 1: Device summary on page 1 (moved from page 17 to page 1, renamed title of Table 1). Updated Figure 1: Block diagram on page 3 (moved from page 1 to page 3, added Section 1: Block diagram on page 3). Updated Section 2.1: Absolute maximum ratings on page 4 (removed note below Table 2: Absolute maximum ratings). Updated Table 5: Pin description on page 5 (added “Type” for several pins). Updated Section 9: Package information on page 14 (added/updated titles, reversed order of Figure 14 and Table 8, Figure 15 and ,Table 9 minor modifications). Minor modifications throughout document. 5 Updated Table 1 on page 4 (added ESD row). Updated note 1. below Table 6 on page 6 (replaced VCBOOTx by VBOOTx). Added Section 10: Order codes on page 16 (moved Table 9 from page 1, updated title). Minor modifications throughout document. 19-Jun-2014 21-Oct-2015 Changes DocID13991 Rev 5 17/18 18 L6388E IMPORTANT NOTICE – PLEASE READ CAREFULLY STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on ST products before placing orders. ST products are sold pursuant to ST’s terms and conditions of sale in place at the time of order acknowledgement. Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or the design of Purchasers’ products. No license, express or implied, to any intellectual property right is granted by ST herein. Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product. ST and the ST logo are trademarks of ST. All other product or service names are the property of their respective owners. Information in this document supersedes and replaces information previously supplied in any prior versions of this document. © 2015 STMicroelectronics – All rights reserved 18/18 DocID13991 Rev 5