L6390D

L6390 High voltage high/low-side driver Datasheet - production data Description SO-16 The L6390 is a full featured high voltage device manufactured with the BCD ™ “offline” technology. It is a single-chip half-bridge gate driver for N-channel power MOSFETs or IGBTs. The high-side (floating) section is able to work with voltage rail up to 600 V. Features  High voltage rail up to 600 V  dV/dt immunity ± 50 V/nsec in full temperature range  Driver current capability: 290 mA source, 430 mA sink  Switching times 75/35 nsec rise/fall with 1 nF load  3.3 V, 5 V TTL/CMOS inputs with hysteresis  Integrated bootstrap diode  Operational amplifier for advanced current sensing  Comparator for fast fault protection  Smart shutdown function  Adjustable deadtime  Interlocking function  Compact and simplified layout  Bill of material reduction Both device outputs can sink and source 430 mA and 290 mA respectively. Prevention from cross conduction is ensured by interlocking and programmable deadtime functions. The device has dedicated input pins for each output and a shutdown pin. The logic inputs are CMOS/TTL compatible down to 3.3 V for easy interfacing with control devices. Matched delays between low-side and high-side sections guarantee no cycle distortion and allow high frequency operation. The L6390 embeds an operational amplifier suitable for advanced current sensing in applications such as field oriented motor control or for sensorless BEMF detection. A comparator featuring advanced smartSD function is also integrated in the device, ensuring fast and effective protection against fault events like overcurrent, overtemperature, etc.  Home appliances The L6390 device features also UVLO protection on both the lower and upper driving sections, preventing the power switches from operating in low efficiency or dangerous conditions.  Motor drivers – DC, AC, PMDC and PMAC motors – FOC and sensorless BEMF detection systems The integrated bootstrap diode as well as all of the integrated features of this IC make the application PCB design easier, more compact and simple thus reducing the overall bill of material.  Industrial applications and drives The device is available in an SO-16 tube and tape and reel packaging options. Applications  Induction heating  HVAC  Factory automation  Power supply systems March 2018 This is information on a product in full production. DocID14493 Rev 11 1/25 www.st.com Contents L6390 Contents 1 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 2 Pin connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 3 Electrical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 4 3.1 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 3.2 Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 3.3 Recommended operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 4.1 AC operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 4.2 DC operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 5 Timing and waveforms definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 6 Input logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 7 Smart shutdown function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 8 Typical application diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 9 Bootstrap driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 CBOOT selection and charging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 10 Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 10.1 SO-16 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 11 Order codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 12 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 2/25 DocID14493 Rev 11 L6390 Block diagram 1 Block diagram Figure 1. Block diagram BOOTSTRAP DRIVER VCC 4 from LVG HVG DRIVER 3 S LEVEL SHIFTER 15 R HVG LOGIC 5V SHOOT THROUGH PREVENTION LIN BOOT UV DETECTION UV DETECTION HIN 16 FLOATING STRUCTURE 14 OUT 1 VCC LVG DRIVER LVG SD/OD GND 2 8 11 SD LATCH SMART SD 5V COMPARATOR 10 + - CP+ + VREF DT OPOUT 5 DEAD VCC TIME 7 OPAMP + - 9 6 DocID14493 Rev 11 OP+ OP- 3/25 25 Pin connection 2 L6390 Pin connection Figure 2. Pin connection (top view) -*/   7#005 4%0%   )7( )*/   065 7$$   /$ %5   /$ 01   -7( 01065   $1 (/%   01 ". Table 1. Pin description Pin no. Pin name Type 1 LIN I 2 SD/OD (1) I/O 3 HIN I High-side driver logic input (active high) 4 VCC P Lower section supply voltage 5 DT I Deadtime setting 6 OP- I Op amp inverting input 7 OPOUT O Op amp output 8 GND P Ground 9 OP+ I Op amp non-inverting input 10 CP+ I Comparator input O Low-side driver output 11 LVG (1) 12, 13 NC 14 OUT Function Low-side driver logic input (active low) Shutdown logic input (active low)/open drain (comparator output) Not connected (1) 15 HVG 16 BOOT P High-side (floating) common voltage O High-side driver output P Bootstrap supply voltage 1. The circuit provides less than 1 V on the LVG and HVG pins (at Isink = 10 mA), with VCC > 3 V. This allows the omission of the “bleeder” resistor connected between the gate and the source of the external MOSFET normally used to hold the pin low; the gate driver assures low impedance also in SD condition. 4/25 DocID14493 Rev 11 L6390 Electrical data 3 Electrical data 3.1 Absolute maximum ratings Table 2. Absolute maximum ratings Value Symbol Parameter Unit Min. Max. VCC Supply voltage - 0.3 21 V VOUT Output voltage VBOOT - 21 VBOOT + 0.3 V VBOOT Bootstrap voltage - 0.3 620 V Vhvg High-side gate output voltage VOUT - 0.3 VBOOT + 0.3 V Vlvg Low-side gate output voltage - 0.3 VCC + 0.3 V VOP+ Op amp non-inverting input - 0.3 VCC + 0.3 V VOP- Op amp inverting input - 0.3 VCC + 0.3 V VCP+ Comparator input voltage - 0.3 VCC + 0.3 V Vi Logic input voltage - 0.3 15 V Vod Open drain voltage - 0.3 15 V - 50 V/ns dVOUT/dt Allowed output slew rate 3.2 Ptot Total power dissipation (TA = 25 °C) - 800 mW TJ Junction temperature - 150 °C Tstg Storage temperature -50 150 °C ESD Human body model 2 kV Thermal data Table 3. Thermal data Symbol Rth(JA) Parameter Thermal resistance junction to ambient DocID14493 Rev 11 SO-16 Unit 120 °C/W 5/25 25 Electrical data 3.3 L6390 Recommended operating conditions Table 4. Recommended operating conditions Symbol Pin VCC 4 VBO(1) Parameter Test condition Min. Max. Unit Supply voltage - 12.5 20 V 16 - 14 Floating supply voltage - 12.4 20 V DC output voltage - (2) -9 580 V - 800 kHz -40 125 °C VOUT 14 fsw - Switching frequency HVG, LVG load CL = 1 nF TJ - Junction temperature - 1. VBO = VBOOT - VOUT. 2. LVG off. VCC = 12.5 V. Logic is operational if VBOOT > 5 V. Refer to the AN2738 for more details. 6/25 DocID14493 Rev 11 L6390 Electrical characteristics 4 Electrical characteristics 4.1 AC operation Table 5. AC operation electrical characteristics (VCC = 15 V; TJ = +25 °C) Symbol ton toff tsd Pin Parameter Test condition Min. Typ. Max. Unit 50 125 200 ns 50 125 200 ns 50 125 200 ns 50 200 250 ns - - 30 ns RDT = 0, CL = 1 nF 0.1 0.18 0.25 s RDT = 37 k, CL = 1 nF, CDT = 100 nF 0.48 0.6 0.72 s RDT = 136 k, CL = 1 nF, CDT = 100 nF 1.35 1.6 1.85 s RDT = 260 k, CL = 1 nF, CDT = 100 nF 2.6 3.0 3.4 s RDT = 0, CL = 1 nF - - 80 ns RDT = 37 k, CL = 1 nF, CDT = 100 nF - - 120 ns RDT = 136 k, CL = 1 nF, CDT = 100 nF - - 250 ns RDT = 260 k, CL = 1 nF, CDT = 100 nF - - 400 ns Rise time CL = 1 nF - 75 120 ns Fall time CL = 1 nF - 35 70 ns High/low-side driver turn-on VOUT = 0 V 1 vs. 11 propagation delay VBOOT = VCC 3 vs. 15 High/low-side driver turn-off CL = 1 nF propagation delay Vi = 0 to 3.3 V Shutdown to high/low-side See Figure 4 on page 12 2 vs. 11, 15 driver propagation delay tisd - Comparator triggering to high/low-side driver turn-off propagation delay MT - Delay matching, HS and LS turn-on/off DT 5 MDT tr tf - 11, 15 Deadtime setting range(1) Matching deadtime(2) Measured applying a voltage step from 0 V to 3.3 V to pin CP+. 1. See Figure 3. 2. MDT = | DTLH - DTHL | see Figure 6 on page 13. DocID14493 Rev 11 7/25 25 Electrical characteristics L6390 Figure 3. Typical deadtime vs. DT resistor value  $SSUR[LPDWHGIRUPXODIRU 5GWFDOFXODWLRQW\S  '7XV  5GW>Nȍ@ Ÿ ā'7>—V@          5GWN2KP 8/25 DocID14493 Rev 11    L6390 4.2 Electrical characteristics DC operation Table 6. DC operation electrical characteristics (VCC = 15 V; TJ = + 25 °C) Symbol Pin Parameter Test condition Min. Typ. Max. Unit Low supply voltage section VCC_hys VCC UV hysteresis - 1200 1500 1800 mV VCC_thON VCC UV turn-ON threshold - 11.5 12 12.5 V VCC_thOFF VCC UV turn-OFF threshold - 10 10.5 11 V Undervoltage quiescent supply current VCC = 10 V SD = 5 V; LIN = 5 V; HIN = GND; RDT = 0 ; CP+ = OP+ = GND; OP- = 5 V 90 120 150 A Quiescent current VCC = 15 V SD = 5 V; LIN = 5 V; HIN = GND; RDT = 0 ; CP+ = OP+ = GND; OP- = 5 V 300 720 1000 A Internal reference voltage - 500 540 580 mV VBO UV hysteresis - 1200 1500 1800 mV VBO_thON VBO UV turn-ON threshold - 11.1 11.5 12.1 V VBO_thOFF VBO UV turn-OFF threshold - 9.8 10 10.6 V Undervoltage VBO quiescent current VBO = 9 V SD = 5 V; LIN and HIN = 5 V; RDT = 0 ; CP+ = OP+ = GND; OP- = 5 V 30 70 110 A VBO quiescent current VBO = 15 V SD = 5 V; LIN and HIN = 5 V; RDT = 0 ; CP+ = OP+ = GND; OP- = 5 V 30 150 240 A IQCCU 4 IQCC Vref - Bootstrapped supply voltage section(1) VBO_hys IQBOU 16 IQBO ILK - High voltage leakage current Vhvg = VOUT = VBOOT = 600 V - - 10 A RDS(on) - Bootstrap driver onresistance(2) LVG ON - 120 -  DocID14493 Rev 11 9/25 25 Electrical characteristics L6390 Table 6. DC operation electrical characteristics (VCC = 15 V; TJ = + 25 °C) (continued) Symbol Pin Parameter Test condition Min. Typ. Max. Unit Driving buffers section High/low-side source shortcircuit current VIN = Vih (tp < 10 s) 200 290 - mA High/low-side sink shortcircuit current VIN = Vil (tp < 10 s) 250 430 - mA Low level logic threshold voltage - 0.8 - 1.1 V High level logic threshold voltage - 1.9 - 2.25 V Single input voltage LIN and HIN connected together and floating - - 0.8 V HIN logic “1” input bias current HIN = 15 V 110 175 260 A IHINl HIN logic “0” input bias current HIN = 0 V - - 1 A ILINl LIN logic “0” input bias current LIN = 0 V 3 6 20 A ILINh LIN logic “1” input bias current LIN = 15 V - - 1 A ISDh SD logic “1” input bias current SD = 15 V 10 40 100 A SD logic “0” input bias current SD = 0 V - - 1 A SD input pull-down resistor SD = 15 V 150 375 1500 k Iso 11, 15 Isi Logic inputs Vil 1, 2, 3 Vih Vil_S 1, 3 IHINh 3 1 2 ISDl RPD_SD 2 1. VBO = VBOOT - VOUT. 2. RDSON is tested in the following way: RDSON = [(VCC - VBOOT1) - (VCC - VBOOT2)] / [I1(VCC,VBOOT1) - I2(VCC,VBOOT2)] where I1 is the pin 16 current when VBOOT = VBOOT1, I2 when VBOOT = VBOOT2. 10/25 DocID14493 Rev 11 L6390 Electrical characteristics Table 7. Op amp characteristics(1) (VCC = 15 V, TJ = +25 °C) Symbol Pin Parameter Vio Input offset voltage Iio Input offset current Iib 6, 9 Min. Typ. Max. Unit - - 6 mV - 4 40 nA - 100 200 nA 0 - VCC-4 V 0.07 - VCC-4 V Source, Vid = +1; Vo = 0 V 16 30 - mA Sink,Vid = -1; Vo = VCC 50 80 - mA 2.5 3.8 - V/s Vic = 0 V, Vo = 7.5 V Vic = 0 V, Vo = 7.5 V (2) Input common mode voltage range Vicm VOPOUT Io Input bias current Test condition Output voltage swing 7 OPOUT = OP-; no load Output short-circuit current SR - Slew rate Vi = 1  4 V; CL = 100 pF; unity gain GBWP - Gain bandwidth product Vo = 7.5 V 8 12 - MHz Avd - Large signal voltage gain RL = 2 k 70 85 - dB SVR - Supply voltage rejection ratio vs. VCC 60 75 - dB CMRR - Common mode rejection ratio 55 70 - dB - 1. The operational amplifier is disabled when VCC is in UVLO condition. 2. Input bias current flows out the IC leads. Table 8. Sense comparator characteristics(1) (VCC = 15 V, TJ = +25 °C) Symbol Pin Parameter Iib 10 Input bias current VOL 2 RON_OD Test condition Min. Typ. Max. Unit VCP+ = 1 V - - 1 A Open drain low level output voltage IOD = - 3 mA - - 0.5 V 2 Open drain ON resistor - - 125 167  td_comp - Comparator delay SD/OD pulled to 5 V through 100 k resistor - 90 130 ns SR 2 Slew rate CL = 180 pF; Rpu = 5 k - 60 - V/s 1. The comparator is disabled when VCC is in UVLO condition. DocID14493 Rev 11 11/25 25 Timing and waveforms definitions 5 L6390 Timing and waveforms definitions Figure 4. Propagation delay timing definition -*/   
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TJHOBM ". DocID14493 Rev 11 13/25 25 Input logic 6 L6390 Input logic Input logic is provided with an interlocking circuitry which avoids cross-conduction in case of wrong signals on LIN and HIN tries to turn-on both LVG and HVG outputs at the same times. In addition, to prevent cross conduction of the external MOSFETs, after each output is turned off, the other output cannot be turned on before a certain amount of time (DT) (see Figure 5: Dead time and interlocking timing definitions). Table 9. Truth table Input Output SD LIN HIN LVG HVG L X(1) X(1) L L H H L L L H L H L L H L L H L H H H L H 1. X: don't care. 14/25 DocID14493 Rev 11 L6390 7 Smart shutdown function Smart shutdown function The L6390 device integrates a comparator committed to the fault sensing function. The comparator has an internal voltage reference Vref connected to the inverting input, while the non-inverting input is available on the pin 10. The comparator input can be connected to an external shunt resistor in order to implement a simple overcurrent detection function. The output signal of the comparator is fed to an integrated MOSFET with the open drain output available on the pin 2, shared with the SD input. When the comparator triggers, the device is set in shutdown state and both its outputs are set to low level leaving the half-bridge in tristate. Figure 7. Smart shutdown timing waveforms DPNQ
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$0/530--&3 $4% 30/@0% 4."35 4% -0(*$ 31%@4% ".W DocID14493 Rev 11 15/25 25 Smart shutdown function L6390 In common overcurrent protection architectures the comparator output is usually connected to the SD input and an RC network is connected to this SD/OD line in order to provide a monostable circuit, which implements a protection time that follows the fault condition. Differently from the common fault detection systems, the L6390 smart shutdown architecture allows immediate turn-off of the outputs of the gate driver in the case of fault, by minimizing the propagation delay between the fault detection event and the actual output switch-off. In fact, the time delay between the fault detection and the output turn-off is no longer dependent on the value of the external RC network connected to the SD/OD pin. In the smart shutdown circuitry the fault signal has a preferential path which directly switches off the outputs after the comparator triggering. At the same time the internal logic turns on the open drain output and holds it on until the SD voltage goes below the SD logic input lower threshold. When such threshold is reached, the open drain output is turned off, allowing the external pull-up to recharge the capacitor. The driver outputs restart following the input pins as soon as the voltage at the SD/OD pin reaches the higher threshold of the SD logic input. The smart shutdown system provides the possibility to increase the time constant of the external RC network (that determines the disable time after the fault event) up to very large values without increasing the delay time of the protection. Any external signal provided to the SD pin is not latched and can be used as control signal in order to perform, for instance, PWM chopping through this pin. In fact when a PWM signal is applied to the SD input and the logic inputs of the gate driver are stable, the outputs switch from the low level to the state defined by the logic inputs and vice versa. In some applications it may be useful to latch the driver in the shutdown condition for an arbitrary time, until the controller decides to reset it to normal operation. This may, for example, be achieved with a circuit similar to the one shown in Figure 8. When the open drain starts pulling down the SD/OD pin, the external latch turns on and keeps the pin to GND, preventing it from being pulled up again once the SD logic input lower threshold is reached and the internal open drain turns off. One pin of the controller is used to release the external latch, and one to externally force a shutdown condition and also to read the status of the SD/OD pin. Figure 8. Protection latching example circuit VBOOT HIN LIN 3.3 / 5 V HVG VCC + VCC µC R1 20 KΩ GND DT 3.3 / 5 V SD_reset VDD GND R3 2.2 KΩ R4 20 KΩ SD_force/sense R2 1.5 K Ω OUT + LVG L6390 CP+ SD/OD OPOUT OP+ OP- To other driver/devices AM12949v1 In applications using only one L6390 for the protection of several different legs (such as a single-shunt inverter, for example) it may be useful to implement the resistor divider shown in Figure 9. This simple network allows the pushing of the SD pins of the other devices to a voltage lower than L6390 Vil, so that each device can reach its low logic level regardless of part-to-part variations of the thresholds. 16/25 DocID14493 Rev 11 L6390 Smart shutdown function Figure 9. SD level shifting example circuit HV BUS VBOOT HIN LIN L6390 HVG VCC - VDD GND R2 R SD_force GND DT R1 9*R VDD VCC C1 SD/OD OPOUT OUT L639x µC + L639x + VCC LVG CP+ OP+ OP- C2 SD/OD C3 SD/OD R3 2*R SD_sense C1: disable time setting capacitor C2, C3: small noise filtering capacitors DocID14493 Rev 11 AM12948v1 17/25 25 Typical application diagram 8 L6390 Typical application diagram Figure 10. Application diagram BOOTSTRAP DRIVER VCC VCC 4 16 FLOATING STRUCTURE from LVG UV DETECTION UV DETECTION FROM CONTROLLER HIN H.V. 3 S LEVEL SHIFTER LIN 14 OUT TO LOAD 1 VCC GND HVG LOGIC VBIAS SD/OD 15 R SHOOT THROUGH PREVENTION FROM CONTROLLER 2 8 LVG 11 SD LATCH SMART SD LVG DRIVER 5V COMPARATOR 10 + CP+ + VBIAS VREF DT 5 DEAD VCC TIME OPOUT OPAMP 7 + 9 6 TO ADC DocID14493 Rev 11 OP+ OP- - 18/25 Cboot HVG DRIVER 5V FROM/TO CONTROLLER BOOT + L6390 9 Bootstrap driver Bootstrap driver A bootstrap circuitry is needed to supply the high voltage section. This function is normally accomplished by a high voltage fast recovery diode (Figure 11.a). In the L6390 device a patented integrated structure replaces the external diode. It is realized by a high voltage DMOS, driven synchronously with the low-side driver (LVG), with a diode in series, as shown in Figure 11.b. An internal charge pump (Figure 11.b) provides the DMOS driving voltage. CBOOT selection and charging To choose the proper CBOOT value the external MOS can be seen as an equivalent capacitor. This capacitor CEXT is related to the MOS total gate charge: Equation 1 Q gate C EXT = -------------V gate The ratio between the capacitors CEXT and CBOOT is proportional to the cyclical voltage loss. It must be: Equation 2 CBOOT >>> CEXT E.g.: if Qgate is 30 nC and Vgate is 10 V, CEXT is 3 nF. With CBOOT = 100 nF the drop would be 300 mV. If HVG must be supplied for a long time, the CBOOT selection must also take the leakage and quiescent losses into account. E.g.: HVG steady-state consumption is lower than 240 A, so if HVG TON is 5 ms, CBOOT must supply 1.2 C to CEXT. This charge on a 1 F capacitor means a voltage drop of 1.2 V. The internal bootstrap driver offers important advantages: the external fast recovery diode can be avoided (it usually has a high leakage current). This structure can work only if VOUT is close to GND (or lower) and, at the same time, the LVG is on. The charging time (Tcharge) of the CBOOT is the time in which both conditions are fulfilled and it must be long enough to charge the capacitor. The bootstrap driver introduces a voltage drop due to the DMOS RDSon (typical value: 120 ). This drop can be neglected at low switching frequency, but it should be taken into account when operating at high switching frequency. DocID14493 Rev 11 19/25 25 Bootstrap driver L6390 The following equation is useful to compute the drop on the bootstrap DMOS: Equation 3 Q gate V drop = I ch arg e R dson  V drop = ------------------R dson T ch arg e where Qgate is the gate charge of the external power MOSFET, Rdson is the on-resistance of the bootstrap DMOS and Tcharge is the charging time of the bootstrap capacitor. For example: using a power MOSFET with a total gate charge of 30 nC, the drop on the bootstrap DMOS is about 1 V, if the Tcharge is 5 s. In fact: Equation 4 30nC V drop = ---------------  120  0.7V 5s Vdrop should be taken into account when the voltage drop on CBOOT is calculated: if this drop is too high, or the circuit topology doesn’t allow a sufficient charging time, an external diode can be used. Figure 11. Bootstrap driver % #005 #005 7$$ #005 7$$ )7 )7 )7( $ #005 065 )7( 50
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-0"% -7( B C %*/7 20/25 DocID14493 Rev 11 L6390 10 Package information Package information In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK® packages, depending on their level of environmental compliance. ECOPACK specifications, grade definitions and product status are available at: www.st.com. ECOPACK is an ST trademark. 10.1 SO-16 package information Figure 12. SO-16 narrow package outline 40 DocID14493 Rev 11 21/25 25 Package information L6390 Table 10. SO-16 narrow package mechanical data Dimensions (mm) Symbol Min. Typ. Max. A - - 1.75 A1 0.10 - 0.25 A2 1.25 - - b 0.31 - 0.51 c 0.17 - 0.25 D 9.80 9.90 10.00 E 5.80 6.00 6.20 E1 3.80 3.90 4.00 e - 1.27 - h 0.25 - 0.50 L 0.40 - 1.27 k 0 - 8° ccc - - 0.10 Figure 13. SO-16 narrow footprint 22/25 DocID14493 Rev 11 L6390 11 Order codes Order codes Table 11. Order codes Order code Package Packaging L6390D SO-16 Tube L6390DTR SO-16 Tape and reel DocID14493 Rev 11 23/25 25 Revision history 12 L6390 Revision history Table 12. Document revision history Date 11-Sep-2015 07-Apr-2017 21-Mar-2018 24/25 Revision Changes 9 Removed DIP-16 package from the whole document. Updated Table 3 on page 6 (added ESD parameter and value). Updated Table 4 on page 6 (updated Rth(JA) value). Updated note 1.and 2. below Table 7 on page 10 (minor modifications, replaced VCBOOTx by VBOOTx ). Minor modifications throughout document. 10 Updated Table 5 on page 7 (updated cross reference to Figure 4 on page 12 instead of removed Figure 3. Timing). Updated Table 6 on page 9 (added RPD_SD) and Table 8 on page 11 (added RON_OD). Updated Section 5 on page 12 (updated title, added Figure 4 and Figure 5). Added Section 6 on page 14 (and moved Table 9: Truth table to this section). Updated Figure 11 on page 20 and Figure 12 on page 21 (replaced by new figure). Minor modifications throughout document. 11 Updated Figure of SO-16 package on page 1 and Figure 2: Pin connection (top view) on page 4. Updated Table 5 on page 7 (updated DT and MDT test conditions). Updated note 2. below Table 7 on page 11. Updated Section 6 on page 14. Minor modifications throughout document. DocID14493 Rev 11 L6390 IMPORTANT NOTICE – PLEASE READ CAREFULLY STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on ST products before placing orders. ST products are sold pursuant to ST’s terms and conditions of sale in place at the time of order acknowledgement. Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or the design of Purchasers’ products. No license, express or implied, to any intellectual property right is granted by ST herein. Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product. ST and the ST logo are trademarks of ST. All other product or service names are the property of their respective owners. Information in this document supersedes and replaces information previously supplied in any prior versions of this document. © 2018 STMicroelectronics – All rights reserved DocID14493 Rev 11 25/25 25