L6392

L6392 High-voltage high and low side driver Preliminary Data Features ■ ■ ■ High voltage rail up to 600 V dV/dt immunity ± 50 V/nsec in full temperature range Driver current capability: – 270 mA source – 430 mA sink Switching times 75/35 nsec rise/fall with 1 nF load 3.3 V, 5 V TTL/CMOS inputs with hysteresis Integrated bootstrap diode Operational amplifier for advanced current sensing Adjustable dead-time Interlocking function Compact and simplified layout Bill of material reduction Flexible, easy and fast design DIP-14 SO-14 ■ ■ ■ ■ ■ ■ ■ ■ ■ Description The L6392 is a high-voltage device, manufactured with the BCD “OFF-LINE" technology. It has a monolitich half-bridge gate driver for N-channel Power MOSFET or IGBT. The high side (floating) section is designed to stand a voltage rail up to 600 V. The logic inputs are CMOS/TTL compatible down to 3.3 V for easy of interfacing microcont roller/DSP The IC embeds an op amp suitable for advanced current sensing in applications such as field oriented motor control. Application Table 1. Device summary Order codes L6392 L6392D L6392D013TR Package DIP-14 SO-14 SO-14 Packaging Tube Tube Tape and reel March 2008 Rev 2 1/19 www.st.com 19 This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice. Contents L6392 Contents 1 2 3 4 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Pin connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Truth table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Electrical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 4.1 4.2 4.3 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Recommended operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 5 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 5.1 5.2 AC operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 DC operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 6 7 8 Waveforms definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Typical application diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Bootstrap driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 8.1 CBOOT selection and charging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 9 10 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 2/19 L6392 Block diagram 1 Block diagram Figure 1. Block diagram BOOTSTRAP DRIVER 4 UV DETECTION from LVG FLOATING STRUCTURE VCC 14 BOOT UV DETECTION HVG DRIVER HIN 3 LEVEL SHIFTER S R 13 HVG LOGIC 5V SHOOT THROUGH PREVENTION LIN 1 VCC LVG DRIVER 10 12 OUT LVG SD 2 GND 7 DT 5 DEAD TIME VCC OPOUT 6 OPAMP + - 8 9 OP+ OP- 3/19 Pin connection L6392 2 Pin connection Figure 2. Pins connection (top view) LIN SD HIN VCC DT OPOUT GND 1 2 3 4 5 6 7 14 13 12 11 10 9 8 BOOT HVG OUT NC LVG OPOP+ Table 2. Pin N# 1 2 3 4 5 6 7 8 9 10 11 12 13 14 Pin description Pin name LIN SD (1) Type I I I P I O P I I O Function Low side driver logic input (active low) Shut down logic input (active low) High side driver logic input (active high) Lower section supply voltage Dead time setting Opamp output Ground Opamp non inverting input Opamp inverting input Low side driver output Not connected HIN VCC DT OPOUT GND OP+ OPLVG (1) NC OUT HVG (1) P O P High side (floating) common voltage High side driver output Bootstrapped supply voltage BOOT 1. The circuit guarantees less than 1 V on the LVG and HVG pins (@ Isink = 10 mA), with VCC > 3 V. This allows to omitting the "bleeder" resistor connected between the gate and the source of the external MOSFET normally used to hold the pin low; the gate driver assures low impedance also in SD condition. 4/19 L6392 Truth table 3 Truth table Table 3. Truth table Inputs SD L H H H H LIN X L L H H HIN X L H L H LVG L H L L L Outputs HVG L L L L H Note: X: don’t care 5/19 Electrical data L6392 4 4.1 Electrical data Absolute maximum ratings Table 4. Symbol Vout VCC Vop+ VopVboot Vhvg VIvg Vi dVout/dt Ptot TJ Tstg Output voltage Supply voltage Opamp non-inverting input Opamp inverting input Floating supply voltage High side gate output voltage Low side gate output voltage Logic input voltage Allowed output slew rate Total power dissipation (TA= 85 °C) Junction temperature Storage temperature Absolute maximum rating Parameter Value Vboot -21 to Vboot +0.3 - 0.3 to + 21 -0.3 to VCC +0.3 -0.3 to VCC +0.3 VCC - 0.3 to 620 Vout - 0.3 to Vboot + 0.3 -0.3 to VCC + 0.3 -0.3 to 15 50 TBD 150 -50 to 150 Unit V V V V V V V V V/ns mW °C °C Note: ESD immunity for pins 12, 13 and 14 is guaranteed up to TBD (Human Body Model) 4.2 Thermal data Table 5. Symbol Rth(JA) Thermal data Parameter Thermal resistance junction to ambient SO-14 165 DIP-14 100 Unit °C/W 4.3 Recommended operating conditions Table 6. Symbol Vout VBS (2) Recommended operating conditions Pin 12 14 Parameter Output voltage (1) Floating supply voltage Switching frequency 4 Supply voltage Junction temperature (1) Test condition Min Max 580 Unit V V kHz V °C TBD HVG, LVG load CL = 1nF TBD -40 TBD 800 TBD 125 fsw VCC TJ 1. If the condition TBDV< Vboot - Vout < TBD V and Vboot < TBD V are guaranteed, Vout can range from TBD V to 580 V. 2. VBS = Vboot -Vout 6/19 L6392 Electrical characteristics 5 5.1 Table 7. Symbol ton toff tsd MT Electrical characteristics AC operation AC operation electrical characteristics (VCC = 15V; TJ =+25 °C) Pin Parameter Test condition Min Typ 125 125 125 40 Rdt=0; CL=1 nF; CDT =100 nF Rdt=37 kΩ;CL=1 nF;CDT=100 nF Rdt=136 kΩ;CL=1 nF;CDT=100 nF Rdt=260 kΩ;CL=1 nF;CDT=100 nF Rdt=0 Ω; CL=1 nF; CDT =100 nF Rdt=37 kΩ;CL=1 nF;CDT=100 nF Rdt=136 kΩ;CL=1 nF;CDT=100 nF Rdt=26 0kΩ;CL=1 nF;CDT=100 nF CL = 1 nF CL = 1 nF 75 35 0.15 0.5 1.5 2.8 60 TBD TBD TBD Max Unit ns ns ns ns µs µs µs µs ns ns ns ns ns ns High/low side driver turnVout = 0 V 1 vs 10 on propagation delay = Vcc V 3 vs 13 High/low side driver turn- boot CL = 1nF off propagation delay Vi = 0 to 3.3 V 2 vs Shut down to high/low See Figure 3 on page 7 10, 13 side propagation delay Delay matching, HS and LS turn-on/off dt 5 Dead time setting range MDT Matching dead time tr tf Rise time 10, 13 Fall time Figure 3. Timing characteristics LIN 50% 50% tr 90% 90% tf LVG ton 10% 10% toff HIN 50% 50% tr 90% 90% tf HVG ton 10% 10% toff SD 50% 50% tr 90% 10% 90% tf LVG/HVG ton 10% toff 7/19 Electrical characteristics L6392 5.2 Table 8. Symbol DC operation DC operation electrical characteristics (VCC = 15 V;TJ = +25 °C) Pin Parameter Test condition Min Typ Max Unit Low supply voltage section Vcc_hys Vcc_thON Vcc_thOFF Vcc UV hysteresis Vcc UV turn ON threshold Vcc UV turn OFF threshold VCC = 10 V SD = 5V; LIN = 5V; HIN = GND; RDT = 0 Ω; OP + = GND; OP - = 5 V VCC = 15 V SD = 5 V; LIN = 5 V; HIN = GND; RDT = 0 Ω; OP + = GND; OP - = 5 V 700 1400 11.8 10.4 mV V V Iqccu 4 Undervoltage quiescent supply current 110 150 µA Iqcc Quiescent current 680 1060 µA Bootstrapped supply voltage section VBS_hys VBS_thON VBS_thOFF 14 VBS UV hysteresis VBS UV turn ON threshold VBS UV turn OFF threshold Undervoltage VBS quiescent current VBS = 10 V SD = 5 V; LIN and HIN = 5 V; RDT = 0 Ω; OP + = GND; OP - = 5 V VBS = 15 V SD = 5 V; LIN and HIN = 5 V; RDT = 0 Ω; OP + = GND; OP - = 5 V 700 1400 11.6 10.2 mV V V IQBSU 70 110 µA IQBS VBS quiescent current 150 210 µA 8/19 L6392 Table 8. Symbol ILK Rdson Electrical characteristics DC operation electrical characteristics (VCC = 15 V;TJ = +25 °C) Pin Parameter High voltage leakage current Bootstrap driver on resistance (1) Test condition Vhvg = Vout = Vboot = 600 V LVG ON 120 Min Typ Max 10 Unit µA Ω Driving buffers section Iso 10, 13 Isi Logic inputs Vil 1, 2, 3 Vih IHINh 3 IHINl ILINh 1 ILINl ISDh 2 ISDl SD logic “0” input bias current SD = 0 V 1 µA LIN logic “0” input bias current SD logic “1” input bias current LIN = 15 V SD = 15 V 30 1 100 µA µA HIN logic “0” input bias current LIN logic “1” input bias current HIN = 0 V LIN = 0 V 6 1 40 µA µA High level logic threshold voltage HIN logic “1” input bias current HIN = 15 V 2.21 175 260 V µA Low level logic threshold voltage 0.83 V High/low side source short circuit current High/low side sink short circuit current Vi= Vih (tp < 10 ms) Vi= Vil (tp < 10 ms) 270 430 mA mA 1. RDSon is tested in the following way: RDSon = [(VCC - VCBOOT1) - (VCC - VCBOOT2)] / [I1(VCC,VCBOOT1) - I2(VCC,VCBOOT2)] where I1 is pin 16 current when VCBOOT = VCBOOT1, I2 when VCBOOT = VCBOOT2 9/19 Electrical characteristics L6392 Table 9. Symbol Vio Iib Vicm VOL VOH OPAMP characteristics (VCC = 15 V, TJ = +25 °C) Pin Parameter Input offset voltage 8, 9 Input bias current (1) Input common mode voltage range Output voltage swing - low level Output voltage swing - high level 6 Isink = 3.5 mA, RL = 2 kΩ Isource = 3.5 mA, RL = 2 kΩ Source, Vid = TBD; Vo = TBD Sink Vid = TBD; Vo = TBD Slew rate Gain bandwith product Large signal voltage gain Power supply rejection ratio Common mode rejection ratio vs Vcc 80 Vi = TBD; RL = 2 kΩ; CL = TBD; unity gain Vo = TBD; RL = 2 kΩ 85 13.5 16 50 2.5 0 180 14.3 30 80 3.8 TBD 95 85 100 Test condition VO = TBD; 0 < Vicm < VCC -TBD 15 Min Typ Max 3 200 VCC TBD 360 mV V mA mA V/µs MHz dB dB dB Unit mV nA Io Output short circuit current SR GBWP Avd SRV CMRR 1. The direction of input current is out of the IC. 10/19 L6392 Waveforms definitions 6 Figure 4. Waveforms definitions Dead time - timing waveforms LIN LVG HVG gate driver outputs OFF (HALF-BRIDGE TRI-STATE) INTE INTE CONTROL SIGNAL EDGES OVERLAPPED: INTERLOCKING + DEAD TIME HIN CKIN G RLO RLO CKIN G DT gate driver outputs OFF (HALF-BRIDGE TRI-STATE) LIN CONTROL SIGNALS EDGES SYNCHRONOUS (*): DEAD TIME HIN LVG DT HVG gate driver outputs OFF (HALF-BRIDGE TRI-STATE) gate driver outputs OFF (HALF-BRIDGE TRI-STATE) DT LIN CONTROL SIGNALS EDGES NOT OVERLAPPED, BUT INSIDE THE DEAD TIME: DEAD TIME HIN LVG DT HVG gate driver outputs OFF (HALF-BRIDGE TRI-STATE) gate driver outputs OFF (HALF-BRIDGE TRI-STATE) DT LIN CONTROL SIGNALS EDGES NOT OVERLAPPED, OUTSIDE THE DEAD TIME: DIRECT DRIVING HIN LVG DT HVG gate driver outputs OFF (HALF-BRIDGE TRI-STATE) gate driver outputs OFF (HALF-BRIDGE TRI-STATE) DT (*) HIN and LIN can be connected togheter and driven by just one control signal 11/19 Typical application diagram L6392 7 Figure 5. Typical application diagram Application diagram BOOTSTRAP DRIVER 4 UV DETECTION from LVG VCC FLOATING STRUCTURE 14 BOOT UV DETECTION HVG DRIVER H.V. 13 HVG Cboot HIN 3 LEVEL SHIFTER S R LOGIC 5V SHOOT THROUGH PREVENTION LIN 1 VCC LVG DRIVER 10 SD LATCH 12 OUT TO LOAD LVG SD 2 GND 7 DT 5 DEAD TIME OPAMP OPOUT 6 + - 8 9 OP+ OP- 12/19 L6392 Bootstrap driver 8 Bootstrap driver A bootstrap circuitry is needed to supply the high voltage section. This function is normally accomplished by a high voltage fast recovery diode (Figure 6 a). In the L6392 a patented integrated structure replaces the external diode. It is realized by a high voltage DMOS, driven synchronously with the low side driver (LVG), with diode in series, as shown in Figure 6 b. An internal charge pump (Figure 6 b) provides the DMOS driving voltage. 8.1 CBOOT selection and charging To choose the proper CBOOT value the external MOS can be seen as an equivalent capacitor. This capacitor CEXT is related to the MOS total gate charge: Q gate C EXT = ------------V gate The ratio between the capacitors CEXT and CBOOT is proportional to the cyclical voltage loss. It has to be: CBOOT >>> CEXT e.g.: if Qgate is 30 nC and Vgate is 10 V, CEXT is 3 nF. With CBOOT = 100 nF the drop would be 300 mV. If HVG has to be supplied for a long time, the CBOOT selection has to take into account also the leakage and quiescent losses. e.g.: HVG steady state consumption is lower than 200 µA, so if HVG TON is 5 ms, CBOOT has to supply 1 µC to CEXT. This charge on a 1µF capacitor means a voltage drop of 1 V. The internal bootstrap driver gives agreat advantage: the external fast recovery diode can be avoided (it usually has great leakage current). This structure can work only if VOUT is close to GND (or lower) and in the meanwhile the LVG is on. The charging time (Tcharge ) of the CBOOT is the time in which both conditions are fulfilled and it has to be long enough to charge the capacitor. The bootstrap driver introduces a voltage drop due to the DMOS RDSON (typical value: 120 Ω). At low frequency this drop can be neglected. Anyway increasing the frequency it must be taken in to account. The following equation is useful to compute the drop on the bootstrap DMOS: Q gate V drop = I ch arg e R dson → V drop = ------------------ R dson T ch arg e where Qgate is the gate charge of the external power MOS, Rdson is the on resistance of the bootstrap DMOS, and Tcharge is the charging time of the bootstrap capacitor. 13/19 Bootstrap driver For example: using a power MOS with a total gate charge of 30 nC the drop on the bootstrap DMOS is about 1 V, if the Tcharge is 5 µs. In fact: L6392 30nC V drop = -------------- ⋅ 120 Ω ∼ 0.7 V 5µs Vdrop has to be taken into account when the voltage drop on CBOOT is calculated: if this drop is too high, or the circuit topology doesn’t allow a sufficient charging time, an external diode can be used. Figure 6. Bootstrap driver DBOOT VS BOOT H.V. HVG VS BOOT H.V. HVG CBOOT VOUT TO LOAD CBOOT VOUT TO LOAD LVG LVG a b D99IN1067 14/19 L6392 Package mechanical data 9 Package mechanical data In order to meet environmental requirements, ST offers these devices in ECOPACK® packages. These packages have a lead-free second level interconnect . The category of second level interconnect is marked on the package and on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. ECOPACK is an ST trademark. ECOPACK specifications are available at: www.st.com 15/19 Package mechanical data Figure 7. DIP-14 mechanical data and package dimensions L6392 DIM. MIN. a1 B b b1 D E e e3 F I L Z 1.27 0.51 1.39 mm TYP. MAX. MIN. 0.020 1.65 0.5 0.25 20 8.5 2.54 15.24 7.1 5.1 3.3 2.54 0.050 0.055 inch TYP. MAX. OUTLINE AND MECHANICAL DATA 0.065 0.020 0.010 0.787 0.335 0.100 0.600 0.280 0.201 0.130 0.100 16/19 L6392 Figure 8. Package mechanical data SO-14 mechanical data and package dimensions mm DIM. MIN. A A1 A2 B C D (1) inch MAX. 1.75 0.30 1.65 0.51 0.25 8.75 4.0 MIN. 0.053 0.004 0.043 0.013 0.007 0.337 0.150 0.050 6.20 0.50 1.27 0.228 0.01 0.016 0.244 0.02 0.050 TYP. MAX. 0.069 0.012 0.065 0.020 0.01 0.344 0.157 TYP. OUTLINE AND MECHANICAL DATA 1.35 0.10 1.10 0.33 0.19 8.55 3.80 1.27 5.8 0.25 0.40 E e H h L k ddd 0° (min.), 8° (max.) 0.10 0.004 (1) “D” dimension does not include mold flash, protusions or gate burrs. Mold flash, protusions or gate burrs shall not exceed 0.15mm per side. SO-14 0016019 D 17/19 Revision history L6392 10 Revision history Table 10. Date 29-Feb-2008 18-Mar-2008 Document revision history Revision 1 2 Initial release Cover page updated Changes 18/19 L6392 Please Read Carefully: Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any time, without notice. All ST products are sold pursuant to ST’s terms and conditions of sale. Purchasers are solely responsible for the choice, selection and use of the ST products and services described herein, and ST assumes no liability whatsoever relating to the choice, selection or use of the ST products and services described herein. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted under this document. 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