L6393D

L6393 Half bridge gate driver Datasheet - production data Application  Motor driver for home appliances  Factory automation  Industrial drives and fans  HID ballasts 40

 Power supply units Features Description  High voltage rail up to 600 V  dV/dt immunity ± 50 V/nsec in full temperature range  Driver current capability: – 290 mA source, – 430 mA sink The high-side (floating) section is designed to stand a voltage rail up to 600 V.  Switching times 75/35 nsec rise/fall with 1 nF load  3.3 V, 5 V CMOS/TTL input comparators with hysteresis  Integrated bootstrap diode  Uncommitted comparator The L6393 is a high voltage device manufactured with the BCD™ “offline” technology. It is a single chip half bridge gate driver for the N-channel power MOSFET or IGBT. The logic inputs are CMOS/TTL compatible down to 3.3 V for the easy interfacing microcontroller/DSP. The IC embeds an uncommitted comparator available for protections against overcurrent, overtemperature, etc.  Adjustable deadtime  Compact and simplified layout  Bill of material reduction  Flexible, easy and fast design September 2015 This is information on a product in full production. DocID14497 Rev 5 1/19 www.st.com Contents L6393 Contents 1 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 2 Pin connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 3 Truth table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 4 Electrical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 5 4.1 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 4.2 Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 4.3 Recommended operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 5.1 AC operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 5.2 DC operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 6 Waveform definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 7 Typical application diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 8 Bootstrap driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 CBOOT selection and charging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 9 Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 SO-14 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 10 Order codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 11 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 2/19 DocID14497 Rev 5 L6393 Block diagram 1 Block diagram Figure 1. Block diagram %227675$3'5,9(5 9&&  )/2$7,1*6758&785(  %227 89 '(7(&7,21 IURP/9* 89 '(7(&7,21 +9* '5,9(5 3+$6(  /(9(/ 6+,)7(5 6  5 +9* /2*,&  %5$.(  6+227 7+528*+ 35(9(17,21 9&& 6' &3287 287 /9* '5,9(5 /9*    9 &203$5$725    &3 &3  '7  '($' 7,0(  *1' ".W DocID14497 Rev 5 3/19 19 Pin connection 2 L6393 Pin connection Figure 2. Pin connection (top view) 3+$6(   %227 6'   +9* %5$.(   287 9&&   1&  '7   /9* &3287   &3 *1'   &3 $0Y Table 1. Pin description Pin no. Pin name Type Function 1 PHASE I Driver logic input (active high) 2 SD(1) I Shutdown input (active low) 3 BRAKE I Driver logic input (active low) 4 VCC P Lower section supply voltage 5 DT I Deadtime setting 6 CPOUT O Comparator output (open drain) 7 GND P Ground 8 CP- I Comparator negative input 9 CP+ I Comparator positive input 10 LVG(1) O Low-side driver output 11 NC 12 OUT Not connected P High-side (floating) common voltage 13 HVG (1) O High-side driver output 14 BOOT P Bootstrapped supply voltage 1. The circuit provides less than 1 V on the LVG and HVG pins (at Isink = 10 mA), with VCC > 3 V. This allows omitting the “bleeder” resistor connected between the gate and the source of the external MOSFET normally used to hold the pin low; the gate driver assures low impedance also in SD condition. 4/19 DocID14497 Rev 5 L6393 3 Truth table Truth table Table 2. Truth table Inputs Outputs SD PHASE BRAKE LVG HVG L X(1) X(1) L L H L L H L H L H H L H H L H L H H H L H 1. X: don’t care. In the L6393 IC the two input signals PHASE and BRAKE are fed into an AND logic port and the resulting signal is in phase with the high-side output HVG and in opposition of phase with the low-side output LVG. This means that if BRAKE is kept to a high level, the PHASE signal drives the half bridge in phase with the HVG output and in opposition of phase with the LVG output. If BRAKE is set to a low level, the low-side output LVG is always ON and the high-side output HVG is always OFF, whatever the PHASE signal. This kind of logic interface provides the possibility to control the power stages using the PHASE signal to select the current direction in the bridge and the BRAKE signal to perform current slow decay on the low-sides. From the point of view of the logic operations the two signals PHASE and BRAKE are completely equivalent, that means the two signals can be exchanged without any change in the behavior on the resulting output signals (see Figure 1). Note: The deadtime between the turn-OFF of one power switch and the turn-ON of the other power switch is defined by the resistor connected between the DT pin and the ground. DocID14497 Rev 5 5/19 19 Electrical data L6393 4 Electrical data 4.1 Absolute maximum ratings Table 3. Absolute maximum ratings Value Symbol Unit Min. Max. VCC Supply voltage -0.3 21 V VOUT Output voltage VBOOT - 21 VBOOT + 0.3 V VBOOT Bootstrap voltage -0.3 620 V Vhvg High-side gate output voltage VOUT - 0.3 VBOOT + 0.3 V Vlvg Low-side gate output voltage -0.3 VCC + 0.3 V VCP+ Comparator positive input voltage -0.3 VCC + 0.3 V VCP- Comparator negative input voltage -0.3 VCC + 0.3 V Vi Logic input voltage -0.3 15 V Vod Open drain voltage -0.3 15 V Allowed output slew rate 50 V/ns Ptot Total power dissipation (TA = 25 °C) 800 mW TJ Junction temperature 150 °C TSTG Storage temperature 150 °C ESD Human body model dVOUT/dt 4.2 Parameter -50 2 kV Thermal data Table 4. Thermal data Symbol Rth(JA) 6/19 Parameter Thermal resistance junction to ambient max. DocID14497 Rev 5 SO-14 Unit 120 °C/W L6393 4.3 Electrical data Recommended operating conditions Table 5. Recommended operating conditions Symbol Pin VCC 4 VBO(1) 14 - 12 Parameter Test condition Min. Max. Unit Supply voltage 10 20 V Floating supply voltage 9.8 20 V 580 V (2) VOUT 12 DC output voltage VCP- 8 Comparator negative input voltage VCP+ 2.5 V VCC(3) V VCP+ 9 Comparator positive input voltage VCP- 2.5 V VCC(3) V fsw Switching frequency HVG, LVG load CL = 1 nF 800 kHz TJ Junction temperature 125 °C -9 -40 1. VBO = VBOOT - VOUT 2. LVG off. VCC = 10 V. Logic is operational if VBOOT > 5 V, refer to AN2785 for more details. 3. At least one of the comparator's input must be lower than 2.5 V to guarantee proper operation. DocID14497 Rev 5 7/19 19 Electrical characteristics L6393 5 Electrical characteristics 5.1 AC operation Table 6. AC operation electrical characteristics (VCC = 15 V, TJ = +25 °C) Symbol Pin Parameter Test condition Min. Typ. Max. Unit AC operation ton toff tsd 1, 3 vs. 10, 13 2 vs. 10, 13 MT DT 5 tf VOUT = 0 V VBOOT = VCC CL = 1 nF Shutdown to high/low-side V = 0 to 3.3 V i propagation delay see Figure 3 Delay matching, HS and LS turn-on/off High/low-side driver turnoff propagation delay Deadtime setting range(1) Matching deadtime (2) MDT tr High/low-side driver turnon propagation delay 10, 13 125 200 ns 50 125 200 ns 50 125 200 ns 30 ns RDT = 0, CL = 1 nF 0.1 0.18 0.25 RDT = 37 kΩ, CL = 1 nF, CDT = 100 nF 0.48 0.6 0.72 RDT = 136 kΩ, CL = 1 nF, CDT = 100 nF 1.35 1.6 1.85 RDT = 260 kΩ, CL = 1 nF, CDT = 100 nF 2.6 3.0 3.4 RDT = 0 Ω; CL = 1 nF 80 RDT = 37 kΩ; CL = 1 nF; CDT = 100 nF 120 RDT = 136 kΩ; CL = 1 nF; CDT = 100 nF 250 RDT = 260 kΩ; CL = 1 nF; CDT = 100 nF 400 μs ns Rise time CL = 1 nF 75 120 ns Fall time CL = 1 nF 35 70 ns 1. See Figure 4. 2. MDT = I DTLH - DTHL I see Figure 5 on page 12. 8/19 50 DocID14497 Rev 5 L6393 Electrical characteristics Figure 3. Timing PHASE IN 50% 50% BRAKE tr tf 90% 90% HVG 10% 10% ton PHASE IN toff 50% 50% BRAKE tf tr 90% 90% LVG 10% 10% ton toff 50% SD tf 90% LVG/HVG 10% tsd Figure 4. Typical deadtime vs. DT resistor value 3.5 3 Approximated formula for Rdt calculation (typ.): Rdt[kΩ] = 92.2 · DT[μs] - 16.6 DT (us) 2.5 2 1.5 1 0.5 0 0 50 100 150 200 250 300 Rdt (kOhm) DocID14497 Rev 5 9/19 19 Electrical characteristics 5.2 L6393 DC operation Table 7. DC operation electrical characteristics (VCC = 15 V; TJ = +25 °C) Symbol Pin Parameter Test condition Min. Typ. Max. Unit Low supply voltage section VCC_hys VCC UV hysteresis 1.2 1.5 1.8 VCC_thON VCC UV turn-ON threshold 9 9.5 10 VCC_thOFF VCC UV turn-OFF threshold 7.6 8 8.4 150 IQCCU 4 IQCC Undervoltage quiescent supply current VCC = 7 V; SD = 5 V; PHASE and BRAKE = GND; RDT = 0 ; CP + = GND; CP - = 0.5 V 110 Quiescent current VCC = 15 V; SD = 5 V; PHASE and BRAKE = GND; RDT = 0 ; CP + = GND; CP - = 0.5 V 600 1000 V V µA Bootstrapped supply voltage section(1) VBO_hys VBO UV hysteresis 0.8 1.0 1.2 V VBO_thON VBO UV turn-ON threshold 8.2 9 9.8 V VBO_thOFF VBO UV turn-OFF threshold 7.3 8 8.7 V 14 IQBOU IQBO ILK Undervoltage VBOOT quiescent current VBO = 7 V SD = 5 V; PHASE and BRAKE = 5 V; RDT = 0 ; CP + = GND; CP - = 0.5 V 40 100 VBOOT quiescent current VBO = 15 V SD = 5 V; PHASE and BRAKE = 5 V; RDT = 0 ; CP + = GND; CP - = 0.5 V 140 210 High voltage leakage current Bootstrap driver on resistance RDSon µA Vhvg = VOUT = VBOOT = 600 V (2) 10 LVG ON 120  Driving buffers section Iso 10, 13 Isi High/low-side source short-circuit current VIN = Vih (tp < 10 µs) 200 290 mA High/low-side sink short-circuit current VIN = Vil (tp < 10 µs) 250 430 mA Logic inputs Vil Vih 10/19 1, 2, 3 Low level logic threshold voltage 0.8 1.1 V High level logic threshold voltage 1.9 2.25 V DocID14497 Rev 5 L6393 Electrical characteristics Table 7. DC operation electrical characteristics (VCC = 15 V; TJ = +25 °C) (continued) Symbol IPHASEh IPHASEl IBRAKEh IBRAKEl ISDh ISDl Pin 1 3 2 Parameter Test condition PHASE logic “1” input bias current PHASE = 15 V Min. Typ. Max. Unit 20 40 100 PHASE logic “0” input bias current PHASE = 0 V BRAKE logic “1” input bias current BRAKE = 15 V 1 20 40 100 BRAKE logic “0” input bias current BRAKE = 0 V SD logic “1” input bias current SD = 15 V SD logic “0” input bias current SD = 0 V 1 10 30 µA 100 1 1. VBO = VBOOT - VOUT. 2. RDSon is tested in the following way: RDSon = [(VCC - VBOOT1) - (VCC - VBOOT2)] / [I1(VCC,VBOOT1) - I2(VCC,VBOOT2)] where I1 is the pin 14 current when VBOOT = VBOOT1, I2 when VBOOT = VBOOT2. Table 8. Sense comparator (VCC = 15 V, TJ = +25 °C)(1) Symbol Vio Iib Vol Pin 8, 9 6 td_comp SR 6 Parameter Test conditions Input offset voltage Min. Typ. Max. Unit -15 Input bias current VCP+ = 1 V Open drain low level output voltage Iod = - 3 mA Comparator delay Rpu = 100 k to 5 V; VCP- = 0.5 V 90 Slew rate CL = 180 pF, Rpu = 5 k 60 15 mV 1 µA 0.5 V 130 ns V/µs 1. The comparator is disabled when VCC is in UVLO condition. DocID14497 Rev 5 11/19 19 Waveform definition 6 L6393 Waveform definition Figure 5. Deadtime waveform definition PHASE BRAKE LVG DTLH DTLH DTHL HVG 12/19 DocID14497 Rev 5 DTHL L6393 Typical application diagram 7 Typical application diagram Figure 6. Application diagram %227675$3'5,9(5 9&&  89 '(7(&7,21 )/2$7,1*6758&785( IURP/9*  %227 89 '(7(&7,21 +9 +9* '5,9(5 3+$6(  /(9(/ 6+,)7(5 6  +9*  287 &ERRW 5 /2*,& %5$.(  6+227 7+528*+ 35(9(17,21 9&& 6' 72/2$' /9* '5,9(5 /9*   &3287  9 &203$5$725   &3  &3  '7  '($' 7,0( *1'  $0Y DocID14497 Rev 5 13/19 19 Bootstrap driver 8 L6393 Bootstrap driver A bootstrap circuitry is needed to supply the high voltage section. This function is normally accomplished by a high voltage fast recovery diode (Figure 7.a). In the L6393 device a patented integrated structure replaces the external diode. It is realized by a high voltage DMOS, driven synchronously with the low-side driver (LVG), with a diode in series, as shown in Figure 7.b. An internal charge pump (Figure 7.b) provides the DMOS driving voltage. CBOOT selection and charging To choose the proper CBOOT value the external MOSFET can be seen as an equivalent capacitor. This capacitor CEXT is related to the MOSFET total gate charge: Equation 1 Q gate C EXT = --------------V gate The ratio between the capacitors CEXT and CBOOT is proportional to the cyclical voltage loss. It has to be: C BOOT » C EXT E.g.: if Qgate is 30 nC and Vgate is 10 V, CEXT is 3 nF. With CBOOT = 100 nF the drop would be 300 mV. If HVG has to be supplied for a long time, the CBOOT selection has to take into account also the leakage and quiescent losses. E.g.: HVG steady state consumption is lower than 200 µA, so if HVG TON is 5 ms, CBOOT has to supply 1 µC to CEXT. This charge on a 1 µF capacitor means a voltage drop of 1 V. The internal bootstrap driver gives a great advantage: the external fast recovery diode can be avoided (it usually has a great leakage current). This structure can work only if VOUT is close to GND (or lower) and in the meanwhile the LVG is on. The charging time (Tcharge) of the CBOOT is the time in which both conditions are fulfilled and it has to be long enough to charge the capacitor. The bootstrap driver introduces a voltage drop due to the DMOS RDSon (typical value: 120 ). At low frequency this drop can be neglected. Anyway increasing the frequency it must be taken in to account. The following equation is useful to compute the drop on the bootstrap DMOS: Equation 2 Q gate V drop = I ch arg e R dson  V drop = -------------------R dson T ch arg e where Qgate is the gate charge of the external power MOSFET, RDSon is the on resistance of the bootstrap DMOS, and Tcharge is the charging time of the bootstrap capacitor. 14/19 DocID14497 Rev 5 L6393 Bootstrap driver For example: using a power MOSFET with a total gate charge of 30 nC the drop on the bootstrap DMOS is about 1 V, if the Tcharge is 5 µs. In fact: Equation 3 30nC V drop = ---------------  120  0.7V 5S Vdrop has to be taken into account when the voltage drop on CBOOT is calculated: if this drop is too high, or the circuit topology doesn’t allow a sufficient charging time, an external diode can be used. Figure 7. Bootstrap driver '%227 96 %227 %227 96 +9 +9 +9* &%227 +9* &%227 9287 9287 72/2$' 72/2$' /9* /9* D E $0Y DocID14497 Rev 5 15/19 19 Package information 9 L6393 Package information In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK® packages, depending on their level of environmental compliance. ECOPACK® specifications, grade definitions and product status are available at: www.st.com. ECOPACK® is an ST trademark. SO-14 package information Figure 8. SO-14 package outline 16/19 DocID14497 Rev 5 L6393 Package information Table 9. SO-14 package mechanical data Dimensions Symbol mm Min. Typ. A a1 inch Max. Min. Typ. 1.75 0.1 0.2 a2 Max. 0.068 0.003 0.007 1.65 0.064 b 0.35 0.46 0.013 0.018 b1 0.19 0.25 0.007 0.010 C 0.5 0.019 c1 45° (typ.) D 8.55 8.75 0.336 0.344 E 5.8 6.2 0.228 0.244 e 1.27 0.050 e3 7.62 0.300 F 3.8 4.0 0.149 0.157 G 4.6 5.3 0.181 0.208 L 0.5 1.27 0.019 0.050 M 0.68 S 0.026 8° (max.) Figure 9. SO-14 footprint 
   ". DocID14497 Rev 5 17/19 19 Order codes 10 L6393 Order codes Table 10. Order codes Order codes Package L6393D Tube SO-14 L6393DTR 11 Packaging Tape and reel Revision history Table 11. Document revision history Date Revision 03-Mar-2008 1 Initial release 18-Mar-2008 2 Cover page updated 17-Nov-2009 3 Updated: Cover page, Table 4 on page 6, Table 6 on page 7, Table 7 on page 8, Table 8 on page 10, Table 9 on page 11 11-Aug-2010 4 Updated: Table 1 on page 1, Table 5 on page 7 and Table 7 on page 10. 5 Removed DIP-14 package from the entire document. Updated Table 3 on page 6 (added ESD parameter and value, removed note below Table 3). Updated Table 4 on page 6 (updated Rth(JA) value). Updated Table 7 on page 10 (updated Vil and Vih parameters and values, updated note 2. below Table 7 - replaced VCBOOTx by VBOOTx ). Updated Table 8 on page 11 (added conditions to title and note 1.). Named and numbered Equation 1 on page 14, Equation 2 on page 14 and Equation 3 on page 15 . Updated Section 9 on page 16 (added/updated titles, reversed order of Figure 8 and Table 9, updated header of Table 9, added Figure 9). Updated Table 10 on page 18 (moved from page 1 to page 18, added and updated titles). Updated cross-references throughout document. Minor modifications throughout document. 18-Sep-2015 18/19 Changes DocID14497 Rev 5 L6393 IMPORTANT NOTICE – PLEASE READ CAREFULLY STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on ST products before placing orders. ST products are sold pursuant to ST’s terms and conditions of sale in place at the time of order acknowledgement. Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or the design of Purchasers’ products. No license, express or implied, to any intellectual property right is granted by ST herein. Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product. ST and the ST logo are trademarks of ST. All other product or service names are the property of their respective owners. Information in this document supersedes and replaces information previously supplied in any prior versions of this document. © 2015 STMicroelectronics – All rights reserved DocID14497 Rev 5 19/19 19