L6395D

L6395 High voltage high and low-side driver Datasheet - production data Applications  Motor driver for home appliances  Factory automation  Industrial drives and fans SO-8 Description The L6395 is a high voltage device manufactured with the BCD™ “offline” technology. It is a singlechip high and low-side gate driver for N-channel power MOSFETs or IGBTs. Features  High voltage rail up to 600 V  dV/dt immunity ± 50 V/ns in full temperature range  Driver current capability: – 290 mA source – 430 mA sink The high-side (floating) section is designed to stand a voltage rail up to 600 V. The logic inputs are CMOS/TTL compatible down to 3.3 V for the easy interfacing microcontroller/DSP.  Switching times 75/35 ns rise/fall with 1 nF load  3.3 V, 5 V TTL/CMOS inputs with hysteresis  Integrated bootstrap diode  Compact and simplified layout  Bill of material reduction  Effective fault protection  Flexible, easy and fast design September 2015 This is information on a product in full production. DocID024048 Rev 2 1/16 www.st.com Contents L6395 Contents 1 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 2 Pin connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 3 Truth table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 4 Electrical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 5 4.1 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 4.2 Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 4.3 Recommended operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 5.1 AC operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 5.2 DC operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 6 Typical application diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 7 Bootstrap driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 CBOOT selection and charging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 8 Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 SO-8 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 9 Order codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 10 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 2/16 DocID024048 Rev 2 L6395 1 Block diagram Block diagram Figure 1. Block diagram VCC BOOTSTRAP DRIVER 3 UV DETECTION from LVG FLOATING STRUCTURE HIN 1 BOOT UV DETECTION LEVEL SHIFTER LIN 8 S HVG DRIVER 7 R HVG LOGIC 6 2 VCC OUT LVG DRIVER LVG GND 4 5 AM16532v1 DocID024048 Rev 2 3/16 16 Pin connection 2 L6395 Pin connection Figure 2. Pin connection LIN 1 8 BOOT HIN 2 7 HVG VCC 3 6 OUT GND 4 5 LVG AM16533v1 Table 1. Pin description Pin Pin name Type Function 1 LIN I Low-side driver logic input (active high) 2 HIN I High-side driver logic input (active high) 3 VCC P Lower section supply voltage 4 GND P Ground O Low-side driver output 5 (1) LVG 6 OUT P High-side (floating) common voltage 7 HVG(1) O High-side driver output 8 BOOT P Bootstrapped supply voltage 1. The circuit guarantees less than 1 V on the LVG and HVG pins (at Isink = 10 mA), with VCC > 3 V. In this manner, the “bleeder”, resistor connected between the gate and the source of the external MOSFET normally used to hold the pin low, is omitted. 4/16 DocID024048 Rev 2 L6395 3 Truth table Truth table Table 2. Truth table Input Output LIN HIN LVG HVG L L L L L H L H H L H L H H H H DocID024048 Rev 2 5/16 16 Electrical data L6395 4 Electrical data 4.1 Absolute maximum ratings Table 3. Absolute maximum ratings Value Symbol Unit Min. Max. VCC Supply voltage - 0.3 21 V VOUT Output voltage VBOOT - 21 VBOOT + 0.3 V VBOOT Bootstrap voltage - 0.3 620 V Vhvg High-side gate output voltage VOUT - 0.3 VBOOT + 0.3 V Vlvg Low-side gate output voltage - 0.3 VCC + 0.3 V Logic input voltage - 0.3 15 V Allowed output slew rate 50 V/ns Ptot Total power dissipation (TA = 25 °C) 800 mW TJ Junction temperature 150 °C Tstg Storage temperature 150 °C ESD Human body model Vi dVOUT/dt 4.2 Parameter -50 2 kV Thermal data Table 4. Thermal data Symbol Rth(JA) 4.3 Parameter SO-8 Unit 150 °C/W Thermal resistance junction to ambient Recommended operating conditions Table 5. Recommended operating conditions Value Symbol Pin Parameter Test condition Max. Supply voltage 10 20 V VCC 3 VBO(1) 8-6 Floating supply voltage 9.4 20 V 6 voltage(1) -11(2) 580 V 800 kHz 125 °C VOUT Output fSW Switching frequency TJ Junction temperature HVG, LVG load CL = 1 nF 1. VBO = VBOOT - VOUT. 2. LVG off. VCC = 10 V. Logic is operational if VBOOT > 5 V. 6/16 Unit Min. DocID024048 Rev 2 -40 L6395 Electrical characteristics 5 Electrical characteristics 5.1 AC operation Table 6. AC operation electrical characteristics (VCC = 15 V; Tj = +25 °C) Value Symbol Pin Parameter Test condition Unit Min. Typ. Max. 1,2 vs. 5, 7 VOUT = 0 V High/low-side driver VBOOT = VCC turn-on CL = 1 nF propagation delay VIN = 0 to 3.3 V See Figure 3 50 125 200 ns toff 1,2 vs. 5, 7 VOUT = 0 V High/low-side driver VBOOT = VCC turn-off CL = 1 nF propagation delay VIN = 3.3 V to 0 See Figure 3 50 125 200 ns tr 5, 7 Rise time CL = 1 nF 75 120 ns tf 5, 7 Fall time CL = 1 nF 35 70 ns ton Figure 3. Timing LIN/HIN 50% 50% tr tf 90% LVG/HVG 90% 10% t on 10% t off AM16534v1 DocID024048 Rev 2 7/16 16 Electrical characteristics 5.2 L6395 DC operation (Vcc = 15 V; Tj = +25 °C) 1 Table 7. DC operation electrical characteristics Value Symbol Pin Parameter Test condition Unit Min. Typ. Max. Low supply voltage section VCC_hys 3 VCC UV hysteresis VCC_thON 3 VCC_thOFF 0.6 0.7 0.8 V VCC UV turn ON threshold 9 9.5 10 V 3 VCC UV turn OFF threshold 8.3 8.8 9.3 V Iqccu 3 Undervoltage quiescent supply current VCC = 7 V LIN = 5V; HIN = GND; 40 90 150 A Iqcc 3 Quiescent current VCC = 15 V LIN = 5 V; HIN = GND; 100 220 350 A Bootstrapped supply voltage section(1) VBO_hys 8 VBO UV hysteresis 0.5 0.6 0.7 V VBO_thON 8 VBO UV turn ON threshold 7.9 8.6 9.4 V VBO_thOFF 8 VBO UV turn OFF threshold 7.3 8 8.7 V IQBOU 8 Undervoltage VBO quiescent current VBO = 7 V LIN = GND; HIN = 5 V 10 30 60 A IQBO 8 VBO quiescent current VBO = 15 V LIN = GND; HIN = 5 V; 190 220 A ILK 8 High voltage leakage current Vhvg = VOUT = VBOOT = 600 V 10 A Bootstrap driver onresistance(2) LVG on RDS(on) 120  Driving buffer section Iso 5, 7 High/low-side source short-circuit current VIN = Vih (tp < 10 μs) 200 290 mA Isi 5, 7 High/low-side sink shortVIN = Vil (tp < 10 μs) circuit current 250 430 mA Logic inputs 8/16 Vil 1, 2 Low level logic threshold voltage 0.8 1.1 V Vih 1, 2 High level logic threshold voltage 1.9 2.25 V DocID024048 Rev 2 L6395 Electrical characteristics Table 7. DC operation electrical characteristics (continued) Value Symbol Pin Parameter Test condition Unit Min. Typ. Max. IHINh 2 HIN logic “1” input bias current HIN = 15 V IHINl 2 HIN logic “0” input bias current HIN = 0 V ILINh 1 LIN logic “1” input bias current LIN = 15 V ILINl 1 LIN logic “0” input bias current LIN = 0 V 10 10 40 40 100 A 1 A 100 A 1 A 1. VBO = VBOOT - VOUT. 2. RDS(on) is tested in the following way: RDS(on)= [(VCC - VBOOT1) - (VCC - VBOOT2)] / [I1(VCC,VBOOT1) I2(VCC,VBOOT2)] where I1 is the pin 8 current when VBOOT = VBOOT1, I2 when VBOOT = VBOOT2. DocID024048 Rev 2 9/16 16 Typical application diagram 6 L6395 Typical application diagram Figure 4. Application diagram BOOTSTRAP DRIVER VCC 3 FLOATING STRUCTURE from LVG UV DETECTION UV DETECTION S LEVEL SHIFTER FROM CONTROLLER LIN FROM CONTROLLER HIN 1 8 BOOT HVG DRIVER H.V. 7 HVG 6 OUT Cboot R LOGIC TO LOAD 2 VCC LVG DRIVER LVG 5 GND 4 AM16535v1 Figure 5. Application diagram for asymmetrical load driving Dboot BOOTSTRAP DRIVER VCC 3 UV DETECTION from LVG FLOATING STRUCTURE UV DETECTION LEVEL SHIFTER FROM CONTROLLER LIN 1 8 BOOT H.V. S HVG DRIVER 7 HVG 6 OUT Cboot R LOGIC LOAD 2 VCC LVG DRIVER GND 4 5 HIN LVG AM16536v1 10/16 DocID024048 Rev 2 L6395 7 Bootstrap driver Bootstrap driver A bootstrap circuitry is needed to supply the high voltage section. This function is normally accomplished using a high voltage fast recovery diode (Figure 6). In the L6395 device a patented integrated structure replaces the external diode. It is implemented using a high voltage DMOS, driven synchronously with the low-side driver (LVG), with a diode in series, as shown in Figure 7. An internal charge pump provides the DMOS driving voltage. CBOOT selection and charging To select the proper CBOOT value the external MOS can be seen as an equivalent capacitor. This capacitor CEXT is related to the MOS total gate charge: Equation 1 Q gate C EXT = --------------V gate The ratio between the capacitors CEXT and CBOOT is proportional to the cyclical voltage loss. It must be: Equation 2 C BOOT » C EXT E.g.: if Qgate is 30 nC and Vgate is 10 V, CEXT is 3 nF. With CBOOT = 100 nF the drop is 300 mV. If HVG needs to be supplied for an extended period, the CBOOT selection has to take into account also the leakage and quiescent losses. E.g.: HVG steady state consumption is lower than 220 A, so if HVG TON is 5 ms, CBOOT must supply 1.1 C to CEXT. This charge on a 1 F capacitor means a voltage drop of 1.1 V. The internal bootstrap driver offers some important advantages: the external fast recovery diode can be avoided (it usually has a high leakage current). This structure can work only if VOUT is close to GND (or lower) and, at the same time, the LVG is on. The charging time (Tcharge) of the CBOOT is the time in which both conditions are fulfilled and it has to be long enough to charge the capacitor. The bootstrap driver introduces a voltage drop due to the DMOS RDS(on) (typical value: 120 ). At low switching frequency, this drop can be neglected but, operating at high switching frequency, it should be taken into account. The following equation is useful to compute the drop on the bootstrap DMOS: Equation 3 Q gate V drop = I ch arg e  R DS  on   V drop = -------------------  R DS  on  T ch arg e where Qgate is the gate charge of the external power MOSFET, RDS(on) is the on-resistance of the bootstrap DMOS and Tcharge is the charging time of the bootstrap capacitor. DocID024048 Rev 2 11/16 16 Bootstrap driver L6395 For example: using a power MOSFET with a total gate charge of 30 nC, the drop on the bootstrap DMOS is about 1 V, if the Tcharge is 5 s. Equation 4 30 nc V drop = ------------  120  0.7V 5 s Vdrop must be taken into account when the voltage drop on CBOOT is calculated: whether this drop is too high, or the circuit topology does not allow a sufficient charging time, an external diode can be used. Figure 6. Bootstrap driver with high voltage fast recovery diode D BO O T VCC BO O T H .V. H VG C BO O T OUT TO LO AD LVG AM16537v1 Figure 7. Bootstrap driver with internal charge pump BO O T V CC H . V. H VG CBO O T OUT TO LO AD LVG AM16538v1 12/16 DocID024048 Rev 2 L6395 8 Package information Package information In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK® packages, depending on their level of environmental compliance. ECOPACK specifications, grade definitions and product status are available at: www.st.com. ECOPACK is an ST trademark. SO-8 package information Figure 8. SO-8 package outline 0016023_G_FU DocID024048 Rev 2 13/16 16 Package information L6395 Table 8. SO-8 package mechanical data Dimensions (mm) Symbol Min. Typ. A Max. 1.75 A1 0.10 A2 1.25 b 0.31 0.51 b1 0.28 0.48 c 0.10 0.25 c1 0.10 0.23 D 4.80 4.90 5.00 E 5.80 6.00 6.20 E1 3.80 3.90 4.00 e 0.25 1.27 h 0.25 0.50 L 0.40 1.27 L1 1.04 L2 0.25 k 0° ccc 8° 0.10 Figure 9. SO-8 footprint Footprint_0016023_G_FU 14/16 DocID024048 Rev 2 L6395 9 Order codes Order codes Table 9. Order codes 10 Order codes Package Packaging L6395D SO-8 Tube L6395DTR SO-8 Tape and reel Revision history Table 10. Document revision history Date Revision 20-Mar-2013 1 Initial release. 2 Updated Table 4 on page 6 (added ESD parameter and value). Updated note 2. below Table 7 on page 8 (replaced VCBOOTx by VBOOTx ). Updated Section 8 on page 13. Moved Table 9 on page 15 (moved from page 1 to page 15, updated/added titles). Minor modifications throughout document. 11-Sep-2015 Changes DocID024048 Rev 2 15/16 16 L6395 IMPORTANT NOTICE – PLEASE READ CAREFULLY STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on ST products before placing orders. ST products are sold pursuant to ST’s terms and conditions of sale in place at the time of order acknowledgement. Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or the design of Purchasers’ products. No license, express or implied, to any intellectual property right is granted by ST herein. Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product. ST and the ST logo are trademarks of ST. All other product or service names are the property of their respective owners. Information in this document supersedes and replaces information previously supplied in any prior versions of this document. © 2015 STMicroelectronics – All rights reserved 16/16 DocID024048 Rev 2