L6482H

L6482 Microstepping motor controller with motion engine and SPI Datasheet - production data Applications  Bipolar stepper motor Description The L6482 device, realized in analog mixed signal technology, is an advanced fully integrated solution suitable for driving two-phase bipolar stepper motors with microstepping. HTSSOP38 Features  Operating voltage: 7.5 V - 85 V  Dual full bridge gate driver for N-channel MOSFETs  Fully programmable gate driving  Embedded Miller clamp function  Programmable speed profile  Up to 1/16 microstepping  Advanced current control with auto-adaptive decay mode  Integrated voltage regulators  SPI interface  Low quiescent standby currents  Programmable non dissipative overcurrent protection It integrates a dual full bridge gate driver for N-channel MOSFET power stages with embedded non dissipative overcurrent protection. Thanks to a new current control, a 1/16 microstepping is achieved through an adaptive decay mode which outperforms traditional implementations. The digital control core can generate user defined motion profiles with acceleration, deceleration, speed or target position easily programmed through a dedicated register set. All application commands and data registers, including those used to set analog values (i.e. current protection trip point, deadtime, PWM frequency, etc.) are sent through a standard 5-Mbit/s SPI. A very rich set of protections (thermal, low bus voltage, overcurrent and motor stall) makes the L6482 device “bullet proof”, as required by the most demanding motor control applications.  Overtemperature protection Table 1. Device summary Order code Package Packaging L6482H HTSSOP38 Tube L6482HTR HTSSOP38 Tape and reel March 2015 This is information on a product in full production. DocID023768 Rev 6 1/73 www.st.com Contents L6482 Contents 1 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2 Electrical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2.1 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2.2 Recommended operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 2.3 Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 3 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 4 Pin connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Pin list . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 5 Typical applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 6 Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 6.1 Device power-up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 6.2 Logic I/O . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 6.3 Charge pump . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 6.4 Microstepping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Automatic Full-step and Boost modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 6.5 Absolute position counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 6.6 Programmable speed profiles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 6.7 Motor control commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 6.8 6.9 2/73 6.7.1 Constant speed commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 6.7.2 Positioning commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 6.7.3 Motion commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 6.7.4 Stop commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 6.7.5 Step-clock mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 6.7.6 GoUntil and ReleaseSW commands . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Internal oscillator and oscillator driver . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 6.8.1 Internal oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 6.8.2 External clock source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Overcurrent detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 DocID023768 Rev 6 L6482 7 Contents 6.10 Undervoltage lockout (UVLO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 6.11 VS undervoltage lockout (UVLO_ADC) . . . . . . . . . . . . . . . . . . . . . . . . . . 29 6.12 Thermal warning and thermal shutdown . . . . . . . . . . . . . . . . . . . . . . . . . 29 6.13 Reset and standby . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 6.14 External switch (SW pin) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 6.15 Programmable gate drivers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 6.16 Deadtime and blanking time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 6.17 Integrated analog-to-digital converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 6.18 Supply management and internal voltage regulators . . . . . . . . . . . . . . . . 33 6.19 BUSY/SYNC pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 6.20 FLAG pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Phase current control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 7.1 Predictive current control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 7.2 Auto-adjusted decay mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 7.3 Auto-adjusted fast decay during the falling steps . . . . . . . . . . . . . . . . . . . 38 7.4 Torque regulation (output current amplitude regulation) . . . . . . . . . . . . . . 39 8 Serial interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 9 Programming manual . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 9.1 Register and flag description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 9.1.1 ABS_POS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 9.1.2 EL_POS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 9.1.3 MARK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 9.1.4 SPEED . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 9.1.5 ACC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 9.1.6 DEC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 9.1.7 MAX_SPEED . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 9.1.8 MIN_SPEED . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 9.1.9 FS_SPD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 9.1.10 TVAL_HOLD, TVAL_RUN, TVAL_ACC and TVAL_DEC . . . . . . . . . . . . 47 9.1.11 T_FAST . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 9.1.12 TON_MIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 9.1.13 TOFF_MIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 9.1.14 ADC_OUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 DocID023768 Rev 6 3/73 73 Contents L6482 9.2 10 9.1.15 OCD_TH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 9.1.16 STEP_MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 9.1.17 ALARM_EN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 9.1.18 GATECFG1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 9.1.19 GATECFG2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 9.1.20 CONFIG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 9.1.21 STATUS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 Application commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 9.2.1 Command management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 9.2.2 Nop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 9.2.3 SetParam (PARAM, VALUE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 9.2.4 GetParam (PARAM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 9.2.5 Run (DIR, SPD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 9.2.6 StepClock (DIR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 9.2.7 Move (DIR, N_STEP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 9.2.8 GoTo (ABS_POS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 9.2.9 GoTo_DIR (DIR, ABS_POS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 9.2.10 GoUntil (ACT, DIR, SPD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 9.2.11 ReleaseSW (ACT, DIR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 9.2.12 GoHome . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 9.2.13 GoMark . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 9.2.14 ResetPos . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 9.2.15 ResetDevice . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 9.2.16 SoftStop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 9.2.17 HardStop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 9.2.18 SoftHiZ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 9.2.19 HardHiZ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 9.2.20 GetStatus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 HTSSOP38 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 11 4/73 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 DocID023768 Rev 6 L6482 List of tables List of tables Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 11. Table 12. Table 13. Table 14. Table 15. Table 16. Table 17. Table 18. Table 19. Table 20. Table 21. Table 22. Table 23. Table 24. Table 25. Table 26. Table 27. Table 28. Table 29. Table 30. Table 31. Table 32. Table 33. Table 34. Table 35. Table 36. Table 37. Table 38. Table 39. Table 40. Table 41. Table 42. Table 43. Table 44. Table 45. Table 46. Table 47. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Recommended operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Thermal data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Typical application values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 CL values according to external oscillator frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 UVLO thresholds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Thermal protection summarizing table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 EL_POS register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 MIN_SPEED register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 FS_SPD register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 Torque regulation by TVAL_HOLD, TVAL_ACC, TVAL_DEC and TVAL_RUN registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 FS_SPD register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 Maximum fast decay times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 Minimum on-time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 Minimum off-time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 ADC_OUT value and torque regulation feature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 Overcurrent detection threshold . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 STEP_MODE register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 Step mode selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 SYNC output frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 SYNC signal source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 ALARM_EN register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 GATECFG1 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 IGATE parameter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 TCC parameter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 TBOOST parameter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 GATECFG2 register (voltage mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 TDT parameter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 TBLANK parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 CONFIG register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 Oscillator management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 External switch HardStop interrupt mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 Overcurrent event . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 Programmable VCC regulator output voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 Programmable UVLO thresholds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 External torque regulation enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 Switching period . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 Motor supply voltage compensation enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 STATUS register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 STATUS register TH_STATUS bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 STATUS register DIR bit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 STATUS register MOT_STATUS bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 Application commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 DocID023768 Rev 6 5/73 73 List of tables Table 48. Table 49. Table 50. Table 51. Table 52. Table 53. Table 54. Table 55. Table 56. Table 57. Table 58. Table 59. Table 60. Table 61. Table 62. Table 63. Table 64. Table 65. Table 66. Table 67. Table 68. 6/73 L6482 Nop command structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 SetParam command structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 GetParam command structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 Run command structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 StepClock command structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 Move command structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 GoTo command structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 GoTo_DIR command structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 GoUntil command structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 ReleaseSW command structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 GoHome command structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 GoMark command structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 ResetPos command structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 ResetDevice command structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 SoftStop command structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 HardStop command structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 SoftHiZ command structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 HardHiZ command structure. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 GetStatus command structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 HTSSOP38 package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 DocID023768 Rev 6 L6482 List of figures List of figures Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Figure 10. Figure 11. Figure 12. Figure 13. Figure 14. Figure 15. Figure 16. Figure 17. Figure 18. Figure 19. Figure 20. Figure 21. Figure 22. Figure 23. Figure 24. Figure 25. Figure 26. Figure 27. Figure 28. Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Pin connection (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Typical application schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Charge pump circuitry. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Normal mode and microstepping (16 microsteps) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Automatic Full-step switching in Normal mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Automatic Full-step switching in Boost mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Constant speed command examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Positioning command examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Motion command examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 OSCIN and OSCOUT pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Overcurrent detection - principle scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 External switch connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Gate driving currents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Device supply pin management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Predictive current control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Non-predictive current control. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Adaptive decay - fast decay tuning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Adaptive decay - switch from normal to slow + fast decay mode and vice versa . . . . . . . . 38 Fast decay tuning during the falling steps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Current sensing and reference voltage generation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 SPI timings diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 Daisy chain configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 Command with 3-byte argument . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 Command with 3-byte response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 Command response aborted . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 HTSSOP38 package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 HTSSOP38 footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 DocID023768 Rev 6 7/73 73 Block diagram 1 L6482 Block diagram Figure 1. Block diagram VSREG Voltage reg. ADC ADCIN VCC VCC REG VCC Voltage reg. VREG VREG CP VBOOT Charge pump VS Vboot HVGA1 VCC Temperature sensing OUTA1 LVGA1 Vboot Vdd VDD HVGA2 VCC CS SDO SPI CK OUTA2 LVGA2 CORE LOGIC VSENSEA SDI Vboot STBY/RESET HVB1 VCC Current sensing FLAG OUTB1 LVGB1 Vboot BUSY/SYNC 16 MHz Oscillator HVGB2 VCC OUTB2 STCK LVGB2 Ext. Osc. driver & Clock gen. SW DGND AGND OSCIN OSCOUT VSENSEB PGND AM15031v1 8/73 DocID023768 Rev 6 L6482 Electrical data 2 Electrical data 2.1 Absolute maximum ratings Table 2. Absolute maximum ratings Symbol Test condition Value Unit V VDD Logic interface supply voltage 5.5 VREG Logic supply voltage 3.6 VS Motor supply voltage 95 V Low-side gate driver supply voltage 18 V Boot voltage 100 V 0 to 20 V VCC VBOOT VBOOT High-side gate driver supply voltage (VBOOT - VS) VSREG Internal VCC regulator supply voltage 95 V VCCREG Internal VREG regulator supply voltage 18 V DC -5 to VBOOT V AC -15 to VBOOT VOUT1A VOUT2A VOUT1B VOUT2B SRout VHVG1A VHVG2A VHVG1B VHVG2B VHVG1A VHVG2A VHVG1B VHVG2B VLVG1A VLVG2A VLVG1B VLVG2B IGATE-CLAMP Full bridge output voltage Full bridge output slew rate (10% - 90%) High-side output driver voltage High-side output driver to respective bridge output voltage(VHVG - VOUT) Low-side output driver voltage High-side gate voltage clamp current capability VADCIN Integrated ADC input voltage range (ADCIN pin) Vout_diff Differential voltage between VBOOT, VS, OUT1A, OUT2A, PGND and VBOOT, VS, OUT1B, OUT2B, PGND pins Vin Ts TOP Ptot 1. Parameter Logic inputs voltage range Storage and operating junction temperature Total power dissipation (Tamb = 25 ºC) (1) 10 V/ns VOUT to VBOOT V 15 V VCC + 0.3 V 100 mA -0.3 to 3.6 V 100 V -0.3 to 5.5 V -40 to 150 °C 4 W HTSSOP38 mounted on a four-layer FR4 PCB with a dissipating copper surface of about 30 cm2. DocID023768 Rev 6 9/73 73 Electrical data 2.2 L6482 Recommended operating conditions Table 3. Recommended operating conditions Symbol Parameter VDD Logic interface supply voltage VREG Logic supply voltage VS Motor supply voltage VSREG VCC VCCREG VADC 2.3 Test condition Min. 3.3 V logic outputs Typ. Max. 3.3 5 V logic outputs Unit V 5 3.3 V VSREG 85 V Internal VCC voltage regulator VCC voltage internally generated VCC +3 Vs V Gate driver supply voltage VCC voltage imposed by external source (VSREG = VCC) 7.5 15 V Internal VREG voltage regulator supply voltage VREG voltage internally generated 6.3 VCC V 0 VREG V Integrated ADC input voltage (ADCIN pin) Thermal data Table 4. Thermal data Symbol Rthj-a Parameter Package Thermal resistance junction to ambient HTSSOP38(1) 1. HTSSOP38 mounted on a four-layer FR4 PCB with a dissipating copper surface of about 30 10/73 DocID023768 Rev 6 cm2. Typ. Unit 31 °C/W L6482 3 Electrical characteristics Electrical characteristics VS = 48 V; VCC = 7.5 V; Tj = 25 °C, unless otherwise specified. Table 5. Electrical characteristics Symbol Parameter Test condition Min. Typ. Max. Unit 9.9 10.4 10.9 V 6.5 6.9 7.3 V 9.5 10 10.5 V UVLO_VAL set low 5.9 6.3 6.7 V UVLO_VAL set high(1) General VCCthOn VCCthOff UVLO_VAL set high(1) VCC UVLO turn-on threshold (1) UVLO_VAL set low UVLO_VAL set VCC UVLO turn-off threshold (1) VBOOTthOn VBOOT - VS UVLO turn-on threshold VBOOTthOff VBOOT - VS UVLO turn-off threshold VREGthOn VREGthOff high(1) 8.6 9.2 9.8 V UVLO_VAL set low(1) 5.7 6 6.3 V UVLO_VAL set high(1) 8.2 8.8 9.5 V UVLO_VAL set low(1) 5.3 5.5 5.8 V VREG turn-on threshold (1) 2.8 3 3.18 V VREG turn-off threshold (1) 2.2 2.4 2.5 V IVREGqu Undervoltage VREG quiescent supply current VCCREG = VREG < 2.2 V 40 A IVREGq Quiescent VSREG supply current VCCREG = VREG = 3.3 V, internal oscillator selected(1) 3.8 mA IVSREGq Quiescent VSREG supply current VCCREG = VREG = 15 V 6.5 mA Thermal protection Tj(WRN)Set Thermal warning temperature 135 °C Tj(WRN)Rec Thermal warning recovery temperature 125 °C Tj(OFF)Set Thermal bridge shutdown temperature 155 °C Tj(OFF)Rec Thermal bridge shutdown recovery temperature 145 °C Tj(SD)Set Thermal device shutdown temperature 170 °C Tj(SD)Rec Thermal device shutdown recovery temperature 130 °C Voltage swing for charge pump oscillator VCC V fpump,min Minimum charge pump oscillator frequency(2) 660 kHz fpump,max Maximum charge pump oscillator frequency(2) 800 kHz Charge pump Vpump DocID023768 Rev 6 11/73 73 Electrical characteristics L6482 Table 5. Electrical characteristics (continued) Symbol Parameter RpumpHS Charge pump high-side RDS(on) resistance 10  RpumpLS Charge pump low-side RDS(ON) resistance 10  Average boot current 2.6 mA Iboot Test condition Min. Typ. Max. Unit Gate driver outputs IGATE,Sink Programmable high-side and low-side gate sink current Programmable high-side and low-side IGATE,Source gate source current IOB VS = 38 V VHVGX - VOUTX > 3 V VLVGX > 3 V VS = 38 V VBOOTX - VHVGX > 3.5 V VCC-VLVGX > 3.5 V High-side and low-side turn-off overboost gate current 2.4 4 5.6 5.4 8 10.6 11.3 16 20.7 17.3 24 30.7 23.2 32 40.8 50.2 64 77.8 81 96 113 2.8 4 5.2 5.8 8 10.2 12 16 20 18 24 30 24 32 40 51 64 77 82 96 112 85 103 117 mA mA mA RCLAMP(LS) Low-side gate driver Miller clamp resistance 6.5 10  RCLAMP(HS) High-side gate driver Miller clamp resistance 3 10  VGATE-CLAMP High-side gate voltage clamp tcc Programmable constant gate current time(2) tOB Programmable. Turn-off overboost; gate current time(2) IDSS tr 12/73 Leakage current Rise time IGATE-CLAMP = 100 mA 16.7 TCC = ’00000’ 125 TCC = 11111 3750 TBOOST = ’001’, internal oscillator 62.5 TBOOST =’111’ 1000 OUT = VS OUT = GND IGATE = 96 mA VCC = 15 V CGATE = 15 nF DocID023768 Rev 6 v ns ns 100 A A -100 2.5 s L6482 Electrical characteristics Table 5. Electrical characteristics (continued) Symbol tf SRgate Parameter Test condition Min. Typ. Max. Unit Fall time IGATE = 96 mA VCC = 15 V CGATE = 15 nF 2.5 s Gate driver output slew rate IGATE = 96 mA VCC = 15 V CGATE = 15 nF 6 V/s TDT = '00000' 125 TDT = ’11111’ 4000 TBLANK = '000' 125 TBLANK = ’111’ 1000 Deadtime and blanking tDT tblank Programmable deadtime(2) Programmable blanking time(2) ns ns Logic VIL Low level logic input voltage VIH High level logic input voltage IIH High level logic input current VIN = 5 V, VDDIO = 5 V IIL Low level logic input current VIN = 0 V, VDDIO = 5 V VOL Low level logic output voltage(3) VOH High level logic output voltage 0.8 2 V 1 -1 0.3 VDD = 5 V, IOL = 4 mA 0.3 2.4 VDD = 5 V, IOH = 4 mA 4.7 µA µA VDD = 3.3 V, IOL = 4 mA VDD = 3.3 V, IOH = 4 mA V V V RPUCS CS pull-up resistor 430 RPDRST STBY/RESET pull-down resistor 450 RPUSW SW pull-up resistor 80 k thigh,STCK Step-clock input high time 300 ns tlow,STCK Step-clock input low time 300 ns Internal oscillator and external oscillator driver fosc,int Internal oscillator frequency fosc,ext Programmable external oscillator frequency Tj = 25 °C -5% 16 8 +5% MHz 32 MHz VOSCOUTH OSCOUT clock source high level voltage Internal oscillator VOSCOUTL OSCOUT clock source low level voltage Internal oscillator 0.3 V trOSCOUT tfOSCOUT OSCOUT clock source rise and fall time Internal oscillator 10 ns thigh OSCOUT clock source high time Internal oscillator DocID023768 Rev 6 2.4 V 31.25 ns 13/73 73 Electrical characteristics L6482 Table 5. Electrical characteristics (continued) Symbol Parameter Test condition textosc Internal to external oscillator switching delay tintosc External to internal oscillator switching delay Min. Typ. Max. Unit 3 ms 100 µs SPI fCK,MAX Maximum SPI clock frequency(4) 5 MHz trCK tfCK SPI clock rise and fall time(4) thCK tlCK SPI clock high and low time(4) 90 ns Chip select setup time(4) 30 ns 30 ns 625 ns 20 ns 30 ns tsetCS tholCS Chip select hold time (4) time(4) tdisCS Deselect tsetSDI Data input setup time(4) tholSDI tenSDO tdisSDO tvSDO tholSDO 1 Data input hold time(4) µs Data output enable time(4) 95 ns Data output disable time(4) 95 ns 35 ns Data output valid time(4) Data output hold time(4) 0 ns Current control VREF, max Maximum reference voltage 1000 mV VREF, min Minimum reference voltage 7.8 mV Overcurrent protection VOCD Programmable overcurrent detection voltage VDS threshold OCD_TH = ‘11111’ 800 1000 1100 mV OCD_TH = ‘00000’ 27 31 35 mV OCD_TH = ‘01001’ 270 312.5 344 mV OCD_TH = ‘10011’ 500 625 688 mV tOCD,Comp OCD comparator delay 100 200 ns tOCD,Flag OCD to flag signal delay time 230 530 ns tOCD,SD OCD to shutdown delay time 400 630 ns 14/73 OCD_TH = '11111' OCD event to 90% of gate voltage DocID023768 Rev 6 L6482 Electrical characteristics Table 5. Electrical characteristics (continued) Symbol Parameter Test condition Min. Typ. Max. Unit Standby ISTBY Standby mode supply current (VSREG pin) ISTBY,vreg Standby mode supply current (VREG pin) tSTBY,min tlogicwu tcpwu VCC = VCCREG = 7.5 V VSREG = 48 V 42 VCC = VCCREG = 7.5 V VSREG = 18 V 37.5 µA 6 µA Minimum standby time 0.5 ms Logic power-on and wake-up time 500 µs 1 ms 7.3 7.5 V 4 15 Power bridges disabled, Charge pump power-on and wake-up time Cp = 10 nF, Cboot = 220 nF, VCC= 15 V Internal voltage regulators VCCOUT Internal VCC voltage regulator output voltage VCCREG, drop VSREG to VCC dropout voltage PCC Low (default), ICC = 10 mA High, ICC = 10 mA ICC = 50 mA Internal VCC voltage regulator power dissipation 3 V 2.5 W Internal VREG voltage regulator output voltage IREG = 10 mA VCCREG to VREG dropout voltage IREG = 50 mA Internal VREG voltage regulator output current VREG pin shorted to ground 125 mA IREGOUT,STB Internal VREG voltage regulator output standby current Y VREG pin shorted to ground 55 mA VREGOUT VSREG, drop IREGOUT PREG 3.13 5 3.3 V 3 Internal VREG voltage regulator power dissipation 0.5 V W Integrated analog-to-digital converter NADC Analog-to-digital converter resolution 5 bit VADC,ref Analog-to-digital converter reference voltage 3.3 V fS Analog-to-digital converter sampling frequency fOSC/512 kHz VADC,UVLO (2) ADCIN UVLO threshold 1.05 1.16 1.35 V 1. Guaranteed in the temperature range -25 to 125 °C. 2. The value accuracy is dependent on oscillator frequency accuracy (Section 6.8 on page 26). 3. FLAG and BUSY open drain outputs included. 4. See Figure 22 on page 41. DocID023768 Rev 6 15/73 73 Pin connection 4 L6482 Pin connection Figure 2. Pin connection (top view) LVGA1 1 38 LVGA2 OUTA1 2 37 OUTA2 HVGA1 3 NC 4 EPAD ADCIN 5 36 HVGA2 35 SENSEA 34 STBY/RESET 33 SW VS 6 VBOOT 7 32 STCK PGND 8 31 FLAG 30 BUSY/SYNC CP 9 VCC 10 29 DGND VCCREG 11 28 SDO VSREG 12 27 VDDIO VREG 13 26 SDI OSCIN 14 25 CK OSCOUT 15 24 CS AGND 16 23 SENSEB HVGB1 17 22 HVGB2 OUTB1 18 21 OUTB2 LVGB1 19 20 LVGB2 AM15032v1 Pin list Table 6. Pin description No. Name 11 VCCREG Power supply Internal VREG voltage regulator supply voltage 13 VREG Power supply Logic supply voltage 27 VDD Power supply Logic interface supply voltage 12 VSREG Power supply Internal VCC voltage regulator supply voltage 10 VCC Power supply Gate driver supply voltage 14 OSCIN Analog input Oscillator pin1. To connect an external oscillator or clock source. 15 OSCOUT Analog output Oscillator pin2. To connect an external oscillator. When the internal oscillator is used, this pin can supply a 2/4/8/16 MHz clock. 9 CP Output Charge pump oscillator output 7 VBOOT Power supply Bootstrap voltage needed for driving the high-side power DMOS of both bridges (A and B). 5 ADCIN Analog input Internal analog-to-digital converter input 6 VS Power supply Motor voltage 16/73 Type Function DocID023768 Rev 6 L6482 Pin connection Table 6. Pin description (continued) No. Name Type Function 3 HVGA1 Power output High-side half-bridge A1 gate driver output 36 HVGA2 Power output High-side half-bridge A2 gate driver output 17 HVGB1 Power output High-side half-bridge B1 gate driver output 22 HVGB2 Power output High-side half-bridge B2 gate driver output 1 LVGA1 Power output Low-side half-bridge A1 gate driver output 38 LVGA2 Power output Low-side half-bridge A2 gate driver output 19 LVGB1 Power output Low-side half-bridge B1 gate driver output 20 LVGB2 Power output Low-side half-bridge B2 gate driver output 8 PGND Ground Power ground pins. They must be connected to other ground pins 35 SENSEA Analog input Phase A current sensing input 23 SENSEB Analog input Phase B current sensing input 2 OUTA1 Power input Full bridge A output 1 37 OUTA2 Power input Full bridge A output 2 18 OUTB1 Power input Full bridge B output 1 21 OUTB2 Power input Full bridge B output 2 16 AGND Ground Analog ground. It must be connected to other ground pins 33 SW Logical input External switch input pin 29 DGND Ground Digital ground. It must be connected to other ground pins 28 SDO Logical output Data output pin for serial interface 26 SDI Logical input Data input pin for serial interface 25 CK Logical input Serial interface clock 24 CS Logical input Chip select input pin for serial interface 30 By default, the BUSY / SYNC pin is forced low when the device is performing a command. BUSY/SYNC Open drain output The pin can be programmed in order to generate a synchronization signal. 31 FLAG Status flag pin. An internal open drain transistor can pull the pin to GND when a programmed alarm condition occurs (step loss, OCD, Open drain output thermal pre-warning or shutdown, UVLO, wrong command, nonperformable command). 34 STBY RESET Logical input Standby and reset pin. LOW logic level puts the device in Standby mode and reset logic. If not used, it should be connected to VREG. 32 STCK Logical input Step-clock input EPAD Exposed pad Ground Exposed pad. It must be connected to other ground pins. DocID023768 Rev 6 17/73 73 Typical applications 5 L6482 Typical applications Table 7. Typical application values Name Value CVSPOL 220 µF CVS 220 nF CBOOT 470 nF CFLY 47 nF CVSREG 100 nF CVCC 470 nF CVCCREG 100 nF CVREG 100 nF CVREGPOL 22 µF CVDD 100 nF D1 Charge pump diodes Q1, Q2, Q3, Q4, Q5, Q6, Q7, Q8 STD25N10F7 RPU 39 k RSENSE 0.2  (maximum phase current 5 A) Figure 3. Typical application schematic V S (10.5V - 85V ) CBOO T C VREG CVDD R PU VREG VDD R PU C C VS VSPOL D1 CVREGPOL C VCCREG CVSREG CVCC VCCREG VCC VSREG VS Analog signal CFLY CP VBOOT ADCIN FLAG HVGA1 OUTA1 L VGA1 BUSY/SYNC STBY/RESET STCK Q1 Q2 Q3 Q4 Q5 Q6 Q7 Q8 RSENSE LVGA2 OUTA2 HVGA2 HOST CS SENSEA CK SDO Motor L6482 SDI SW HV GB1 OUTB1 LVGB1 OSCIN LVGB2 OUTB2 OSCOUT HVGB2 R SENSE SENSEB DGND AGND PGND AM15033v1 18/73 DocID023768 Rev 6 L6482 Functional description 6 Functional description 6.1 Device power-up During power-up, the device is under reset (all logic IOs disabled and power bridges in high impedance state) until the following conditions are satisfied:  VREG is greater than VREGthOn  Internal oscillator is operative  STBY/RESET input is forced high. After power-up, the device state is the following:  Parameters are set to default  Internal logic is driven by internal oscillator and a 2-MHz clock is provided by the OSCOUT pin  Bridges are disabled (high impedance).  FLAG output is forced low (UVLO failure indication). After power-up, a period of tlogicwu must pass before applying a command to allow proper oscillator and logic startup. Any movement command makes the device exit from High Z state (HardStop and SoftStop included). 6.2 Logic I/O Pins CS, CK, SDI, STCK, SW and STBY/RESET are TTL/CMOS 3.3 V -5 V compatible logic inputs. Pin SDO is a TTL/CMOS compatible logic output. VDD pin voltage imposes a logical output voltage range. Pins FLAG and BUSY/SYNC are open drain outputs. SW and CS inputs are internally pulled up to VDD and STBY/RESET input is internally pulled down to ground. 6.3 Charge pump To ensure the correct driving of the high-side gate drivers, a voltage higher than the motor power supply voltage needs to be applied to the VBOOT pin. The high-side gate driver supply voltage VBOOT is obtained through an oscillator and a few external components realizing a charge pump (see Figure 4). DocID023768 Rev 6 19/73 73 Functional description L6482 Figure 4. Charge pump circuitry VS + VCP VD1 CBOOT VS D2 CFLY VS + VCP VD1 VD2 VBOOT D1 CP VCP to high-side gate drivers VDD fPUMP Charge pump oscillator AM15034v1 6.4 Microstepping The driver is able to divide the single step into up to 16 microsteps. Stepping mode can be programmed by the STEP_SEL parameter in the STEP_MODE register (Table 22 on page 50). Step mode can only be changed when bridges are disabled. Every time the step mode is changed, the electrical position (i.e. the point of microstepping sine wave that is generated) is reset to zero and the absolute position counter value (Section 6.5) becomes meaningless. Figure 5. Normal mode and microstepping (16 microsteps) Reset position Normal driving PHASE A current PHASE B current Reset position Microstepping PHASE A current PHASE B current microsteps step 1 step 2 step 3 step 4 step 1 step 1 step 2 step 3 step 4 step 1 16 16 16 16 microsteps microsteps microsteps microsteps AM15035v1 20/73 DocID023768 Rev 6 L6482 Functional description Automatic Full-step and Boost modes When motor speed is greater than a programmable full-step speed threshold, the L6482 device switches automatically to Full-step mode; the driving mode returns to microstepping when motor speed decreases below the full-step speed threshold. The switching between the microstepping and Full-step mode and vice versa is always performed at an electrical position multiple of /4 (Figure 6 and Figure 7). Full-step speed threshold is set through the related parameter in the FS_SPD register (Section 9.1.9 on page 47). When the BOOST_MODE bit of the FS_SPD register is low (default), the amplitude of the voltage squarewave in Full-step mode is equal to the peak of the voltage sine wave multiplied by sine(/4) (Figure 6). This avoids the current drop between the two driving modes. When the BOOST_MODE bit of the FS_SPD register is high, the amplitude of the voltage squarewave in Full-step mode is equal to the peak of the voltage sine wave (Figure 7). That improves the output current increasing the maximum motor torque. Figure 6. Automatic Full-step switching in Normal mode Vpeak sin(π /4)x Vpeak Phase A Phase B Full-Step Microstepping (2N+1) x π /4 Microstepping (2N+1) x π /4 AM15036v1 DocID023768 Rev 6 21/73 73 Functional description L6482 Figure 7. Automatic Full-step switching in Boost mode Vpeak Phase A Vpeak Phase B Full-Step Microstepping (2N+1) x π /4 Microstepping (2N+1) x π/4 AM15037v1 6.5 Absolute position counter An internal 22-bit register (ABS_POS) records all the motor motions according to the selected step mode; the stored value unit is equal to the selected step mode (full, half, quarter, etc.). The position range is from -221 to +221-1 steps (see Section 9.1.1 on page 44). 6.6 Programmable speed profiles The user can easily program a customized speed profile defining independently acceleration, deceleration, and maximum and minimum speed values by ACC, DEC, MAX_SPEED and MIN_SPEED registers respectively (see Section 9.1.5 on page 45, 9.1.6 on page 45, 9.1.7 on page 46 and 9.1.8 on page 46). When a command is sent to the device, the integrated logic generates the microstep frequency profile that performs a motor motion compliant to speed profile boundaries. All acceleration parameters are expressed in step/tick2 and all speed parameters are expressed in step/tick; the unit of measurement does not depend on the selected step mode. Acceleration and deceleration parameters range from 2-40 to (212-2) 2-40 step/tick2 (equivalent to 14.55 to 59590 step/s2). Minimum speed parameter ranges from 0 to (212-1) 2-24 step/tick (equivalent to 0 to 976.3 step/s). Maximum speed parameter ranges from 2-18 to (210-1) 2-18 step/tick (equivalent to 15.25 to 15610 step/s). 22/73 DocID023768 Rev 6 L6482 6.7 Functional description Motor control commands The L6482 can accept different types of commands:  constant speed commands (Run, GoUntil, ReleaseSW)  absolute positioning commands (GoTo, GoTo_DIR, GoHome, GoMark)  motion commands (Move)  stop commands (SoftStop, HardStop, SoftHiz, HardHiz). For detailed command descriptions refer to Section 9.2 on page 60. 6.7.1 Constant speed commands A constant speed command produces a motion in order to reach and maintain a userdefined target speed starting from the programmed minimum speed (set in the MIN_SPEED register) and with the programmed acceleration/deceleration value (set in the ACC and DEC registers). A new constant speed command can be requested anytime. Figure 8. Constant speed command examples Speed (step frequency) SPD3 Run(SPD4,BW) SPD1 SPD2 Run(SPD2,FW) Run(SPD3,FW) Minimum speed Minimum speed time Run(SPD1,FW) SPD4 AM15039v1 6.7.2 Positioning commands An absolute positioning command produces a motion in order to reach a user-defined position that is sent to the device together with the command. The position can be reached performing the minimum path (minimum physical distance) or forcing a direction (see Figure 9). Performed motor motion is compliant to programmed speed profile boundaries (acceleration, deceleration, minimum and maximum speed). Note that with some speed profiles or positioning commands, the deceleration phase can start before the maximum speed is reached. DocID023768 Rev 6 23/73 73 Functional description L6482 Figure 9. Positioning command examples Forward direction 0 0 Present position Present position Target position Target position -2 21 +2 21-1 -2 21 +2 21-1 GoTo_DIR(Target pos,FW) GoTo(Target pos) AM15040v1 6.7.3 Motion commands Motion commands produce a motion in order to perform a user-defined number of microsteps in a user-defined direction that are sent to the device together with the command (see Figure 10). Performed motor motion is compliant to programmed speed profile boundaries (acceleration, deceleration, minimum and maximum speed). Note that with some speed profiles or motion commands, the deceleration phase can start before the maximum speed is reached. Figure 10. Motion command examples SPEED SPEED programmed number of microsteps programmed number of microsteps programmed maximum speed programmed maximum speed programmed ACCELERATION programmed minimum speed programmed ACCELERATION programmed DECELERATION programmed minimum speed Note: with some Acceleration/Decelaration profiles the programmed maximum speed is never reached programmed DECELERATION time time AM15041v1 24/73 DocID023768 Rev 6 L6482 6.7.4 Functional description Stop commands A stop command forces the motor to stop. Stop commands can be sent anytime. The SoftStop command causes the motor to decelerate with a programmed deceleration value until the MIN_SPEED value is reached and then stops the motor keeping the rotor position (a holding torque is applied). The HardStop command stops the motor instantly, ignoring deceleration constraints and keeping the rotor position (a holding torque is applied). The SoftHiZ command causes the motor to decelerate with a programmed deceleration value until the MIN_SPEED value is reached and then forces the bridges into high impedance state (no holding torque is present). The HardHiZ command instantly forces the bridges into high impedance state (no holding torque is present). 6.7.5 Step-clock mode In Step-clock mode the motor motion is defined by the step-clock signal applied to the STCK pin. At each step-clock rising edge, the motor is moved one microstep in the programmed direction and the absolute position is consequently updated. When the system is in Step-clock mode, the SCK_MOD flag in the STATUS register is raised, the SPEED register is set to zero and the motor status is considered stopped regardless of the STCK signal frequency (the MOT_STATUS parameter in the STATUS register equal to “00”). 6.7.6 GoUntil and ReleaseSW commands In most applications the power-up position of the stepper motor is undefined, so an initialization algorithm driving the motor to a known position is necessary. The GoUntil and ReleaseSW commands can be used in combination with external switch input (see Section 6.14 on page 30) to easily initialize the motor position. The GoUntil command makes the motor run at target constant speed until the SW input is forced low (falling edge). When this event occurs, one of the following actions can be performed:  ABS_POS register is set to zero (home position) and the motor decelerates to zero speed (as a SoftStop command)  ABS_POS register value is stored in the MARK register and the motor decelerates to zero speed (as a SoftStop command). If the SW_MODE bit of the CONFIG register is set to ‘0’, the motor does not decelerate but it immediately stops (as a HardStop command). The ReleaseSW command makes the motor run at a programmed minimum speed until the SW input is forced high (rising edge). When this event occurs, one of the following actions can be performed:  ABS_POS register is set to zero (home position) and the motor immediately stops (as a HardStop command)  ABS_POS register value is stored in the MARK register and the motor immediately stops (as a HardStop command). If the programmed minimum speed is less than 5 step/s, the motor is driven at 5 step/s. DocID023768 Rev 6 25/73 73 Functional description 6.8 L6482 Internal oscillator and oscillator driver The control logic clock can be supplied by the internal 16-MHz oscillator, an external oscillator (crystal or ceramic resonator) or a direct clock signal. These working modes can be selected by EXT_CLK and OSC_SEL parameters in the CONFIG register (see Table 35 on page 56). At power-up the device starts using the internal oscillator and provides a 2-MHz clock signal on the OSCOUT pin. Attention: In any case, before changing clock source configuration, a hardware reset is mandatory. Switching to different clock configurations during operation may cause unexpected behavior. 6.8.1 Internal oscillator In this mode the internal oscillator is activated and OSCIN is unused. If the OSCOUT clock source is enabled, the OSCOUT pin provides a 2, 4, 8 or 16-MHz clock signal (according to OSC_SEL value); otherwise it is unused (see Figure 11). 6.8.2 External clock source Two types of external clock source can be selected: crystal/ceramic resonator or direct clock source. Four programmable clock frequencies are available for each external clock source: 8, 16, 24 and 32-MHz. When an external crystal/resonator is selected, the OSCIN and OSCOUT pins are used to drive the crystal/resonator (see Figure 11). The crystal/resonator and load capacitors (CL) must be placed as close as possible to the pins. Refer to Table 8 for the choice of the load capacitor value according to the external oscillator frequency. Table 8. CL values according to external oscillator frequency Crystal/resonator frequency (1) CL(2) 8 MHz 25 pF (ESRmax = 80 ) 16 MHz 18 pF (ESRmax = 50 ) 24 MHz 15 pF (ESRmax = 40 ) 32 MHz 10 pF (ESRmax = 40 ) 1. First harmonic resonance frequency. 2. Lower ESR value allows greater load capacitors to be driven. If a direct clock source is used, it must be connected to the OSCIN pin and the OSCOUT pin supplies the inverted OSCIN signal (see Figure 11). The L6482 integrates a clock detection system that resets the device in the case of a failure of the external clock source (direct or crystal/resonator). The monitoring of the clock source is disabled by default, it can be enabled setting high the WD_EN bit in the GATECFG1 26/73 DocID023768 Rev 6 L6482 Functional description register (Section 9.1.18 on page 52). When the external clock source is selected, the device continues to work with the integrated oscillator for textosc milliseconds and then the clock management system switches to the OSCIN input. Figure 11. OSCIN and OSCOUT pin configuration EXT_CLK = "0" EXT_CLK = "1" 8/16/24/32 MHz CL CL 8/16/24/32 MHz OSC_SEL = "1xx" OSCIN OSCOUT OSCIN External oscillator configuration OSCOUT External clock source configuration 2/4/8/16 MHz OSC_SEL = "0xx" UNUSED UNUSED UNUSED OSCIN OSCOUT OSCIN Internal oscillator configuration without clock source OSCOUT Internal oscillator configuration with clock generation AM15042v1 Note: When OSCIN is UNUSED, it should be left floating. When OSCOUT is UNUSED, it should be left floating. 6.9 Overcurrent detection The L6482 measures the load current of each half-bridge sensing the VDS voltage of all the Power MOSFETs (Figure 12). When any of the VDS voltages rise above the programmed threshold, the OCD flag in the STATUS register is forced low until the event expires and a GetStatus command is sent to the device (Section 9.1.21 on page 58 and Section 9.2.20 on page 69). The overcurrent event expires when all the Power MOSFET VDS voltages fall below the programmed threshold. The overcurrent threshold can be programmed by the OCD_TH register in one of 32 available values ranging from 31.25 mV to 1 V with steps of 31.25 mV (Table 21 on page 50 and Section 9.1.17 on page 52). DocID023768 Rev 6 27/73 73 Functional description L6482 Figure 12. Overcurrent detection - principle scheme Vs LOGIC CORE OCD_HSxx Vs + - HVGxx Voltage Comparator BLANKING OUTxx Voltage Comparator OCD_LSxx OC THRESHOLD CURRENT DAC LVGxx + GNDx - GND GND AM15043v1 The overcurrent detection comparators are disabled, in order to avoid wrong voltage measurements, in the following cases:  The respective half-bridge is in high impedance state (both MOSFETs forced off)  The respective half-bridge is commutating  The respective half-bridge is commutated and the programmed blanking time has not yet elapsed  The respective gate is turned off. It is possible to set, if an overcurrent event causes the bridge turn-off or not, through the OC_SD bit in the CONFIG register. When the power bridges are turned off by an overcurrent event, they cannot be turned on until the OCD flag is released by a GetStatus command. 6.10 Undervoltage lockout (UVLO) The L6482 provides a programmable gate driver supply voltage UVLO protection. When one of the supply voltages of the gate driver (VCC for the low sides and VBOOT - VS for the high sides) falls below the respective turn-off threshold, an undervoltage event occurs. In this case, all MOSFETs are immediately turned off and the UVLO flag in the STATUS register is forced low. The UVLO flag is forced low and the MOSFETs are kept off until the gate driver supply voltages return to above the respective turn-on threshold; in this case the undervoltage event expires and the UVLO flag can be released through a GetStatus command. The UVLO thresholds can be selected between two sets according to the UVLOVAL bit value in the CONFIG register. 28/73 DocID023768 Rev 6 L6482 Functional description Table 9. UVLO thresholds UVLOVAL Parameter 0 1 Low-side gate driver supply turn-off threshold (VCCthOff) 6.3 V 10 V Low-side gate driver supply turn-on threshold (VCCthOn) 6.9 V 10.4 V High-side gate driver supply turn-off threshold (VBOOTthOff) 5.5 V 8.8 V High-side gate driver supply turn-on threshold (VBOOTthOff) 6V 9.2 V 6.11 VS undervoltage lockout (UVLO_ADC) The device provides an undervoltage signal of the integrated ADC input voltage (the UVLO_ADC flag in the STATUS register). When VADCIN falls below the VADC,UVLO value, the UVLO_ADC flag is forced low and it is kept in this state until the ADCIN voltage is greater than VADC,UVLO and a GetStatus command is sent to the device. The ADCIN undervoltage event does not turn off the MOSFETs of the power bridges. The motor supply voltage undervoltage detection can be performed by means of this feature, connecting the ADCIN pin to VS through a voltage divider. 6.12 Thermal warning and thermal shutdown An integrated sensor allows detection of the internal temperature and implementation of a 3-level protection. When the Tj(WRN)Set threshold is reached, a warning signal is generated. This is the thermal warning condition and it expires when the temperature falls below the Tj(WRN)Rel threshold. When the Tj(OFF)Set threshold is reached, all the MOSFETs are turned off and the gate driving circuitry is disabled (Miller clamps are still operative). This condition expires when the temperature falls below the Tj(OFF)Rel threshold. When the Tj(SD)OFF threshold is reached, all the MOSFETs are turned off using Miller clamps, the internal VCC voltage regulator is disabled and the current capability of the internal VREG voltage regulator is reduced (thermal shutdown). In this condition, logic is still active (if supplied). The thermal shutdown condition only expires when the temperature goes below Tj(SD)ON. The thermal condition of the device is shown by TH_STATUS bits in the STATUS register (Table 10). DocID023768 Rev 6 29/73 73 Functional description L6482 Table 10. Thermal protection summarizing table State Set condition Release condition Normal Description TH_STATUS Normal operation state 00 Warning Tj > Tj(WRN)Set Tj > Tj(WRN)Rel Temperature warning: operation is not limited 01 Bridge shutdown Tj > Tj(OFF)Set Tj > Tj(OFF)Rel High temperature protection: the MOSFETs are turned off and the gate drivers are disabled 10 Tj > Tj(SD)Rel Overtemperature protection: the MOSFETs are turned off, the gate drivers are disabled, the internal VCC voltage regulator is disabled, the current capability of the internal VREG voltage regulator is limited, and the charge pump is disabled 11 Device shutdown 6.13 Tj > Tj(SD)Set Reset and standby The device can be reset and put into Standby mode through the STBY/RESET pin. When it is forced low, all the MOSFETs are turned off (High Z state), the charge pump is stopped, the SPI interface and control logic are disabled and the internal VREG voltage regulator maximum output current is limited; as a result, the L6482 device heavily reduces the power consumption. At the same time the register values are reset to their default and all the protection functions are disabled. The STBY/RESET input must be forced low at least for tSTBY,min in order to ensure the complete switch to Standby mode. On exiting Standby mode, as well as for IC power-up, a delay must be given before applying a new command to allow proper oscillator and charge pump startup. Actual delay could vary according to the values of the charge pump external components. On exiting Standby mode all the MOSFETs are off and the HiZ flag is high. The registers can be reset to the default values without putting the device into Standby mode through the ResetDevice command (Section 9.2.15 on page 67). 6.14 External switch (SW pin) The SW input is internally pulled up to VDD and detects if the pin is open or connected to ground (see Figure 13). The SW_F bit of the STATUS register indicates if the switch is open (‘0’) or closed (‘1’) (Section 9.1.21 on page 58); the bit value is refreshed at every system clock cycle (125 ns). The SW_EVN flag of the STATUS register is raised when a switch turn-on event (SW input falling edge) is detected (Section 9.1.21). A GetStatus command releases the SW_EVN flag (Section 9.2.20 on page 69). By default, a switch turn-on event causes a HardStop interrupt (SW_MODE bit of the CONFIG register set to ‘0’). Otherwise (SW_MODE bit of the CONFIG register set to ‘1’), switch input events do not cause interrupts and the switch status information is at the user’s disposal (Table 36 on page 56 and Section 9.1.20 on page 55). 30/73 DocID023768 Rev 6 L6482 Functional description The switch input can be used by GoUntil and ReleaseSW commands as described in Section 9.2.10 on page 65 and Section 9.2.11 on page 66. If the SW input is not used, it should be connected to VDD. Figure 13. External switch connection VDD External Switch SW AM15044v1 6.15 Programmable gate drivers The L6482 integrates eight programmable gate drivers that allow the fitting of a wide range of applications. The following parameters can be adjusted:  gate sink/source current (IGATE)  controlled current time (tCC)  turn-off overboost time (tOB). During turn-on, the gate driver charges the gate forcing an IGATE current for all the controlled current time period. At the end of the controlled current phase the gate of the external MOSFET should be completely charged, otherwise the gate driving circuitry continues to charge it using a holding current. This current is equal to IGATE for the low-side gate drivers and 1 mA for the high-side ones. During turn-off, the gate driver discharges the gate sinking an IGATE current for all the controlled current time period. At the beginning of turn-off an overboost phase can be added: in this case the gate driver sinks an IOB current for the programmed tOB period in order to rapidly reach the plateau region. At the end of the controlled current time the gate of the external MOSFET should be completely charged, otherwise the gate driving circuitry discharges it using the integrated Miller clamp. DocID023768 Rev 6 31/73 73 Functional description L6482 Figure 14. Gate driving currents tOB t CC Gate charged tCC Gate discharged IOB Igate Igate Gate Current Gate turn-on Gate turn-off AM15045v1 The gate current can be set to one of the following values: 4, 8, 16, 24, 32, 64 and 96 mA through the IGATE parameter in the GATECFG1 register (see Section 9.1.18 on page 52). Controlled current time can be programmed within range from 125 ns to 3.75 s with a resolution of 125 ns (TCC parameter in the GATECFG1 register) (see Section 9.1.18). Turn-off overboost time can be set to one of the following values: 0, 62.5, 125, 250 ns (TBOOST parameter in the GATECFG1 register). The 62.5 ns value is only available when clock frequency is 16 MHz or 32 MHz; when clock frequency is 8 MHz it is changed to 125 ns and when a 24-MHz clock is used it is changed to 83.3 ns. (see Section 9.1.18). 6.16 Deadtime and blanking time During the bridge commutation, a deadtime is added in order to avoid cross conductions. The deadtime can be programmed within a range from 125 ns to 4 s with a resolution of 125 ns (TDT parameter in the GATECFG2 register) (see Section 9.1.19 on page 54). At the end of each commutation the overcurrent and stall detection comparators are disabled (blanking) in order to avoid the respective systems detecting body diode turn-off current peaks. The duration of blanking time is programmable through the TBLANK parameter in the GATECFG2 register at one of the following values: 125, 250, 375, 500, 625, 750, 875, 1000 ns (see Section 9.1.19). 6.17 Integrated analog-to-digital converter The L6482 integrates an NADC bit ramp-compare analog-to-digital converter with a reference voltage equal to VREG. The analog-to-digital converter input is available through the ADCIN pin and the conversion result is available in the ADC_OUT register (Section 9.1.14 on page 50). The ADC_OUT value can be used for torque regulation or can be at the user’s disposal. 32/73 DocID023768 Rev 6 L6482 6.18 Functional description Supply management and internal voltage regulators The L6482 integrates two linear voltage regulators: the first one can be used to obtain gate driver supply starting from a higher voltage (e.g. the motor supply one). Its output voltage can be set to 7.5 V or 15 V according to the VCCVAL bit value (CONFIG register). The second linear voltage regulator can be used to obtain the 3.3 V logic supply voltage. The regulators are designed to supply the internal circuitry of the IC and should not be used to supply external components. The input and output voltages of both regulators are connected to external pins and the regulators are totally independent: in this way a very flexible supply management can be performed using external components or external supply voltages (Figure 15). Figure 15. Device supply pin management All voltages are internally generated All voltages are externally supplied VBOOT VBOOT CP CP VBUS VBUS VS VS VSREG VSREG VCC 7V5 - 15V VCC Using external components (zener diodes, resistors, ...) it is possible to reduce internal power dissipation constrains. 7V5 - 15V 3.3 V VCCREG 3V3 VCC VCCREG 3V3 VREG VREG AM15046v1 If VCC is externally supplied, the VSREG and VCC pins must be shorted (VSREG must be compliant with VCC range). If VREG is externally supplied, the VCCREG and VREG pins must be shorted and equal to 3.3 V. VSREG must be always less than VBOOT in order to avoid related ESD protection diode turnon. The device can be protected from this event by adding an external low drop diode between the VSREG and VS pins, charge pump diodes should be low drop too. VCCREG must be always less than VCC in order to avoid ESD protection diode turn-on. The device can be protected from this event by adding an external low drop diode between the VCCREG and VSREG pins. Both regulators provide a short-circuit protection limiting the load current within the respective maximum ratings. DocID023768 Rev 6 33/73 73 Functional description 6.19 L6482 BUSY/SYNC pin This pin is an open drain output which can be used as busy flag or synchronization signal according to the SYNC_EN bit value (STEP_MODE register) (see Section 9.1.17 on page 52). 6.20 FLAG pin By default, an internal open drain transistor pulls the FLAG pin to ground when at least one of the following conditions occurs:  Power-up or standby/reset exit  Overcurrent detection  Thermal warning  Thermal shutdown  UVLO  UVLO on ADC input  Switch turn-on event  Command error. It is possible to mask one or more alarm conditions by programming the ALARM_EN register (see Section 9.1.17 and Table 26 on page 52). If the corresponding bit of the ALARM_EN register is low, the alarm condition is masked and it does not cause a FLAG pin transition; all other actions imposed by alarm conditions are performed anyway. In case of daisy chain configuration, FLAG pins of different ICs can be OR-wired to save host controller GPIOs. 34/73 DocID023768 Rev 6 L6482 Phase current control 7 Phase current control The L6482 performs a new current control technique, named predictive current control, allowing the device to obtain the target average phase current. This method is described in detail in Section 7.1. Furthermore, the L6482 automatically selects the better decay mode in order to follow the current profile. Current control algorithm parameters can be programmed by T_FAST, TON_MIN, TOFF_MIN and CONFIG registers (see Section 9.1.11 on page 48, 9.1.12 on page 48, 9.1.13 on page 49 and 9.1.20 on page 55 for details). Different current amplitude can be set for acceleration, deceleration and constant speed phases and when the motor is stopped through TVAL_ACC, TVAL_DEC, TVAL_RUN and TVAL_HOLD registers (see Section 9.1.10 on page 47). The output current amplitude can also be regulated by the ADCIN voltage value (see Section 7.4 on page 39). Each bridge is driven by an independent control system that shares with the other bridge the control parameters only. 7.1 Predictive current control Unlike classical peak current control systems, that make the phase current decay when the target value is reached, this new method keeps the power bridge ON for an extra time after reaching the current threshold. At each cycle the system measures the time required to reach the target current (tSENSE). After that the power stage is kept in a “predictive” ON state (tPRED) for a time equal to the mean value of tSENSE in the last two control cycles (actual one and previous one), as shown in Figure 16. Figure 16. Predictive current control Iout predictive ON state t tPRED (n) = SENSE OFF state (n-1) + tSENSE(n) 2 Iref t SENSE (n-1) tPRED(n-1) tPRED (n) tOFF tSENSE (n) tOFF AM15048v1 At the end of the predictive ON state the power stage is set in OFF state for a fixed time, as in a constant tOFF current control. During the OFF state both slow and fast decay can be DocID023768 Rev 6 35/73 73 Phase current control L6482 performed; the better decay combination is automatically selected by the L6482 device, as described in Section 7.2. As shown in Figure 16, the system is able to center the triangular wave on the desired reference value, improving dramatically the accuracy of the current control system: in fact the average value of a triangular wave is exactly equal to the middle point of each of its segment and at steady-state the predictive current control tends to equalize the duration of the tSENSE and the tPRED time. Furthermore, the tOFF value is recalculated each time a new current value is requested (microstep change) in order to keep the PWM frequency as near as possible to the programmed one (TSW parameter in the CONFIG register). The device can be forced to work using classic peak current control setting low the PRED_EN bit in the CONFIG register (default condition). In this case, after the sense phase (tSENSE) the power stage is set in OFF state, as shown in Figure 17. Figure 17. Non-predictive current control Iout sense ON state OFF state Iref tOFF 7.2 tOFF AM15049v1 Auto-adjusted decay mode During the current control, the device automatically selects the better decay mode in order to follow the current profile reducing the current ripple. At reset, the off-time is performed turning on both the low-side MOS of the power stage and the current recirculates in the lower half of the bridge (slow decay). If, during a PWM cycle, the target current threshold is reached in a time shorter than the TON_MIN value, a fast decay of TOFF_FAST/8 (T_FAST register) is immediately performed turning on the opposite MOS of both half-bridges and the current recirculates back to the supply bus. After this time, the bridge returns to ON state: if the time needed to reach the target current value is still less than TON_MIN, a new fast decay is performed with a period twice the previous one. Otherwise, the normal control sequence is followed as described in Section 7.1. The maximum fast decay duration is set by the TOFF_FAST value. 36/73 DocID023768 Rev 6 L6482 Phase current control Figure 18. Adaptive decay - fast decay tuning VWIDVWGHFD\ W)$67   72))B)$67 UGIDVWGHFD\ W)$67 72))B)$67 7RQ!721B0,1 W)$67   72))B)$67 QGIDVWGHFD\ W)$67  72))B)$67 UHIHUHQFHFXUUHQW 1RWH VWDU WLQJIURPQG IDVWGHFD\WKHV\VWHPFRPELQHV IDVWDQGVORZGHFD\GXULQJWKH2))SKDVH $0Y When two or more fast decays are performed with the present target current, the control system adds a fast decay at the end of every off-time keeping the OFF state duration constant (tOFF is split into tOFF,SLOW and tOFF,FAST). When the current threshold is increased by a microstep change (rising step), the system returns to normal decay mode (slow decay only) and the tFAST value is halved. Stopping the motor or reaching the current sine wave zero crossing causes the current control system to return to the reset state. DocID023768 Rev 6 37/73 73 Phase current control L6482 Figure 19. Adaptive decay - switch from normal to slow + fast decay mode and vice versa 2 nd fast decay switch to fast + slow decay mode 1st fast decay reference current Time tOFF tOFF tOFF,SLOW t FAST tOFF,FAST Target current is increased (raising step) system returns to slow decay mode and tFAST vaule is halved reference current Time AM15051v1 7.3 Auto-adjusted fast decay during the falling steps When the target current is decreased by a microstep change (falling step), the device performs a fast decay in order to reach the new value as fast as possible. However, exceeding the fast duration could cause a strong ripple on the step change. The L6482 device automatically adjusts these fast decays reducing the current ripple. At reset the fast decay value (tFALL) is set to FALL_STEP/4 (T_FAST register). The tFALL value is doubled every time, within the same falling step, an extra fast decay is necessary to obtain an on-time greater than TON_MIN (see Section 9.1.12 on page 48). The maximum tFALL value is equal to FALL_STEP. At the next falling step, the system uses the last tFALL value of the previous falling step. Stopping the motor or reaching the current sine wave zero crossing causes the current control system to return to the reset state. 38/73 DocID023768 Rev 6 L6482 Phase current control Figure 20. Fast decay tuning during the falling steps Falling step 1st fast decay: t FALL = FALL_STEP/4 Falling step 1st fast decay: tFALL= FALL_STEP/2 reference current 2 nd fast decay: tFALL = FALL_STEP/2 Time AM15052v1 7.4 Torque regulation (output current amplitude regulation) The phase currents are monitored through two shunt resistors (one for each power bridge) connected to the respective sense pin (see Figure 21). The integrated comparator compares the sense resistor voltage with the internal reference generated using the peak value, which is proportional to the output current amplitude, and the microstepping code. The comparison result is provided to the logic in order to implement the current control algorithm as described in previous sections. The peak reference voltage can be regulated in two ways: writing TVAL_ACC, TVAL_DEC, TVAL_RUN and TVAL_HOLD registers or varying the ADCIN voltage value. The EN_TQREG bit (CONFIG register) sets the torque regulation method. If this bit is high, ADC_OUT prevalue is used to regulate output current amplitude (see Table 20 on page 50 and Section 9.1.14 on page 50). Otherwise the internal analog-to-digital converter is at the user’s disposal and the output current amplitude is managed by TVAL_HOLD, TVAL_RUN, TVAL_ACC and TVAL_DEC registers (see Table 14 on page 47 and Section 9.1.10 on page 47). The voltage applied to the ADCIN pin is sampled at fS frequency and converted in an NADC bit digital signal. The analog-to-digital conversion result is available in the ADC_OUT register. DocID023768 Rev 6 39/73 73 Phase current control L6482 Figure 21. Current sensing and reference voltage generation Peak reference DAC To gate drivers To gate drivers TVAL_X or ADCIN Load Microstepping DAC Microstep To gate drivers To current control logic To gate drivers Vref SENSEX Rsense AM15047v1 40/73 DocID023768 Rev 6 L6482 Serial interface 8 Serial interface The integrated 8-bit serial peripheral interface (SPI) is used for a synchronous serial communication between the host microprocessor (always master) and the L6482 (always slave). The SPI uses chip select (CS), serial clock (CK), serial data input (SDI) and serial data output (SDO) pins. When CS is high the device is unselected and the SDO line is inactive (high impedance). The communication starts when CS is forced low. The CK line is used for synchronization of data communication. All commands and data bytes are shifted into the device through the SDI input, most significant bit first. The SDI is sampled on the rising edges of the CK. All output data bytes are shifted out of the device through the SDO output, most significant bit first. The SDO is latched on the falling edges of the CK. When a return value from the device is not available, an all zero byte is sent. After each byte transmission the CS input must be raised and be kept high for at least tdisCS in order to allow the device to decode the received command and put the return value into the shift register. All timing requirements are shown in Figure 22 (see Section 3 on page 11 for values). Multiple devices can be connected in daisy chain configuration, as shown in Figure 23. Figure 22. SPI timings diagram CS t disCS t setCS t rCK t hCK t fCK t lCK CK t enSDO t setSDI t holCS MSB SDI N-1 HiZ MSB N-2 LSB t vSDO t holSDO SDO t disSDO t holSDI N-1 N-2 LSB MSB AM15053v1 DocID023768 Rev 6 41/73 73 Serial interface L6482 Figure 23. Daisy chain configuration 42/73 DocID023768 Rev 6 L6482 Programming manual 9 Programming manual 9.1 Register and flag description Table 11 shows the user registers available (a detailed description can be found in the respective paragraphs from Section 9.1.1 on page 44 to Section 9.1.21 on page 58): Table 11. Register map Register function Len. [bit] Reset Reset [Hex] Register name [Hex] value h01 ABS_POS Current position 22 000000 0 R, WS h02 EL_POS Electrical position 9 000 0 R, WS h03 MARK Mark position 22 000000 0 R, WR h04 SPEED Current speed 20 00000 0 step/tick (0 step/s) R h05 ACC Acceleration 12 08A 125.5e-12 step/tick2 (2008 step/s2) Address 125.5e-12 step/tick2 Remarks(1) 2 R, WS h06 DEC Deceleration 12 08A h07 MAX_SPEED Maximum speed 10 041 248e-6 step/tick (991.8 step/s) R, WR h08 MIN_SPEED Minimum speed 12 000 0 step/tick (0 step/s) R, WS h15 FS_SPD Full-step speed 11 027 150.7e-6 step/tick (602.7 step/s) R, WR h09 TVAL_HOLD Holding reference voltage 7 29 328 mV R, WR h0A TVAL_RUN Constant speed reference voltage 7 29 328 mV R, WR h0B TVAL_ACC Acceleration starting reference voltage 7 29 328 mV R, WR h0C TVAL_DEC Deceleration starting reference voltage 7 29 328 mV R, WR h0D RESERVED - 16 - - - h0E T_FAST Fast decay settings 8 19 1 µs / 5 µs R, WH h0F TON_MIN Minimum on-time 8 29 20.5 µs R, WH h10 TOFF_MIN Minimum off-time 8 29 20.5 µs R, WH h11 RESERVED - 8 - - - 0 R (2) (2008 step/s ) R, WS h12 ADC_OUT ADC output 5 XX h13 OCD_TH OCD threshold 5 8 281.25 mV R, WR h14 RESERVED - 8 - - - h16 STEP_MODE Step mode 8 7 16 steps, SYNC mode disabled R, WH h17 ALARM_EN Alarms enabled 8 FF All alarms enabled R, WS h18 GATECFG1 Gate driver configuration 11 0 Igate = 4 mA, tCC = 125 ns, no boost R, WH DocID023768 Rev 6 43/73 73 Programming manual L6482 Table 11. Register map (continued) Register name Register function Len. [bit] Reset Reset [Hex] [Hex] value h19 GATECFG2 Gate driver configuration 8 0 tBLANK = 125 ns, tDT = 125 ns R, WH 2C88 Internal 16 MHz oscillator (OSCOUT at 2 MHz), SW event causes HardStop, motor supply voltage compensation disabled, overcurrent shutdown, VCC = 7.5 V, UVLO threshold low, tSW = 44 µs R, WH Address h1A h1B CONFIG IC configuration STATUS Status 16 16 Remarks(1) High impedance state, motor stopped, reverse direction, XXXX(2) all fault flags released UVLO/Reset flag set R 1. R: readable, WH: writable, only when outputs are in high impedance, WS: writable only when motor is stopped, WR: always writable. 2. According to startup conditions. 9.1.1 ABS_POS The ABS_POS register contains the current motor absolute position in agreement with the selected step mode; the stored value unit is equal to the selected step mode (full, half, quarter, etc.). The value is in 2's complement format and it ranges from -221 to +221-1. At power-on the register is initialized to “0” (HOME position). Any attempt to write the register when the motor is running causes the command to be ignored and the CMD_ERROR flag to rise (Section 9.1.21 on page 58). 9.1.2 EL_POS The EL_POS register contains the current electrical position of the motor. The two MSbits indicate the current step and the other bits indicate the current microstep (expressed in step/16) within the step. Table 12. EL_POS register Bit 8 Bit 7 STEP Bit 6 Bit 5 Bit 4 MICROSTEP Bit 3 Bit 2 Bit 1 Bit 0 0 0 0 When the EL_POS register is written by the user, the new electrical position is instantly imposed. When the EL_POS register is written, its value must be masked in order to match with the step mode selected in the STEP_MODE register in order to avoid a wrong microstep value generation (Section 9.1.17 on page 52); otherwise the resulting microstep sequence is incorrect. Any attempt to write the register when the motor is running causes the command to be ignored and the CMD_ERROR flag to rise (Section 9.1.21). 44/73 DocID023768 Rev 6 L6482 9.1.3 Programming manual MARK The MARK register contains an absolute position called MARK, according to the selected step mode; the stored value unit is equal to the selected step mode (full, half, quarter, etc.). It is in 2's complement format and it ranges from -221 to +221-1. 9.1.4 SPEED The SPEED register contains the current motor speed, expressed in step/tick (format unsigned fixed point 0.28). In order to convert the SPEED value in step/s, the following formula can be used: Equation 1 – 28 SPEED  2  step/s  = ------------------------------------tick where SPEED is the integer number stored in the register and tick is 250 ns. The available range is from 0 to 15625 step/s with a resolution of 0.015 step/s. Note: The range effectively available to the user is limited by the MAX_SPEED parameter. Any attempt to write the register causes the command to be ignored and the CMD_ERROR flag to rise (Section 9.1.21 on page 58). 9.1.5 ACC The ACC register contains the speed profile acceleration expressed in step/tick2 (format unsigned fixed point 0.40). In order to convert the ACC value in step/s2, the following formula can be used: Equation 2 – 40 2 ACC  2  step/s  = ---------------------------2 tick where ACC is the integer number stored in the register and tick is 250 ns. The available range is from 14.55 to 59590 step/s2 with a resolution of 14.55 step/s2. The 0xFFF value of the register is reserved and it should never be used. Any attempt to write to the register when the motor is running causes the command to be ignored and the CMD_ERROR flag to rise (Section 9.1.21). 9.1.6 DEC The DEC register contains the speed profile deceleration expressed in step/tick2 (format unsigned fixed point 0.40). DocID023768 Rev 6 45/73 73 Programming manual L6482 In order to convert the DEC value in step/s2, the following formula can be used: Equation 3 – 40 DEC  2 2  step/s  = ---------------------------2 tick where DEC is the integer number stored in the register and tick is 250 ns. The available range is from 14.55 to 59590 step/s2 with a resolution of 14.55 step/s2. Any attempt to write the register when the motor is running causes the command to be ignored and the CMD_ERROR flag to rise (Section 9.1.21 on page 58). 9.1.7 MAX_SPEED The MAX_SPEED register contains the speed profile maximum speed expressed in step/tick (format unsigned fixed point 0.18). In order to convert it in step/s, the following formula can be used: Equation 4 – 18 MAX_SPEED  2  step/s  = ----------------------------------------------------tick where MAX_SPEED is the integer number stored in the register and tick is 250 ns. The available range is from 15.25 to 15610 step/s with a resolution of 15.25 step/s. 9.1.8 MIN_SPEED The MIN_SPEED register contains the following parameters: Table 13. MIN_SPEED register Bit 12 0 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 MIN_SPEED The MIN_SPEED parameter contains the speed profile minimum speed. Its value is expressed in step/tick and to convert it in step/s the following formula can be used: Equation 5 – 24 MIN_SPEED  2  step/s  = --------------------------------------------------tick where MIN_SPEED is the integer number stored in the register and tick is the ramp 250 ns. The available range is from 0 to 976.3 step/s with a resolution of 0.238 step/s. Any attempt to write the register when the motor is running causes the CMD_ERROR flag to rise. 46/73 DocID023768 Rev 6 L6482 9.1.9 Programming manual FS_SPD The FS_SPD register contains the following parameters: Table 14. FS_SPD register Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 BOOST_MODE Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 FS_SPD The FS_SPD threshold speed value over which the step mode is automatically switched to full-step two-phase on. Its value is expressed in step/tick (format unsigned fixed point 0.18) and to convert it in step/s the following formula can be used: Equation 6 – 18  FS_SPD + 0.5   2  step/s  = ----------------------------------------------------------tick If FS_SPD value is set to hFF (max.) the system always works in Microstepping mode (SPEED must go over the threshold to switch to Full-step mode). Setting FS_SPD to zero does not have the same effect as setting the step mode to full-step two-phase on: the zero FS_SPD value is equivalent to a speed threshold of about 7.63 step/s. The available range is from 7.63 to 15625 step/s with a resolution of 15.25 step/s. The BOOST_MODE bit sets the amplitude of the voltage squarewave during the full-step operation (see Section : Automatic Full-step and Boost modes on page 21). 9.1.10 TVAL_HOLD, TVAL_RUN, TVAL_ACC and TVAL_DEC The TVAL_HOLD register contains the reference voltage that is assigned to the torque regulation DAC when the motor is stopped. The TVAL_RUN register contains the reference voltage that is assigned to the torque regulation DAC when the motor is running at constant speed. The TVAL_ACC register contains the reference voltage that is assigned to the torque regulation DAC during acceleration. The TVAL_DEC register contains the reference voltage that is assigned to the torque regulation DAC during deceleration. The available range is from 7.8 mV to 1 V with a resolution of 7.8 mV, as shown in Table 15. DocID023768 Rev 6 47/73 73 Programming manual L6482 Table 15. Torque regulation by TVAL_HOLD, TVAL_ACC, TVAL_DEC and TVAL_RUN registers TVAL_X [6…0] 9.1.11 Peak reference voltage 0 0 0 0 0 0 1 15.6 mV … 7.8 mV … 0 … 0 … 0 … 0 … 0 … 0 … 0 1 1 1 1 1 1 0 992.2 mV 1 1 1 1 1 1 1 1V T_FAST The T_FAST register contains the maximum fast decay time (TOFF_FAST) and the maximum fall step time (FALL_STEP) used by the current control system (Section 7.2 on page 36 and Section 7.3 on page 38 for details): Table 16. FS_SPD register Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 TOFF_FAST Bit 2 Bit 1 Bit 0 FAST_STEP The available range for both parameters is from 2 µs to 32 µs. Table 17. Maximum fast decay times TOFF_FAST [3…0] FAST_STEP [3…0] Fast decay time 0 0 0 0 2 µs 0 0 0 1 4 µs … … … … … 1 1 1 0 28 µs 1 1 1 1 32 µs Any attempt to write to the register when the motor is running causes the command to be ignored and CMD_ERROR to rise (Section 9.1.21 on page 58). 9.1.12 TON_MIN This parameter is used by the current control system when current mode operation is selected. The TON_MIN register contains the minimum on-time value used by the current control system (see Section 7.2). The available range for both parameters is from 0.5 µs to 64 µs. 48/73 DocID023768 Rev 6 L6482 Programming manual Table 18. Minimum on-time TON MIN [6…0] Time 0 0 0 0 0 0 0 0.5 µs 0 0 0 0 0 0 1 1 µs … … … … … … … … 1 1 1 1 1 1 0 63.5 µs 1 1 1 1 1 1 1 64 µs Any attempt to write to the register when the motor is running causes the command to be ignored and the CMD_ERROR to rise (see Section 9.1.21 on page 58). 9.1.13 TOFF_MIN This parameter is used by the current control system when current mode operation is selected. The TOFF_MIN register contains the minimum off-time value used by the current control system (see Section 7.1 on page 35 for details). The available range for both parameters is from 0.5 µs to 64 µs. Table 19. Minimum off-time TOFF MIN [6…0] Time 0 0 0 0 0 0 0 0.5 µs 0 0 0 0 0 0 1 1 µs … … … … … … … … 1 1 1 1 1 1 0 63.5 µs 1 1 1 1 1 1 1 64 µs Any attempt to write to the register when the motor is running causes the command to be ignored and CMD_ERROR to rise (see Section 9.1.21). DocID023768 Rev 6 49/73 73 Programming manual 9.1.14 L6482 ADC_OUT The ADC_OUT register contains the result of the analog-to-digital conversion of the ADCIN pin voltage. Any attempt to write to the register causes the command to be ignored and the CMD_ERROR flag to rise (see Section 9.1.21 on page 58). Table 20. ADC_OUT value and torque regulation feature VADCIN/ VREG Reference voltage 0 0 0 0 0 0 31.25 mV 1/32 0 0 0 0 1 62.5 mV … … … … … … … 9.1.15 ADC_OUT [4…0] 30/32 1 1 1 1 0 968.8 mV 31/32 1 1 1 1 1 1V OCD_TH The OCD_TH register contains the overcurrent threshold value (see Section 6.9 on page 27 for details). The available range is from 31.25 mV to 1 V, steps of 31.25 mV, as shown in Table 21. Table 21. Overcurrent detection threshold OCD_TH [4…0] 0 0 0 0 0 31.25 mV 0 0 0 0 1 62.5 mV … … … … … … 9.1.16 Overcurrent detection threshold 1 1 1 1 0 968.8 mV 1 1 1 1 1 1V STEP_MODE The STEP_MODE register has the following structure: Table 22. STEP_MODE register Bit 7 SYNC_EN Bit 6 Bit 5 Bit 4 SYNC_SEL 1. When the register is written this bit must be set to 1. 50/73 DocID023768 Rev 6 Bit 3 1(1) Bit 2 Bit 1 STEP_SEL Bit 0 L6482 Programming manual The STEP_SEL parameter selects one of five possible stepping modes: Table 23. Step mode selection STEP_SEL[2…0] Step mode 0 0 0 Full-step 0 0 1 Half-step 0 1 0 1/4 microstep 0 1 1 1/8 microstep 1 X X 1/16 microstep Every time the step mode is changed, the electrical position (i.e. the point of microstepping sine wave that is generated) is reset to the first microstep. Warning: Every time STEP_SEL is changed, the value in the ABS_POS register loses meaning and should be reset. Any attempt to write the register when the motor is running causes the command to be ignored and the CMD_ERROR flag to rise (see Section 9.1.21 on page 58). When the SYNC_EN bit is set low, the BUSY/SYNC output is forced low during the command execution, otherwise, when the SYNC_EN bit is set high, the BUSY/SYNC output provides a clock signal according to the SYNC_SEL parameter. Table 24. SYNC output frequency SYNC_SEL STEP_SEL (fFS is the full-step frequency) 000 001 010 011 100 101 110 111 000 fFS/2 fFS/2 fFS/2 fFS/2 fFS/2 fFS/2 fFS/2 fFS/2 001 NA fFS fFS fFS fFS fFS fFS fFS 010 NA NA 2 · fFS 2 · fFS 2 · fFS 2 · fFS 2 · fFS 2 · fFS 011 NA NA NA 4 · fFS 4 · fFS 4 · fFS 4 · fFS 4 · fFS 100 NA NA NA NA 8 · fFS 8 · fFS 8 · fFS 8 · fFS 101 NA NA NA NA NA NA NA NA 110 NA NA NA NA NA NA NA NA 111 NA NA NA NA NA NA NA NA DocID023768 Rev 6 51/73 73 Programming manual L6482 The synchronization signal is obtained starting from the electrical position information (EL_POS register), according to Table 25: Table 25. SYNC signal source SYNC_SEL[2…0] Source 0 0 0 EL_POS[7] 0 0 1 EL_POS[6] 0 1 0 EL_POS[5] 0 1 1 EL_POS[4] 1 0 0 EL_POS[3] 1 0 1 UNUSED(1) 1 1 0 UNUSED(1) 1 1 1 UNUSED(1) 1. When this value is selected, the BUSY output is forced low. 9.1.17 ALARM_EN The ALARM_EN register allows the selection of which alarm signals are used to generate the FLAG output. If the respective bit of the ALARM_EN register is set high, the alarm condition forces the FLAG pin output down. Table 26. ALARM_EN register 9.1.18 ALARM_EN bit Alarm condition 0 (LSB) Overcurrent 1 Thermal shutdown 2 Thermal warning 3 UVLO 4 ADC UVLO 5 Unused 6 Switch turn-on event 7 (MSB) Command error GATECFG1 The GATECFG1 register has the following structure: Table 27. GATECFG1 register Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 WD_EN Bit 7 Bit 6 Bit 5 Bit 4 IGATE 52/73 Bit 3 Bit 8 TBOOST Bit 2 TCC DocID023768 Rev 6 Bit 9 Bit 1 Bit 0 L6482 Programming manual The IGATE parameter selects the sink/source current used by gate driving circuitry to charge/discharge the respective gate during commutations. Seven possible values ranging from 4 mA to 96 mA are available, as shown in Table 28. Table 28. IGATE parameter IGATE [2…0} Gate current [mA} 0 0 0 4 0 0 1 4 0 1 0 8 0 1 1 16 1 0 0 24 1 0 1 32 1 1 0 64 1 1 1 96 The TCC parameter defines the duration of constant current phase during gate turn-on and turn-off sequences (Section 6.15 on page 31). Table 29. TCC parameter TCC [4…0] Constant current time [ns] 0 0 0 0 0 125 0 0 0 0 1 250       1 1 1 0 0 3625 1 1 1 0 1 3750 1 1 1 1 0 3750 1 1 1 1 1 3750 The TBOOST parameter defines the duration of the overboost phase during gate turn-off (Section 6.15). DocID023768 Rev 6 53/73 73 Programming manual L6482 Table 30. TBOOST parameter TBOOST Turn-off boost time [ns] [2…0] 0 0 0 0 (1) 62.5 / 83.3(2) / 125(3) 0 0 1 0 1 0 125 0 1 1 250 1 0 0 375 1 0 1 500 1 1 0 750 1 1 1 1000 1. Clock frequency equal to 16 MHz or 32 MHz. 2. Clock frequency equal to 24 MHz. 3. Clock frequency equal to 8 MHz. The WD_EN bit enables the clock source monitoring (Section 6.8.2 on page 26). 9.1.19 GATECFG2 The GATECFG2 register has the following structure: Table 31. GATECFG2 register (voltage mode) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 TBLANK Bit 1 Bit 0 TDT The TDT parameter defines the deadtime duration between the gate turn-off and the opposite gate turn-on sequences (Section 6.16 on page 32). Table 32. TDT parameter TDT [4…0] Deadtime [ns] 0 0 0 0 0 125 0 0 0 0 1 250       1 1 1 1 0 3875 1 1 1 1 1 4000 The TBLANK parameter defines the duration of the blanking of the current sensing comparators (stall detection and overcurrent) after each commutation (Section 6.16). 54/73 DocID023768 Rev 6 L6482 Programming manual Table 33. TBLANK parameters TBLANK [2…0] 9.1.20 Blanking time [ns] 0 0 0 125 0 0 1 250     1 1 0 875 1 1 1 1000 CONFIG The CONFIG register has the following structure: Table 34. CONFIG register Bit 15 Bit 14 Bit 13 PRED_EN Bit 12 Bit 11 Bit 10 TSW Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 OC_SD RESERVED EN_TQREG SW_MODE EXT_CLK DocID023768 Rev 6 Bit 2 Bit 9 Bit 8 VCCVAL UVLOVAL Bit 1 Bit 0 OSC_SEL 55/73 73 Programming manual L6482 The OSC_SEL and EXT_CLK bits set the system clock source: Table 35. Oscillator management EXT_CLK OSC_SEL [2…0] Clock source OSCIN OSCOUT Internal oscillator: 16 MHz Unused Unused 0 0 0 0 0 0 0 1 0 0 1 0 0 0 1 1 1 0 0 0 Internal oscillator: 16 MHz Unused Supplies a 2-MHz clock 1 0 0 1 Internal oscillator: 16 MHz Unused Supplies a 4-MHz clock 1 0 1 0 Internal oscillator: 16 MHz Unused Supplies an 8-MHz clock 1 0 1 1 Internal oscillator: 16 MHz Unused Supplies a 16-MHz clock 0 1 0 0 External crystal or resonator: 8 MHz Crystal/resonator driving Crystal/resonator driving 0 1 0 1 External crystal or resonator: 16 MHz Crystal/resonator driving Crystal/resonator driving 0 1 1 0 External crystal or resonator: 24 MHz Crystal/resonator driving Crystal/resonator driving 0 1 1 1 External crystal or resonator: 32 MHz Crystal/resonator driving Crystal/resonator driving 1 1 0 0 Ext. clock source: 8 MHz (crystal/resonator driver disabled) Clock source Supplies inverted OSCIN signal 1 1 0 1 Ext. clock source: 16 MHz (crystal/resonator driver disabled) Clock source Supplies inverted OSCIN signal 1 1 1 0 Ext. clock source: 24 MHz (crystal/resonator driver disabled) Clock source Supplies inverted OSCIN signal 1 1 1 1 Ext. clock source: 32 MHz (crystal/resonator driver disabled) Clock source Supplies inverted OSCIN signal The SW_MODE bit sets the external switch to act as HardStop interrupt or not: Table 36. External switch HardStop interrupt mode 56/73 SW_MODE Switch mode 0 HardStop interrupt 1 User disposal DocID023768 Rev 6 L6482 Programming manual The OC_SD bit sets if an overcurrent event causes or not the bridges to turn off; the OCD flag in the status register is forced low anyway: Table 37. Overcurrent event OC_SD Overcurrent event 1 Bridges shutdown 0 Bridges do not shutdown The VCCVAL bit sets the internal VCC regulator output voltage. Table 38. Programmable VCC regulator output voltage VCCVAL VCC voltage 0 7.5 V 1 15 V The UVLOVAL bit sets the UVLO protection thresholds. Table 39. Programmable UVLO thresholds UVLOVAL VCCthOn VCCthOff VBOOTthOn VBOOTthOff 0 6.9 V 6.3 V 6V 5.5 V 1 10.4 V 10 V 9.2 V 8.8 V The EN_TQREG bit sets if the torque regulation is performed through ADCIN voltage (external) or the TVAL_HOLD, TVAL_ACC, TVAL_DEC and TVAL_RUN registers (internal). Table 40. External torque regulation enable EN_TQREG External torque regulation 0 Disabled 1 Enabled The TSW parameter is used by the current control system and it sets the target switching period. Table 41. Switching period TSW [4…0] Switching period 0 0 0 0 0 4 µs (250 kHz) 0 0 0 0 1 4 µs (250 kHz) 0 0 0 1 0 8 µs (125 kHz) … … … … … … 1 1 1 1 1 124 µs (8 kHz) DocID023768 Rev 6 57/73 73 Programming manual L6482 Any attempt to write the CONFIG register when the motor is running causes the command to be ignored and the CMD_ERROR flag to rise (see Section 9.1.21 on page 58). The PRED_EN bit sets if the predictive current control method is enabled or not. . Table 42. Motor supply voltage compensation enable PRED_EN Predictive current control 0 Disabled 1 Enabled Any attempt to write the CONFIG register when the motor is running causes the command to be ignored and the CMD_ERROR flag to rise (Section 9.1.20 on page 55). 9.1.21 STATUS The STATUS register has the following structure: Table 43. STATUS register Bit 15 Bit 14 Bit 13 Unused Unused OCD Bit 7 Bit 6 Bit 5 CMD_ERROR MOT_STATUS Bit 12 Bit 11 TH_STATUS Bit 10 Bit 9 Bit 8 UVLO_ADC UVLO STCK_MOD Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 DIR SW_EVN SW_F BUSY HiZ When the HiZ flag is high it indicates that the bridges are in high impedance state. Any motion command causes the device to exit from High Z state (HardStop and SoftStop included), unless error flags forcing a High Z state are active. The UVLO flag is active low and is set by an undervoltage lockout or reset events (power-up included). The UVLO_ADC flag is active low and indicates an ADC undervoltage event. The OCD flag is active low and indicates an overcurrent detection event. The CMD_ERROR flag is active high and indicates that the command received by SPI can't be performed or does not exist at all. The SW_F reports the SW input status (low for open and high for closed). The SW_EVN flag is active high and indicates a switch turn-on event (SW input falling edge). 58/73 DocID023768 Rev 6 L6482 Programming manual TH_STATUS bits indicate the current device thermal status (Section 6.12 on page 29): Table 44. STATUS register TH_STATUS bits TH_STATUS Status 0 0 Normal 0 1 Warning 1 0 Bridge shutdown 1 1 Device shutdown UVLO, UVLO_ADC, OCD, CMD_ERROR, SW_EVN and TH_STATUS bits are latched: when the respective conditions make them active (low or high) they remain in that state until a GetStatus command is sent to the IC. The BUSY bit reflects the BUSY pin status. The BUSY flag is low when a constant speed, positioning or motion command is under execution and is released (high) after the command has been completed. The STCK_MOD bit is an active high flag indicating that the device is working in Step-clock mode. In this case the step-clock signal should be provided through the STCK input pin. The DIR bit indicates the current motor direction: Table 45. STATUS register DIR bit DIR Motor direction 1 Forward 0 Reverse MOT_STATUS indicates the current motor status: Table 46. STATUS register MOT_STATUS bits MOT_STATUS Motor status 0 0 Stopped 0 1 Acceleration 1 0 Deceleration 1 1 Constant speed Any attempt to write to the register causes the command to be ignored and the CMD_ERROR to rise. DocID023768 Rev 6 59/73 73 Programming manual 9.2 L6482 Application commands The command summary is given in Table 47. Table 47. Application commands Command Mnemonic Command binary code [7…5] [4] [3] [2…1] [0] 0 00 0 NOP 000 SetParam (PARAM, VALUE) 000 [PARAM] Writes VALUE in PARAM register GetParam (PARAM) 001 [PARAM] Returns the stored value in PARAM register Run (DIR, SPD) 010 1 0 00 DIR Sets the target speed and the motor direction StepClock (DIR) 010 1 1 00 DIR Puts the device in Step-clock mode and imposes DIR direction Move (DIR,N_STEP) 010 0 0 00 DIR Makes N_STEP (micro)steps in DIR direction (not performable when motor is running) GoTo (ABS_POS) 011 0 0 00 0 GoTo_DIR (DIR, ABS_POS) 011 0 1 00 DIR GoUntil (ACT, DIR, SPD) 100 0 ACT 01 Performs a motion in DIR direction with speed DIR SPD until SW is closed, the ACT action is executed then a SoftStop takes place ReleaseSW (ACT, DIR) 100 1 ACT 01 Performs a motion in DIR direction at minimum DIR speed until the SW is released (open), the ACT action is executed then a HardStop takes place GoHome 011 1 0 00 0 Brings the motor in HOME position GoMark 011 1 1 00 0 Brings the motor in MARK position ResetPos 110 1 1 00 0 Resets the ABS_POS register (sets HOME position) ResetDevice 110 0 0 00 0 Device is reset to power-up conditions SoftStop 101 1 0 00 0 Stops motor with a deceleration phase HardStop 101 1 1 00 0 Stops motor immediately SoftHiZ 101 0 0 00 0 Puts the bridges in high impedance status after a deceleration phase HardHiZ 101 0 1 00 0 Puts the bridges in high impedance status immediately GetStatus 110 1 0 00 0 Returns the status register value RESERVED 111 0 1 01 1 RESERVED COMMAND RESERVED 111 1 1 00 0 RESERVED COMMAND 60/73 0 Action Nothing Brings motor in ABS_POS position (minimum path) Brings motor in ABS_POS position forcing DIR direction DocID023768 Rev 6 L6482 9.2.1 Programming manual Command management The host microcontroller can control motor motion and configure the L6482 device through a complete set of commands. All commands are composed by a single byte. After the command byte, some bytes of arguments should be needed (see Figure 24). Argument length can vary from 1 to 3 bytes. Figure 24. Command with 3-byte argument SDI (from host) Command byte Argument byte 2 (MSB) Argument byte 1 Argument byte 0 (LSB) 0x00 0x00 0x00 0x00 SDO (to host) AM15055v1 By default, the device returns an all zero response for any received byte, the only exceptions are GetParam and GetStatus commands. When one of these commands is received, the following response bytes represent the related register value (see Figure 25). Response length can vary from 1 to 3 bytes. Figure 25. Command with 3-byte response SDI (from host) Command byte NOP NOP NOP 0x00 Response byte 2 (MSB) Response byte 1 Response byte 0 (LSB) SDO (to host) AM15056v1 During response transmission, new commands can be sent. If a command requiring a response is sent before the previous response is completed, the response transmission is aborted and the new response is loaded into the output communication buffer (see Figure 26). Figure 26. Command response aborted SDI (from host) SDO (to host) Command 1 (3 byte resp expected) Command 2 (no resp. expected) Command 3 (2 byte resp expected) Command 4 (no resp. expected) Command 5 (no resp. expected) 0x00 Response byte 2 (MSB) Response byte 1 Response byte 1 (MSB) Response byte 0 (LSB) Command 1 response is aborted AM15057v1 When a byte that does not correspond to a command is sent to the IC it is ignored and the CMD_ERROR flag in the STATUS register is raised (see Section 9.1.21 on page 58). DocID023768 Rev 6 61/73 73 Programming manual 9.2.2 L6482 Nop Table 48. Nop command structure Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 0 0 0 0 0 0 0 0 From host Nothing is performed. 9.2.3 SetParam (PARAM, VALUE) Table 49. SetParam command structure Bit 7 Bit 6 Bit 5 0 0 0 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 PARAM VALUE Byte 2 (if needed) From host VALUE Byte 1 (if needed) VALUE Byte 0 The SetParam command sets the PARAM register value equal to VALUE; PARAM is the respective register address listed in Table 11 on page 43. The command should be followed by the new register VALUE (most significant byte first). The number of bytes composing the VALUE argument depends on the length of the target register (see Table 11). Some registers cannot be written (see Table 11); any attempt to write one of those registers causes the command to be ignored and the CMD_ERROR flag to rise at the end of the command byte, as if an unknown command code were sent (see Section 9.1.21 on page 58). Some registers can only be written in particular conditions (see Table 11); any attempt to write one of those registers when the conditions are not satisfied causes the command to be ignored and the CMD_ERROR flag to rise at the end of the last argument byte (see Section 9.1.21). Any attempt to set an inexistent register (wrong address value) causes the command to be ignored and the CMD_ERROR flag to rise at the end of the command byte as if an unknown command code were sent. 9.2.4 GetParam (PARAM) Table 50. GetParam command structure 62/73 Bit 7 Bit 6 Bit 5 0 0 1 Bit 4 Bit 3 Bit 2 PARAM Bit 1 Bit 0 From host ANS Byte 2 (if needed) To host ANS Byte 1 (if needed) To host ANS Byte 0 To host DocID023768 Rev 6 L6482 Programming manual This command reads the current PARAM register value; PARAM is the respective register address listed in Table 11 on page 43. The command response is the current value of the register (most significant byte first). The number of bytes composing the command response depends on the length of the target register (see Table 11). The returned value is the register one at the moment of GetParam command decoding. If register values change after this moment, the response is not updated accordingly. All registers can be read anytime. Any attempt to read an inexistent register (wrong address value) causes the command to be ignored and the CMD_ERROR flag to rise at the end of the command byte as if an unknown command code were sent. 9.2.5 Run (DIR, SPD) Table 51. Run command structure Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 0 1 0 1 0 0 0 DIR X X X X SPD (Byte 2) From host From host SPD (Byte 1) From host SPD (Byte 0) From host The Run command produces a motion at SPD speed; the direction is selected by the DIR bit: '1' forward or '0' reverse. The SPD value is expressed in step/tick (format unsigned fixed point 0.28) that is the same format as the SPEED register (Section 9.1.4 on page 45). Note: The SPD value should be lower than MAX_SPEED and greater than MIN_SPEED, otherwise the Run command is executed at MAX_SPEED or MIN_SPEED respectively. This command keeps the BUSY flag low until the target speed is reached. This command can be given anytime and is immediately executed. 9.2.6 StepClock (DIR) Table 52. StepClock command structure Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 0 1 0 1 1 0 0 DIR From host The StepClock command switches the device in Step-clock mode (Section 6.7.5 on page 25) and imposes the forward (DIR = '1') or reverse (DIR = '0') direction. When the device is in Step-clock mode, the SCK_MOD flag in the STATUS register is raised and the motor is always considered stopped (Section 6.7.5 and 9.1.21 on page 58). The device exits Step-clock mode when a constant speed, absolute positioning or motion command is sent through SPI. Motion direction is imposed by the respective StepClock command argument and can by changed by a new StepClock command without exiting Step-clock mode. DocID023768 Rev 6 63/73 73 Programming manual L6482 Events that cause bridges to be forced into high impedance state (overtemperature, overcurrent, etc.) do not cause the device to leave Step-clock mode. The StepClock command does not force the BUSY flag low. This command can only be given when the motor is stopped. If a motion is in progress, the motor should be stopped and it is then possible to send a StepClock command. Any attempt to perform a StepClock command when the motor is running causes the command to be ignored and the CMD_ERROR flag to rise (Section 9.1.21 on page 58). 9.2.7 Move (DIR, N_STEP) Table 53. Move command structure Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 0 1 0 0 0 0 0 DIR X X N_STEP (Byte 2) From host From host N_STEP (Byte 1) From host N_STEP (Byte 0) From host The move command produces a motion of N_STEP microsteps; the direction is selected by the DIR bit ('1' forward or '0' reverse). The N_STEP value is always in agreement with the selected step mode; the parameter value unit is equal to the selected step mode (full, half, quarter, etc.). This command keeps the BUSY flag low until the target number of steps is performed. This command can only be performed when the motor is stopped. If a motion is in progress the motor must be stopped and it is then possible to perform a move command. Any attempt to perform a move command when the motor is running causes the command to be ignored and the CMD_ERROR flag to rise (Section 9.1.21). 9.2.8 GoTo (ABS_POS) Table 54. GoTo command structure Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 0 1 1 0 0 0 0 0 X X ABS_POS (Byte 2) From host From host ABS_POS (Byte 1) From host ABS_POS (Byte 0) From host The GoTo command produces a motion to the ABS_POS absolute position through the shortest path. The ABS_POS value is always in agreement with the selected step mode; the parameter value unit is equal to the selected step mode (full, half, quarter, etc.). The GoTo command keeps the BUSY flag low until the target position is reached. This command can be given only when the previous motion command has been completed (BUSY flag released). 64/73 DocID023768 Rev 6 L6482 Programming manual Any attempt to perform a GoTo command when a previous command is under execution (BUSY low) causes the command to be ignored and the CMD_ERROR flag to rise (Section 9.1.21 on page 58). 9.2.9 GoTo_DIR (DIR, ABS_POS) Table 55. GoTo_DIR command structure Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 0 1 1 0 1 0 0 DIR X X ABS_POS (Byte 2) From host From host ABS_POS (Byte 1) From host ABS_POS (Byte 0) From host The GoTo_DIR command produces a motion to the ABS_POS absolute position imposing a forward (DIR = '1') or a reverse (DIR = '0') rotation. The ABS_POS value is always in agreement with the selected step mode; the parameter value unit is equal to the selected step mode (full, half, quarter, etc.). The GoTo_DIR command keeps the BUSY flag low until the target speed is reached. This command can be given only when the previous motion command has been completed (BUSY flag released). Any attempt to perform a GoTo_DIR command when a previous command is under execution (BUSY low) causes the command to be ignored and the CMD_ERROR flag to rise (Section 9.1.21). 9.2.10 GoUntil (ACT, DIR, SPD) Table 56. GoUntil command structure Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 1 0 0 0 ACT 0 1 DIR X X X X SPD (Byte 2) From host From host SPD (Byte 1) From host SPD (Byte 0) From host The GoUntil command produces a motion at SPD speed imposing a forward (DIR = '1') or a reverse (DIR = '0') direction. When an external switch turn-on event occurs (Section 6.14 on page 30), the ABS_POS register is reset (if ACT = '0') or the ABS_POS register value is copied into the MARK register (if ACT = '1'); the system then performs a SoftStop command. The SPD value is expressed in step/tick (format unsigned fixed point 0.28) that is the same format as the SPEED register (Section 9.1.4 on page 45). The SPD value should be lower than MAX_SPEED and greater than MIN_SPEED, otherwise the target speed is imposed at MAX_SPEED or MIN_SPEED respectively. If the SW_MODE bit of the CONFIG register is set low, the external switch turn-on event causes a HardStop interrupt instead of the SoftStop one (Section 6.14 on page 30 and DocID023768 Rev 6 65/73 73 Programming manual L6482 Section 9.1.20 on page 55). This command keeps the BUSY flag low until the switch turn-on event occurs and the motor is stopped. This command can be given anytime and is immediately executed. 9.2.11 ReleaseSW (ACT, DIR) Table 57. ReleaseSW command structure Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 1 0 0 1 ACT 0 1 DIR From host The ReleaseSW command produces a motion at minimum speed imposing a forward (DIR = '1') or reverse (DIR = '0') rotation. When SW is released (opened) the ABS_POS register is reset (ACT = '0') or the ABS_POS register value is copied into the MARK register (ACT = '1'); the system then performs a HardStop command. Note that, resetting the ABS_POS register is equivalent to setting the HOME position. If the minimum speed value is less than 5 step/s or low speed optimization is enabled, the motion is performed at 5 step/s. The ReleaseSW command keeps the BUSY flag low until the switch input is released and the motor is stopped. 9.2.12 GoHome Table 58. GoHome command structure Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 0 1 1 1 0 0 0 0 From host The GoHome command produces a motion to the HOME position (zero position) via the shortest path. Note that, this command is equivalent to the “GoTo(0…0)” command. If a motor direction is mandatory, the GoTo_DIR command must be used (Section 9.2.9). The GoHome command keeps the BUSY flag low until the home position is reached. This command can be given only when the previous motion command has been completed. Any attempt to perform a GoHome command when a previous command is under execution (BUSY low) causes the command to be ignored and the CMD_ERROR to rise (Section 9.1.21 on page 58). 9.2.13 GoMark Table 59. GoMark command structure 66/73 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 0 1 1 1 1 0 0 0 DocID023768 Rev 6 From host L6482 Programming manual The GoMark command produces a motion to the MARK position performing the minimum path. Note that, this command is equivalent to the “GoTo (MARK)” command. If a motor direction is mandatory, the GoTo_DIR command must be used. The GoMark command keeps the BUSY flag low until the MARK position is reached. This command can be given only when the previous motion command has been completed (BUSY flag released). Any attempt to perform a GoMark command when a previous command is under execution (BUSY low) causes the command to be ignored and the CMD_ERROR flag to rise (Section 9.1.21 on page 58). 9.2.14 ResetPos Table 60. ResetPos command structure Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 1 1 0 1 1 0 0 0 From host The ResetPos command resets the ABS_POS register to zero. The zero position is also defined as the HOME position (Section 6.5 on page 22). 9.2.15 ResetDevice Table 61. ResetDevice command structure Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 1 1 0 0 0 0 0 0 From host The ResetDevice command resets the device to power-up conditions (Section 6.1 on page 19). The command can be performed only when the device is in high impedance state. Note: At power-up the power bridges are disabled. 9.2.16 SoftStop Table 62. SoftStop command structure Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 1 0 1 1 0 0 0 0 From host The SoftStop command causes an immediate deceleration to zero speed and a consequent motor stop; the deceleration value used is the one stored in the DEC register (Section 9.1.6 on page 45). When the motor is in high impedance state, a SoftStop command forces the bridges to exit from high impedance state; no motion is performed. This command can be given anytime and is immediately executed. This command keeps the BUSY flag low until the motor is stopped. DocID023768 Rev 6 67/73 73 Programming manual 9.2.17 L6482 HardStop Table 63. HardStop command structure Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 1 0 1 1 1 0 0 0 From host The HardStop command causes an immediate motor stop with infinite deceleration. When the motor is in high impedance state, a HardStop command forces the bridges to exit high impedance state; no motion is performed. This command can be given anytime and is immediately executed. This command keeps the BUSY flag low until the motor is stopped. 9.2.18 SoftHiZ Table 64. SoftHiZ command structure Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 1 0 1 0 0 0 0 0 From host The SoftHiZ command disables the power bridges (high impedance state) after a deceleration to zero; the deceleration value used is the one stored in the DEC register (Section 9.1.6 on page 45). When bridges are disabled, the HiZ flag is raised. When the motor is stopped, a SoftHiZ command forces the bridges to enter high impedance state. This command can be given anytime and is immediately executed. This command keeps the BUSY flag low until the motor is stopped. 9.2.19 HardHiZ Table 65. HardHiZ command structure Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 1 0 1 0 1 0 0 0 From host The HardHiZ command immediately disables the power bridges (high impedance state) and raises the HiZ flag. When the motor is stopped, a HardHiZ command forces the bridges to enter high impedance state. This command can be given anytime and is immediately executed. This command keeps the BUSY flag low until the motor is stopped. 68/73 DocID023768 Rev 6 L6482 9.2.20 Programming manual GetStatus Table 66. GetStatus command structure Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 1 1 0 1 0 0 0 0 From host STATUS MSByte To host STATUS LSByte To host The GetStatus command returns the Status register value. The GetStatus command resets the STATUS register warning flags. The command forces the system to exit from any error state. The GetStatus command DOES NOT reset the HiZ flag. DocID023768 Rev 6 69/73 73 Package information 10 L6482 Package information In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK® packages, depending on their level of environmental compliance. ECOPACK specifications, grade definitions and product status are available at: www.st.com. ECOPACK is an ST trademark. HTSSOP38 package information Figure 27. HTSSOP38 package outline   ( (  F H  ' ƒ PP $ $ 3 E $ / ‘ 3  70/73 DocID023768 Rev 6 L6482 Package information Table 67. HTSSOP38 package mechanical data Dimensions (mm) Symbol Min. A Typ. Max. - 1.1 A1 0.05 - 0.15 A2 0.85 0.9 0.95 b 0.17 - 0.27 c 0.09 - 0.20 D 9.60 9.70 9.80 E1 4.30 4.40 4.50 e - 0.50 - E - 6.40 - L 0.50 0.60 0.70 P 6.40 6.50 6.60 P1 3.10 3.20 3.30  0° - 8° Figure 28. HTSSOP38 footprint         DocID023768 Rev 6 71/73 73 Revision history 11 L6482 Revision history Table 68. Document revision history Date Revision 08-Oct-2012 1 Initial release. 2 Changed the title. Inserted footnote in Table 2 and Table 4 Removed Tj parameter in Table 3. Updated Section 9.1.10 and Section 9.1.15. Updated Table 17. Minor text changes. 3 Updated Section 6.3 (replaced “integrated MOSFETs” by “gate drivers”). Updated Section 6.9 to Section 6.13 (replaced “gates” by “MOSFETs”). Added cross-references to Section 9. Updated Section 9.1.19 (replaced “TCC parameter” by “TDT parameter”). Updated Section 9.2.15 (Added “The command can be performed only when the device is in high impedance state.”). Updated Section 10 (updated titles, reversed order of Figure 27 and Table 67). Minor modifications throughout document. 19-May-2014 4 Updated Table 2 on page 9 [added (VBOOT - VS) to VBOOT]. Updated Table 5 on page 11 (updated IVREGqu and IVREGq symbols, values of thigh,STCK, tlow,STCK, and thigh symbols). Updated Table 7 on page 18 (replaced STD25NF10 by STD25N10F7). Updated Section 6.1 on page 19 (removed VCC and VBOOT, added FLAG output...). Updated Section 6.4 on page 20 (replaced “the first microstep” by “zero”). Removed Section “Infinite acceleration/deceleration mode” from page 23. Replaced NOTPERF_CMD and WRONG_CMD flag by CMD_ERROR flag throughout document. Updated Section 9.1.5 on page 45 (replaced sentence: “When the ACC value is set to 0xFFF, the device works in infinite acceleration mode.” by “The 0xFFF value of the register is reserved and it should never be used.”). Updated Section 9.1.6 on page 45 (removed sentence: “When the device is working in infinite acceleration mode this value is ignored.”). Updated Section 9.1.20 on page 55 (replaced PRED_E and EN_PRED by PRED_EN). Updated Table 43 on page 58 (replaced TH_SD by TH_STATUS). Updated title of Table 46 on page 59 (replaced MOT_STATE by MOT_STATUS). Updated cross-references throughout document. 05-Mar-2015 5 Updated main title on page 1 (removed cSPIN™). Updated Table 11 on page 43 (h15 - Len. [bit]: replaced 10 by 11). 23-Mar-2015 6 Updated Table 14 on page 47 (“Bit 11” removed). Minor modifications throughout document. 19-Dec-2012 13-Dec-2013 72/73 Changes DocID023768 Rev 6 L6482 IMPORTANT NOTICE – PLEASE READ CAREFULLY STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on ST products before placing orders. ST products are sold pursuant to ST’s terms and conditions of sale in place at the time of order acknowledgement. Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or the design of Purchasers’ products. No license, express or implied, to any intellectual property right is granted by ST herein. Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product. ST and the ST logo are trademarks of ST. All other product or service names are the property of their respective owners. Information in this document supersedes and replaces information previously supplied in any prior versions of this document. © 2015 STMicroelectronics – All rights reserved DocID023768 Rev 6 73/73 73