L6498LDTR

L6498 High voltage high and low-side 2 A gate driver Datasheet - production data Description SO-8 SO-14 Features  Transient withstand voltage 600 V  dV/dt immunity ± 50 V/ns in full temperature range The L6498 is a high voltage device manufactured with the BCD6 “OFF-LINE” technology. It is a single chip half-bridge gate driver for the N-channel power MOSFET or IGBT. The high-side (floating) section is designed to stand a DC voltage rail up to 500 V, with 600 V transient withstand voltage. The logic inputs are CMOS/TTL compatible down to 3.3 V for easy interfacing control units such as microcontrollers or DSP. Both device outputs can sink 2.5 A and source 2 A, making the L6498 particularly suited for medium and high capacity power MOSFETs\IGBTs.  Driver current capability: – 2 A source typ. at 25 °C – 2.5 A sink typ. at 25 °C  Short propagation delay: 85 ns  Switching times 25 ns rise/fall with 1 nF load  3.3 V, 5 V TTL/CMOS inputs with hysteresis  Integrated bootstrap diode  Interlocking function  UVLO on both high-side and low-side sections  Compact and simplified layout The outputs cannot be simultaneously driven high thanks to an integrated interlocking function. The independent UVLO protection circuits present on both the lower and upper driving sections prevent the power switches from being operated in low efficiency or dangerous conditions. The integrated bootstrap diode as well as all of the integrated features of this driver make the application PCB design simpler and more compact, and help to reduce the overall bill of material.  Bill of material reduction  Flexible, easy and fast design Applications  Motor driver for home appliances, factory automation, industrial drives and fans  HID ballasts  Power supply units  DC-DC converters  Induction heating  Wireless chargers  Industrial inverters  UPS  Welding September 2017 This is information on a product in full production. DocID030318 Rev 3 1/20 www.st.com Contents L6498 Contents 1 Block diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 2 Pin description and connection diagram . . . . . . . . . . . . . . . . . . . . . . . . 4 3 Electrical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 3.1 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 3.2 Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 3.3 Recommended operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 4 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 5 Truth table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 6 Typical application diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 7 Bootstrap driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 CBOOT selection and charging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 8 Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 8.1 SO-8 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 8.2 SO-14 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 9 Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 10 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 2/20 DocID030318 Rev 3 L6498 Block diagrams 1 Block diagrams Figure 1. Block diagram SO-8       7$$  (/%  ". Figure 2. Block diagram SO-14       7$$  1(/%   ". DocID030318 Rev 3 3/20 20 Pin description and connection diagram 2 L6498 Pin description and connection diagram Figure 3. Pin connection SO-8 (top view) )*/   #005 -*/   )7( (/%   065 -7(   7$$ ". Figure 4. Pin connection SO-14 (top view) )*/   /$ -*/   #005 4(/%   )7( /$   065 1(/%   /$ -7(   /$ 7$$   /$ ". Table 1. Pin description Pin no. Pin name Type Function 1 HIN I High-side driver logic input (active high) 2 2 LIN I Low-side driver logic input (active high) 3 - GND P Device ground O Low-side driver output SO-8 SO-14 1 (1) 4 6 LVG 5 7 VCC P Lower section supply voltage 6 11 OUT P High-side (floating) common voltage 7 12 HVG(1) O High-side driver output 8 13 BOOT P Bootstrapped supply voltage - 3 SGND P Signal ground - 5 PGND P Power ground - 4, 8, 9, 10, 14 NC - Not connected 1. The circuit guarantees less than 1 V on the LVG and HVG pins (at Isink = 10 mA), with VCC > 3 V. This allows omitting the “bleeder” resistor connected between the gate and the source of the external MOSFET normally used to hold the pin low. 4/20 DocID030318 Rev 3 L6498 Electrical data 3 Electrical data 3.1 Absolute maximum ratings Table 2. Absolute maximum ratings(1) Value Symbol VCC VPGND VOUT VBOOT Parameter Supply voltage Low-side driver ground Output voltage Boot DC voltage Boot transient withstand voltage (Tpulse < 1 ms) Unit Min. Max. -0.3 21 V VCC - 21 VCC + 0.3 V VBOOT - 21 VBOOT + 0.3 V -0.3 500 V - 620 V Vhvg High-side gate output voltage VOUT - 0.3 VBOOT + 0.3 V Vlvg Low-side gate output voltage (P)GND - 0.3 VCC + 0.3 V Vi Logic input pins voltage -0.3 15 V dVOUT/dt Allowed output slew rate - 50 V/ns Total power dissipation (TA = 25 °C) SO-14 - 1 W TJ Junction temperature - 150 °C Tstg Storage temperature -50 150 °C ESD Human body model PTOT 2 kV 1. Each voltage referred to GND\SGND unless otherwise specified. 3.2 Thermal data Table 3. Thermal data Symbol Rth(JA) Parameter Thermal resistance junction to ambient DocID030318 Rev 3 Package Value SO-8 185 SO-14 120 Unit °C/W 5/20 20 Electrical data 3.3 L6498 Recommended operating conditions Table 4. Recommended operating conditions Symbol Pin VCC VCC VPS(1) VBO(2) Parameter Min. Max. Unit - 10 20 V - -5 +5 V - 9.3 20 V - 9(3) 480 V Tpulse < 1 ms - 600 V HVG, LVG load CL = 1 nF - 800 kHz - -40 125 °C - -40 125 °C Supply voltage SGND - PGND Low-side driver ground BOOT - OUT Floating supply voltage DC output voltage VOUT OUT fSW - Maximum switching frequency TJ - Junction temperature TA Test condition - OUT transient withstand voltage Ambient temperature(4) 1. VPS = VPGND - SGND. 2. VBO = VBOOT - VOUT. 3. LVG off. VCC = 12.5 V. Logic is operational if VBOOT > 5 V. 4. Maximum ambient temperature is actually limited by TJ. 6/20 DocID030318 Rev 3 - L6498 Electrical characteristics 4 Electrical characteristics Table 5. Electrical characteristics (VCC = 15 V; TJ = +25 °C; PGND = SGND Symbol Pin Parameter Test condition Min. Typ. Max. Unit Low-side section supply VCC_hys VCC _thON VCC _thOFF VCC vs. (S)GND IQCCU IQCC VCC UV hysteresis - 0.5 0.6 0.72 V VCC UV turn ON threshold - 8.7 9.3 9.8 V VCC UV turn OFF threshold - 8.2 8.7 9.2 V Undervoltage quiescent supply current VCC = 7 V LIN = GND; HIN = GND - 160 210 µA Quiescent current VCC = 15 V LIN = 5 V; HIN = GND - 340 480 µA High-side floating section supply(1) VBO_hys VBO UV hysteresis - 0.48 0.6 0.7 V VBO UV turn ON threshold - 8.0 8.6 9.1 V VBO UV turn OFF threshold - 7.5 8.0 8.5 V Undervoltage VBO quiescent current VBO = 7 V LIN = GND; HIN = 5 V - 20 30 µA VBO quiescent current VBO = 15 V LIN = GND; HIN = 5 V - 90 120 µA - High voltage leakage current Vhvg = VOUT = VBOOT = 600 V - - 8 µA - Bootstrap diode on resistance(2) - - 175 -  LVG/HVG ON TJ = 25 °C 1.7 2 - A Full temperature range 1.4 - - A 2 2.5 - A Full temperature range 1.55 - - A - 0.95 - 1.45 V - 2 - 2.5 V VBO_thON VBO_thOFF BOOT vs. OUT IQBOU IQBO ILK RDS(on) Output driving buffers High/low-side source shortcircuit current Iso LVG, HVG High/low-side sink short-circuit current Isi LVG/HVG ON TJ = 25 °C Logic inputs Vil Vih IHINh IHINl ILINl ILINh Low level logic threshold voltage LIN, HIN vs. (S)GND High level logic threshold voltage HIN vs. (S)GND HIN logic “1” input bias current HIN = 15 V 120 200 260 µA HIN logic “0” input bias current HIN = 0 V - - 1 µA LIN vs. (S)GND LIN logic “1” input bias current LIN = 15 V 120 200 260 µA LIN logic “0” input bias current LIN = 0 V - - 1 µA DocID030318 Rev 3 7/20 20 Electrical characteristics L6498 Table 5. Electrical characteristics (VCC = 15 V; TJ = +25 °C; PGND = SGND (continued) Symbol RPD Pin Parameter Test condition LIN, HIN Logic inputs pull-down resistor vs. (S)GND Min. Typ. Max. Unit - 58 75 125 k - 85 120 ns - 85 120 ns Dynamic characteristics (see Figure 5) toff HIN vs. HVG; LIN vs. LVG MT - ton tr tf LVG, HVG VOUT = 0 V; VBOOT = VCC; CL = 1 nF; Vi = 0 to 3.3 V High/low-side driver turn-on propagation delay High/low-side driver turn-off propagation delay Delay matching, HS and LS turn-on/off(3) - - - 30 ns Rise time CL = 1 nF - 25 - ns Fall time CL = 1 nF - 25 - ns 1. VBO = VBOOT - VOUT. 2. RDSON is tested in the following way: RDSON = [(VCC - VBOOT1) - (VCC - VBOOT2)] / [I1 (VCC, VBOOT1) - I2(VCC, VBOOT2)] where I1 is BOOT pin current when VBOOT = VBOOT1, I2 when VBOOT = VBOOT2. 3. MT = max. (|ton (LVG) - toff (LVG)|, |ton (HVG) - toff (HVG)|, |toff (LVG) - ton (HVG)|, |toff (HVG) - ton (LVG)|). Figure 5. Timing -*/)*/   US UG  -7()7(    U PO U PGG ". 8/20 DocID030318 Rev 3 L6498 5 Truth table Truth table Table 6. Truth table Input LIN HIN LVG HVG L L L L L H L H H L H L H (1) H 1. Output L L(1) Interlocking function. DocID030318 Rev 3 9/20 20 Typical application diagram 6 L6498 Typical application diagram Figure 6. Typical application diagram 7$$ 7$$ #005  $ 7$$ $CPPU '30.
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HSPVOE 1(/% ". Figure 7. Suggested PCB layout (SO-8) 10/20 DocID030318 Rev 3 L6498 Typical application diagram Figure 8. Suggested PCB layout (SO-14) DocID030318 Rev 3 11/20 20 Bootstrap driver 7 L6498 Bootstrap driver A bootstrap circuitry is needed to supply the high voltage section. This function is usually accomplished by a high voltage fast recovery diode (Figure 9). In the L6498 an integrated structure replaces the external diode. CBOOT selection and charging To choose the proper CBOOT value the external MOS can be seen as an equivalent capacitor. This capacitor CEXT is related to the MOS total gate charge: Equation 1 Q gate C EXT = -------------V gate The ratio between the capacitors CEXT and CBOOT is proportional to the cyclical voltage loss. It has to be: Equation 2 C BOOT >>>C EXT if Qgate is 30 nC and Vgate is 10 V, CEXT is 3 nF. With CBOOT = 100 nF the drop is 300 mV. If HVG has to be supplied for a long time, the CBOOT selection has also to take into account the leakage and quiescent losses. HVG steady-state consumption is lower than 120 A, so if HVG TON is 5 ms, CBOOT has to supply 0.6 C. This charge on a 1 F capacitor means a voltage drop of 0.6 V. The internal bootstrap driver gives a great advantage: the external fast recovery diode can be avoided (it usually has great leakage current). This structure can work only if VOUT is close to SGND (or lower) and in the meanwhile the LVG is on. The charging time (Tcharge) of the CBOOT is the time in which both conditions are fulfilled and it has to be long enough to charge the capacitor. The bootstrap driver introduces a voltage drop due to the DMOS RDS(on) (typical value: 175 ). At low frequency this drop can be neglected. Anyway, the rise of frequency has to take into account. The following equation is useful to compute the drop on the bootstrap DMOS: Equation 3 Q gate V drop = I ch arg e R DS  on   V drop = ------------------R DS  on  T ch arg e where Qgate is the gate charge of the external power MOS, RDS(on) is the on resistance of the bootstrap DMOS and Tcharge is the charging time of the bootstrap capacitor. 12/20 DocID030318 Rev 3 L6498 Bootstrap driver For example: using a power MOS with a total gate charge of 30 nC the drop on the bootstrap DMOS is about 1 V, if the Tcharge is 5 s. In fact: Equation 4 30nC V drop = ---------------  175  1V 5s Vdrop has to be taken into account when the voltage drop on CBOOT is calculated: if this drop is too high, or the circuit topology doesn’t allow a sufficient charging time, an external diode can be used. Figure 9. Bootstrap driver with external high voltage fast recovery diode DBOOT VCC BOOT H.V. HVG CBOOT OUT TO LOAD LVG DocID030318 Rev 3 13/20 20 Package information 8 L6498 Package information In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK® packages, depending on their level of environmental compliance. ECOPACK® specifications, grade definitions and product status are available at: www.st.com. ECOPACK® is an ST trademark. 14/20 DocID030318 Rev 3 L6498 8.1 Package information SO-8 package information Figure 10. SO-8 package outline Table 7. SO-8 package mechanical data Dimensions (mm) Symbol Notes Min. Typ. Max. A - - 1.75 - A1 0.10 - 0.25 - A2 1.25 - - - b 0.28 - 0.48 - c 0.17 - 0.23 - D 4.80 4.90 5.00 - E 5.80 6.00 6.20 - E1 3.80 3.90 4.00 - e - 1.27 - - h 0.25 - 0.50 - L 0.40 - 1.27 - L1 - 1.04 - - k 0 - 8 Degrees ccc - - 0.10 - DocID030318 Rev 3 15/20 20 Package information L6498 Figure 11. SO-8 suggested land pattern 0.6 1.27 3.9 6.7 16/20 DocID030318 Rev 3 L6498 8.2 Package information SO-14 package information Figure 12. SO-14 package outline Table 8. SO-14 package mechanical data Dimensions (mm) Symbol Min. Typ. Max. A 1.35 - 1.75 A1 0.10 - 0.25 A2 1.10 - 1.65 B 0.33 - 0.51 C 0.19 - 0.25 D 8.55 - 8.75 E 3.80 - 4.00 e - 1.27 - H 5.80 - 6.20 h 0 - - 25 - 0.50 - L 0.40 - 1.27 k 0 - 8 ddd - - 0.10 DocID030318 Rev 3 17/20 20 Package information L6498 Figure 13. SO-14 suggested land pattern 0.6 1.27 4.0 6.7 18/20 DocID030318 Rev 3 L6498 9 Ordering information Ordering information Table 9. Device summary 10 Order code Package Packaging L6498D SO-8 Tube L6498DTR SO-8 Tape and reel L6498LD SO-14 Tube L6498LDTR SO-14 Tape and reel Revision history Table 10. Document revision history Date Revision Changes 08-Feb-2017 1 Initial release. 26-Apr-2017 2 Updated Table 5 on page 7 (replaced “INR_PD” by “RPD”, added Test condition to “toff”). Updated order codes in Table 9 on page 19. Minor modifications throughout document. 13-Sep-2017 3 Updated Table 4 on page 6 (added TA symbol and note 4.). DocID030318 Rev 3 19/20 20 L6498 IMPORTANT NOTICE – PLEASE READ CAREFULLY STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on ST products before placing orders. ST products are sold pursuant to ST’s terms and conditions of sale in place at the time of order acknowledgement. Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or the design of Purchasers’ products. No license, express or implied, to any intellectual property right is granted by ST herein. Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product. ST and the ST logo are trademarks of ST. All other product or service names are the property of their respective owners. Information in this document supersedes and replaces information previously supplied in any prior versions of this document. © 2017 STMicroelectronics – All rights reserved 20/20 DocID030318 Rev 3