L6560D

® L6560 L6560A POWER FACTOR CORRECTOR VERY PRECISE ADJUSTABLE INTERNAL OUTPUT OVERVOLTAGE PROTECTION HYSTERETIC START-UP (ISTART-UP < 0.5mA) VERY LOW QUIESCENT CURRENT (< 3.5mA) INTERNAL START-UP TIMER TRANSITION MODE OPERATING TOTEM POLE OUTPUT CURRENT: ±400mA DIP8/SO8 PACKAGES DESCRIPTION The L6560/A is a monolithic integrated circuit in Minidip and SO8 packages, designed as a controller and driver of a discrete power MOS transistor for the implementation of active power factor correction, for sinusoidal line current consumption. Realized in mixed BCD technology, the chip integrates: - An undervoltage lockout with micropower startup and hysteresis. - An internal temperature compensated precise band gap reference. - A stable error amplifier. BLOCK DIAGRAM MULTIPOWER BCD TECHNOLOGY Minidip SO8 ORDERING NUMBERS: L6560 L6560D L6560A L6560AD - One quadrant multiplier. - Current sense comparator. - An output overvoltage protection circuit. - A totem-pole output stage able to drive a POWER MOS or IGBT devices with source and sink current of 400mA. The chip works in transition mode and is particularly intended for lamp ballast applications and for low power SMPS. June 2000 1/11 L6560 - L6560A ABSOLUTE MAXIMUM RATINGS Symbol IVcc IGD INV, COMP MULT CS ZCD Ptot Tj Tstg Pin 8 7 1, 2, 3 4 5 ICC + IZ Output Totem Pole Peak Current (2µs) Analog Inputs & Outputs Current Sense Input Zero Current Detector Power Dissipation @Tamb = 50 °C Junction Temperature Operating Range Storage Temperature (Minidip) (SO8) Parameter Value 30 ±700 -0.3 to 7 -0.3 to 7 5 (source) 10 (sink) 1 0.65 -25 to 150 -55 to 150 Unit mA mA V V mA mA W °C °C PIN CONNECTION THERMAL DATA Symbol Rth j-amb Parameter Thermal Resistance Junction-ambient SO 8 150 MINIDIP 100 Unit °C/W PIN FUNCTIONS N. 1 2 3 4 5 6 7 8 2/11 Name INV COMP MULT CS ZCD GND GD VCC Function Inverting input of the error amplifier. A resistive divider is connected between output regulated voltage and this point, to provide the voltage feedback. Output of error amplifier. A feedback compensation network is placed between this pin and the INV pin. Input of the multipler stage. A resistive divider connects to this pin the rectified mains. A voltage signal, proportional to the rectified mains, appears on this pin. Input to the comparator of the control loop. The current is sensed by a resistor and the resulting voltage is applied to this pin. Zero current detection input. Ground of the control section. Gate driver output. A push pull output stage is able to drive the Power MOS with peak current of 400mA (source and sink). Supply voltage of driver and control circuits. L6560 - L6560A ELECTRICAL CHARACTERISTICS (VCC = 14.5V; Tj = 25°C unless otherwise specified) SUPPLY VOLTAGE SECTION Symbol VCC VCC ON VCC OFF Hys Pin 8 8 8 8 Parameter Operating Range Turn-on Threshold Turn-off Threshold Hysteresis Test Condition after turn-on L6560 L6560A L6560 L6560A L6560 L6560A Min. 11 13.5 11 9 8.7 4.3 2.5 14.5 12 10 9.6 4.7 2.8 Typ. Max. 18 15.5 13 11 10.5 5.1 3.1 Unit V V v V V V V SUPPLY CURRENT SECTION Symbol ISTART-U Pin 8 Parameter Start-up Current Test Condition before turn-on at: VCC = 13V (L6560) VCC = 10.5V (L6560A) CL = 0nF @ 70KHz CL = 1nF @ 70KHz in OVP condition Vpin1 = 2.7V VZ 8 Zener Voltage ICC = 25mA 18 Min. Typ. 0.3 Max. 0.5 Unit mA ICC 8 Operating Supply Current 2.5 3.2 0.9 20 3.5 4 1.3 22 mA mA mA V ERROR AMPLIFIER SECTION Symbol VINV TS RL IINV GV ICOMP 2 1 Pin 1 Parameter Voltage Feedback Input Threshold Temperature Stability Line Regulation Input Bias Current Voltage Gain Source Current (V1 < Vref) Sink Current (V1 > Vref) Open loop VCOMP = 5V 60 0.14 0.5 Test Condition –25 ≤ TJ ≤ 85°C; 12V < VCC < 18V Tamb = -25 to 85°C VCC = 11 to 18V Min. 2.46 2.43 0.5 1 0.1 80 0.2 1 4 1 Typ. 2.5 Max. 2.54 2.56 % mV µA dB mA mA Unit V MULTIPLIER SECTION Symbol VMULT ∆VCS ∆Vmult K Pin 3 Parameter Operating Voltage Output Max. Slope VMULT = from 0V to 1V VCOMP = 6V VMULT = 1V VCOMP = 5V Test Condition Min. 0.9 Typ. 1.25 Max. 1.6 Unit V 0 to 2.5 0 to 4.2 Gain 0.45 0.65 0.85 1/V CURRENT SENSE COMPARATOR Symbol VCS ICS td (H-L) Pin 4 4 4 Parameter Voltage Threshold Input Bias Current Delay to Output 200 Test Condition VMULT = 2.5V VCOMP = 6V Min. 1.6 Typ. Max. 1.9 5 400 Unit V µA ns 3/11 L6560 - L6560A ELECTRICAL CHARACTERISTICS (continued) ZERO CURRENT DETECTOR Symbol VZCD Pin 5 Parameter Input Threshold Voltage Rising Edge Hysteresis VZCD VZCD 5 5 Clamp Voltage Clamp Voltage IZCD = 3mA IZCD = –3mA Test Condition Min. 1.8 0.3 5 0.4 0.5 5.7 0.7 Typ. Max. 2.3 0.7 6.4 1 Unit V V V V OUTPUT SECTION Symbol VGD Pin 7 Parameter Dropout Voltage Test Condition IGDsource = 200mA IGDsource = 20mA IGDsink = 200mA IGDsink = 20mA tr tf 7 7 Output Voltage Rise Time Output Voltage Fall Time CL = 1nF CL = 1nF 50 40 Min. Typ. 1.2 0.7 Max. 2 1 1.5 0.3 120 100 Unit V V V V ns ns OUTPUT OVERVOLTAGE SECTION Symbol IOVP Pin 2 Parameter OVP Triggering Current Test Condition Min. 36 Typ. 40 Max. 44 Unit µA RESTART TIMER Symbol tSTART Pin Parameter Start Timer Test Condition Min. 45 Typ. 60 Max. Unit µs OVER VOLTAGE PROTECTION OVP The output voltage is expected to be kept by the operation of the PFC circuits close to its reference value that is set by the ratio of the two external resistors R1 and R2 (see fig. 2), taking into consideration that the non inverting input of the error amplifier is biased inside the L6560 at 2.5V. In steady state conditions, the current through R1 and R2 is: ISC = ∆Voutsc − 2.5 R1 2.5 or ISC = R2 IR1 = Voutsc + ∆VOUT − 2.5 = Isc + ∆I. R1 and, if the external compensation network is made only with a capacitor C, the current through C is equal zero. When the output voltage increases abruptly the current through R1 becomes: IR1 = Vout − 2.5 R1 Since the current through R2 doesn’t change, the ∆I current must flow through the capacitor C and enter in the error amplifier. This current is mirrored inside the L6560, and compared with a precise internal reference of 40µA. Whenever such 40µA limit is exceed, the OVP protection is triggered (Dynamic OVP), and the external power transistor is switched off, until the overvoltage situation disappears. However if the overvoltage persists, before that the transient condition of dynamic circuit exhausts, an internal comparator (Static OVP) latches the OVP condition keeping the external power switch turned off (see fig. 1). The OVP value is threfore set by the equation OVP = ∆Vout = R1 ⋅ 40µA. Typical values for R1, R2 and C are reported in the application circuit. The overvoltage can be set independently from the average output voltage. The precision in setting the overvoltage threshold is 7% of the overvoltage value (for instance ∆V = 60V ± 4.2V). 4/11 L6560 - L6560A Figure 1. OVER VOLTAGE VOUT nominal 40µA ISC E/A OUTPUT 3.1V DYNAMIC OVP STATIC OVP D95IN219A Figure 2: Overvoltage Protection Circuit Ccomp. +Vo R1 1 R2 + 2.5V 3.1V ∆I + E/A ∆I 2 X PWM DRIVER 40µA D93IN035B 5/11 L6560 - L6560A Figure 3: Typical Application Circuit (100W) D1 BYT03-400 C6 T R7 1.5M 1% C3 330nF + Vo=240V Po=100W R3 68K 5% BRIDGE + 4 x BY255 FUSE 4A/250V Vac (85V to 135V) R10 16K 1% D3 1N4150 D2 1N5248B R2 100 5% 10nF R1 68K 5% 5 2 1 7 4 R4 330 C7 10nF C4 1nF R6 0.33 1W R8 16K 1% D94IN050B C1 1µF 250V R9 1.5M 1% 8 L6560 3 C2 22µF 25V 6 R5 10 MOS IRF740 C5 150µF 315V - TRANSFORMER T: core THOMSON-CSF B1ET2910A (ETD 29 x 16 x 10mm) OR EQUIVALENT primary 90T of Litz wire 10 x 0.2mm secondary 11T of #27 AWG (0.15mm) gap 1.9mm for a total primary inductance of 0.6mH Figure 4: Typical Application Circuit (120W) D1 BYT13-600 C6 T R7 1M 1% + Vo=400V Po=120W R3 220K 5% BRIDGE + 4 x BY255 FUSE 4A/250V Vac (175V to 265V) R10 6.2K 1% D3 1N4150 D2 1N5248B R2 100 5% 4.7nF C3 1µF R1 68K 5% 5 2 1 7 4 R4 330 C7 10nF C4 1nF R6 0.4 1W R8 6.34K 1% D94IN049A C1 1µF 400V R9 1.8M 1% 8 L6560 3 C2 22µF 25V 6 R5 10 MOS STP8NA50 C5 47µF 450V - TRANSFORMER T: core THOMSON-CSF B1ET2910A (ETD 29 x 16 x 10mm) OR EQUIVALENT primary 90T of Litz wire 10 x 0.2mm secondary 7T of #27 AWG (0.15mm) gap 1.25mm for a total primary inductance of 0.8mH 6/11 L6560 - L6560A F igure 5: P.C. Board and Component Layout of the Figg. 3 and 4 (1:1.25 scale) Figure 6: OVPCurrent Threshold vs. Temperature D94IN047 Figure 7: Undervoltage Lockout Threshold vs. Temperature VCC-TH-ON (V) 14 D94IN044 IOVP (mA) 42 13 41 12 VCC-TH-OFF (V) 10 9 40 39 -50 -25 0 25 50 75 100 125 T (°C) -25 0 25 50 T (°C) 75 100 125 7/11 L6560 - L6560A Figure 9: Voltage Feedback Input Threshold vs. Temperature VREF (V) D94IN048 Figure 8: Supply Current vs. Supply Voltage ICC (mA) 4 CL = 1nF f = 70KHz TA = 25°C D94IN045 2.50 3 2 2.48 1 0 -5 0 5 10 15 20 VCC(V) 2.46 -50 0 50 100 T (°C) Figure 10: Output Saturation Voltage vs. Sink Current VPIN7 (V) VCC = 14.5V 2.0 D94IN046 Figure 11: Output Saturation Voltage vs. Source Current VPIN7 (V) VCC = 14.5V VCC -0.5 D94IN053 SINK 1.5 VCC -1.0 1.0 VCC -1.5 0.5 VCC -2.0 SOURCE 0 0 100 200 300 400 IGD (mA) 0 0 100 200 300 400 IGD (mA) Figure 12: Multiplier Characteristics Family VCS(pin4) (V) 1.8 1.6 1.4 1.2 1.0 0.8 0.6 0.4 0.2 0.0 -1.0 0.0 1.0 2.0 3.0 VMULT(pin3) (V) 4.0 5.0 3.7 3.9 D94IN042 Figure 13: Multiplier Characteristics Family (V) 5.7 5.1 4.7 VCOMP(pin2) VCS (pin4) (mV) 550 500 450 400 350 300 250 200 150 100 50 0 -200 -100 D94IN043 VCOMP 5.7 4.3 4.1 5.1 4.7 4.3 4.1 3.9 3.7 3.6 0 100 200 VMULT (pin3) (mV) 300 400 3.6 8/11 L6560 - L6560A DIM. MIN. A a1 B b b1 D E e e3 e4 F I L Z 3.18 7.95 0.51 1.15 0.356 0.204 mm TYP. 3.32 0.020 1.65 0.55 0.304 10.92 9.75 2.54 7.62 7.62 6.6 5.08 3.81 1.52 0.125 0.313 0.045 0.014 0.008 MAX. MIN. inch TYP. 0.131 MAX. OUTLINE AND MECHANICAL DATA 0.065 0.022 0.012 0.430 0.384 0.100 0.300 0.300 0.260 0.200 0.150 0.060 Minidip 9/11 L6560 - L6560A mm MIN. A a1 a2 a3 b b1 C c1 D (1) E e e3 F (1) L M S 3.8 0.4 4.8 5.8 1.27 3.81 4.0 1.27 0.6 8 ° (max.) 0.15 0.016 0.65 0.35 0.19 0.25 0.1 TYP. MAX. 1.75 0.25 1.65 0.85 0.48 0.25 0.5 0.026 0.014 0.007 0.010 0.004 MIN. inch TYP. MAX. 0.069 0.010 0.065 0.033 0.019 0.010 0.020 DIM. OUTLINE AND MECHANICAL DATA 45° (typ.) 5.0 6.2 0.189 0.228 0.050 0.150 0.157 0.050 0.024 0.197 0.244 SO8 (1) D and F do not include mold flash or protrusions. Mold flash or potrusions shall not exceed 0.15mm (.006inch). 10/11 L6560 - L6560A I nformation furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specification mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is a registered trademark of STMicroelectronics © 2000 STMicroelectronics – Printed in Italy – All Rights Reserved STMicroelectronics GROUP OF COMPANIES Australia - Brazil - China - Finland - France - Germany - Hong Kong - India - Italy - Japan - Malaysia - Malta - Morocco Singapore - Spain - Sweden - Switzerland - United Kingdom - U.S.A. http://www.st.com 11/11