L6561D013TR

L6561 POWER FACTOR CORRECTOR 1 ■ ■ FEATURES VERY PRECISE ADJUSTABLE OUTPUT OVERVOLTAGE PROTECTION MICRO POWER START-UP CURRENT (50µA TYP.) VERY LOW OPERATING SUPPLY CURRENT(4mA TYP.) INTERNAL START-UP TIMER CURRENT SENSE FILTER ON CHIP DISABLE FUNCTION 1% PRECISION (@ Tj = 25°C) INTERNAL REFERENCE VOLTAGE TRANSITION MODE OPERATION TOTEM POLE OUTPUT CURRENT: ±400mA DIP-8/SO-8 PACKAGES Figure 1. Packages DIP-8 SO-8 ■ Table 1. Order Codes Part Number L6561 L6561D L6561D013TR Package DIP-8 SO-8 Tape & Reel ■ ■ ■ ■ ■ ■ ■ 2 DESCRIPTION L6561 is the improved version of the L6560 standard Power Factor Corrector. Fully compatible with the standard version, it has a superior performant multiplier making the device capable of working in wide input voltage range applications (from 85V to 265V) with an excellent THD. Furthermore the start up current has been reduced at few tens of mA and a disable function has been implemented on the ZCD pin, guaranteeing lower current consumption in stand by mode. Figure 2. Block Diagram COMP 2 INV 1 2.5V + Realised in mixed BCD technology, the chip gives the following benefits: – micro power start up current – 1% precision internal reference voltage – (Tj = 25°C) – Soft Output Over Voltage Protection – no need for external low pass filter on the current sense – very low operating quiescent current minimises power dissipation The totem pole output stage is capable of driving a Power MOS or IGBT with source and sink currents of ±400mA. The device is operating in transition mode and it is optimised for Electronic Lamp Ballast application, AC-DC adaptors and SMPS. MULT 3 4 40K CS MULTIPLIER VOLTAGE REGULATOR OVER-VOLTAGE DETECTION - + 5pF VCC 8 VCC INTERNAL SUPPLY 7V R1 + UVLO R S DRIVER Q 7 20V GD R2 VREF2 2.1V 1.6V ZERO CURRENT DETECTOR STARTER 6 GND June 2004 + DISABLE 5 ZCD D97IN547E REV. 16 1/13 L6561 Table 2. Absolute Maximum Ratings Symbol IVcc IGD INV, COMP MULT CS ZCD Ptot Tj Tstg Pin 8 7 1, 2, 3 4 5 Iq + IZ; (IGD = 0) Output Totem Pole Peak Current (2µs) Analog Inputs & Outputs Current Sense Input Zero Current Detector Power Dissipation @Tamb = 50 °C Junction Temperature Operating Range Storage Temperature (DIP-8) (SO-8) Parameter Value 30 ±700 -0.3 to 7 -0.3 to 7 50 (source) -10 (sink) 1 0.65 -40 to 150 -55 to 150 Unit mA mA V V mA mA W W °C °C Figure 3. Pin Connection (Top view) INV COMP MULT CS 1 2 3 4 DIP8 8 7 6 5 VCC GD GND ZCD Table 3. Thermal Data Symbol Rth j-amb Parameter Thermal Resistance Junction to ambient SO 8 150 MINIDIP 100 Unit °C/W Table 4. Pin Description N. 1 2 3 4 5 6 7 8 Name INV COMP MULT CS ZCD GND GD VCC Function Inverting input of the error amplifier. A resistive divider is connected between the output regulated voltage and this point, to provide voltage feedback. Output of error amplifier. A feedback compensation network is placed between this pin and the INV pin. Input of the multiplier stage. A resistive divider connects to this pin the rectified mains. A voltage signal, proportional to the rectified mains, appears on this pin. Input to the comparator of the control loop. The current is sensed by a resistor and the resulting voltage is applied to this pin. Zero current detection input. If it is connected to GND, the device is disabled. Current return for driver and control circuits. Gate driver output. A push pull output stage is able to drive the Power MOS with peak current of 400mA (source and sink). Supply voltage of driver and control circuits. (1) Parameter guaranteed by design, not tested in production. 2/13 L6561 Table 5. Electrical Characteristics (VCC = 14.5V; Tamb = -25°C to 125°C;unless otherwise specified) Symbol VCC VCC ON VCC OFF Hys ISTART-U Iq ICC Iq VZ VINV Pin 8 8 8 8 8 8 8 8 8 8 1 Zener Voltage Voltage Feedback Input Threshold Line Regulation IINV GV GB ICOMP VCOMP 2 2 1 Input Bias Current Voltage Gain Gain Bandwidth Source Current Sink Current Upper Clamp Voltage Lower Clamp Voltage MULTIPLIER SECTION VMULT ∆V CS ----------------∆V mult K VCS ICS td (H-L) 4 4 4 4 VZCD 5 3 Linear Operating Voltage Output Max. Slope VMULT = from 0V to 0.5V VCOMP = Upper Clamp Voltage VMULT = 1V VCOMP = 4V VMULT = 2.5V VCOMP = Upper Clamp Voltage VOS = 0 0 to 3 1.65 0 to 3.5 1.9 V VCOMP = 4V, VINV = 2.4V VCOMP = 4V, VINV = 2.6V ISOURCE = 0.5mA ISink = 0.5mA -2 2.5 Open loop 60 ERROR AMPLIFIER SECTION Tamb = 25°C 12V < VCC < 18V VCC = 12 to 18V 2.465 2.44 2 -0.1 80 1 -4 4.5 5.8 2.25 -8 2.5 2.535 2.56 5 -1 V V mV µA dB MHz mA mA V V Parameter Operating Range Turn-on Threshold Turn-off Threshold Hysteresis Start-up Current Quiescent Current Operating Supply Current Quiescent Current CL = 1nF @ 70KHz in OVP condition Vpin1 = 2.7V VPIN5 ≤150mV, VCC > VCC off VPIN5 ≤ 150mV, VCC < VCC off ICC = 25mA 20 18 before turn-on (VCC =11V) Test Condition after turn-on Min. 11 11 8.7 2.2 20 12 9.5 2.5 50 2.6 4 1.4 1.4 50 20 Typ. Max. 18 13 10.3 2.8 90 4 5.5 2.1 2.1 90 22 Unit V V V V µA mA mA mA mA µA V SUPPLY VOLTAGE SECTION SUPPLY CURRENT SECTION Gain Current Sense Reference Clamp Input Bias Current Delay to Output Current Sense Offset Input Threshold Voltage Rising Edge Hysteresis Upper Clamp Voltage Upper Clamp Voltage (1) (1) 0.45 1.6 0.6 1.7 -0.05 200 0 2.1 0.75 1.8 -1 450 15 1/V V µA ns mV V CURRENT SENSE COMPARATOR ZERO CURRENT DETECTOR 0.3 4.5 4.7 0.5 5.1 5.2 0.7 5.9 6.1 V V V VZCD VZCD 5 5 IZCD = 20µA IZCD = 3mA 3/13 L6561 Table 5. Electrical Characteristics (continued) (VCC = 14.5V; Tamb = -25°C to 125°C;unless otherwise specified) Symbol VZCD IZCD IZCD IZCD VDIS IZCD VGD Pin 5 5 5 5 5 5 7 Parameter Lower Clamp Voltage Sink Bias Current Source Current Capability Sink Current Capability Disable threshold Restart Current After Disable Dropout Voltage VZCD < Vdis; VCC > VCCOFF IGDsource = 200mA IGDsource = 20mA IGDsink = 200mA IGDsink = 20mA tr tf IGD off IOVP 7 7 7 2 Output Voltage Rise Time Output Voltage Fall Time IGD Sink Current OVP Triggering Current Static OVP Threshold RESTART TIMER tSTART Start Timer 70 150 400 µs CL = 1nF CL = 1nF VCC =3.5V VGD = 1V 5 35 2.1 40 40 10 40 2.25 Test Condition IZCD = -3mA 1V ≤ VZCD ≤ 4.5V -3 3 150 -100 200 -200 1.2 0.7 Min. 0.3 Typ. 0.65 2 -10 10 250 -300 2 1 1.5 0.3 100 100 45 2.4 Max. 1 Unit V µA mA mA mV µA V V V V ns ns mA µA V OUTPUT SECTION OUTPUT OVERVOLTAGE SECTION 3 OVER VOLTAGE PROTECTION OVP The output voltage is expected to be kept by the operation of the PFC circuit close to its nominal value. This is set by the ratio of the two external resistors R1 and R2 (see fig. 5), taking into consideration that the non inverting input of the error amplifier is biased inside the L6561 at 2.5V. In steady state conditions, the current through R1 and R2 is: V out – 2.5 2.5V I R1sc = ------------------------- = I R2 = -----------R1 R2 and, if the external compensation network is made only with a capacitor Ccomp, the current through Ccomp equals zero.When the output voltage increases abruptly the current through R1 becomes: V outsc + ∆V out – 2.5 I R1 = ---------------------------------------------------- = I R1sc + ∆I R1 R1 Since the current through R2 does not change, ∆IR1 must flow through the capacitor Ccomp and enter the error amplifier. This current is monitored inside the L6561 and when reaches about 37µA the output voltage of the multiplier is forced to decrease, thus reducing the energy drawn from the mains. If the current exceeds 40µA, the OVP protection is triggered (Dynamic OVP), and the external power transistor is switched off until the current falls approximately below 10µA. However, if the overvoltage persists, an internal comparator (Static OVP) confirms the OVP condition keeping the external power switch turned off (see fig. 4).Finally, the overvoltage that triggers the OVP function is: ∆Vout = R1 · 40µA. Typical values for R1, R2 and C are shown in the application circuits. The overvoltage can be set indepen- 4/13 L6561 dently from the average output voltage. The precision in setting the overvoltage threshold is 7% of the overvoltage value (for instance ∆V = 60V ± 4.2V). 3.1 Disable function The zero current detector (ZCD) pin can be used for device disabling as well. By grounding the ZCD voltage the device is disabled reducing the supply current consumption at 1.4mA typical (@ 14.5V supply voltage). Releasing the ZCD pin the internal start-up timer will restart the device. Figure 4. OVER VOLTAGE VOUT nominal ISC 40µA 10µA E/A OUTPUT 2.25V DYNAMIC OVP STATIC OVP D97IN592A Figure 5. Overvoltage Protection Circuit Ccomp. +Vo R1 1 R2 + 2.5V 2.25V ∆I + E/A ∆I 2 X PWM DRIVER 40µA D97IN591 5/13 L6561 Figure 6. Typical Application Circuit (80W, 110VAC) D1 BYT03-400 C6 T R7 (*) 950K C3 680nF 68K 5 2 1 7 4 + Vo=240V Po=80W R3 (*) 240K BRIDGE + 4 x 1N4007 FUSE 4A/250V Vac (85V to 135V) NTC R10 10K D3 1N4150 D2 1N5248B R2 100 10nF R1 C1 1µF 250V R9 (*) 950K 8 R5 10 L6561 3 C2 22µF 25V C7 10nF 6 MOS STP7NA40 C5 100µF 315V R6 (*) 0.31 1W R8 10K 1% D97IN549B - (*) R3 = 2 x 120KΩ R6 = 0.619Ω/2 R7 = 2 x 475KΩ, 1% R9 = 2 x 475KΩ TRANSFORMER T: core THOMSON-CSF B1ET2910A (ETD 29 x 16 x 10mm) OR EQUIVALENT (OREGA 473201A7) primary 90T of Litz wire 10 x 0.2mm secondary 11T of #27 AWG (0.15mm) gap 1.8mm for a total primary inductance of 0.7mH Figure 7. Typical Application Circuit (120W, 220VAC) D1 BYT13-600 C6 T R7 (*) 998K C3 1µF 68K 5 2 1 7 4 + Vo=400V Po=120W R3 (*) 440K BRIDGE + 4 x 1N4007 FUSE 2A/250V Vac (175V to 265V) NTC R10 10K D3 1N4150 D2 1N5248B R2 100 10nF R1 C1 560nF 400V R9 (*) 1.82M 8 R5 10 L6561 3 C2 22µF 25V C7 10nF 6 MOS STP5NA50 C5 56µF 450V R6 (*) 0.41 1W R8 6.34K 1% D97IN550B - (*) R3 = 2 x 220KΩ R6 = 0.82Ω/2 R7 = 2 x 499KΩ, 1% R9 = 2 x 909KΩ TRANSFORMER T: core THOMSON-CSF B1ET2910A (ETD 29 x 16 x 10mm) OR EQUIVALENT (OREGA 473201A8) primary 90T of Litz wire 10 x 0.2mm secondary 7T of #27 AWG (0.15mm) gap 1.25mm for a total primary inductance of 0.8mH Figure 8. Typical Application Circuit (80W, Wide-range Mains) D1 BYT13-600 C6 T R7 (*) 998K C3 1µF 68K 5 2 1 7 4 + Vo=400V Po=80W R3 (*) 240K BRIDGE + 4 x 1N4007 FUSE 4A/250V Vac (85V to 265V) NTC R10 10K D3 1N4150 D2 1N5248B R2 100 12nF R1 C1 1µF 400V R9 (*) 1.24M 8 R5 10 L6561 3 C2 22µF 25V C7 10nF 6 MOS STP8NA50 C5 47µF 450V R6 (*) 0.41 1W R8 6.34K 1% D97IN553B - (*) R3 = 2 x 120KΩ R6 = 0.82Ω/2 R7 = 2 x 499KΩ, 1% R9 = 2 x 620KΩ TRANSFORMER T: core THOMSON-CSF B1ET2910A (ETD 29 x 16 x 10mm) OR EQUIVALENT (OREGA 473201A8) primary 90T of Litz wire 10 x 0.2mm secondary 7T of #27 AWG (0.15mm) gap 1.25mm for a total primary inductance of 0.8mH 6/13 L6561 Figure 9. Demo Board (EVAL6561-80) Electrical Schematic D1 STTH1L06 R4 180 k R5 180 k T D8 1N4150 C5 12 nF R14 100 R1 750 k D2 1N5248B R6 68 k R50 12 k C3 470 nF R12 750 k R11 750 k Vo=400V Po=80W NTC 2.5 BRIDGE FUSE 4A/250V + W04M C1 1 µF 400V C23 1 µF R2 750 k 8 3 6 C2 10nF 5 2 1 7 4 R7 33 C6 47 µF 450V V ac (85V to 265V) - L6561 MOS STP8NM50 R3 10 k C29 22 µF 25V C4 100 nF D3 1N4148 C7 10 µF 35 V R16 91 k R15 220 R9 0.41 1W R10 0.41 1W R13 9.53 k - Boost Inductor Spec (ITACOIL E2543/E) E25x13x7 core, 3C85 ferrite 1.5 mm gap for 0.7 mH primary inductance Primary: 105 turns 20x0.1 mm Secondary: 11 turns 0.1mm THD REDUCER (optional) Figure 10. EVAL6561-80: PCB and Component Layout (Top view, real size 57x108mm) Table 6. EVAL6561-80: Evaluation Results. Vin (Vac) 85 110 135 175 220 265 Pin (W) 87.2 85.2 84.2 83.5 83.1 82.9 Vo (Vdc) 400.1 400.1 400.1 400.1 400.1 400.1 ∆Vo (Vdc) 14 14 14 14 14 14 Po (W) 80.7 80.7 80.7 80.7 80.7 80.7 η (%) 92.8 94.7 95.8 96.6 97.1 97.3 w/o THD reducer PF 0.999 0.996 0.989 0.976 0.940 0.890 THD (%) 3.7 5.0 6.2 8.3 10.7 13.7 with THD reducer PF 0.999 0.996 0.989 0.976 0.941 0.893 THD (%) 2.9 3.2 3.7 4.3 5.6 8.1 7/13 L6561 Figure 11. OVP Current Threshold vs. Temperature D94IN047A Figure 13. Supply Current vs. Supply Voltage ICC (mA) 10 D97IN548A IOVP (µA) 41 5 1 40 0.5 0.1 0.05 39 0.01 0.005 CL = 1nF f = 70KHz TA = 25˚C 0 5 10 15 20 VCC(V) 38 -50 -25 0 25 50 75 100 125 T (˚C) 0 Figure 12. Undervoltage Lockout Threshold vs. Temperature VCC-ON (V) 13 12 11 VCC-OFF (V) 10 9 -25 0 25 50 T (˚C) 75 100 125 D94IN044A Figure 14. Voltage Feedback Input Threshold vs. Temperature VREF (V) D94IN048A 2.50 2.48 2.46 -50 0 50 100 T (˚C) 8/13 L6561 Figure 15. Output Saturation Voltage vs. Sink Current VPIN7 (V) VCC = 14.5V 2.0 D94IN046 Figure 17. Multiplier Characteristics Family VCS(pin4) (V) upper voltage clamp D97IN555A VCOMP(pin2) (V) 3.5 SINK 1.6 1.4 1.2 5.0 4.5 4.0 3.2 1.5 1.0 1.0 0.8 0.6 0.5 0.4 0.2 0 0 100 200 300 400 IGD (mA) 0 0 3.0 2.8 2.6 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 VMULT(pin3) (V) Figure 16. Output Saturation Voltage vs. Source Current VPIN7 (V) VCC = 14.5V VCC -0.5 D94IN053 VCC -1.0 VCC -1.5 VCC -2.0 SOURCE 0 0 100 200 300 400 IGD (mA) 9/13 L6561 Figure 18. DIP-8 Mechanical Data & Package Dimensions mm DIM. MIN. A a1 B b b1 D E e e3 e4 F I L Z 3.18 7.95 2.54 7.62 7.62 6.6 5.08 3.81 1.52 0.125 0.51 1.15 0.356 0.204 1.65 0.55 0.304 10.92 9.75 0.313 0.100 0.300 0.300 0.260 0.200 0.150 0.060 TYP. 3.32 0.020 0.045 0.014 0.008 0.065 0.022 0.012 0.430 0.384 MAX. MIN. TYP. 0.131 MAX. inch OUTLINE AND MECHANICAL DATA DIP-8 10/13 L6561 Figure 19. SO-8 Mechanical Data & Package Dimensions mm DIM. MIN. A A1 A2 B C D (1) E e H h L k ddd 5.80 0.25 0.40 1.35 0.10 1.10 0.33 0.19 4.80 3.80 1.27 6.20 0.50 1.27 0.228 0.010 0.016 TYP. MAX. 1.75 0.25 1.65 0.51 0.25 5.00 4.00 MIN. 0.053 0.004 0.043 0.013 0.007 0.189 0.15 0.050 0.244 0.020 0.050 TYP. MAX. 0.069 0.010 0.065 0.020 0.010 0.197 0.157 inch OUTLINE AND MECHANICAL DATA 0˚ (min.), 8˚ (max.) 0.10 0.004 Note: (1) Dimensions D does not include mold flash, protrusions or gate burrs. Mold flash, potrusions or gate burrs shall not exceed 0.15mm (.006inch) in total (both side). SO-8 0016023 C 11/13 L6561 Table 7. Revision History Date January 2004 June 2004 Revision 15 16 First Issue Modified the Style-look in compliance with the “Corporate Technical Publications Design Guide”. Changed input of the power amplifier connected to Multiplier (Fig. 2). Description of Changes 12/13 L6561 Information furnished is believed to be accurate and reliable. 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