L6562ATDTR

L6562AT Transition-mode PFC controller Features ■ Guaranteed for extreme temperature range (outdoor) ■ Proprietary multiplier design for minimum THD ■ Very accurate adjustable output overvoltage protection DIP-8 ■ SO-8 DIP-8/SO-8 packages ■ Ultra-low (30 μA) start-up current ■ Low (2.5 mA) quiescent current Applications ■ Digital leading-edge blanking on current sense PFC pre-regulators for: ■ Disable function on E/A input ■ Street lighting ■ 1% (@ TJ = 25 °C) internal reference voltage ■ ■ -600/+800 mA totem pole gate driver with active pull-down during UVLO and voltage clamp IEC61000-3-2 compliant SMPS (Flat TV, monitors, desktop PC, games) ■ Electronic ballast Figure 1. Block diagram Table 1. Device summary Order codes Package Packaging L6562ATN DIP-8 Tube L6562ATD L6562ATDTR March 2009 SO-8 Rev 2 Tube Tape and reel 1/25 www.st.com 25 Contents L6562AT Contents 1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 2 Pin settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 2.1 Pin connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 2.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 3 Maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 4 Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 5 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 6 Typical electrical characteristic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 7 Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 7.1 Overvoltage protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 7.2 Disable function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 7.3 THD optimizer circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 7.4 Operating with no auxiliary winding on the boost inductor . . . . . . . . . . . . 15 7.5 Comparison between the L6562AT and the L6562 . . . . . . . . . . . . . . . . . 16 8 Application examples and ideas . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 9 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 10 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 2/25 Description 1 L6562AT Description The L6562AT is a current-mode PFC controller operating in transition mode (TM). Coming with the same pin-out as its predecessors L6561 and L6562, it offers improved performance. The highly linear multiplier includes a special circuit, able to reduce AC input current distortion, that allows wide-range-mains operation with an extremely low THD, even over a large load range. The output voltage is controlled by means of a voltage-mode error amplifier and an accurate (1% @TJ = 25 °C) internal voltage reference. The device features extremely low consumption (60 µA max. before start-up and < 5.5 mA operating) and includes a disable function suitable for IC remote ON/OFF, which makes it easier to comply with energy saving requirements (Blue Angel, EnergyStar, Energy2000, etc.). An effective two-step OVP enables to safely handle over-voltages either occurring at startup or resulting from load disconnection. The totem-pole output stage, capable of 600 mA source and 800 mA sink current, is suitable to drive high current MOSFETs or IGBTs. This, combined with the other features and the possibility to operate with the proprietary fixed-off-time control, makes the device an excellent low-cost solution for EN61000-3-2 compliant SMPS in excess of 350 W. 3/25 Pin settings L6562AT 2 Pin settings 2.1 Pin connection Figure 2. 2.2 INV 1 8 Vcc COMP 2 7 GD MULT 3 6 GND CS 4 5 ZCD Pin description Table 2. 4/25 Pin connection (top view) Pin description Pin N° Name Description 1 INV Inverting input of the error amplifier. The information on the output voltage of the PFC pre-regulator is fed into this pin through a resistor divider. The pin doubles as an ON/OFF control input. 2 COMP Output of the error amplifier. A compensation network is placed between this pin and INV to achieve stability of the voltage control loop and ensure high power factor and low THD. 3 MULT Main input to the multiplier. This pin is connected to the rectified mains voltage via a resistor divider and provides the sinusoidal reference to the current loop. Input to the PWM comparator. The current flowing in the MOSFET is sensed through a resistor, the resulting voltage is applied to this pin and compared with an internal sinusoidal-shaped reference, generated by the multiplier, to determine MOSFET’s turn-off. The pin is equipped with 200 ns leading-edge blanking for improved noise immunity. 4 CS 5 ZCD Boost inductor’s demagnetization sensing input for transition-mode operation. A negative-going edge triggers MOSFET’s turn-on. 6 GND Ground. Current return for both the signal part of the IC and the gate driver. 7 GD Gate driver output. The totem pole output stage is able to drive power MOSFET’s and IGBT’s with a peak current of 600 mA source and 800 mA sink. The high-level voltage of this pin is clamped at about 12 V to avoid excessive gate voltages in case the pin is supplied with a high Vcc. 8 Vcc Supply voltage of both the signal part of the IC and the gate driver. The supply voltage upper limit is extended to 22 V min. to provide more headroom for supply voltage changes. Maximum ratings 3 Maximum ratings Table 3. 4 L6562AT Absolute maximum ratings Symbol Pin VCC 8 IGD 7 --- 1 to 4 IZCD 5 Parameter Value Unit IC supply voltage (ICC ≤ 20 mA) Self-limited V Output totem pole peak current Self-limited A -0.3 to 8 V ±10 mA Analog inputs and outputs Zero current detector max. current Thermal data Table 4. Thermal data Value Symbol Unit SO8 DIP8 RthJA Max. thermal resistance, junction-toambient 150 100 °C/W PTOT Power dissipation @TA = 50 °C 0.65 1 W TJ TSTG 5/25 Parameter Junction temperature operating range -40 to 150 °C Storage temperature -55 to 150 °C Electrical characteristics 5 L6562AT Electrical characteristics -40 °C < TJ < +125 °C, VCC = 12 V, CO = 1 nF; unless otherwise specified Table 5. Electrical characteristics Symbol Parameter Test condition Min Typ Max Unit 22.5 V Supply voltage VCC VccOn VccOff Operating range After turn-on 10.5 Turn-on threshold (1) 11.7 12.5 13.3 V Turn-off threshold (1) 9.5 10 10.5 V 2.8 V 25 28 V Hys Hysteresis VZ Zener voltage 2.2 ICC = 20 mA 22.5 Supply current Istart-up Iq ICC Iq Start-up current Before turn-on, VCC = 11 V 30 60 µA Quiescent current After turn-on 2.5 3.9 mA 3.5 5.5 mA 1.7 2.2 mA -1 µA Operating supply current @ 70 kHz Quiescent current During OVP (either static or dynamic) or VINV ≤ 150 mV Multiplier input IMULT Input bias current VMULT Linear operation range ΔV cs -------------------ΔV MULT K VMULT = 0 to 4 V 0 to 3 Output max. slope VMULT = 0 to 1 V, VCOMP = Upper clamp Gain (2) V 1 1.1 V/V VMULT = 1 V, VCOMP = 4 V, 0.32 0.38 0.47 TJ = 25 °C 2.475 2.5 2.525 V Error amplifier VINV Voltage feedback input threshold 10.5 V < VCC < 22.5 V Line regulation VCC = 10.5 V to 22.5 V IINV Input bias current VINV = 0 to 3 V Gv Voltage gain Open loop GB Gain-bandwidth product ICOMP VCOMP (1) V 2.44 2.545 2 60 5 mV -1 µA 80 dB 1 MHz Source current VCOMP = 4 V, VINV = 2.4 V -2 -3.5 Sink current VCOMP = 4 V, VINV = 2.6 V 2.5 4.5 Upper clamp voltage ISOURCE = 0.5 mA 5.1 5.7 6 V 2.1 2.25 2.4 V Lower clamp voltage ISINK = 0.5 mA (1) -5 mA mA VINVdis Disable threshold 150 200 250 mV VINVen Restart threshold 380 450 520 mV 6/25 Electrical characteristics Table 5. Symbol L6562AT Electrical characteristics (continued) Parameter Test condition Min Typ Max Unit 19.5 27 30.5 µA Output overvoltage IOVP Dynamic OVP triggering current Hys Hysteresis (3) Static OVP threshold (1) 20 2.1 2.25 µA 2.4 V -1 µA 300 ns Current sense comparator ICS Input bias current tLEB Leading edge blanking td(H-L) VCS = 0 100 Delay to output 200 175 VCS Current sense clamp Vcsoffset Current sense offset VCOMP = Upper clamp, Vmult = 1.5 V 1.0 1.08 VMULT = 0 25 VMULT = 2.5 V 5 ns 1.16 V mV Zero current detector VZCDH Upper clamp voltage IZCD = 2.5 mA 5.0 5.7 6.5 V VZCDL Lower clamp voltage IZCD = - 2.5 mA -0.5 0 0.5 V VZCDA Arming voltage (positive-going edge) (3) 1.4 V VZCDT Triggering voltage (negative-going edge) (3) 0.7 V IZCDb Input bias current VZCD = 1 to 4.5 V 2 µA IZCDsrc Source current capability -1.5 mA IZCDsnk Sink current capability 1.5 mA Start timer period 75 Starter tSTART 190 300 µs 0.6 1.2 V Gate driver VOL Output low voltage Isink = 100 mA VOH Output high voltage Isource = 5 mA Isrcpk Peak source current -0.6 A Isnkpk Peak sink current 0.8 A 10.3 V tf Voltage fall time 30 70 ns tr Voltage rise time 60 130 ns 12 15 V 1.1 V VOclamp Output clamp voltage Isource = 5 mA; Vcc = 20 V UVLO saturation Vcc = 0 to VCCon, Isink = 2 mA 1. All the parameters are in tracking 2. The multiplier output is given by: Vcs = K ⋅ VMULT ⋅ (VCOMP − 2.5 ) 3. Parameters guaranteed by design, functionality tested in production. 7/25 9.5 10 Typical electrical characteristic 6 L6562AT Typical electrical characteristic Figure 3. Supply current vs supply voltage Figure 4. Start-up and UVLO vs TJ p 10.00 j 13 Vcc-ON 12 0.10 (V) Icc (mA) 1.00 11 10 0.01 Co = 1 nF f = 70 kHz Tj = 25°C 0.00 0.00 Vcc-OFF 9 5.00 10.00 15.00 20.00 -50 25.00 0 Vcc (V) Figure 5. IC consumption vs TJ p 50 100 150 Tj (°C) Figure 6. j Vcc Zener voltage vs TJ 28 10 Operating 27 Quiescent Disabled or during OVP 26 Icc (mA) VccZ (V) 1 24 Vcc = 12 V Co= 1 nF f = 70 kHz 0.1 25 23 Before start-up -50 0 50 Tj (°C) 8/25 22 -50 0.01 100 150 0 50 Tj (°C) 100 150 Typical electrical characteristic Figure 7. L6562AT Feedback reference vs TJ Figure 8. OVP current vs TJ j 35 2.6 34 Vcc = 12V Vcc = 12V 33 32 2.55 Iovp (uA) VREF (V) 31 2.5 30 29 28 27 26 2.45 25 24 2.4 23 -50 0 50 100 150 -50 0 Tj (°C) Figure 9. 50 Tj (°C) 100 150 E/A output clamp levels vs TJ Figure 10. Delay-to-output vs TJ 300 6 Upper clamp 5 tD (H-L) (ns) V COMP pin2 (V) 200 4 Vcc = 12V 3 Vcc = 12V 100 Lower clamp 2 0 1 -50 -50 0 50 Tj (°C) 9/25 100 150 0 50 Tj (°C) 100 150 Typical electrical characteristic L6562AT Figure 11. Multiplier characteristic Figure 12. Vcs clamp vs TJ p 1.3 1.2 V COMP (pin2) (V) Upper Volt. Clamp 1.1 Vcc = 12V 5.75 V 1.0 VCOMP = Upper clamp 4V 0.9 3.5V 5V 1.2 4.5V 0.7 Vcsx (V) Vcs (pin4) (V) 0.8 0.6 0.5 3V 0.4 1.1 0.3 0.2 0.1 2.5 V 0.0 1 -0.1 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2 VMULT (pin3) (V) 2.2 2.4 2.6 2.8 0 50 100 150 Tj (°C) Figure 13. ZCD clamp levels vs TJ p -50 3 Figure 14. Start-up timer vs TJ p j j 200 7 Upper clamp 6 190 5 Vzcd (V) Tstart (us) Vcc = 12V 4 IZCD = ±2.5 mA 3 2 180 170 Vcc = 12V 1 160 Lower clamp 0 -1 -50 10/25 0 50 Tj (°C) 100 150 150 -50 0 50 Tj (°C) 100 150 Typical electrical characteristic L6562AT Figure 15. Gate-driver output low saturation Figure 16. Gate-drive output high saturation 5.00 12.00 Tj = 25 °C 11.00 4.00 Vcc = 12V SOURCE 10.00 Vpin7 (V) Vpin7 (V) 3.00 2.00 9.00 8.00 Tj = 25 °C 1.00 7.00 Vcc = 12V SINK 0.00 6.00 0 200 400 600 800 1000 0 200 400 600 I GD (mA) I GD (m A) Figure 17. Gate-drive clamp vs TJ Figure 18. Output gate drive low saturation vs TJ during UVLO 13.5 1.1 Vcc = 20V Isink = 2 mA 1 Vcc = 11V 0.9 Vpin7 (V) Vpin7 clamp (V) 13.25 13 Vcc = 0V 0.8 0.7 12.75 0.6 0.5 12.5 -50 11/25 0 50 Tj (°C) 100 150 -50 0 50 Tj (°C) 100 150 Application information L6562AT 7 Application information 7.1 Overvoltage protection Under steady-state conditions, the voltage control loop keeps the output voltage Vo of a PFC pre-regulator close to its nominal value, set by the resistors R1 and R2 of the output divider. Neglecting ripple components, the current through R1, IR1, equals that through R2, IR2. Considering that the non-inverting input of the error amplifier is internally referenced at 2.5 V, also the voltage at pin INV will be 2.5 V, then: Equation 1 V O – 2.5 I R2 = I R1 = 2.5 -------- = --------------------R1 R2 If the output voltage experiences an abrupt change ΔVo > 0 due to a load drop, the voltage at pin INV will be kept at 2.5 V by the local feedback of the error amplifier, a network connected between pins INV and COMP that introduces a long time constant to achieve high PF (this is why ΔVo can be large). As a result, the current through R2 will remain equal to 2.5/R2 but that through R1 will become: Equation 2 V O – 2.5 + ΔV O I' R1 = --------------------------------------R1 The difference current ΔIR1=I'R1-IR2=I'R1-IR1= ΔVo/R1 will flow through the compensation network and enter the error amplifier output (pin COMP). This current is monitored inside the device and if it reaches about 24 µA the output voltage of the multiplier is forced to decrease, thus smoothly reducing the energy delivered to the output. As the current exceeds 27 µA, the OVP is triggered (Dynamic OVP): the gate-drive is forced low to switch off the external power transistor and the IC put in an idle state. This condition is maintained until the current falls below approximately 7 µA, which re-enables the internal starter and allows switching to restart. The output ΔVo that is able to trigger the Dynamic OVP function is then: Equation 3 ΔVO = R1 · 20 · 10 - 6 An important advantage of this technique is that the OV level can be set independently of the regulated output voltage: the latter depends on the ratio of R1 to R2, the former on the individual value of R1. Another advantage is the precision: the tolerance of the detection current is 13%, i.e. 13% tolerance on ΔVo. Since ΔVo