L6563H

L6563H High voltage start-up transition-mode PFC Features ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ On-board 700 V start-up source Tracking boost function Fast “bidirectional” input voltage feedforward (1/V2 correction) Interface for cascaded converter's PWM controller Remote ON/OFF control Accurate adjustable output overvoltage protection Protection against feedback loop disconnection (latched shutdown) Inductor saturation protection Low (≤ 100 µA) start-up current 6 mA max. operating bias current 1% (@ TJ = 25 °C) internal reference voltage -600/+800 mA totem pole gate driver with active pull-down during UVLO Block diagram SO16 SO-16 Applications PFC pre-regulators for: ■ ■ Hi-end AC-DC adapter/charger IEC61000-3-2 or JEITA-MITI compliant SMPS, in excess of 400 W Figure 1. February 2010 Doc ID 16047 Rev 2 1/48 www.st.com 48 Contents L6563H Contents 1 2 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2.1 2.2 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 3 4 5 6 Pin connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Typical electrical performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 6.1 6.2 6.3 6.4 6.5 6.6 6.7 6.8 Overvoltage protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Feedback failure protection (FFP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Voltage feedforward . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 THD optimizer circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Tracking boost function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Inductor saturation detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Power management/housekeeping functions . . . . . . . . . . . . . . . . . . . . . . 32 High-voltage start-up generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 7 8 9 10 Application examples and ideas . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 Ordering codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 2/48 Doc ID 16047 Rev 2 L6563H List of table List of table Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Thermal data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Summary of L6563H idle states . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 SO16 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 Doc ID 16047 Rev 2 3/48 List of figure L6563H List of figure Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Figure 10. Figure 11. Figure 12. Figure 13. Figure 14. Figure 15. Figure 16. Figure 17. Figure 18. Figure 19. Figure 20. Figure 21. Figure 22. Figure 23. Figure 24. Figure 25. Figure 26. Figure 27. Figure 28. Figure 29. Figure 30. Figure 31. Figure 32. Figure 33. Figure 34. Figure 35. Figure 36. Figure 37. Figure 38. Figure 39. Figure 40. Figure 41. Figure 42. Figure 43. Figure 44. Figure 45. Figure 46. Figure 47. Figure 48. Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Pin connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Typical system block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 IC consumption vs VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 IC consumption vs TJ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Vcc Zener voltage vs TJ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Start-up and UVLO vs TJ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Feedback reference vs TJ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 E/A output clamp levels vs TJ. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 UVLO saturation vs TJ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 OVP levels vs TJ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Inductor saturation threshold vs TJ. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Vcs clamp vs TJ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 ZCD sink/source capability vs TJ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 ZCD clamp level vs TJ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 TBO clamp vs TJ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 VVFF - VTBO dropout vs TJ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 IINV - ITBO current mismatch vs TJ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 IINV - ITBO mismatch vs ITBO current. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 R discharge vs TJ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Line drop detection threshold vs TJ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 VMULTpk - VVFF dropout vs TJ. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 PFC_OK threshold vs TJ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 PFC_OK FFD threshold vs TJ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 PWM_LATCH high saturation vs TJ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 RUN threshold vs TJ. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 PWM_STOP low saturation vs TJ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Multiplier characteristics @ VFF = 1 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Multiplier characteristics @ VFF = 3 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Multiplier gain vs TJ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Gate drive clamp vs TJ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Gate drive output saturation vs TJ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Delay to output vs TJ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Start-up timer period vs TJ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 HV start voltage vs TJ. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 VCC restart voltage vs TJ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 HV breakdown voltage vs TJ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Output voltage setting, OVP and FFP functions: internal block diagram . . . . . . . . . . . . . . 24 Voltage feedforward: squarer-divider (1/V2) block diagram and transfer characteristic . . 26 RFF·CFF as a function of 3rd harmonic distortion introduced in the input current . . . . . . . 27 THD optimizer circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 THD optimization: standard TM PFC controller (left side) and L6563H (right side) . . . . . . 28 Tracking boost block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Tracking output voltage vs Input voltage characteristic with TBO . . . . . . . . . . . . . . . . . . . 31 Effect of boost inductor saturation on the MOSFET current and detection method . . . . . . 31 Interface circuits that let dc-dc converter's controller IC drive L6563H in burst mode . . . . 32 Interface circuits that let the L6563H switch on or off a PWM controller. . . . . . . . . . . . . . . 33 Interface circuits for power up sequencing when dc-dc has the SS function . . . . . . . . . . . 33 4/48 Doc ID 16047 Rev 2 L6563H Figure 49. Figure 50. Figure 51. Figure 52. Figure 53. Figure 54. Figure 55. Figure 56. Figure 57. Figure 58. Figure 59. Figure 60. Figure 61. Figure 62. Figure 63. List of figure Interface circuits for actual power-up sequencing (master PFC) . . . . . . . . . . . . . . . . . . . . 34 Brownout protection (master PFC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 High-voltage start-up generator: internal schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Timing diagram: normal power-up and power-down sequences . . . . . . . . . . . . . . . . . . . . 36 High-voltage start-up behaviour during latch-off protection . . . . . . . . . . . . . . . . . . . . . . . . 37 High-voltage start-up managing the dc-dc output short-circuit . . . . . . . . . . . . . . . . . . . . . . 37 Demonstration board EVL6563H-100W, wide-range mains: electrical schematic . . . . . . . 39 L6563H 100 W TM PFC evaluation board: compliance to EN61000-3-2 standard . . . . . . 40 L6563H 100 W TM PFC evaluation board: compliance to JEITA-MITI standard . . . . . . . . 40 L6563H 100 W TM PFC evaluation board: input current waveform @230-50 Hz - 100 W 40 L6563H 100W TM PFC evaluation board: input current waveform @100-50 Hz - 100 W 40 Application board 90W-19V adapter with L6563H, L6599A, SRK2000 . . . . . . . . . . . . . . . 41 Application board 130 W-12 V adapter with L6563H, L6599A, SRK2000 . . . . . . . . . . . . . 42 Demonstration board EVL6563H-650W wide-range mains: electrical schematics. . . . . . . 43 SO16 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 Doc ID 16047 Rev 2 5/48 Description L6563H 1 Description The L6563H is a current-mode PFC controller operating in transition mode (TM) which embeds the same features existing in the L6563S with the addition of a high voltage start-up source. These functions make the IC especially suitable for applications that have to be compliant with energy saving regulations and where the PFC pre-regulator works as the master stage. The highly linear multiplier, along with a special correction circuit that reduces crossover distortion of the mains current, allows wide-range-mains operation with an extremely low THD even over a large load range. The output voltage is controlled by means of a voltage-mode error amplifier and an accurate (1% @Tj = 25 °C) internal voltage reference. Loop's stability is optimized by the voltage feedforward function (1/V2 correction), which in this IC uses a proprietary technique that considerably improves line transient response as well in case of mains both drops and surges (“bidirectional”). Additionally, the IC provides the option for tracking boost operation, i.e. the output voltage is changed tracking the mains voltage. The device includes disable functions suitable for remote ON/OFF control too. In addition to an over voltage protection able to keep the output voltage under control during transient conditions, the IC is provided also with a protection against feedback loop failures or erroneous settings. Other on-board protection functions allow that brownout conditions and boost inductor saturation can be safely handled. An interface with the PWM controller of the DC-DC converter supplied by the PFC preregulator is provided: the purpose is to stop the operation of the converter in case of anomalous conditions for the PFC stage (feedback loop failure, boost inductor's core saturation, etc.) and to handle the PFC stage in case of light load for the DC-DC converter, to make it easier to comply with energy saving regulations (Blue Angel, EnergyStar, Energy2000, etc.). The totem-pole output stage, capable of 600 mA source and 800 mA sink current, is suitable for big MOSFET or IGBT drive. This, combined with the other features and the possibility to operate with ST's proprietary fixed-off-time control, makes the device an excellent solution for SMPS up to 400 W that need to be compliant with EN61000-3-2 and JEITA-MITI standards. 6/48 Doc ID 16047 Rev 2 L6563H Maximum ratings 2 2.1 Maximum ratings Absolute maximum ratings Table 1. Symbol VHVS IHVS Vcc ----IPWM_STOP IZCD Absolute maximum ratings Pin 9 9 16 1, 3, 7 Parameter Voltage range (referred to ground) Output current IC supply voltage (Icc = 20 mA) Max. pin voltage (Ipin =1 mA) Value -0.3 to 700 Unit V Self-limited IHVS self-limited Self-limited -0.3 to 8 3 V V V mA 2, 4 to 6, 8, 11, 12 Analog inputs and outputs 11 13 Max. sink current Zero current detector max. current -10 (source) mA 10 (sink) 2.2 Thermal data Table 2. Symbol RthJA Ptot TJ Tstg Thermal data Parameter Max. thermal resistance, junction-to-ambient Power dissipation @TA = 50 °C Junction temperature operating range Storage temperature Value 120 0.75 -40 to 150 -55 to 150 Unit °C/W W °C °C Doc ID 16047 Rev 2 7/48 Pin connection L6563H 3 Pin connection Figure 2. Pin connection Table 3. n° Pin description Function Inverting input of the error amplifier. The information on the output voltage of the PFC preregulator is fed into the pin through a resistor divider. The pin normally features high impedance but, if the tracking boost function is used, an internal current generator programmed by TBO (pin 6) is activated. It sinks current from the pin to change the output voltage so that it tracks the mains voltage. Output of the error amplifier. A compensation network is placed between this pin and INV (pin 1) to achieve stability of the voltage control loop and ensure high power factor and low THD. To avoid uncontrolled rise of the output voltage at zero load, when the voltage on the pin falls below 2.4 V the gate driver output is inhibited (burst-mode operation). Mains input to the multiplier. This pin is connected to the rectified mains voltage via a resistor divider and provides the sinusoidal reference to the current loop. The voltage on this pin is used also to derive the information on the RMS mains voltage. Input to the PWM comparator. The current flowing in the MOSFET is sensed through a resistor, the resulting voltage is applied to this pin and compared with an internal reference to determine MOSFET’s turn-off. A second comparison level at 1.7 V detects abnormal currents (e.g. due to boost inductor saturation) and, on this occurrence, activates a safety procedure that temporarily stops the converter and limits the stress of the power components. Second input to the multiplier for 1/V2 function. A capacitor and a parallel resistor must be connected from the pin to GND. They complete the internal peak-holding circuit that derives the information on the RMS mains voltage. The voltage at this pin, a dc level equal to the peak voltage on pin MULT (3), compensates the control loop gain dependence on the mains voltage. Never connect the pin directly to GND but with a resistor ranging from 100 kΩ (minimum) to 2 M Ω (maximum). Tracking boost function. This pin provides a buffered VFF voltage. A resistor connected between this pin and GND defines a current that is sunk from pin INV (1). In this way, the output voltage is changed proportionally to the mains voltage (tracking boost). If this function is not used leave this pin open. Name 1 INV 2 COMP 3 MULT 4 CS 5 VFF 6 TBO 8/48 Doc ID 16047 Rev 2 L6563H Table 3. n° Pin connection Pin description (continued) Function PFC pre-regulator output voltage monitoring/disable function. This pin senses the output voltage of the PFC pre-regulator through a resistor divider and is used for protection purposes. If the voltage on the pin exceeds 2.5 V the IC stops switching and restarts as the voltage on the pin falls below 2.4 V. However, if the voltage of the pin INV falls 40 mV below that one of the pin PFC_OK, a feedback failure is assumed. In this case the device is latched off and the PWM_LATCH (8) pin is asserted high. Normal operation can be resumed only by cycling Vcc bringing its value lower than 6V before to move up to Turn on threshold. If the voltage on this pin is brought below 0.23 V the IC is shut down. To restart the IC the voltage on the pin must go above 0.27 V. This can be used as a remote on/off control input. Name 7 PFC_OK Output pin for fault signaling. During normal operation this pin features high impedance. If a feedback failure is detected (PFC_OK > 2.5 V and INV+40 mV < PFC_OK) the pin is asserted 8 PWM_LATCH high. Normally, this pin is used to stop the operation of the dc-dc converter supplied by the PFC pre-regulator by invoking a latched disable of its PWM controller. If not used, the pin is left floating. High-voltage start-up. The pin, able to withstand 700 V, is to be tied directly to the rectified mains voltage. A 1 mA internal current source charges the capacitor connected between pin Vcc (16) and pin GND (14) until the voltage on the pin Vcc reaches the start-up threshold, then it is shut down. Normally, the generator is re-enabled when the Vcc voltage falls below 6 V to ensure a low power throughput during short circuit. Otherwise, when a latched protection is tripped the generator is re-enabled as Vcc reaches the UVLO threshold to keep the latch supplied. Not internally connected. Provision for clearance on the PCB to meet safety requirements. 9 HVS 10 N.C. Output pin for fault signaling. During normal operation this pin features high impedance. If the IC is disabled by a voltage below 0.8 V on pin RUN (12) the voltage on the pin is pulled to ground. Normally, this pin is used to temporarily stop the operation of the dc-dc converter 11 PWM_STOP supplied by the PFC pre-regulator by disabling its PWM controller. A typical usage of this function is brownout protection in systems where the PFC pre-regulator is the master stage. If not used, the pin is left floating. Remote ON/OFF control. A voltage below 0.8 V shuts down (not latched) the IC and brings its consumption to a considerably lower level. PWM_STOP is asserted low. The IC restarts as the voltage at the pin goes above 0.88V. Connect this pin to pin VFF (5) either directly or through a resistor divider to use this function as brownout (AC mains undervoltage) protection. Boost inductor’s demagnetization sensing input for transition-mode operation. A negative-going edge triggers MOSFET’s turn-on. Ground. Current return for both the signal part of the IC and the gate driver. Gate driver output. The totem pole output stage is able to drive power MOSFET’s and IGBT’s with a peak current of 600 mA source and 800 mA sink. The high-level voltage of this pin is clamped at about 12 V to avoid excessive gate voltages. Supply voltage of both the signal part of the IC and the gate driver. Sometimes a small bypass capacitor (0.1 µF typ.) to GND might be useful to get a clean bias voltage for the signal part of the IC. 12 RUN 13 14 15 ZCD GND GD 16 Vcc Doc ID 16047 Rev 2 9/48 Pin connection Figure 3. Typical system block diagram L6563H 10/48 Doc ID 16047 Rev 2 L6563H Electrical characteristics 4 Electrical characteristics TJ = -25 to 125 °C, VCC = 12 V, CO = 1 nF between pin GD and GND, CFF = 1 µF and RFF = 1 MΩ between pin VFF and GND; unless otherwise specified Table 4. Symbol Electrical characteristics Parameter Test condition Min. Typ. Max. Unit Supply voltage Vcc VccOn VccOff Vccrestart Hys VZ Operating range Turn-on threshold Turn-off threshold Vcc for resuming from latch Hysteresis Zener voltage Icc = 20 mA After turn-on (1) (1) 10.3 11 8.7 5 2.3 22.5 25 12 9.5 6 22.5 13 10.3 7 2.7 28 V V V V V V OVP latched Supply current Istart-up Iq ICC Start-up current Quiescent current Operating supply current Before turn-on, Vcc = 10 V After turn-on, VMULT = 1 V @ 70 kHz VPFC_OK > VPFC_OK_S AND VINV < VPFC_OK – VFFD VPFC_OK < VPFC_OK_D OR VRUN < VDIS Quiescent current VPFC_OK > VPFC_OK_S OR VCOMP < 2.3 V 90 4 5 180 1.5 2.2 150 5 6.0 280 2.2 3 µA mA mA µA mA mA Iqdis Idle state quiescent current Iq High-voltage start-up generator VHV VHVstart Icharge IHV, ON IHV, OFF VCCrestart Breakdown voltage Start voltage Vcc charge current ON-state current IHV < 100 µA IVcc < 100 µA VHV > VHvstart, Vcc > 3 V VHV > VHvstart, Vcc > 3 V VHV > VHvstart, Vcc = 0 700 65 80 100 1 1.6 mA 0.8 40 5 8.7 6 9.5 7 V 10.3 µA V V mA 0.55 0.85 OFF-state leakage current Vcc restart voltage VHV = 400 V Vcc falling IC latched off (1) Multiplier input IMULT VMULT VCLAMP Input bias current Linear operation range Internal clamp level IMULT = 1 mA VMULT = 0 to 3 V 0 to 3 9 9.5 -0.2 -1 µA V V Doc ID 16047 Rev 2 11/48 Electrical characteristics Table 4. Symbol ΔVcs ΔVMULT KM L6563H Electrical characteristics (continued) Parameter Output max. slope Gain (2) Test condition VMULT =0 to 0.4 V, VVFF = 0.8 V VCOMP = Upper clamp VMULT = 1 V, VCOMP = 4 V Min. Typ. Max. Unit 2.2 2.34 V/V 0.375 0.45 0.525 1/V Error amplifier VINV Voltage feedback input threshold Line regulation IINV Input bias current TJ = 25 °C 10.3 V < Vcc < 22.5 V (3) 2.475 2.455 2.5 2.525 V 2.545 2 -0.2 5 -1 mV µA V dB MHz mA mA 6.7 2.5 2.4 V Vcc = 10.3 V to 22.5 V TBO open, VINV = 0 to 4 V IINV = 1 mA Open loop 8 60 VINVCLAMP Internal clamp level Gv GB ICOMP Voltage gain Gain-bandwidth product Source current Sink current Upper clamp voltage VCOMP Burst-mode voltage Lower clamp voltage Current sense comparator ICS tLEB td(H-L) VCSclamp Vcsofst Input bias current Leading edge blanking Delay to output Current sense reference clamp 9 80 1 VCOMP = 4 V, VINV = 2.4 V VCOMP = 4 V, VINV = 2.6 V ISOURCE = 0.5 mA (3) 2 2.5 5.7 2.3 2.1 4 4.5 6.2 2.4 2.25 ISINK = 0.5 mA (3) VCS = 0 100 100 VCOMP = Upper clamp, VMULT =1 V VVFF = 1 V VMULT = 0, VVFF = 3 V VMULT = 3 V, VVFF = 3 V 1.0 150 200 1.08 40 20 1 250 300 1.16 70 µA ns ns V Current sense offset mV Boost inductor saturation detector VCS_th IINV Threshold on current sense E/A input pull-up current (3) 1.6 7 1.7 10 1.8 13 V µA After VCS > VCS_th, before restarting PFC_OK functions IPFC_OK Input bias current VPFC_OK = 0 to 2.6 V IPFC_OK = 1 mA (1) (1) (1) (1) -0.1 9 2.435 2.34 0.12 0.17 0.23 9.5 -1 µA V V V V V VPFC_OK_C Clamp voltage VPFC_OK_S OVP threshold VPFC_OK_R Restart threshold after OVP VPFC_OK_D Disable threshold VPFC_OK_D Disable threshold voltage rising voltage falling voltage falling voltage falling TJ = 25 °C 2.5 2.565 2.4 2.46 0.35 0.29 12/48 Doc ID 16047 Rev 2 L6563H Table 4. Symbol Electrical characteristics Electrical characteristics (continued) Parameter (1) (1) Test condition voltage rising voltage rising Tj = 25 °C Min. Typ. Max. Unit 0.15 0.21 0.27 15 25 40 40 0.38 0.32 65 55 V V mV mV VPFC_OK_E Enable threshold VPFC_OK_E Enable threshold VFFD VFFD Feedback failure detection threshold (VPFC_OK -VINV) Feedback failure detection threshold (VPFC_OK -VINV) VPFC_OK = VPFC_OK_S VPFC_OK = VPFC_OK_S Tj = 25 °C Zero current detector VZCDH VZCDL VZCDA VZCDT IZCDb IZCDsrc IZCDsnk Upper clamp voltage Lower clamp voltage Arming voltage (positive-going edge) Triggering voltage (negative-going edge) Input bias current Source current capability Sink current capability VZCD = 1 to 4.5 V -2.5 2.5 -4 5 IZCD = 2.5 mA IZCD = - 2.5 mA 5.0 -0.3 1.1 0.5 5.7 0 1.4 0.7 0.3 1.9 0.9 1 V V V V µA mA mA Tracking boost function ΔV ITBO Dropout voltage VVFF-VTBO Linear operation IINV-ITBO current mismatch IINV-ITBO current mismatch ITBO = 0.2 mA -20 0 20 0.2 1.0 +0 3 3.1 2 mV mA % % V μA ITBO = 25 µA to 0.2mA ITBO = 25 µA to 0.2mA TJ = 25 °C (3) V VFF -5.5 -4.0 2.9 VTBOclamp Clamp voltage ITBO_Pull Pull-up current =4V VTBO = 1 V VFF = VMULT = 0 V PWM_STOP Ileak VL High level leakage current Low level VPWM_STOP = Vcc IPWM_STOP = 0.5 mA 1 1 µA V RUN function IRUN VDIS VEN Input bias current Disable threshold Enable threshold VRUN = 0 to 3 V (3) (3) -1 0.745 0.8 0.855 µA V V voltage falling voltage rising 0.845 0.88 0.915 Start-up timer tSTART_DEL Start-up delay First cycle after wake-up 25 50 75 µs Doc ID 16047 Rev 2 13/48 Electrical characteristics Table 4. Symbol tSTART L6563H Electrical characteristics (continued) Parameter Timer period Restart after VCS > VCS_th 150 300 600 Test condition Min. Typ. Max. Unit 75 150 300 µs Voltage feedforward VVFF ΔV ΔVVFF ΔVVFF RDISCH VVFF Linear operation range Dropout VMULTpk-VVFF Line drop detection threshold Line drop detection threshold Vcc < VccOn Vcc > or = to VccOn Below peak value Below peak value TJ = 25 °C TJ = 25 °C 40 50 7.5 5 Linear operation range 0.8 70 70 10 0.8 3 800 mV 20 100 90 12.5 20 3 V mV mV kΩ V Internal discharge resistor PWM_LATCH Ileak VH VH VH Gate driver VOL VOH Isrcpk Isnkpk tf tr VOclamp Low level leakage current High level High level High level VPWM_LATCH = 0 IPWM_LATCH = -0.5 mA IPWM_LATCH = -0.25 mA Vcc = VccOff IPWM_LATCH = -0.25 mA Vcc = VccOff TJ = 25 °C 4.5 2.5 2.8 -1 µA V V V Output low voltage Output high voltage Peak source current Peak sink current Voltage fall time Voltage rise time Output clamp voltage UVLO saturation Isink = 100 mA Isource = 5 mA 9.8 -0.6 0.8 0.6 10.3 1.2 V V A A 30 45 Isource = 5 mA; Vcc = 20 V Vcc= 0 to VCCon, Isink = 2 mA 10 12 60 110 15 1.1 ns ns V V 1. Parameters tracking each other 2. The multiplier output is given by: Vcs = VCS_Ofst + K M ⋅ VMULT ⋅ VCOMP − 2.5 2 V VFF ( ) 3. Parameters tracking each other 14/48 Doc ID 16047 Rev 2 L6563H Typical electrical performance 5 Figure 4. Typical electrical performance IC consumption vs VCC Figure 5. IC consumption vs TJ   100   10 Operating 10 Quiescent Disabled or d uring OV P VCC=12V Co = 1nF f =70kHz L atched off 0.1 1 1 I cc [m A] Co=1nF f =70kHz Tj = 25°C 0.1 I c current (m A) 0.01 VccOFF VccON 0. 001 0 5 10 15 Vcc [V ] 20 25 30 0.01 -50 -25 0 25 50 Tj (C) 75 Before Start up 100 125 150 175 Figure 6. Vcc Zener voltage vs TJ Figure 7. Start-up and UVLO vs TJ   28   13 12 V CC- ON 27 11 26 10 25 VCC-OFF V 9 8 7 6 -50 -25 0 25 50 Tj (C) 75 100 125 150 175 V 24 23 22 -50 -25 0 25 50 Tj (C) 75 100 125 150 175 Doc ID 16047 Rev 2 15/48 Typical electrical performance L6563H Figure 8. Feedback reference vs TJ Figure 9. E/A output clamp levels vs TJ   2. 6   7 U per Clam p VCC = 12V 2.55 6 5 V CC = 12V V COM P (V ) pi n INV (V ) 4 2. 5 3 Lower Clamp 2 2.45 1 2. 4 -50 -25 0 25 50 75 Tj (C) 100 125 150 175 0 -50 -25 0 25 50 Tj (C) 75 100 125 150 175 Figure 10. UVLO saturation vs TJ Figure 11. OVP levels vs TJ   1 0.9 VCC = 0V 0.8 0.7 0.6 V 0.5 0.4 0.3 0.2 0.1   2. 5 2. 48 OV P T h 2. 46 P FC_OK l evels (V ) 2. 44 2. 42 2. 4 Resta rt Th 2. 38 2. 36 0 -50 -25 0 25 50 Tj (C) 75 100 125 150 175 -50 -25 0 25 50 Tj (C) 75 100 125 150 175 16/48 Doc ID 16047 Rev 2 L6563H Typical electrical performance Figure 12. Inductor saturation threshold vs TJ Figure 13. Vcs clamp vs TJ   1.9 1.8   1. 4 1.7 1.6 CS pi n (V ) VCSx (V ) 1. 3 VCC = 12V VCOMP =Upp clamp er 1. 2 1.5 1.4 1.3 1.2 1. 1 1.1 -50 -25 0 25 50 Tj (C) 75 100 125 150 175 1 -50 -25 0 25 50 Tj (C) 75 100 125 150 175 Figure 14. ZCD sink/source capability vs TJ Figure 15. ZCD clamp level vs TJ   8 6 4 2 V CC = 12V Si nk curren t   7 6 Upper Clamp 5 4 3 2 IZCDsrc (mA ) 0 -2 Source current -4 -6 -8 -50 -25 0 25 50 Tj (C) 75 100 125 150 175 V ZCD pin (V ) VCC = 12V Izcd =± 2.5mV 1 0 Lower Cl am p -1 -50 -25 0 25 50 Tj (C) 75 100 125 150 175 Doc ID 16047 Rev 2 17/48 Typical electrical performance L6563H Figure 16. TBO clamp vs TJ Figure 17. VVFF - VTBO dropout vs TJ 5 4 3   3.5 3.25 2 1 mV 3 V 0 -1 -2 2.75 -3 -4 -5 2.5 -50 -25 0 25 50 T (C) j 75 100 125 150 175 -50 -25 0 25 50 T j (C) 75 100 125 150 175 Figure 18. IINV - ITBO current mismatch vs TJ Figure 19. IINV - ITBO mismatch vs ITBO current   0 VCC = 12V -0.5 -1 I TBO = 200uA -1.5 -2   -1.6 -1.8 100*{I(I NV )-I(TBO)}/I (TBO) [ % ] 100*{I(INV)-I(TBO)}/I(TBO) [ % ] -2 -2.2 ITBO = 25uA -2.4 -2.5 -3 -3.5 VCC = 12V T = 25°C j -2.6 -2.8 -4 -50 -25 0 25 50 T (C) j 75 100 125 150 175 -3 0 100 200 300 I(TBO) 400 500 600 18/48 Doc ID 16047 Rev 2 L6563H Typical electrical performance Figure 20. R discharge vs TJ Figure 21. Line drop detection threshold vs TJ   20 18 16 14   90 80 70 60 12 kOhm 50 10 8 mV 40 30 20 10 0 -50 -25 0 25 50 Tj (C) 75 100 125 150 175 6 4 2 0 -50 -25 0 25 50 75 Tj (C) 100 125 150 175 Figure 22. VMULTpk - VVFF dropout vs TJ Figure 23. PFC_OK threshold vs TJ 0.4 0.35   2 1. 5 1 0. 5 ⎯ (m V) 0.3 0.25 Th (V ) ON 0.2 OF F 0 -0. 5 -1 0.15 0.1 -1. 5 0.05 -2 -50 -25 0 25 50 75 Tj (C) 100 125 150 175 0 -50 -25 0 25 50 Tj (C) 75 100 125 150 175 Doc ID 16047 Rev 2 19/48 Typical electrical performance L6563H Figure 24. PFC_OK FFD threshold vs TJ Figure 25. PWM_LATCH high saturation vs TJ   60   10 VCC = 12V 9 50 40 VFFD Th (V) 8 Iso urce =500u A V 30 7 Iso urce =250u A 20 6 10 5 0 -50 -25 0 25 50 75 T j (C) 100 125 150 175 4 -50 -25 0 25 50 75 T j (C) 100 125 150 175 Figure 26. RUN threshold vs TJ Figure 27. PWM_STOP low saturation vs TJ 0. 25   1 ON 0.2 VCC = 12V Isink = 0. 5m A 0.8 OF F 0. 15 V VCC = 12V V 0.1 0. 05 0 -50 0.6 0.4 -50 -25 0 25 50 T j (C) 75 100 125 150 175 -25 0 25 50 Tj (C) 75 100 125 150 175 20/48 Doc ID 16047 Rev 2 L6563H Typical electrical performance Figure 28. Multiplier characteristics @ VFF = 1 V Figure 29. Multiplier characteristics @ VFF = 3 V   1. 2 1. 1 1 0. 9 0. 8 VCOMP Upper voltage cl amp 5 .5 5 .0V 4.5 V   700 V COM P 600 Upper vo ltage 500 5. 5V 0. 6 0. 5 3.5 V V CS (m V) 0. 7 V CS (V ) 4. 0V 400 5. 0V 4. 5V 4. 0V 300 0. 4 0. 3 0. 2 0. 1 2.6 V 3.0 200 3. 5V 100 3. 0V 2. 6V 0 0 0. 1 0.2 0. 3 0. 4 0.5 0.6 0.7 0. 8 0.9 1 1.1 VM UL T (V ) 0 0 0. 5 1 1. 5 2 V MULT (V ) 2. 5 3 3. 5 Figure 30. Multiplier gain vs TJ Figure 31. Gate drive clamp vs TJ   0. 5   12. 9 V CC = 20V 12.85 0. 4 Gai n (1/V ) 12. 8 VCC = 12V VCOMP = 4V VMUL = VFF= 1V T 0. 3 V 12.75 12. 7 150 175 0. 2 -50 -25 0 25 50 Tj (C) 75 100 125 12.65 -50 -25 0 25 50 75 Tj (C) 100 125 150 175 Doc ID 16047 Rev 2 21/48 Typical electrical performance L6563H Figure 32. Gate drive output saturation vs TJ Figure 33. Delay to output vs TJ 300   12 10 High level 250 8 TD(H-L) (n s) 200 VCC = 12V 150 6 V 4 2 Low level 100 0 -50 -25 0 25 50 Tj (C) 75 100 125 150 175 50 -50 -25 0 25 50 Tj (C) 75 100 125 150 175 Figure 34. Start-up timer period vs TJ Figure 35. HV start voltage vs TJ 100   450 After OCP 400 350 300 80 60 Ti m e (us) 250 200 150 100 50 Timer V 40 F irst Cicle 20 0 0 -50 -25 0 25 50 Tj (C) 75 100 125 150 175 -50 -25 0 25 50 75 Tj (C) 100 125 150 175 22/48 Doc ID 16047 Rev 2 L6563H Typical electrical performance Figure 36. VCC restart voltage vs TJ Figure 37. HV breakdown voltage vs TJ   14   800 750 12 ICC 700 10 V fa ll i ng 6 V 8 650 600 4 550 2 0 -50 -25 0 25 50 75 100 125 150 175 T j (C) 500 -50 -25 0 25 50 75 Tj (C) 100 125 150 175 Doc ID 16047 Rev 2 23/48 Application information L6563H 6 6.1 Application information Overvoltage protection Normally, the voltage control loop keeps the output voltage Vo of the PFC pre-regulator close to its nominal value, set by the ratio of the resistors R1 and R2 of the output divider. A pin of the device (PFC_OK) has been dedicated to monitor the output voltage with a separate resistor divider (R3 high, R4 low, see Figure 38). This divider is selected so that the voltage at the pin reaches 2.5 V if the output voltage exceeds a preset value, usually larger than the maximum Vo that can be expected. Example: VO = 400 V, VOX = 434 V. Select: R3 = 8.8 MΩ; then: R4 = 8.8 MΩ ·2.5/(434-2.5) = 51 kΩ. When this function is triggered, the gate drive activity is immediately stopped until the voltage on the pin PFC_OK drops below 2.4 V. Notice that R1, R2, R3 and R4 can be selected without any constraints. The unique criterion is that both dividers have to sink a current from the output bus which needs to be significantly higher than the bias current of both INV and PFC_OK pins. Figure 38. Output voltage setting, OVP and FFP functions: internal block diagram 24/48 Doc ID 16047 Rev 2 L6563H Application information 6.2 Feedback failure protection (FFP) The OVP function above described handles “normal” over voltage conditions, i.e. those resulting from an abrupt load/line change or occurring at start-up. In case the overvoltage is generated by a feedback disconnection, for instance when the upper resistor of the output divider (R1) fails open, an additional circuitry behind the pin PFC_OK detects the voltage gap with respect to pin INV. If the voltage gap is greater than 40 mV and the OVP is active, the FFP is triggered, the gate drive activity is immediately stopped, the device is shut down, its quiescent consumption is reduced below 180 µA and the condition is latched as long as the supply voltage of the IC is above the UVLO threshold. At the same time the pin PWM_LATCH is asserted high. PWM_LATCH is an open source output able to deliver 2.8 V minimum with 0.25 mA load, intended for tripping a latched shutdown function of the PWM controller IC in the cascaded dc-dc converter, so that the entire unit is latched off. To restart the system it is necessary to recycle the input power, so that the Vcc voltage of both the L6563H goes below 6V and that one of the PWM controller goes below its UVLO threshold. The pin PFC_OK doubles its function as a not-latched IC disable: a voltage below 0.23V shutdown the IC, reducing its consumption below 2 mA. In this case both PWM_STOP and PWM_LATCH keep their high impedance status. To restart the IC simply let the voltage at the pin go above 0.27 V. Note that these functions offer a complete protection against not only feedback loop failures or erroneous settings, but also against a failure of the protection itself. Either resistor of the PFC_OK divider failing short or open or a PFC_OK pin floating results in shutting down the IC and stopping the pre-regulator. 6.3 Voltage feedforward The power stage gain of PFC pre-regulators varies with the square of the RMS input voltage. So does the crossover frequency fc of the overall open-loop gain because the gain has a single pole characteristic. This leads to large trade-offs in the design. For example, setting the gain of the error amplifier to get fc = 20 Hz @ 264 Vac means having fc 4 Hz @ 88 Vac, resulting in a sluggish control dynamics. Additionally, the slow control loop causes large transient current flow during rapid line or load changes that are limited by the dynamics of the multiplier output. This limit is considered when selecting the sense resistor to let the full load power pass under minimum line voltage conditions, with some margin. But a fixed current limit allows excessive power input at high line, whereas a fixed power limit requires the current limit to vary inversely with the line voltage. Voltage Feedforward can compensate for the gain variation with the line voltage and allow minimizing all of the above-mentioned issues. It consists of deriving a voltage proportional to the input RMS voltage, feeding this voltage into a squarer/divider circuit (1/V2 corrector) and providing the resulting signal to the multiplier that generates the current reference for the inner current control loop (see Figure 39). Doc ID 16047 Rev 2 25/48 Application information L6563H Figure 39. Voltage feedforward: squarer-divider (1/V2) block diagram and transfer characteristic In this way a change of the line voltage causes an inversely proportional change of the half sine amplitude at the output of the multiplier (if the line voltage doubles the amplitude of the multiplier output is halved and vice versa) so that the current reference is adapted to the new operating conditions with (ideally) no need for invoking the slow dynamics of the error amplifier. Additionally, the loop gain is constant throughout the input voltage range, which improves significantly dynamic behavior at low line and simplifies loop design. Actually, deriving a voltage proportional to the RMS line voltage implies a form of integration, which has its own time constant. If it is too small the voltage generated is affected by a considerable amount of ripple at twice the mains frequency that causes distortion of the current reference (resulting in high THD and poor PF); if it is too large there is a considerable delay in setting the right amount of feedforward, resulting in excessive overshoot and undershoot of the pre-regulator's output voltage in response to large line voltage changes. Clearly a trade-off was required. The L6563H realizes a NEW voltage feed forward that, with a technique that makes use of just two external parts, strongly minimizes this time constant trade-off issue whichever voltage change occurs on the mains, both surges and drops. A capacitor CFF and a resistor RFF, both connected from the pin VFF (#5) to ground, complete an internal peak-holding circuit that provides a DC voltage equal to the peak of the rectified sine wave applied on pin MULT (#3). In this way, in case of sudden line voltage rise, CFF is rapidly charged through the low impedance of the internal diode; in case of line voltage drop, an internal “mains drop” detector enables a low impedance switch which suddenly discharges CFF avoiding long settling time before reaching the new voltage level. Consequently, an acceptably low steady-state ripple and low current distortion can be achieved without any considerable undershoot or overshoot on the pre-regulator's output, like in systems with no feedforward compensation. The twice-mains-frequency (2•fL) ripple appearing across CFF is triangular with a peak-topeak amplitude that, with good approximation, is given by: ΔVFF = 2 VMULTpk 1 + 4fLRFF CFF 26/48 Doc ID 16047 Rev 2 L6563H Application information where fL is the line frequency. The amount of 3rd harmonic distortion introduced by this ripple, related to the amplitude of its 2•fL component, is: D3 % = 100 2π fLRFF CFF Figure 40 shows a diagram that helps choose the time constant RFF·CFF based on the amount of maximum desired 3rd harmonic distortion. Always connect RFF and CFF to the pin, the IC does not work properly if the pin is either left floating or connected directly to ground. Figure 40. RFF·CFF as a function of 3rd harmonic distortion introduced in the input current   10 1 f L= 50 Hz R FF · C FF [s] 0.1 f L= 60 Hz 0.01 0.1 1 10 D3 % The dynamics of the voltage feedforward input, that is the output of the multiplier, is limited downwards at 0.8 V (see Figure 39), so that cannot increase any more if the voltage on the VFF pin is below 0.8 V. This helps to prevent excessive power flow when the line voltage is lower than the minimum specified value. 6.4 THD optimizer circuit The L6563H is provided with a special circuit that reduces the conduction dead-angle occurring to the AC input current near the zero-crossings of the line voltage (crossover distortion). In this way the THD (total harmonic distortion) of the current is considerably reduced. A major cause of this distortion is the inability of the system to transfer energy effectively when the instantaneous line voltage is very low. This effect is magnified by the highfrequency filter capacitor placed after the bridge rectifier, which retains some residual voltage that causes the diodes of the bridge rectifier to be reverse-biased and the input current flow to temporarily stop. To overcome this issue the device forces the PFC pre-regulator to process more energy near the line voltage zero-crossings as compared to that commanded by the control loop. This results in both minimizing the time interval where energy transfer is lacking and fully discharging the high-frequency filter capacitor after the bridge. Figure 41 shows the internal block diagram of the THD optimizer circuit. Doc ID 16047 Rev 2 27/48 Application information Figure 41. THD optimizer circuit L6563H Figure 42. THD optimization: standard TM PFC controller (left side) and L6563H (right side)   Input current Input current Rectified mains voltage Rectified mains voltage Imains Input current Vdrain MOSFET's drain voltage Imains Input current Vdrain MOSFET's drain voltage 28/48 Doc ID 16047 Rev 2 L6563H Application information Essentially, the circuit artificially increases the ON-time of the power switch with a positive offset added to the output of the multiplier in the proximity of the line voltage zero-crossings. This offset is reduced as the instantaneous line voltage increases, so that it becomes negligible as the line voltage moves toward the top of the sinusoid. Furthermore the offset is modulated by the voltage on the VFF pin (see “Voltage Feedforward” section) so as to have little offset at low line, where energy transfer at zero crossings is typically quite good, and a larger offset at high line where the energy transfer gets worse. The effect of the circuit is shown in Figure 42, where the key waveforms of a standard TM PFC controller are compared to those of this chip. To take maximum benefit from the THD optimizer circuit, the high-frequency filter capacitor after the bridge rectifier should be minimized, compatibly with EMI filtering needs. A large capacitance, in fact, introduces a conduction dead-angle of the AC input current in itself even with an ideal energy transfer by the PFC pre-regulator - thus reducing the effectiveness of the optimizer circuit. 6.5 Tracking boost function In some applications it may be advantageous to regulate the output voltage of the PFC preregulator so that it tracks the RMS input voltage rather than at a fixed value like in conventional boost pre-regulators. This is commonly referred to as “tracking boost” or “follower boost” approach. With the L6563H this can be realized by connecting a resistor (RT) between the TBO pin and ground. The TBO pin presents a DC level equal to the peak of the MULT pin voltage and is then representative of the mains RMS voltage. The resistor defines a current, equal to V(TBO)/RT, that is internally 1:1 mirrored and sunk from pin INV (#1) input of the L6563H's error amplifier. In this way, when the mains voltage increases the voltage at TBO pin increases as well and so does the current flowing through the resistor connected between TBO and GND. Then a larger current is sunk by INV pin and the output voltage of the PFC pre-regulator is forced to get higher. Obviously, the output voltage moves in the opposite direction if the input voltage decreases. To avoid undesired output voltage rise should the mains voltage exceed the maximum specified value, the voltage at the TBO pin is clamped at 3V. By properly selecting the multiplier bias it is possible to set the maximum input voltage above which input-to-output tracking ends and the output voltage becomes constant. If this function is not used, leave the pin open: the device regulates a fixed output voltage. Starting from the following data: ● ● ● ● ● Vin1 = minimum specified input RMS voltage; Vin2 = maximum specified input RMS voltage; Vo1 = regulated output voltage @ Vin = Vin1; Vo2 = regulated output voltage @ Vin = Vin2; Vox = absolute maximum limit for the regulated output voltage; to set the output voltage at the desired values use the following design procedure: Doc ID 16047 Rev 2 29/48 Application information L6563H 1. Determine the input RMS voltage Vinclamp that produces Vo = Vox: Vin clamp = Vox − Vo1 Vox − Vo 2 ⋅ Vin 2 − ⋅ Vin1 Vo 2 − Vo1 Vo 2 − Vo1 and choose a value Vinx such that Vin2 ≤ Vinx < Vinclamp. This results in a limitation of the output voltage range below Vox (it is equal Vox if one chooses Vinx = Vinclamp) 2. Determine the divider ratio of the MULT pin (#3) bias: k= 3 2 ⋅ Vin x 3. 4. and check that at minimum mains voltage Vin1 the peak voltage on pin 3 is greater than 0.65 V. Determine R1, the upper resistor of the output divider, for instance 3 MΩ. Calculate the lower resistor R2 of the output divider and the adjustment resistor RT: Vin 2 − Vin1 ⎧ ⎪R2 = 2.5 ⋅ R1⋅ (Vo − 2.5 ) ⋅ Vin − (Vo − 2.5 ) ⋅ Vin ⎪ 1 2 2 1 ⎨ Vin 2 − Vin1 ⎪R T = 2 ⋅ k ⋅ R1⋅ ⎪ Vo 2 − Vo1 ⎩ 5. Check that the maximum current sourced by the TBO pin (#6) does not exceed the maximum specified (0.2 mA): ITBO max = 3 ≤ 0.2 ⋅ 10 − 3 RT Figure 43 shows the internal block diagram of the tracking boost function. Figure 43. Tracking boost block 30/48 Doc ID 16047 Rev 2 L6563H Application information Figure 44. Tracking output voltage vs Input voltage characteristic with TBO 6.6 Inductor saturation detection Boost inductor's hard saturation may be a fatal event for a PFC pre-regulator: the current upslope becomes so large (50-100 times steeper, see Figure 45) that during the current sense propagation delay the current may reach abnormally high values. The voltage drop caused by this abnormal current on the sense resistor reduces the gate-to-source voltage, so that the MOSFET may work in the active region and dissipate a huge amount of power, which leads to a catastrophic failure after few switching cycles. However, in some applications such as ac-dc adapters, where the PFC pre-regulator is turned off at light load for energy saving reasons, even a well-designed boost inductor may occasionally slightly saturate when the PFC stage is restarted because of a larger load demand. This happens when the restart occurs at an unfavorable line voltage phase, i.e. when the output voltage is significantly below the rectified peak voltage. As a result, in the boost inductor the inrush current coming from the bridge rectifier adds up to the switched current and, furthermore, there is little or no voltage available for demagnetization. To cope with a saturated inductor, the L6563H is provided with a second comparator on the current sense pin (CS, pin 4) that stops the IC if the voltage, normally limited within 1.1 V, exceeds 1.7 V. After that, the IC attempts to restart by the internal starter circuitry; the starter repetition time is twice the nominal value to guarantee lower stress for the inductor and boost diode. Hence, the system safety is considerably increased. Figure 45. Effect of boost inductor saturation on the MOSFET current and detection method Doc ID 16047 Rev 2 31/48 Application information L6563H 6.7 Power management/housekeeping functions A special feature of this IC is that it facilitates the implementation of the “housekeeping” circuitry needed to co-ordinate the operation of the PFC stage to that of the cascaded DCDC converter. The functions realized by the housekeeping circuitry ensure that transient conditions like power-up or power down sequencing or failures of either power stage be properly handled. This device provides some pins to do that. One communication line between the IC and the PWM controller of the cascaded dc-dc converter is the pin PWM_LATCH (Figure 47b), which is normally open (high impedance) when the PFC works properly, and goes high if it loses control of the output voltage (because of a feedback loop disconnection) with the aim of latching off the PWM controller of the cascaded dc-dc converter as well (see “Feedback failure protection” section for more details). A second communication line can be established via the disable function included in the PFC_OK pin (see “Feedback failure protection” section for more details). Typically this line is used to allow the PWM controller of the cascaded dc-dc converter to drive in burst mode operation the L6563H in case of light load and to minimize the no-load input consumption. Interface circuits like those are shown in Figure 46. Figure 46. Interface circuits that let dc-dc converter's controller IC drive L6563H in burst mode The third communication line is the pin PWM_STOP (#11), which works in conjunction with the pin RUN (#12). The purpose of the PWM_STOP pin is to inhibit the PWM activity of both the PFC stage and the cascaded dc-dc converter. The pin is an open collector, normally open, that goes low if the device is disabled by a voltage lower than 0.8 V on the RUN pin. It is important to point out that this function works correctly in systems where the PFC stage is the master and the cascaded dc-dc converter is the slave or, in other words, where the PFC stage starts first, powers both controllers and enables/disables the operation of the dc-dc stage. The pin RUN can be used to start and stop the main converter. In the simplest case, to enable/disable the PWM controller the pin PWM_STOP can be connected to the output of the error amplifier (Figure 47a). 32/48 Doc ID 16047 Rev 2 L6563H Application information Figure 47. Interface circuits that let the L6563H switch on or off a PWM controller If the chip is provided with a soft-start pin, it is possible to delay the start-up of the dc-dc stage with respect to that of the PFC stage, which is often desired, as described in Figure 48. An underlying assumption in order for that to work properly is that the UVLO thresholds of the PWM controller are certainly higher than those of the L6563H. Figure 48. Interface circuits for power up sequencing when dc-dc has the SS function If this is not the case or it is not possible to achieve a start-up delay long enough (because this prevents the dc-dc stage from starting up correctly) or, simply, the PWM controller is devoid of soft start, the arrangement of Figure 49 lets the dc-dc converter start-up when the voltage generated by the PFC stage reaches a preset value. The technique relies on the UVLO thresholds of the PWM controller. Doc ID 16047 Rev 2 33/48 Application information Figure 49. Interface circuits for actual power-up sequencing (master PFC) L6563H Another possible use of the RUN and PWM_STOP pins (again, in systems where the PFC stage is the master) is the brownout protection, thanks to the hysteresis provided. The brownout protection is basically a not-latched device shutdown function that is activated when a condition of mains undervoltage is detected. This condition may cause overheating of the primary power section due to an excess of RMS current. Brownout can also cause the PFC pre-regulator to work open loop and this could be dangerous to the PFC stage itself and the downstream converter, should the input voltage return abruptly to its rated value. Another problem is the spurious restarts that may occur during converter power down and that cause the output voltage of the converter not to decay to zero monotonically. For these reasons it is usually preferable to shutdown the unit in case of brownout. IC shutdown upon brownout can be easily realized as shown in Figure 50. The scheme on the left is of general use, that one on the right can be used if the bias levels of the multiplier and the RFF·CFF time constant are compatible with the specified brownout level and with the specified holdup time respectively. In this latest case, an additional resistor voltage divider and one capacitor are not needed. In table 1 it is possible to find a summary of all of the above mentioned working conditions that cause the device to stop operating. Figure 50. Brownout protection (master PFC)   L6563H 12 RUN 12 RUN L6563H 34/48 Doc ID 16047 Rev 2 L6563H Application information 6.8 High-voltage start-up generator Figure 51 shows the internal schematic of the high-voltage start-up generator (HV generator). It is made up of a high-voltage N-channel FET, whose gate is biased by a 15 MΩ resistor, with a temperature-compensated current generator connected to its source. Figure 51. High-voltage start-up generator: internal schematic The HV generator is physically located on a separate chip, made with BCD off-line technology able to withstand 700 V, controlled by a low-voltage chip, where all of the control functions reside. With reference to the timing diagram of Figure 52, when power is first applied to the converter the voltage on the bulk capacitor (Vin) builds up and, at about 80 V, the HV generator is enabled to operate (HV_EN is pulled high) so that it draws about 1 mA. This current, minus the device's consumption, charges the bypass capacitor connected from pin Vcc (16) to ground and makes its voltage rise almost linearly. Doc ID 16047 Rev 2 35/48 Application information Figure 52. Timing diagram: normal power-up and power-down sequences L6563H As the Vcc voltage reaches the start-up threshold (12 V typ.) the low-voltage chip starts operating and the HV generator is cut off by the Vcc_OK signal asserted high. The device is powered by the energy stored in the Vcc capacitor until the self-supply circuit (we assume that it is made with an auxiliary winding in the transformer of the cascaded dc-dc converter and a steering diode) develops a voltage high enough to sustain the operation. The residual consumption of this circuit is just the one on the 15 MΩ resistor (10 mW at 400 Vdc), typically 50-70 times lower, under the same conditions, as compared to a standard start-up circuit made with external dropping resistors. At converter power-down the dc-dc converter loses regulation as soon as the input voltage is so low that either peak current or maximum duty cycle limitation is tripped. Vcc then drops and stops IC activity as it falls below the UVLO threshold (9.5 V typ.). The Vcc_OK signal is de-asserted as the Vcc voltage goes below a threshold VCCrestart located at about 6 V. The HV generator can now restart. However, if Vin < VHVstart, HV_EN is de-asserted too and the HV generator is disabled. This prevents converter's restart attempts and ensures monotonic output voltage decay at power-down in systems where brownout protection (see the relevant section) is not used. If the device detects a fault due to feedback failure the pin PWM_LATCH is asserted high (see “Feedback failure protection” section for more details) and, in order to maintain alive this signal to be provided to the DC-DC converter, the internal VCCrestart is brought up to over the VccOff (Turn-off threshold). As a result, shown in Figure 53, the voltage at pin Vcc, oscillates between its turn-on and turn-off thresholds until the HV bus is recycled and drops below the start up threshold of the HV generator. The High Voltage Start-up circuitry is capable to guarantee a safe behavior in case of short circuit present on the dc-dc output when the Vcc of both controllers are generated by the same auxiliary winding. The Figure 54 shows how the PFC manages the Vcc cycling and the associated power transfer. At short circuit the auxiliary circuit is no longer able to sustain the Vcc which start dropping; reaching its VccOFF threshold the IC stops switching, reduces 36/48 Doc ID 16047 Rev 2 L6563H Application information consumption and drops more until the Vccrestart threshold is tripped. Now, the high voltage start-up generator restarts and when the Vcc crosses again its turn on threshold the IC starts switching. In this manner the power is transferred from mains to PFC output only during a short time for each Trep cycle. Figure 53. High-voltage start-up behaviour during latch-off protection Figure 54. High-voltage start-up managing the dc-dc output short-circuit Doc ID 16047 Rev 2 37/48 Application information L6563H Table 5. Condition UVLO Feedback disconnected Standby AC brownout OVP Low consumption Saturated boost inductor Summary of L6563H idle states Caused or revealed bey Vcc < VccOff PFC_OK > VPFC_OK_S AND INV < PFC_OK - 40mV PFC_OK < VPFC_OK_D RUN < VDIS PFC_OK > VPFC_OK_S COMP < 2.4V Burst mode Doubled Tstart Stop switching IC behavior Disabled Latched Restart condition Vcc > VccOn Vcc < Vccrestart then Vcc > VccOn PFC_OK > VPFC_OK_E RUN > VEN PFC_OK < VPFC_OK_R COMP > 2.4V Typical IC consumption 90 µA 180 µA PWM_LATCH PWM_STOP Status Off High Status High High 1.5 mA 1.5 mA 2.2 mA 2.2 mA Off Off Off Off High Low High High Vcs > VCS_th Auto restart 2.2 mA Off High 38/48 Doc ID 16047 Rev 2 L6563H Application examples and ideas 7 Application examples and ideas Figure 55. Demonstration board EVL6563H-100W, wide-range mains: electrical schematic Doc ID 16047 Rev 2 39/48 Application examples and ideas L6563H Figure 56. L6563H 100 W TM PFC evaluation board: compliance to EN61000-3-2 standard Figure 57. L6563H 100 W TM PFC evaluation board: compliance to JEITA-MITI standard Measured value 10 JEITA-MITI Class-D limits   1 Me as ur e d v alue EN61 000 -3- 2 clas s -D lim it s 0 .1 Harmonic Current [A] Harmonic Current [A] 1 0.1 0.01 0.001 0.01 0.001 0 .0 001 1 3 5 7 9 11 13 1 5 17 19 2 1 2 3 25 2 7 2 9 31 3 3 3 5 37 3 9 0.0001 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 Harmonic Order [n] Harmonic Order [n] Vin = 230 Vac - 50 Hz, Pout = 100 W THD = 7.58%, PF = 0.979 Vin = 100 Vac - 50 Hz, Pout = 100 W THD = 2.5%, PF = 0.997 Figure 58. L6563H 100 W TM PFC evaluation board: input current waveform @230-50 Hz - 100 W load Figure 59. L6563H 100W TM PFC evaluation board: input current waveform @100 V-50 Hz - 100 W load 40/48 Doc ID 16047 Rev 2 L6563H Application examples and ideas Figure 60. Application board 90W-19V adapter with L6563H, L6599A, SRK2000 Doc ID 16047 Rev 2 41/48 Application examples and ideas Figure 61. Application board 130 W-12 V adapter with L6563H, L6599A, SRK2000 L6563H 42/48 Doc ID 16047 Rev 2 L6563H Application examples and ideas Figure 62. Demonstration board EVL6563H-650W wide-range mains: electrical schematics Doc ID 16047 Rev 2 43/48 Package mechanical data L6563H 8 Package mechanical data In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK® packages, depending on their level of environmental compliance. ECOPACK® specifications, grade definitions and product status are available at: www.st.com. ECOPACK is an ST trademark. Table 6. SO16 mechanical data mm Dim. Min. A A1 A2 b c D E E1 e h L k ccc 0.25 0.4 0 0.1 1.25 0.31 0.17 9.8 5.8 3.8 9.9 6 3.9 1.27 0.5 1.27 8 0.1 0.51 0.25 10 6.2 4 Typ. Max. 1.75 0.25 44/48 Doc ID 16047 Rev 2 L6563H Figure 63. SO16 mechanical data Package mechanical data Doc ID 16047 Rev 2 45/48 Ordering codes L6563H 9 Ordering codes Table 7. Ordering information Order codes L6563H SO16 L6563HTR Tape and reel Package Packing Tube 46/48 Doc ID 16047 Rev 2 L6563H Revision history 10 Revision history Table 8. Date 22-Jul-2009 01-Feb-2010 Document revision history Revision 1 2 Initial release. Updated Table 4 on page 11 Changes Doc ID 16047 Rev 2 47/48 L6563H Please Read Carefully: Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any time, without notice. All ST products are sold pursuant to ST’s terms and conditions of sale. Purchasers are solely responsible for the choice, selection and use of the ST products and services described herein, and ST assumes no liability whatsoever relating to the choice, selection or use of the ST products and services described herein. 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The ST logo is a registered trademark of STMicroelectronics. All other names are the property of their respective owners. © 2010 STMicroelectronics - All rights reserved STMicroelectronics group of companies Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan Malaysia - Malta - Morocco - Philippines - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States of America www.st.com 48/48 Doc ID 16047 Rev 2