L6564H

L6564H High voltage startup transition-mode PFC Datasheet − production data Features ■ Onboard 700 V startup source ■ Fast “bi-directional” input voltage feedforward (1/V2 correction) ■ Accurate adjustable output overvoltage protection ■ Protection against feedback loop disconnection (latched shutdown) ■ Inductor saturation protection ■ AC brownout detection ■ Low (≤100 µA) startup current ■ 6 mA max. operating bias current ■ 1% (@ TJ = 25 °C) internal reference voltage ■ -600/+800 mA totem pole gate driver with active pull-down during UVLO ■ SO-14 package Figure 1. SO-14 Application ■ PFC pre-regulators for: – High-end AC-DC adapter/charger – IEC61000-3-2 or JEITA-MITI compliant SMPS, in excess of 400 W – SMPS for LED luminaires Block diagram HVS ZCD 11 Vcc 8 14 Icharge Zero Current Detector + - Disable 1.4V 0.7V - PFC_OK 2.5 V 2.4 V Voltage ref erences … 6 0.23 V 0.27 V + VOLTAGE REGULATOR - OVP UVLO 13 L_OVP GD + S Q1 + 1.66 V R - STARTER COMP INV 2 Starter OFF 1 2.5 V DISABLE + Error Amplif ier Disable Q1 Q OVP ON/OFF Control LEB MULT UVLO Internal Supply Bus 3 L_OVP R UVLO 12 - GND + Ideal rectif ier S - + 4 1/V2 ON/OFF Control + - CS MULTIPLIER 0.8 V 0.88 V + MAINS DROP DETECTOR 1.7 V Disable - 5 VFF AM11475v1 June 2012 This is information on a product in full production. Doc ID 022960 Rev 2 1/35 www.st.com 35 Contents L6564H Contents 1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 2 Maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2.1 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2.2 Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 3 Pin connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 4 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 5 Typical electrical performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 6 Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 6.1 Overvoltage protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 6.2 Feedback failure protection (FFP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 6.3 Voltage feedforward . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 6.4 THD optimizer circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 6.5 Inductor saturation detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 6.6 Power management/housekeeping functions . . . . . . . . . . . . . . . . . . . . . . 24 7 High voltage startup generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 8 Application examples and ideas . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 9 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 10 Ordering codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 11 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 2/35 Doc ID 022960 Rev 2 L6564H List of tables List of tables Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Thermal data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Summary of L6564H idle states . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 SO-14 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Doc ID 022960 Rev 2 3/35 List of figures L6564H List of figures Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Figure 10. Figure 11. Figure 12. Figure 13. Figure 14. Figure 15. Figure 16. Figure 17. Figure 18. Figure 19. Figure 20. Figure 21. Figure 22. Figure 23. Figure 24. Figure 25. Figure 26. Figure 27. Figure 28. Figure 29. Figure 30. Figure 31. Figure 32. Figure 33. Figure 34. Figure 35. Figure 36. Figure 37. Figure 38. Figure 39. Figure 40. Figure 41. Figure 42. Figure 43. Figure 44. Figure 45. Figure 46. Figure 47. 4/35 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Pin connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Typical system block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 IC consumption vs. VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 IC consumption vs. TJ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 VCC Zener voltage vs. TJ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Startup and UVLO vs. TJ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Feedback reference vs. TJ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 E/A output clamp levels vs. TJ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 UVLO saturation vs. TJ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 OVP levels vs. TJ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Inductor saturation threshold vs. TJ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Vcs clamp vs. TJ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 ZCD sink/source capability vs. TJ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 ZCD clamp level vs. TJ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 R discharge vs. TJ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Line drop detection threshold vs. TJ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 VMULTpk - VVFF dropout vs. TJ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 PFC_OK threshold vs. TJ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 PFC_OK FFD threshold vs. TJ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Multiplier characteristics @VFF=1 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Multiplier characteristics @VFF=3 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Multiplier gain vs. TJ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Gate drive clamp vs. TJ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Gate drive output saturation vs. TJ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Delay to output vs. TJ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Startup timer period vs. TJ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 HV start voltage vs. TJ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 VCC restart voltage vs. TJ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 HV breakdown voltage vs. TJ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Output voltage setting, OVP and FFP functions: internal block diagram . . . . . . . . . . . . . . 18 Voltage feedforward: squarer/divider (1/V2) block diagram and transfer characteristics . . 19 RFF·CFF as a function of 3rd harmonic distortion introduced in the input current . . . . . . . 21 THD optimizer circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 THD optimization: standard TM PFC controller (left side) and L6564H (right side) . . . . . . 23 Effect of boost inductor saturation on the MOSFET current and detection method . . . . . . 24 Interface circuits that let the DC-DC converter’s controller IC disable the L6564H . . . . . . 25 High voltage startup generator: internal schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Timing diagram: normal power-up and power-down sequences . . . . . . . . . . . . . . . . . . . . 26 High voltage startup behavior during latch-off protection . . . . . . . . . . . . . . . . . . . . . . . . . . 27 High voltage startup managing the DC-DC output short-circuit . . . . . . . . . . . . . . . . . . . . . 28 Demonstration board EVL6564H - 100 W, wide-range mains: electrical schematic. . . . . . 29 EVL6564H demonstration board: compliance to EN61000-3-2 standard . . . . . . . . . . . . . . 30 EVL6564H demonstration board: compliance to JEITA-MITI standard . . . . . . . . . . . . . . . 30 EVL6564H demonstration board: input current waveform @230 V -50 Hz - 100 W load . . 30 EVL6564H demonstration board: input current waveform @100 V - 50 Hz - 100 W load . 30 SO-14 package dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Doc ID 022960 Rev 2 L6564H 1 Description Description The L6564H is a current-mode PFC controller operating in transition mode (TM) which embeds the same features existing in the L6564 with the addition of a high voltage startup source. These functions make the IC especially suitable for applications that must be compliant with energy saving regulations and where the PFC preregulator works as the master stage. The highly linear multiplier, along with a special correction circuit that reduces crossover distortion of the mains current, allows wide-range-mains operation with an extremely low THD even over a large load range. The output voltage is controlled by means of a voltage-mode error amplifier and an accurate (1% @TJ = 25 °C) internal voltage reference. The loop stability is optimized by the voltage feedforward function (1/V2 correction), which, in this IC, uses a proprietary technique that also considerably improves line transient response in the case of both mains drops and surges (“bi-directional”). In addition to overvoltage protection able to control the output voltage during transient conditions, the IC also provides protection against feedback loop failures or erroneous settings. Other onboard protection functions allow brownout conditions and boost inductor saturation to be safely handled. The totem pole output stage, capable of a 600 mA source and 800 mA sink current, is suitable for a high power MOSFET or IGBT drive. This, combined with the other features and the possibility to operate with ST's proprietary fixed-off-time control, makes the device an excellent solution for SMPS up to 400 W that requires compliance with EN61000-3-2 and JEITA-MITI standards. Doc ID 022960 Rev 2 5/35 Maximum ratings L6564H 2 Maximum ratings 2.1 Absolute maximum ratings Table 1. Symbol Pin Value Unit VHVS 8 Voltage range (referred to ground) -0.3 to 700 V IHVS 8 Output current Self-limited IHVS VCC 14 IC supply voltage (Icc ≤ 20 mA) Self-limited V --- 1, 3, 6 Max. pin voltage (Ipin ≤ 1 mA) Self-limited V --- 2, 4, 5 Analog inputs and outputs -0.3 to 8 V IZCD 11 -10 (source) 10 (sink) mA VFF pin 5 +/- 1750 V +/- 2000 V Value Unit Other pins 2.2 Absolute maximum ratings Parameter Zero current detector max. current Maximum withstanding voltage range test condition: CDF-AEC-Q100-002 1 to 4 “human body model” 6, 8, 11 to 14 acceptance criteria: “normal performance” Thermal data Table 2. Thermal data Symbol 6/35 Parameter RthJA Max. thermal resistance, junction-to-ambient 120 °C/W Ptot Power dissipation @TA = 50 °C 0.75 W TJ Junction temperature operating range -40 to 150 °C Tstg Storage temperature -55 to 150 °C Doc ID 022960 Rev 2 L6564H Pin connection 3 Pin connection Figure 2. Pin connection INV 1 14 Vcc COMP 2 13 GD MULT 3 12 GND CS 4 11 ZCD VFF 5 10 N.C. PFC_OK 6 9 N.C. N.C. 7 8 HVS AM11476v1 Table 3. Pin description n° Name 1 INV Function Inverting input of the error amplifier. The information on the output voltage of the PFC preregulator is fed into the pin through a resistor divider. The pin normally features high impedance. 2 COMP Output of the error amplifier. A compensation network is placed between this pin and INV (pin 1) to achieve stability of the voltage control loop and ensure high power factor and low THD. To avoid an uncontrolled rise of the output voltage at zero load, when the voltage on the pin falls below 2.4 V the gate driver output is inhibited (burst-mode operation). 3 MULT Main input to the multiplier. This pin is connected to the rectified mains voltage via a resistor divider and provides the sinusoidal reference to the current loop. The voltage on this pin is used also to derive the information on the RMS mains voltage. CS Input to the PWM comparator. The current flowing in the MOSFET is sensed through a resistor, the resulting voltage is applied to this pin and compared with an internal reference to determine MOSFET turn-off. A second comparison level at 1.7 V detects abnormal currents (e.g. due to boost inductor saturation) and, on this occurrence, activates a safety procedure that temporarily stops the converter and limits the stress of the power components. VFF Second input to the multiplier for 1/V2 function. A capacitor and a parallel resistor must be connected from the pin to GND. They complete the internal peak-holding circuit that derives the information on the RMS mains voltage. The voltage at this pin, a DC level equal to the peak voltage on the MULT pin (3), compensates the control loop gain dependence on the mains voltage. Never connect the pin directly to GND but with a resistor ranging from 100 KΩ (minimum) to 2 MΩ (maximum). 4 5 Doc ID 022960 Rev 2 7/35 Pin connection Table 3. n° L6564H Pin description (continued) Name Function 6 PFC_OK PFC pre-regulator output voltage monitoring/disable function. This pin senses the output voltage of the PFC pre-regulator through a resistor divider and is used for protection purposes. If the voltage on the pin exceeds 2.5 V, the IC stops switching and restarts as the voltage on the pin falls below 2.4 V. However, if at the same time the voltage of the INV pin falls below 1.66 V, a feedback failure is assumed. In this case the device is latched off. Normal operation can be resumed only by cycling VCC. bringing its value lower than 6 V before moving up to the turn-on threshold. If the voltage on this pin is brought below 0.23 V, the IC is shut down. To restart the IC the voltage on the pin must go above 0.27 V. This can be used as a remote on/off control input. 7 N.C. Not internally connected. Provision for clearance on the PCB to meet safety requirements. 8 HVS High voltage startup. The pin, able to withstand 700 V, is to be tied directly to the rectified mains voltage. A 1 mA internal current source charges the capacitor connected between the VCC pin (14) and the GND pin (12) until the voltage on the VCC pin reaches the startup threshold, it is then shut down. Normally, the generator is re-enabled when the VCC voltage falls below 6 V to ensure a low power throughput during short-circuit. Otherwise, when a latched protection is tripped the generator is re-enabled as VCC reaches the UVLO threshold to keep the latch supplied. 9 N.C. Not internally connected. Provision for clearance on the PCB to meet safety requirements. 10 N.C. Not internally connected. Provision for clearance on the PCB to meet safety requirements. 11 ZCD Boost inductor demagnetization sensing input for transition-mode operation. A negative-going edge triggers MOSFET turn-on. 12 GND Ground. Current return for both the signal part of the IC and the gate driver. 13 GD Gate driver output. The totem pole output stage is able to drive Power MOSFETs and IGBTs with a peak current of 600 mA source and 800 mA sink. The high level voltage of this pin is clamped at about 12 V to avoid excessive gate voltages. 14 VCC Supply voltage of both the signal part of the IC and the gate driver. Sometimes a small bypass capacitor (0.1 µF typ.) to GND might be useful to get a clean bias voltage for the signal part of the IC. Figure 3. Typical system block diagram PFC PRE-REGULATOR DC-DC CONVERTER Voutdc Vinac PWM is turned off in case of PFC's anomalous operation for safety L6564H PWM or Resonant CONTROLLER PFC can be handled off/on according to the load condition to ease compliance with energy saving regulations. AM11477v1 8/35 Doc ID 022960 Rev 2 L6564H 4 Electrical characteristics Electrical characteristics (TJ = -25 to 125 °C, VCC= 12 V, CO = 1 nF between pin GD and GND, CFF = 1 µF and RFF = 1 MΩ between pin VFF and GND; unless otherwise specified.) Table 4. Electrical characteristics Symbol Parameter Test condition Min. Typ. Max. Unit 22.5 V Supply voltage VCC Operating range After turn-on VCCOn Turn-on threshold (1) 11 12 13 V VCCOff Turn-off threshold (1) 8.7 9.5 10.3 V VCC for resuming from latch OVP latched 5 6 7 V 2.7 V 25 28 V VCCrestart Hys Hysteresis VZ Zener voltage 10.3 2.3 Icc = 20 mA 22.5 Supply current Istart-up Startup current Before turn-on, VCC = 10 V 90 150 µA Quiescent current After turn-on, VMULT = 1 V 4 5 mA ICC Operating supply current @ 70 kHz 5 6.0 mA 280 µA Idle state quiescent current VPFC_OK> VPFC_OK_S AND VINV VHvstart, VCC> 3 V 0.55 0.85 1 mA IHV, ON ON-state current VHV > VHvstart, VCC> 3 V 1.6 mA VHV > VHvstart, VCC = 0 0.8 VHV = 400 V 40 VHVstart IHV, OFF VCCrestart OFF-state leakage current VCC restart voltage VCC falling (1) IC latched off V 5 6 7 8.7 9.5 10.3 -0.2 -1 µA V Multiplier input IMULT Input bias current VMULT Linear operation range VCLAMP Internal clamp level VMULT = 0 to 3 V 0 to 3 IMULT = 1 mA Doc ID 022960 Rev 2 9 µA V 9.5 V 9/35 Electrical characteristics Table 4. Electrical characteristics (continued) Symbol ∆V CS --------------------∆VMULT KM L6564H Parameter Test condition Min. Typ. Max. Output max. slope VMULT = 0 to 0.4 V, VVFF = 1 V VCOMP = upper clamp 1.33 1.66 Gain (2) VMULT = 1 V, VCOMP = 4 V 0.375 0.45 0.525 Voltage feedback input threshold TJ = 25 °C 2.475 2.5 2.525 10.3 V < VCC < 22.5 V (2) 2.455 Line regulation VCC = 10.3 V to 22.5 V Input bias current VINV = 0 to 4 V Unit V/V V Error amplifier VINV IINV VINVCLAMP Internal clamp level Gv Voltage gain GB Gain-bandwidth product ICOMP VCOMP V 2.545 2 5 mV -0.2 -1 µA IINV = 1 mA 8 9 V Open loop 60 80 dB 1 MHz Source current VCOMP = 4 V, VINV = 2.4 V 2 4 mA Sink current VCOMP = 4 V, VINV = 2.6 V 2.5 4.5 mA Upper clamp voltage ISOURCE = 0.5 mA 5.7 6.2 6.7 Burst-mode voltage (1) 2.3 2.4 2.5 2.1 2.25 2.4 Lower clamp voltage ISINK = 0.5 mA (1) V Current sense comparator ICS Input bias current tLEB Leading edge blanking 100 Delay to output td(H-L) VCSclamp Vcsofst Current sense reference clamp Current sense offset VCS = 0 1 µA 150 250 ns 100 200 300 ns 1.0 1.08 1.16 V VMULT = 0, VVFF = 3 V 40 70 VMULT = 3 V, VVFF = 3 V 20 VCOMP = upper clamp, VMULT =1 V, VVFF = 1 V mV Boost inductor saturation detector VCS_th IINV Threshold on current sense (1) E/A input pull-up current After VCS > VCS_th, before restarting 1.6 1.7 1.8 V 5 10 13 µA -0.1 -1 µA PFC_OK functions IPFC_OK Input bias current VPFC_OK = 0 to 2.6 V VPFC_OK_C Clamp voltage IPFC_OK = 1 mA VPFC_OK_S OVP threshold (1) VPFC_OK_R Restart threshold after OVP (1) 10/35 9 9.5 voltage rising 2.435 2.5 2.565 V voltage falling 2.34 2.4 2.46 V Doc ID 022960 Rev 2 V L6564H Table 4. Electrical characteristics Electrical characteristics (continued) Symbol Parameter Test condition Min. Max. Unit 0.35 V 0.29 V 0.38 V 0.27 0.32 V 1.61 1.66 1.71 V VPFC_OK_D Disable threshold (1) voltage falling 0.12 VPFC_OK_D Disable threshold (1) voltage falling TJ = 25 °C 0.17 VPFC_OK_E Enable threshold (1) voltage rising 0.15 VPFC_OK_E Enable threshold (1) voltage rising TJ = 25 °C 0.21 VPFC_OK > VPFC_OK_S VFFD VINV feedback failure detection threshold (VINV falling) Typ. 0.23 Zero current detector VZCDH Upper clamp voltage IZCD = 2.5 mA 5.0 5.7 VZCDL Lower clamp voltage IZCD = - 2.5 mA -0.3 0 0.3 V VZCDA Arming voltage (positive-going edge) 1.1 1.4 1.9 V VZCDT Triggering voltage (negative-going edge) 0.5 0.7 0.9 V IZCDb Input bias current 1 µA VZCD = 1 to 4.5 V V IZCDsrc Source current capability -2.5 -4 mA IZCDsnk Sink current capability 2.5 5 mA 25 50 75 µs 75 150 300 µs 150 300 600 Startup timer tSTART_DEL Startup delay tSTART First cycle after wake-up Timer period Restart after VCS > VCS_th Voltage feedforward VVFF Linear operation range ∆V Dropout VMULTpk-VVFF 1 3 V VCC< VCCOn 800 mV VCC > or = to VCCOn 20 ∆VVFF Line drop detection threshold Below peak value 40 70 100 mV ∆VVFF Line drop detection threshold Below peak value TJ = 25 °C 50 70 90 mV 10 12.5 kΩ Internal discharge resistor TJ = 25 °C 7.5 RDISCH 5 20 Disable threshold (1) voltage falling 0.745 0.8 0.855 V Enable threshold (1) voltage rising 0.845 0.88 0.915 V VOL Output low voltage Isink = 100 mA 0.6 1.2 V VOH Output high voltage Isource = 5 mA Isrcpk Peak source current -0.6 A Isnkpk Peak sink current 0.8 A VDIS VEN Gate driver Doc ID 022960 Rev 2 9.8 10.3 V 11/35 Electrical characteristics Table 4. L6564H Electrical characteristics (continued) Symbol Parameter Test condition Typ. Max. Unit tf Voltage fall time 30 60 ns tr Voltage rise time 45 110 ns 12 15 V 1.1 V VOclamp Output clamp voltage Isource = 5 mA; VCC = 20 V UVLO saturation VCC= 0 to VCCOn, Isink= 2 mA 1. Parameters tracking each other. 2. The multiplier output is given by: Vcs = VCS_Ofst + K M· ( VMULT · VCOMP - 2. 5 ) 2 VVF F 12/35 Min. Doc ID 022960 Rev 2 10 L6564H Typical electrical performance 5 Typical electrical performance Figure 4. IC consumption vs. VCC Figure 5. 100 IC consumption vs. TJ 10 Operating 10 Quiescent Disabled or during OVP 1 Co=1nF f =70kHz Tj = 25°C Icc [mA] VCC=12V Co = 1nF f =70kHz Ic current (mA) 1 0.1 Latched off 0.1 Before Start up 0.01 VccOFF VccON 0.01 0.001 0 5 10 15 Vcc [V] 20 25 -50 30 -25 0 25 50 75 100 125 150 AM11433v1 AM11478v1 Figure 6. 175 Tj (C) VCC Zener voltage vs. TJ Figure 7. 28 Startup and UVLO vs. TJ 13 VCC-ON 12 27 11 26 10 V V VCC-OFF 25 9 24 8 23 7 6 22 -50 -25 0 25 50 75 100 125 150 175 -50 -25 0 25 50 Tj (C) 75 100 125 150 AM11435v1 AM11434v1 Figure 8. 175 Tj (C) Feedback reference vs. TJ Figure 9. 2.6 E/A output clamp levels vs. TJ 7 Uper Clamp 6 VCC = 12V 2.55 5 VCOMP (V) pin INV (V) VCC = 12V 2.5 4 3 Lower Clamp 2 2.45 1 0 2.4 -50 -25 0 25 50 75 Tj (C) 100 125 150 175 -50 -25 0 25 50 75 100 125 150 175 Tj (C) AM11436v1 Doc ID 022960 Rev 2 AM11437v1 13/35 Typical electrical performance L6564H Figure 10. UVLO saturation vs. TJ Figure 11. OVP levels vs. TJ 2.5 1 0.9 2.48 VCC = 0V 0.8 OVP Th 2.46 PFC_OK levels (V) 0.7 V 0.6 0.5 0.4 2.44 2.42 2.4 0.3 Restart Th 0.2 2.38 0.1 2.36 0 -50 -50 -25 0 25 50 75 Tj (C) 100 125 150 -25 0 25 50 175 75 100 125 150 175 Tj (C) AM11438v1 AM11439v1 Figure 12. Inductor saturation threshold vs. TJ Figure 13. Vcs clamp vs. TJ 1.4 1.9 1.8 1.7 1.3 VCC = 12V VCOMP =Upper clamp VCSx (V) CS pin (V) 1.6 1.5 1.2 1.4 1.3 1.1 1.2 1.1 1 -50 -25 0 25 50 75 100 125 150 175 -50 -25 0 25 50 Tj (C) 75 100 125 150 AM11440v1 Figure 14. ZCD sink/source capability vs. TJ AM11441v1 Figure 15. ZCD clamp level vs. TJ 8 7 Sink current Upper Clamp 6 6 4 5 2 4 VZCD pin (V) IZCDsrc (mA) 175 Tj (C) VCC = 12V 0 -2 VCC = 12V Izcd = ±2.5mV 3 2 Source current -4 1 -6 0 Lower Clamp -8 -1 -50 -25 0 25 50 75 100 125 150 175 AM11442v1 14/35 -50 -25 0 25 50 75 100 125 150 175 Tj (C) Tj (C) Doc ID 022960 Rev 2 AM11443v1 L6564H Typical electrical performance Figure 16. R discharge vs. TJ Figure 17. Line drop detection threshold vs. TJ 90 20 80 18 70 16 60 14 50 mV kOhm 12 10 40 8 30 6 20 4 10 2 0 0 -50 -25 0 25 50 75 100 125 150 175 -50 -25 0 25 Tj (C) 50 75 100 125 150 175 Tj (C) AM11444v1 Figure 18. VMULTpk - VVFF dropout vs. TJ AM11445v1 Figure 19. PFC_OK threshold vs. TJ 0.4 2 0.35 1.5 0.3 1 0.25 Th (V) (mV) 0.5 0 ON 0.2 OFF 0.15 -0.5 -1 0.1 -1.5 0.05 -2 0 -50 -25 0 25 50 75 Tj (C) 100 125 150 175 AM11446v1 -50 -25 0 25 50 Tj (C) 75 100 125 150 175 AM11447v1 Figure 20. PFC_OK FFD threshold vs. TJ 2 1.9 VFFD Th (V) 1.8 1.7 1.6 1.5 1.4 -50 -25 0 25 50 75 100 125 150 175 Tj(C) AM11448v1 Doc ID 022960 Rev 2 15/35 Typical electrical performance L6564H Figure 21. Multiplier characteristics @VFF=1 V Figure 22. Multiplier characteristics @VFF=3 V 700 1.2 VCOMP 1.1 VCOMP Upper voltage clamp 1 600 5.5 5.0V 4.5V 0.9 Upper voltage 500 0.8 5.5V 4.0V VCS (mV) VCS (V) 0.7 0.6 0.5 400 5.0V 4.5V 300 3.5V 4.0V 0.4 200 0.3 3.5V 0.2 3.0 100 3.0V 0.1 2.6V 2.6V 0 0 0 0.1 0.2 0.3 0.4 0.5 0.6 VMULT (V) 0.7 0.8 0.9 1 1.1 0 0.5 1 1.5 2 VMULT (V) 2.5 3 AM11449v1 Figure 23. Multiplier gain vs. TJ 3.5 AM11450v1 Figure 24. Gate drive clamp vs. TJ 12.9 0.5 VCC = 20V 12.85 0.4 Gain (1/V) 12.8 V VCC = 12V VCOMP = 4V VMULT = VFF = 1V 12.75 0.3 12.7 0.2 -50 -25 0 25 50 75 100 125 150 175 12.65 -50 -25 0 25 Tj (C) 50 75 Tj (C) 100 125 150 AM11451v1 175 AM11452v1 Figure 25. Gate drive output saturation vs. TJ Figure 26. Delay to output vs. TJ 12 300 High level 10 250 TD(H-L) (ns) V 8 6 200 VCC = 12V 150 4 100 Low level 2 50 0 -50 -25 0 25 50 75 100 125 150 175 Tj (C) AM11453v1 16/35 Doc ID 022960 Rev 2 -50 -25 0 25 50 75 Tj (C) 100 125 150 175 AM11454v1 L6564H Typical electrical performance Figure 27. Startup timer period vs. TJ Figure 28. HV start voltage vs. TJ 450 100 After OCP 400 80 350 300 V Time (us) 60 250 Timer 200 40 150 100 First Cicle 20 50 0 0 -50 -25 0 25 50 75 100 125 150 -50 175 -25 0 25 Tj (C) 50 75 100 125 150 175 Tj (C) AM11455v1 Figure 29. VCC restart voltage vs. TJ AM11456v1 Figure 30. HV breakdown voltage vs. TJ 800 14 12 750 ICC 10 700 V V 8 falling 650 6 600 4 550 2 0 500 -50 -25 0 25 50 75 100 125 150 175 Tj (C) -50 -25 0 25 50 75 100 125 150 175 Tj (C) AM11457v1 Doc ID 022960 Rev 2 AM11458v1 17/35 Application information L6564H 6 Application information 6.1 Overvoltage protection Normally, the voltage control loop keeps the output voltage Vo of the PFC pre-regulator close to its nominal value, set by the ratio of the resistors R1 and R2 of the output divider. A pin of the device (PFC_OK) has been dedicated to monitor the output voltage with a separate resistor divider (R3 high, R4 low, see Figure 31). This divider is selected so that the voltage at the pin reaches 2.5 V if the output voltage exceeds a preset value, usually larger than the maximum Vo that can be expected. Example 1: Vo = 400 V, VOX = 434 V. Select: R3 = 8.8 MΩ; then: R4 = 8.8 MΩ ·2.5/(434-2.5) = 51 kΩ. When this function is triggered, the gate drive activity is immediately stopped until the voltage on the PFC_OK pin drops below 2.4 V. Note that R1, R2, R3 and R4 can be selected without any constraints. The unique criterion is that both dividers must sink a current from the output bus which needs to be significantly higher than the bias current of both INV and PFC_OK pins. Figure 31. Output voltage setting, OVP and FFP functions: internal block diagram Vout R3a R3 R3b 0.23 V 0.27 V 6 Disable 2.5 V 2.4 V PFC_OK R1a + - OVP L_OVP + R1 1.66 V R1b + - Frequency COMP compensation 2 - 1 INV R4 2.5 V + Error Amplifier R2 AM11459v1 6.2 Feedback failure protection (FFP) The OVP function described above handles “normal” overvoltage conditions, i.e. those resulting from an abrupt load/line change or occurring at startup. If the overvoltage is generated by a feedback disconnection, for instance when the upper resistor of the output divider (R1) fails to open, the comparator detects the voltage at the INV pin. If the voltage is lower than 1.66 V and the OVP is active, the FFP is triggered, the gate drive activity is 18/35 Doc ID 022960 Rev 2 L6564H Application information immediately stopped, the device is shut down, its quiescent consumption is reduced below 180 µA, and the condition is latched as long as the supply voltage of the IC is above the UVLO threshold. To restart the system it is necessary to recycle the input power, so that the VCC voltage of the L6564H goes below 6 V. The PFC_OK pin doubles its function as a not-latched IC ‘disable’: a voltage below 0.23 V shuts down the IC, reducing its consumption below 2 mA. To restart the IC simply let the voltage at the pin go above 0.27 V. Note that these functions offer complete protection against not only feedback loop failures or erroneous settings, but also against a failure of the protection itself. Either resistor of the PFC_OK voltage divider in a short condition or open, or the PFC_OK pin left floating, results in shutting down the IC and stopping the pre-regulator. 6.3 Voltage feedforward The power stage gain of PFC pre-regulators varies with the square of the RMS input voltage. So does the crossover frequency fc of the overall open-loop gain because the gain has a single pole characteristic. This leads to a large trade-off in the design. For example, setting the gain of the error amplifier to get fc = 20 Hz @ 264 Vac means having fc≈ 4 Hz @ 88 Vac, resulting in sluggish control dynamics. Additionally, the slow control loop causes large transient current flow during rapid line or load changes that are limited by the dynamics of the multiplier output. This limit is considered when selecting the sense resistor to let the full load power pass under minimum line voltage conditions, with some margin. But a fixed current limit allows excessive power input at high line, whereas a fixed power limit requires the current limit to vary inversely with the line voltage. Voltage feedforward can compensate for the gain variation with the line voltage and allow the minimizing of all the issues mentioned above. It consists of deriving a voltage proportional to the input RMS voltage, feeding this voltage into a squarer/divider circuit (1/V2 corrector) and providing the resulting signal to the multiplier that generates the current reference for the inner current control loop (see Figure 32). Figure 32. Voltage feedforward: squarer/divider (1/V2) block diagram and transfer characteristics 2ECTIFIEDMAINS CURRENT REFERENCE 6CSX %!OUTPUT 6 #/-0 6CSX  ,( -5,4)0,)%2  6 #/-06 IDEAL DIOD E 6  !CTUAL )DEAL    6 -!).3$2/0 $%4%#4/2 -5,4    6&& # &&  2 &&      6 &&6 -5,4 !-V Doc ID 022960 Rev 2 19/35 Application information L6564H In this way a change of the line voltage causes an inversely proportional change of the half sine amplitude at the output of the multiplier (if the line voltage doubles the amplitude of the multiplier output is halved and vice versa) so that the current reference is adapted to the new operating conditions with (ideally) no need for invoking the slow dynamics of the error amplifier. Additionally, the loop gain is constant throughout the input voltage range, which significantly improves dynamic behavior at low line and simplifies loop design. Actually, deriving a voltage proportional to the RMS line voltage implies a form of integration, which has its own time constant. If it is too small, the voltage generated is affected by a considerable amount of ripple at twice the mains frequency which causes distortion of the current reference (resulting in high HD and poor PF); if it is too large there is a considerable delay in setting the right amount of feedforward, resulting in excessive overshoot and undershoot of the pre-regulator output voltage in response to large line voltage changes. Clearly a trade-off was required. The L6564H realizes a new voltage feedforward that, with a technique that makes use of just two external parts, strongly minimizes this time constant trade-off issue whichever voltage change occurs on the mains, both surges and drops. A capacitor CFF and a resistor RFF, both connected from the VFF pin (#5) to ground, complete an internal peak-holding circuit that provides a DC voltage equal to the peak of the rectified sine wave applied on the MULT pin (#3). In this way, in the case of sudden line voltage rise, CFF is rapidly charged through the low impedance of the internal diode; in the case of line voltage drop, an internal “mains drop” detector enables a low impedance switch which suddenly discharges CFF avoiding a long settling time before reaching the new voltage level. The discharge of CFF is stopped as its voltage equals the voltage on the MULT pin or if the voltage on the VFF pin falls below 0.88 V, to prevent the “brownout protection” function from being improperly activated (see Section 6.6: Power management/housekeeping functions). As a result of the VFF pin functionality, an acceptably low steady-state ripple and low current distortion can be achieved with a limited undershoot or overshoot on the pre-regulator output. The twice-mains-frequency (2• fL) ripple appearing across CFF is triangular with a peak-topeak amplitude that, with good approximation, is given by: ∆VFF = 2 VMULTpk 1 + 4fLRFFCFF where fL is the line frequency. The amount of 3rd harmonic distortion introduced by this ripple, related to the amplitude of its 2• fL component, is: D3% = 2π f100 R C L FF FF Figure 33 shows a diagram that helps in choosing the time constant RFF · CFF based on the amount of maximum desired 3rd harmonic distortion. Note that there is a minimum value for the time constant RFF×CFF below which improper activation of the VFF fast discharge may occur. In fact, the twice-mains frequency ripple across CFF under steady-state conditions must be lower than the minimum line drop detection threshold (DVVFF_min = 40 mV). Therefore: must be lower than the minimum line drop detection threshold (∆VFF_min = 40 mV). 20/35 Doc ID 022960 Rev 2 L6564H Application information So: 2 RFF CFF > VMULTpk _ max ∆VVFF _ min -1 4 fL _ min Always connect RFF and CFF to the pin, the IC does not work properly if the pin is either left floating or connected directly to ground. Figure 33. RFF·CFF as a function of 3rd harmonic distortion introduced in the input current 10 1 f L = 50 Hz RFF · CFF [s] 0.1 f L= 60 Hz 0.01 0.1 1 10 D3 % AM11460v1 Doc ID 022960 Rev 2 21/35 Application information 6.4 L6564H THD optimizer circuit The L6564H is provided with a special circuit that reduces the conduction dead-angle occurring at the AC input current near the zero-crossings of the line voltage (crossover distortion). In this way the THD (total harmonic distortion) of the current is considerably reduced. A major cause of this distortion is the inability of the system to transfer energy effectively when the instantaneous line voltage is very low. This effect is magnified by the highfrequency filter capacitor placed after the bridge rectifier, which retains some residual voltage that causes the diodes of the bridge rectifier to be reverse-biased and the input current flow to temporarily stop. To overcome this issue the device forces the PFC pre-regulator to process more energy near the line voltage zero-crossings as compared to that commanded by the control loop. This results in both minimizing the time interval where energy transfer is lacking and fully discharging the high-frequency filter capacitor after the bridge. Figure 34 shows the internal block diagram of the THD optimizer circuit. Figure 34. THD optimizer circuit T T 6 6&& T  #/-0 -5,4)0,)%2  -5,4 T TO07COMPARATOR  /&&3%4 '%.%2!4/2 T 6AC 6AC6AC T !-V 22/35 Doc ID 022960 Rev 2 L6564H Application information Figure 35. THD optimization: standard TM PFC controller (left side) and L6564H (right side) Input current Input current Rectified mains voltage Rectified mains voltage Imains Input current Imains Input current Vdrain MOSFET's drain voltage MOSFET's drain voltage Vdrain AM11461v1 Essentially, the circuit artificially increases the ON-time of the power switch with a positive offset added to the output of the multiplier in the proximity of the line voltage zero-crossings. This offset is reduced as the instantaneous line voltage increases, so that it becomes negligible as the line voltage moves toward the top of the sinusoid. Furthermore, the offset is modulated by the voltage on the VFF pin (see Section 6.3) so as to have little offset at low line, where energy transfer at zero crossings is typically quite good, and a larger offset at high line where the energy transfer worsens. The effect of the circuit is shown in Figure 35, where the key waveforms of a standard TM PFC controller are compared to those of this chip. To take maximum benefit from the THD optimizer circuit, the high-frequency filter capacitor after the bridge rectifier should be minimized, compatibly with EMI filtering needs. A large capacitance, in fact, introduces a conduction dead-angle of the AC input current in itself even with an ideal energy transfer by the PFC pre-regulator - therefore reducing the effectiveness of the optimizer circuit. 6.5 Inductor saturation detection The boost inductor's hard saturation may be a fatal event for a PFC pre-regulator: the current up-slope becomes so large (50-100 times steeper, see Figure 36) that during the current sense propagation delay the current may reach abnormally high values. The voltage drop caused by this abnormal current on the sense resistor reduces the gate-to-source voltage, so that the MOSFET may work in the active region and dissipate a huge amount of power, which leads to a catastrophic failure after few switching cycles. However, in some applications such as AC-DC adapters, where the PFC pre-regulator is turned off at light load for energy saving reasons, even a well-designed boost inductor may Doc ID 022960 Rev 2 23/35 Application information L6564H occasionally slightly saturate when the PFC stage is restarted because of a larger load demand. This happens when the restart occurs at an unfavorable line voltage phase, i.e. when the output voltage is significantly below the rectified peak voltage. As a result, in the boost inductor, the inrush current coming from the bridge rectifier adds to the switched current and, furthermore, there is little or no voltage available for demagnetization. To cope with a saturated inductor, the L6564H is provided with a second comparator on the current sense pin (CS, pin 4) that stops the IC if the voltage, normally limited within 1.1 V, exceeds 1.7 V. After that, the IC attempts to restart through the internal starter circuitry; the starter repetition time is twice the nominal value to guarantee lower stress for the inductor and boost diode. Hence, system safety is considerably increased. Figure 36. Effect of boost inductor saturation on the MOSFET current and detection method AM11462v1 6.6 Power management/housekeeping functions A communication line with the control IC of the cascaded DC-DC converter can be established via the disable function included in the PFC_OK pin (see Section 6.2 for more details). This line is typically used to allow the PWM controller of the cascaded DC-DC converter to shut down the L6564H in case of light load and to minimize the no-load input consumption. Should the residual consumption of the chip be an issue, it is also possible to cut down the supply voltage. Interface circuits are shown in Figure 37. Needless to say, this operation assumes that the cascaded DC-DC converter stage works as the master and the PFC stage as the slave or, in other words, that the DC-DC stage starts first, it powers both controllers and enables/disables the operation of the PFC stage. 24/35 Doc ID 022960 Rev 2 L6564H Application information Figure 37. Interface circuits that let the DC-DC converter’s controller IC disable the L6564H ,!  6##  6##?0&# , ,( 6##   0&#?/+  ,!  , ,( 0&#?34/0 0&#?/+ ,  0&#?34/0  , ,( !-V Another function available is the brownout protection which is basically a not-latched shutdown function that is activated when a condition of mains undervoltage is detected. This condition may cause overheating of the primary power section due to an excess of RMS current. Brownout can also cause the PFC pre-regulator to function in open loop and this may be dangerous to the PFC stage itself and the downstream converter, should the input voltage return abruptly to its rated value. Another problem is the spurious restarts that may occur during converter power-down and that cause the output voltage of the converter not to decay to zero monotonically. For these reasons it is usually preferable to shut down the unit in case of brownout. The brownout threshold is internally fixed at 0.8 V and is sensed on the VFF pin (#5) during the voltage falling and an 80 mV threshold hysteresis prevents rebounding at input voltage turn-off. In Table 5 it is possible to find a summary of all of the above mentioned working conditions that cause the device to stop operating. Doc ID 022960 Rev 2 25/35 High voltage startup generator 7 L6564H High voltage startup generator Figure 38 shows the internal schematic of the high voltage startup generator (HV generator). It is made up of a high voltage N-channel FET, whose gate is biased by a 15 MΩ resistor, with a temperature-compensated current generator connected to its source. Figure 38. High voltage startup generator: internal schematic HVS 8 15MW Vcc_OK HV_EN IHV 14 Vcc CONTROL Icharge 12 GND AM11463v1 The HV generator is physically located on a separate chip, made with BCD offline technology able to withstand 700 V, controlled by a low voltage chip, where all of the control functions reside. With reference to the timing diagram of Figure 39, when power is first applied to the converter the voltage on the bulk capacitor (Vin) builds up and, at about 80 V, the HV generator is enabled to operate (HV_EN is pulled high) so that it draws about 1 mA. This current, minus device consumption, charges the bypass capacitor connected from the VCC pin (14) to ground and causes its voltage to rise almost linearly. Figure 39. Timing diagram: normal power-up and power-down sequences VHV Rectified input voltage Input source is removed here Bulk cap voltage VHVstart DC- DC loses regulation here Vcc (pin 14) t Vcc ON Vcc OFF Vcc restart t GD (pin 13) HV connected to bulk cap HV_EN t HV connected to rectified input voltage t Vcc_OK Icharge t 0.85 mA Power-on Normal operation Power-of f t AM11464v1 26/35 Doc ID 022960 Rev 2 L6564H High voltage startup generator As the VCC voltage reaches the startup threshold (12 V typ.) the low voltage chip starts operating and the HV generator is cut off by the VCC_OK signal asserted high. The device is powered by the energy stored in the VCC capacitor until the self-supply circuit (we assume that it is made with an auxiliary winding in the transformer of the cascaded DC-DC converter and a steering diode) develops a voltage high enough to sustain the operation. The residual consumption of this circuit is just the one on the 15 MΩ resistor (≈ 10 mW at 400 Vdc), typically 50-70 times lower, under the same conditions, as compared to a standard startup circuit made with external dropping resistors. At converter power-down the DC-DC converter loses regulation as soon as the input voltage is so low that either peak current or maximum duty cycle limitation is tripped. VCC then drops and stop IC activity as it falls below the UVLO threshold (9.5 V typ.). The VCC_OK signal is de-asserted as the VCC voltage goes below a threshold VCCrestart located at about 6 V. The HV generator can now restart. However, if Vin < VHVstart, HV_EN is de-asserted too and the HV generator is disabled. This prevents converter restart attempts and ensures monotonic output voltage decay at power-down in systems where brownout protection (see Section 6.6: Power management/housekeeping functions) is not used. If the device detects a fault due to feedback failure, the internal VCCrestart is brought up to over the VCCOff (turn-off threshold). As a result, shown in Figure 40, the voltage at the VCC pin oscillates between its turn-on and turn-off thresholds until the HV bus is recycled and drops below the startup threshold of the HV generator. The high voltage startup circuitry is capable of guaranteeing a safe behavior in case of short-circuit present on the DC-DC output when the VCC of both controllers are generated by the same auxiliary inding. Figure 41 shows how the PFC manages the VCC cycling and the associated power transfer. At short-circuit the auxiliary circuit is no longer able to sustain the VCC which starts dropping; reaching its VCCOff threshold the IC stops switching, reduces consumption and drops more until the VCCrestart threshold is tripped. Now, the high voltage startup generator restarts and when the VCC again crosses its turn-on threshold the IC starts switching. In this manner the power is transferred from mains to PFC output only during a short time for each trep cycle. Figure 40. High voltage startup behavior during latch-off protection Vcc (pin 14) VccON Fault occurs here VccOFF Vccrestart HV generator is turned on Disable latch is reset here GD (pin 13) HV generator turn-on is disabled here t Input source is removed here t HV_EN t Vin VHVstart t AM11465v1 Doc ID 022960 Rev 2 27/35 High voltage startup generator L6564H Figure 41. High voltage startup managing the DC-DC output short-circuit Vcc (pin 14) Short-circuit occurs here VccON VccOFF Vccrestart Trep GD (pin 13) t Vcc_OK t Icharge t 0.85 mA t AM11466v1 Table 5. 28/35 Summary of L6564H idle states Typical IC Condition Caused or revealed by IC behavior Restart condition UVLO VCC < VCCOff Disabled VCC > VCCOn 90 µA Feedback disconnected PFC_OK > VPFC_OK_S and INV < 1.66 V Latched VCC < VCCrestart then VCC > VCCOn 180 µA Standby PFC_OK < VPFC_OK_D Stop switching PFC_OK > VPFC_OK_E 1.5 mA AC brownout RUN < VDIS Stop switching RUN > VEN 1.5 mA OVP PFC_OK > VPFC_OK_S Stop Switching PFC_OK < VPFC_OK_R 2.2 mA Low consumption COMP < 2.4 V Burst mode COMP > 2.4 V 2.2 mA Saturated boost inductor Vcs > VCS_th Doubled Tstart Auto restart 2.2 mA Doc ID 022960 Rev 2 consumption C12 2N2 90-264Vac 3 2 1 Doc ID 022960 Rev 2 C13 1uF R17 2M2 R12 2M2 R9 2M2 R19 51K R27 1M C9 68N C1 470N C15 220p C8 680N R18 82K C16 2N2 7 6 5 4 3 2 1 NC PFC_OK VFF CS MULT COMP INV U1 L6564H R13 62K HVS NC NC ZCD GND GD VCC R14 27K C4 470N D1 GBU4J 8 9 10 11 12 13 14 ~ ~ L1 HF2826-203Y 1R5-T01 C10 100N R30 1K _ + J1 MKDS 1,5/ 3-5,08 C11 47uF-50V C5 470N - 400V 8 6 R5 68K C7 4N7 R31 10R 3 R21 27R D6 N.M. D5 BZX79-C18 R4 100R 5 1 2 3 J3 CON3 R24 220R R20 N.M. R25 0R47 R22 100K D3 STTH2L06 ON/OFF GND VCC D4 LL4148 1N4005 L2 SRW2620PQ-XXXV002 SUBMIT X08041-01-B (TDK VERSION) D2 R26 0R68 HS1 HEAT-SINK Q1 STF8NM50N R10 1M0 R1 NTC 2R5-S237 C6 47uF - 450V R8 1M0 R2 1M0 R15 51K R11 2M2 R6 3M3 R3 3M3 J2 MKDS 1,5/ 2-5,08 1 2 8 F1 FUSE 4A L6564H Application examples and ideas Application examples and ideas Figure 42. Demonstration board EVL6564H - 100 W, wide-range mains: electrical schematic AM11471v1 29/35 Application examples and ideas L6564H Figure 43. EVL6564H demonstration board: compliance to EN61000-3-2 standard Figure 44. EVL6564H demonstration board: compliance to JEITA-MITI standard Figure 45. EVL6564H demonstration board: Figure 46. EVL6564H demonstration board: input current waveform @230 V -50 input current waveform @100 V - 50 Hz - 100 W load Hz - 100 W load 30/35 Doc ID 022960 Rev 2 L6564H 9 Package mechanical data Package mechanical data In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK® packages, depending on their level of environmental compliance. ECOPACK specifications, grade definitions and product status are available at: www.st.com. ECOPACK is an ST trademark. Table 6. SO-14 mechanical data Databook (mm.) Dim. Min. Typ. Max. A 1.35 1.75 A1 0.10 0.25 A2 1.10 1.65 B 0.33 0.51 C 0.19 0.25 D 8.55 8.75 E 3.80 4.00 e 1.27 H 5.80 6.20 h 0.25 0.50 L 0.40 1.27 K 0 8 e 0.40 ddd 0.10 Doc ID 022960 Rev 2 31/35 Package mechanical data L6564H Figure 47. SO-14 package dimensions 0016019_E 32/35 Doc ID 022960 Rev 2 L6564H 10 Ordering codes Ordering codes Table 7. Ordering information Order codes Package L6564H Packing Tube SO-14 L6564HTR Tape and reel Doc ID 022960 Rev 2 33/35 Revision history 11 L6564H Revision history Table 8. 34/35 Document revision history Date Revision Changes 19-Apr-2012 1 Initial release. 07-Jun-2012 2 Datasheet promoted from preliminary data to production data. Doc ID 022960 Rev 2 L6564H Please Read Carefully: Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any time, without notice. All ST products are sold pursuant to ST’s terms and conditions of sale. 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