L6564TDTR

L6564T 10-pin transition-mode PFC controller Features ■ Guaranteed for extreme temperature range (outdoor) ■ Fast “bi-directional” input voltage feedforward (1/V2 correction) ■ Accurate adjustable output overvoltage protection ■ Protection against feedback loop disconnection (latched shutdown) ■ Inductor saturation protection ■ AC brownout detection ■ Low (≤100 µA) startup current ■ 6 mA max. operating bias current ■ 1% (@ TJ = 25 °C) internal reference voltage ■ -600/+800 mA totem pole gate driver with active pull-down during UVLO ■ SSOP10 Applications ■ PFC pre-regulators for: – High-end AC-DC adapter/charger – Desktop PC, server, web server – IEC61000-3-2 or JEITA-MITI compliant SMPS ■ SMPS for LED luminaires SSOP10 package Figure 1. Block diagram =&'  9FF   =HUR&XUUHQW 'HWHFWRU  'LVDEOH  9 9  3)&B2. 9 9 9  293 9ROWDJH UHIHUHQFHV 92/7$*( 5(*8/$725 « 9 9  89/2 ,QWHUQDO6XSSO\%XV  89/2 /B293  6  5  4 *' '5,9(5 &/$03  67$57(5 6WDUWHU 2))  &203 ',6$%/( 'LVDEOH ,19  9 08/7 4   /(% 4 293 212))&RQWURO 6 /B293 5 89/2 (UURU$PSOLILHU  *1'  ,GHDOUHFWLILHU 9    08/7,3/,(5  &6   212))&RQWURO 9 9  0$,16'523 '(7(&725 9 'LVDEOH    9)) !-V January 2012 Doc ID 022671 Rev 1 1/33 www.st.com 33 Contents L6564T Contents 1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 2 Maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2.1 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2.2 Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 3 Pin connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 4 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 5 Typical electrical performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 6 Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 6.1 Overvoltage protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 6.2 Feedback failure protection (FFP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 6.3 Voltage feedforward . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 6.4 THD optimizer circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 6.5 Inductor saturation detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 6.6 Power management/housekeeping functions . . . . . . . . . . . . . . . . . . . . . . 25 7 Application examples and ideas . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 8 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 9 Ordering codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 10 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 2/33 Doc ID 022671 Rev 1 L6564T List of tables List of tables Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Thermal data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Summary of L6564 idle states . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 SSO10 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Doc ID 022671 Rev 1 3/33 List of figures L6564T List of figures Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Figure 10. Figure 11. Figure 12. Figure 13. Figure 14. Figure 15. Figure 16. Figure 17. Figure 18. Figure 19. Figure 20. Figure 21. Figure 22. Figure 23. Figure 24. Figure 25. Figure 26. Figure 27. Figure 28. Figure 29. Figure 30. Figure 31. Figure 32. Figure 33. Figure 34. Figure 35. Figure 36. Figure 37. Figure 38. Figure 39. 4/33 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Pin connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 IC consumption vs. VCC. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 IC consumption vs. TJ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Vcc Zener voltage vs. TJ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Startup and UVLO vs. TJ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Feedback reference vs. TJ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 E/A output clamp levels vs. TJ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 UVLO saturation vs. TJ. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 OVP levels vs. TJ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Inductor saturation threshold vs. TJ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Vcs clamp vs. TJ. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 ZCD sink/source capability vs. TJ. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 ZCD clamp level vs. TJ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 R discharge vs. TJ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Line drop detection threshold vs. TJ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 VMULTpk - VVFF dropout vs. TJ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 PFC_OK threshold vs. TJ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 PFC_OK FFD threshold vs. TJ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Multiplier characteristics @ VFF = 1 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Multiplier characteristics @ VFF = 3 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Multiplier gain vs. TJ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Gate drive clamp vs. TJ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Gate drive output saturation vs. TJ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Delay to output vs. TJ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Startup timer period vs. TJ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Output voltage setting, OVP and FFP functions: internal block diagram . . . . . . . . . . . . . . 18 Voltage feedforward: squarer/divider (1/V2) block diagram and transfer characteristic . . 20 RFF·CFF as a function of 3rd harmonic distortion introduced in the input current . . . . . . . 21 THD optimizer circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 THD optimization: standard TM PFC controller (left side) and L6564T (right side) . . . . . . 23 Effect of boost inductor saturation on the MOSFET current and detection method . . . . . . 24 Interface circuits that let DC-DC converter's controller IC disable the L6564T. . . . . . . . . . 25 Demonstration board EVL6564-100W, wide-range mains: electrical schematic . . . . . . . . 27 L6564 100 W TM PFC: compliance with EN61000-3-2 standard . . . . . . . . . . . . . . . . . . . . 28 L6564 100 W TM PFC: compliance with JEITA-MITI standard . . . . . . . . . . . . . . . . . . . . . 28 L6564 100 W TM PFC: input current waveform @230-50 Hz - 100 W load . . . . . . . . . . . . 28 L6564 100W TM PFC: input current waveform @100 V-50 Hz - 100 W load . . . . . . . . . . 28 SSO10 package dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Doc ID 022671 Rev 1 L6564T 1 Description Description The L6564T is a current-mode PFC controller operating in transition mode (TM) and represents the compact version of the L6563S as it embeds the same driver, reference and control stages in a very compact 10-pin SO package. The highly linear multiplier, along with a special correction circuit that reduces crossover distortion of the mains current, allows wide-range-mains operation with an extremely low THD even over a large load range. The output voltage is controlled by means of a voltage-mode error amplifier and an accurate (1% @TJ = 25 °C) internal voltage reference. The loop stability is optimized by the voltage feedforward function (1/V2 correction), which in this IC uses a proprietary technique that also considerably improves line transient response in case of both mains drops and surges (“bidirectional”). In addition to overvoltage protection able to control the output voltage during transient conditions, the IC also provides protection against feedback loop failures or erroneous settings. Other on-board protection functions allow brownout conditions and boost inductor saturation to be safely handled. The totem-pole output stage, capable of a 600 mA source and 800 mA sink current, is suitable for a high power MOSFET or IGBT drive. This, combined with the other features and the possibility to operate with ST's proprietary fixed-off-time control, makes the device an excellent solution for SMPS up to 400 W that requires compliance with EN61000-3-2 and JEITA-MITI standards. Doc ID 022671 Rev 1 5/33 Maximum ratings L6564T 2 Maximum ratings 2.1 Absolute maximum ratings Table 1. 2.2 Absolute maximum ratings Symbol Pin Parameter Value Unit Vcc 10 IC supply voltage (Icc ≤20 mA) Self-limited V --- 1, 3, 6 Max. pin voltage (Ipin ≤1 mA) Self-limited V --- 2, 4, 5 Analog inputs and outputs -0.3 to 8 V IZCD 7 Zero current detector max. current -10 (source) 10 (sink) mA VFF pin 5 +/- 1750 V Other pins 1 to 4 6 to 10 Maximum withstanding voltage range test condition: CDF-AEC-Q100-002 “human body model” Acceptance criteria: “normal performance” +/- 2000 V Value Unit Thermal data Table 2. Thermal data Symbol RthJA Max. thermal resistance, junction-to-ambient 120 °C/W Ptot Power dissipation @TA = 50 °C 0.75 W Junction temperature operating range -40 to 150 °C Storage temperature -55 to 150 °C TJ Tstg 6/33 Parameter Doc ID 022671 Rev 1 L6564T Pin connection 3 Pin connection Figure 2. Pin connection ,19   9FF &203   *' 08/7   *1' &6   =&' 9))   3)&B2. !-V Table 3. Pin description n° Name 1 INV Function Inverting input of the error amplifier. The information on the output voltage of the PFC preregulator is fed into the pin through a resistor divider. The pin normally features high impedance. 2 COMP Output of the error amplifier. A compensation network is placed between this pin and INV (pin 1) to achieve stability of the voltage control loop and ensure high power factor and low THD. To avoid uncontrolled rise of the output voltage at zero load, when the voltage on the pin falls below 2.4 V the gate driver output is inhibited (burst-mode operation). 3 MULT Main input to the multiplier. This pin is connected to the rectified mains voltage via a resistor divider and provides the sinusoidal reference to the current loop. The voltage on this pin is used also to derive the information on the RMS mains voltage. CS Input to the PWM comparator. The current flowing in the MOSFET is sensed through a resistor, the resulting voltage is applied to this pin and compared with an internal reference to determine MOSFET’s turn-off. A second comparison level at 1.7 V detects abnormal currents (e.g. due to boost inductor saturation) and, on this occurrence, activates a safety procedure that temporarily stops the converter and limits the stress of the power components. VFF Second input to the multiplier for 1/V2 function. A capacitor and a parallel resistor must be connected from the pin to GND. They complete the internal peak-holding circuit that derives the information on the RMS mains voltage. The voltage at this pin, a DC level equal to the peak voltage on pin MULT (3), compensates the control loop gain dependence on the mains voltage. Never connect the pin directly to GND but with a resistor ranging from 100 K ohm (minimum) to 2 M ohm (maximum). This pin is internally connected to a comparator in order to provide the brownout (AC mains undervoltage) protection. A voltage below 0.8 V shuts down (not latched) the IC and brings its consumption to a considerably lower level. The IC restarts as the voltage at the pin goes above 0.88 V. 4 5 Doc ID 022671 Rev 1 7/33 Pin connection Table 3. n° L6564T Pin description (continued) Name Function 6 PFC_OK PFC pre-regulator output voltage monitoring/disable function. This pin senses the output voltage of the PFC pre-regulator through a resistor divider and is used for protection purposes. If the voltage on the pin exceeds 2.5 V the IC stops switching and restarts as the voltage on the pin falls below 2.4 V. However, if at the same time the voltage of the INV pin falls below 1.66 V, a feedback failure is assumed. In this case the device is latched off. Normal operation can be resumed only by cycling Vcc. bringing its value lower than 6 V before moving up to the turn-on threshold. If the voltage on this pin is brought below 0.23 V the IC is shut down. To restart the IC the voltage on the pin must go above 0.27 V. This can be used as a remote on/off control input. 7 ZCD Boost inductor’s demagnetization sensing input for transition-mode operation. A negative-going edge triggers MOSFET’s turn-on. 8 GND Ground. Current return for both the signal part of the IC and the gate driver. 9 GD Gate driver output. The totem pole output stage is able to drive power MOSFET’s and IGBT’s with a peak current of 600 mA source and 800 mA sink. The high-level voltage of this pin is clamped at about 12 V to avoid excessive gate voltages. 10 Vcc Supply voltage of both the signal part of the IC and the gate driver. Sometimes a small bypass capacitor (0.1 µF typ.) to GND might be useful to get a clean bias voltage for the signal part of the IC. 8/33 Doc ID 022671 Rev 1 L6564T 4 Electrical characteristics Electrical characteristics TJ = -40 to 125 °C, VCC = 12 V, CO = 1 nF between pin GD and GND, CFF = 1 µF and RFF = 1 MΩ between pin VFF and GND; unless otherwise specified. Table 4. Electrical characteristics Symbol Parameter Test condition Min. Typ. Max. Unit Supply voltage Vcc Operating range After turn-on VccOn Turn-on threshold (1) 11 VccOff Turn-off threshold (1) Vcc for resuming from latch OVP latched Vccrestart Hys Hysteresis VZ Zener voltage 10.3 22.5 V 12 13.2 V 8.7 9.5 10.5 V 5 6 7 V 2.7 V 25 28 V 2.3 Icc = 20 mA 22.5 Supply current Startup current Before turn-on, Vcc=10 V 90 180 µA Quiescent current After turn-on, VMULT = 1 V 4 5.5 mA ICC Operating supply current @ 70 kHz 5 6.0 mA 320 µA Idle state quiescent current VPFC_OK> VPFC_OK_S AND VINV < VFFD 180 Iqdis VPFC_OKVPFC_OK_S OR VCOMP VCS_th, before restarting 5 10 13 µA 20 50 100 µs 75 150 350 150 300 700 V Boost inductor saturation detector VCS_th IINV Startup timer tSTART_DEL Startup delay tSTART First cycle after wake-up Timer period µs Restart after VCS > VCS_th Current sense comparator ICS Input bias current tLEB Leading edge blanking 70 Delay to output td(H-L) VCSclamp Vcsofst Current sense reference clamp Current sense offset VCS = 0 1 µA 150 300 ns 70 200 350 ns 0.97 1.08 1.2 V VMULT = 0 V, VVFF = 3 V 40 70 VMULT = 3 V, VVFF = 3 V 20 VPFC_OK = 0 to 2.6 V -0.1 VCOMP = upper clamp, VMULT =1 V, VVFF = 1 V mV PFC_OK functions IPFC_OK Input bias current VPFC_OK_C Clamp voltage IPFC_OK = 1 mA VPFC_OK_S OVP threshold (1) Voltage rising VPFC_OK_R Restart threshold after OVP (1) VPFC_OK_D Disable threshold (1) VPFC_OK_D Disable threshold (1) VPFC_OK_E Enable threshold (1) VPFC_OK_E Enable threshold (1) VFFD 10/33 Feedback failure detection threshold (VINV falling) µA 9.5 V 2.435 2.5 2.565 V Voltage falling 2.34 2.4 2.46 V Voltage falling 0.08 0.40 V Voltage falling Tj = 25 °C 0.17 0.29 V Voltage rising 0.10 0.43 V Voltage rising Tj = 25 °C 0.21 0.27 0.32 V 1.61 1.66 1.71 V VPFC_OK = VPFC_OK_S Doc ID 022671 Rev 1 8.5 -1 0.23 L6564T Table 4. Electrical characteristics Electrical characteristics (continued) Symbol Parameter Test condition Min. Typ. Max. Unit Voltage feedforward VVFF Linear operation range ∆V Dropout VMULTpk-VVFF 1 3 Vcc < VccOn 850 Vcc > or = to VccOn 20 V mV ∆VVFF Line drop detection thresh. Below peak value 30 70 110 mV ∆VVFF Line drop detection thresh. Below peak value Tj =25°C 50 70 90 mV Tj = 25 °C 7.5 10 12.5 RDISCH Internal discharge resistor kΩ 5 20 VDIS Disable threshold (2) Voltage falling 0.725 0.8 0.875 V VEN Enable threshold (2) Voltage rising 0.845 0.88 0.915 V Zero current detector VZCDH Upper clamp voltage IZCD = 2.5 mA 5.0 5.7 VZCDL Lower clamp voltage IZCD = - 2.5 mA -0.3 0 0.3 V VZCDA Arming voltage (positive-going edge) 1.1 1.4 1.9 V VZCDT Triggering voltage (negative-going edge) 0.5 0.7 1 V IZCDb Input bias current 1 µA VZCD = 1 to 4.5 V V IZCDsrc Source current capability -2.0 -4 mA IZCDsnk Sink current capability 2.0 5 mA Gate driver VOL Output low voltage Isink = 100 mA 0.6 VOH Output high voltage Isource = 5 mA Isrcpk Peak source current -0.6 A Isnkpk Peak sink current 0.8 A 9.5 1.4 10.3 V V tf Voltage fall time 30 60 ns tr Voltage rise time 45 150 ns 12 15 V 1.2 V VOclamp Output clamp voltage Isource = 5 mA; Vcc = 20 V UVLO saturation Vcc= 0 to VCCon, Isink= 2 mA 1. Parameters tracking each other. ( VMULT ⋅ VCOMP − 2.5 2. The multiplier output is given by: Vcs = VCS_Ofst + K M ⋅ 2 3. Parameters tracking each other. 10 ) V VFF Doc ID 022671 Rev 1 11/33 Typical electrical performance L6564T 5 Typical electrical performance Figure 3. IC consumption vs. VCC Figure 4. 100 IC consumption vs. TJ 10 Operating 10 Quiescent Disabled or during OV P 1 I c current (m A) 1 I cc [m A] VCC=12V Co = 1nF f =70kHz Co=1nF f =70kHz Tj = 25°C 0.1 Latched off 0.1 Before Start up 0.01 VccOFF VccON 0.01 0. 001 0 5 10 15 20 25 -50 30 -25 0 25 50 Figure 5. 75 100 125 150 175 Tj (C) Vcc [V ] Vcc Zener voltage vs. TJ Figure 6. 28 Startup and UVLO vs. TJ 13 V CC-ON 12 27 11 26 10 V V VCC-OFF 25 9 24 8 23 7 6 22 -50 -25 0 25 50 75 100 125 150 175 -50 Tj (C) 12/33 -25 0 25 50 75 Tj (C) Doc ID 022671 Rev 1 100 125 150 175 L6564T Typical electrical performance Figure 7. Feedback reference vs. TJ Figure 8. 2. 6 E/A output clamp levels vs. TJ 7 Uper Clam p 6 VCC = 12V 2.55 5 V COM P (V ) pi n INV (V ) V CC = 12V 2. 5 4 3 Lower Clamp 2 2.45 1 0 2. 4 -50 Figure 9. -25 0 25 50 75 Tj (C) 100 125 150 -50 175 -25 0 25 50 75 100 125 150 175 Tj (C) UVLO saturation vs. TJ Figure 10. OVP levels vs. TJ 2. 5 1 0.9 2. 48 VCC = 0V 0.8 OV P T h 2. 46 P FC_OK l evels (V ) 0.7 V 0.6 0.5 0.4 2. 44 2. 42 2. 4 0.3 Resta rt Th 0.2 2. 38 0.1 2. 36 0 -50 -50 -25 0 25 50 75 100 125 150 175 Tj (C) Doc ID 022671 Rev 1 -25 0 25 50 75 100 125 150 175 Tj (C) 13/33 Typical electrical performance L6564T Figure 11. Inductor saturation threshold vs. TJ Figure 12. Vcs clamp vs. TJ 1.9 1. 4 1.8 1.7 1. 3 VCSx (V ) CS pi n (V ) 1.6 1.5 VCC = 12V VCOMP =Upper clamp 1. 2 1.4 1.3 1. 1 1.2 1.1 1 -50 -25 0 25 50 75 100 125 150 175 -50 -25 0 25 50 75 Figure 13. ZCD sink/source capability vs. TJ 125 150 175 Figure 14. ZCD clamp level vs. TJ 8 7 Si nk curren t Upper Clamp 6 6 4 5 V ZCD pin (V ) 2 IZCDsrc (mA) 100 Tj (C) Tj (C) V CC = 12V 0 -2 4 VCC = 12V Izcd =±2.5mV 3 2 Source current -4 1 -6 0 Lower Cl amp -8 -50 -1 -25 0 25 50 75 100 125 150 175 -50 14/33 -25 0 25 50 75 Tj (C) Tj (C) Doc ID 022671 Rev 1 100 125 150 175 L6564T Typical electrical performance Figure 15. R discharge vs. TJ Figure 16. Line drop detection threshold vs. TJ 20 90 18 80 16 70 14 60 12 mV kOhm 50 10 40 8 30 6 20 4 10 2 0 0 -50 -25 0 25 50 75 100 125 150 -50 175 -25 0 25 50 Figure 17. VMULTpk - VVFF dropout vs. TJ 100 125 150 175 150 175 Figure 18. PFC_OK threshold vs. TJ 0.4 1. 5 0.35 1 0.3 0. 5 0.25 Th (V ) 2 ⎯ (m V) 75 Tj (C) Tj (C) 0 ON 0.2 -0. 5 0.15 -1 0.1 -1. 5 0.05 -2 OFF 0 -50 -25 0 25 50 75 Tj (C) 100 125 150 175 -50 -25 0 25 50 75 100 125 Tj (C) Figure 19. PFC_OK FFD threshold vs. TJ 2 1.9 VFFD Th (V ) 1.8 1.7 1.6 1.5 1.4 -50 -25 0 25 50 75 100 12 5 150 175 Tj (C) Doc ID 022671 Rev 1 15/33 Typical electrical performance L6564T Figure 20. Multiplier characteristics @ VFF = 1 V Figure 21. Multiplier characteristics @ VFF = 3 V 700 1. 2 VCOMP 1. 1 V COM P Upper voltage cl amp 1 600 Upper vo ltage l 5 .5 5 .0V 0. 9 4.5 V 500 4. 0V 400 0. 8 V CS (V ) V CS (m V) 5. 5V 0. 7 0. 6 0. 5 5. 0V 4. 5V 300 3.5 V 4. 0V 0. 4 200 0. 3 3. 5V 0. 2 3.0 100 3. 0V 0. 1 2. 6V 2.6 V 0 0 0 0.1 0.2 0. 3 0. 4 0.5 0.6 0.7 0. 8 0.9 1 1.1 0 0. 5 1 1. 5 2 V MULT (V ) VM UL T (V ) Figure 22. Multiplier gain vs. TJ 2. 5 3 3. 5 Figure 23. Gate drive clamp vs. TJ 12. 9 0. 5 V CC = 20V 12.85 0. 4 Gai n (1/V ) 12. 8 V VCC = 12V VCOMP = 4V VMULT = VFF= 1V 12.75 0. 3 12. 7 0. 2 -50 -25 0 25 50 75 100 125 150 175 12.65 -50 Tj (C) 16/33 Doc ID 022671 Rev 1 -25 0 25 50 75 Tj (C) 100 125 150 175 L6564T Typical electrical performance Figure 24. Gate drive output saturation vs. TJ Figure 25. Delay to output vs. TJ 12 300 High level 10 250 TD(H-L) (n s) V 8 6 200 VCC = 12V 150 4 100 Low level 2 50 0 -50 -25 0 25 50 75 100 125 150 175 -50 -25 0 25 50 75 100 125 150 175 Tj (C) Tj (C) Figure 26. Startup timer period vs. TJ 450 After OCP 400 350 Ti m e (us) 300 250 Timer 200 150 100 First Cicle 50 0 -50 -25 0 25 50 75 100 125 150 175 Tj (C) Doc ID 022671 Rev 1 17/33 Application information L6564T 6 Application information 6.1 Overvoltage protection Normally, the voltage control loop keeps the output voltage Vo of the PFC pre-regulator close to its nominal value, set by the ratio of the resistors R1 and R2 of the output divider. A pin of the device (PFC_OK) has been dedicated to monitor the output voltage with a separate resistor divider (R3 high, R4 low, see Figure 27). This divider is selected so that the voltage at the pin reaches 2.5 V if the output voltage exceeds a preset value, usually larger than the maximum Vo that can be expected. Example: VO = 400 V, VOX = 434 V. Select: R3 = 8.8 MΩ; then: R4 = 8.8 MΩ ·2.5/(434-2.5) = 51 kΩ. When this function is triggered, the gate drive activity is immediately stopped until the voltage on the pin PFC_OK drops below 2.4 V. Note that R1, R2, R3 and R4 can be selected without any constraints. The unique criterion is that both dividers have to sink a current from the output bus which needs to be significantly higher than the bias current of both INV and PFC_OK pins. Figure 27. Output voltage setting, OVP and FFP functions: internal block diagram  9RXW 5D 5 5E   'LVDEOH  9 9 3)&B2. 5D 9 9  293 /B293  5 9 5E   )UHTXHQF\ &203 FRPSHQVDWLRQ    ,19 5 9  (UURU$PSOLILHU 5 !-V 18/33 Doc ID 022671 Rev 1 L6564T 6.2 Application information Feedback failure protection (FFP) The OVP function described above handles “normal” overvoltage conditions, i.e. those resulting from an abrupt load/line change or occurring at startup. In case the overvoltage is generated by a feedback disconnection, for instance when the upper resistor of the output divider (R1) fails to open, the comparator detects the voltage at pin INV. If the voltage is lower than 1.66 V and the OVP is active, the FFP is triggered, the gate drive activity is immediately stopped, the device is shut down, its quiescent consumption is reduced below 180 µA and the condition is latched as long as the supply voltage of the IC is above the UVLO threshold. To restart the system it is necessary to recycle the input power, so that the Vcc voltage of the L6564T goes below 6 V. The pin PFC_OK doubles its function as a not-latched IC ‘Disable’: a voltage below 0.23 V shuts down the IC, reducing its consumption below 2 mA. To restart the IC simply let the voltage at the pin go above 0.27 V. Note that these functions offer complete protection against not only feedback loop failures or erroneous settings, but also against a failure of the protection itself. Either resistor of the PFC_OK divider failing short or open or a PFC_OK pin floating results in shutting down the IC and stopping the pre-regulator. 6.3 Voltage feedforward The power stage gain of PFC pre-regulators varies with the square of the RMS input voltage. So does the crossover frequency FC of the overall open-loop gain because the gain has a single pole characteristic. This leads to a large trade-off in the design. For example, setting the gain of the error amplifier to get FC = 20 Hz @ 264 Vac means having FC 4 Hz @ 88 Vac, resulting in a sluggish control dynamics. Additionally, the slow control loop causes large transient current flow during rapid line or load changes that are limited by the dynamics of the multiplier output. This limit is considered when selecting the sense resistor to let the full load power pass under minimum line voltage conditions, with some margin. But a fixed current limit allows excessive power input at high line, whereas a fixed power limit requires the current limit to vary inversely with the line voltage. Voltage feedforward can compensate for the gain variation with the line voltage and allow the minimizing of all the above-mentioned issues. It consists in deriving a voltage proportional to the input RMS voltage, feeding this voltage into a squarer/divider circuit (1/V2 corrector) and providing the resulting signal to the multiplier that generates the current reference for the inner current control loop (see Figure 28). Doc ID 022671 Rev 1 19/33 Application information L6564T Figure 28. Voltage feedforward: squarer/divider (1/V2) block diagram and transfer characteristic  5HFWLILHGPDLQV FXUUHQW UHIHUHQFH 9FV[ ($RXWSXW 9 &203  9FV[  /+ /7 08/7,3/,(5  9 &203 9 LGHDOGLRGH 9   $FWXDO ,GHDO    9 08/7  0$,16'523 '(7(&725   9)) & ))  5 ))      9)) 908/7 !-V In this way a change of the line voltage causes an inversely proportional change of the half sine amplitude at the output of the multiplier (if the line voltage doubles the amplitude of the multiplier output is halved and vice versa) so that the current reference is adapted to the new operating conditions with (ideally) no need for invoking the slow dynamics of the error amplifier. Additionally, the loop gain is constant throughout the input voltage range, which significantly improves dynamic behavior at low line and simplifies loop design. In fact, deriving a voltage proportional to the RMS line voltage implies a form of integration, which has its own time constant. If it is too small the voltage generated is affected by a considerable amount of ripple at twice the mains frequency that causes distortion of the current reference (resulting in high THD and poor PF); if it is too large there is a considerable delay in setting the right amount of feedforward, resulting in excessive overshoot and undershoot of the pre-regulator's output voltage in response to large line voltage changes. Clearly a trade-off was required. The L6564T realizes a NEW voltage feed forward that, with a technique that makes use of just two external parts, strongly minimizes this time constant trade-off issue whichever voltage change occurs on the mains, both surges and drops. A capacitor CFF and a resistor RFF, both connected from pin VFF (#5) to ground, complete an internal peak-holding circuit that provides a DC voltage equal to the peak of the rectified sine wave applied on pin MULT (#3). In this way, in case of sudden line voltage rise, CFF is rapidly charged through the low impedance of the internal diode; in case of line voltage drop, an internal “mains drop” detector enables a low impedance switch which suddenly discharges CFF avoiding long settling time before reaching the new voltage level. The discharge of CFF is stopped as its voltage equals the voltage on the MULT pin or if the voltage on the VFF pin falls below 0.88 V, to prevent the “Brownout protection” function from being improperly activated (see Section 6.3). As a result of the VFF pin functionality, an acceptably low steady-state ripple and low current distortion can be achieved with a limited undershoot or overshoot on the pre-regulator's output. 20/33 Doc ID 022671 Rev 1 L6564T Application information The twice-mains-frequency (2• fL) ripple appearing across CFF is triangular with a peak-topeak amplitude that, with good approximation, is given by: ∆VFF = 2 VMULTpk 1 + 4fLRFF CFF where fL is the line frequency. The amount of 3rd harmonic distortion introduced by this ripple, related to the amplitude of its 2• fL component, is: 100 2π fLRFF CFF D3 % = Figure 29 shows a diagram that helps choose the time constant RFF·CFF based on the amount of maximum desired 3rd harmonic distortion. Note that there is a minimum value for the time constant RFF · CFF below which improper activation of the VFF fast discharge may occur. In fact, the twice-mains-frequency ripple across CFF under steady-state conditions must be lower than the minimum line drop detection threshold (∆VFF_min = 40 mV). Therefore: 2 RFF ⋅ CFF > VMULTpk _ max ∆VVFF _ min −1 4 fL _ min Always connect RFF and CFF to the pin, the IC does not work properly if the pin is either left floating or connected directly to ground. Figure 29. RFF·CFF as a function of 3rd harmonic distortion introduced in the input current 10 1 f L= 50 Hz R FF · C FF [s] 0.1 f L= 60 Hz 0.01 0.1 1 10 D3 % Doc ID 022671 Rev 1 21/33 Application information 6.4 L6564T THD optimizer circuit The L6564T is provided with a special circuit that reduces the conduction dead-angle occurring to the AC input current near the zero-crossings of the line voltage (crossover distortion). In this way the THD (total harmonic distortion) of the current is considerably reduced. A major cause of this distortion is the inability of the system to transfer energy effectively when the instantaneous line voltage is very low. This effect is magnified by the highfrequency filter capacitor placed after the bridge rectifier, which retains some residual voltage that causes the diodes of the bridge rectifier to be reverse-biased and the input current flow to temporarily stop. To overcome this issue the device forces the PFC pre-regulator to process more energy near the line voltage zero-crossings as compared to that commanded by the control loop. This results in both minimizing the time interval where energy transfer is lacking and fully discharging the high-frequency filter capacitor after the bridge. Figure 30 shows the internal block diagram of the THD optimizer circuit. Figure 30. THD optimizer circuit W W 9 9)) W  &203 08/7,3/,(5  08/7 W WR3:0 FRPSDUDWRU  2))6(7 *(1(5$725 W #9DF #9DF!9DF W !-V 22/33 Doc ID 022671 Rev 1 L6564T Application information Figure 31. THD optimization: standard TM PFC controller (left side) and L6564T (right side) Input current Input current Rectified mains voltage Rectified mains voltage Imains Input current Imains Input current Vdrain MOSFET's drain voltage Vdrain MOSFET's drain voltage Essentially, the circuit artificially increases the ON-time of the power switch with a positive offset added to the output of the multiplier in the proximity of the line voltage zero-crossings. This offset is reduced as the instantaneous line voltage increases, so that it becomes negligible as the line voltage moves toward the top of the sinusoid. Furthermore, the offset is modulated by the voltage on the VFF pin (see Section 6.3) so as to have little offset at low line, where energy transfer at zero crossings is typically quite good, and a larger offset at high line where the energy transfer gets worse. The effect of the circuit is shown in Figure 31, where the key waveforms of a standard TM PFC controller are compared to those of this chip. To take maximum benefit from the THD optimizer circuit, the high-frequency filter capacitor after the bridge rectifier should be minimized, compatibly with EMI filtering needs. A large capacitance, in fact, introduces a conduction dead-angle of the AC input current in itself even with an ideal energy transfer by the PFC pre-regulator - therefore reducing the effectiveness of the optimizer circuit. 6.5 Inductor saturation detection The boost inductor's hard saturation may be a fatal event for a PFC pre-regulator: the current up-slope becomes so large (50-100 times steeper, see Figure 32) that during the current sense propagation delay the current may reach abnormally high values. The voltage drop caused by this abnormal current on the sense resistor reduces the gate-to-source voltage, so that the MOSFET may work in the active region and dissipate a huge amount of power, which leads to a catastrophic failure after few switching cycles. Doc ID 022671 Rev 1 23/33 Application information L6564T However, in some applications such as AC-DC adapters, where the PFC pre-regulator is turned off at light load for energy saving reasons, even a well-designed boost inductor may occasionally slightly saturate when the PFC stage is restarted because of a larger load demand. This happens when the restart occurs at an unfavorable line voltage phase, i.e. when the output voltage is significantly below the rectified peak voltage. As a result, in the boost inductor the inrush current coming from the bridge rectifier adds up to the switched current and, furthermore, there is little or no voltage available for demagnetization. To cope with a saturated inductor, the L6564T is provided with a second comparator on the current sense pin (CS, pin 4) that stops the IC if the voltage, normally limited within 1.1 V, exceeds 1.7 V. After that, the IC is attempted to restart by the internal starter circuitry; the starter repetition time is twice the nominal value to guarantee lower stress for the inductor and boost diode. Hence, the system safety is considerably increased. Figure 32. Effect of boost inductor saturation on the MOSFET current and detection method 24/33 Doc ID 022671 Rev 1 L6564T 6.6 Application information Power management/housekeeping functions A communication line with the control IC of the cascaded DC-DC converter can be established via the disable function included in the PFC_OK pin (see Section 6.2 for more details). This line is typically used to allow the PWM controller of the cascaded DC-DC converter to shut down the L6564T in case of light load and to minimize the no-load input consumption. Should the residual consumption of the chip be an issue, it is also possible to cut down the supply voltage. The interface circuits are shown in Figure 32. Needless to say, this operation assumes that the cascaded DC-DC converter stage works as the master and the PFC stage as the slave or, in other words, that the DC-DC stage starts first, it powers both controllers and enables/disables the operation of the PFC stage. Figure 33. Interface circuits that let DC-DC converter's controller IC disable the L6564T ,!   6## 6##?0&# , ,4 6##  0&#?/+  ,!  , ,4 0&#?34/0 0&#?/+ ,  0&#?34/0  , ,4 !-V Another function available is the brownout protection which is basically a not-latched shutdown function that is activated when a condition of mains undervoltage is detected. This condition may cause overheating of the primary power section due to an excess of RMS current. Brownout can also cause the PFC pre-regulator to function in open loop and this may be dangerous to the PFC stage itself and the downstream converter, should the input voltage return abruptly to its rated value. Another problem is the spurious restarts that may occur during converter power-down and that cause the output voltage of the converter not to decay to zero monotonically. For these reasons it is usually preferable to shut down the unit in case of brownout. The brownout threshold is internally fixed at 0.8 V and is sensed on pin VFF (5) during the voltage falling and an 80 mV threshold hysteresis prevents rebounding at input voltage turn-off. In Table 5 it is possible to find a summary of all of the above mentioned working conditions that cause the device to stop operating. Doc ID 022671 Rev 1 25/33 Application information Table 5. 26/33 L6564T Summary of L6564 idle states Typical IC Condition Caused or revealed by IC behavior Restart condition UVLO Vcc < VccOff Disabled Vcc > VccOn 90 µA Feedback disconnected PFC_OK > VPFC_OK_S and INV < 1.66 V Latched Vcc < Vccrestart then Vcc > VccOn 180 µA Standby PFC_OK < VPFC_OK_D Stop switching PFC_OK > VPFC_OK_E 1.5 mA AC brownout VFF < VDIS Stop switching RUN > VEN 1.5 mA OVP PFC_OK > VPFC_OK_S Stop Switching PFC_OK < VPFC_OK_R 2.2 mA Low consumption COMP < 2.4 V Burst mode COMP > 2.4V 2.2 mA Saturated boost inductor Vcs > VCS_th Doubled Tstart Auto restart 2.2 mA Doc ID 022671 Rev 1 consumption L6564T Application examples and ideas 7 Application examples and ideas Figure 34. Demonstration board EVL6564-100W, wide-range mains: electrical schematic ) )8 6($    & 1 9DF     ' 1 5 17& 56 & 1 - 0.'6   ' 677+/  & 1 9 B a    / 65: 34;;;9 ' *%8- a  / +) < 57  - 0.'6  & X) 9 & 1 5 5 ' // 5 0 5 0 ' %=;& 5 0 5 . 5 0 5 . 5 0 5 0 5 . 5 . 5 . 5 0 5 . -3; 5 5 . & 1 5 0 8 / & 1    & 1 5 0 5 .   5 0 ,1 9 &203 & 1 9&& *' 08/7 *1' &6 =& ' 9)) 3)& 2. & X)9  4 67)101   +6 +($76,1 . 5 5 5 .  5 5  5 5 & 1 5 5 & X) & S 5 5 5 . Doc ID 022671 Rev 1 - &21  9&&  *1'  212)) 27/33 Application examples and ideas L6564T Figure 35. L6564 100 W TM PFC: compliance with EN61000-3-2 standard Meas ured value Figure 36. L6564 100 W TM PFC: compliance with JEITA-MITI standard EN61000-3- 2 class- D limits Measur ed value JEITA-MITI Class-Dlim its 10 Harmonic Current [A] Harmonic Current [A] 1 0.1 0.01 0.001 1 0.1 0.01 0.001 0.0001 0.0001 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 Harmonic Order [n] Harmonic Order [n] Figure 37. L6564 100 W TM PFC: input current Figure 38. L6564 100W TM PFC: input current waveform @230-50 Hz - 100 W load waveform @100 V-50 Hz - 100 W load 28/33 Doc ID 022671 Rev 1 L6564T 8 Package mechanical data Package mechanical data In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK® packages, depending on their level of environmental compliance. ECOPACK specifications, grade definitions and product status are available at: www.st.com. ECOPACK is an ST trademark. Table 6. SSO10 mechanical data Databook (mm.) Dim. Min. Typ. A Max. 1.75 A1 0.10 A2 1.25 b 0.31 0.51 c 0.17 0.25 D 4.80 4.90 5 E 5.80 6 6.20 E1 3.80 3.90 4 e 0.25 1 h 0.25 0.50 L 0.40 0.90 K 0° 8° Doc ID 022671 Rev 1 29/33 Package mechanical data L6564T Figure 39. SSO10 package dimensions 8140761 rev. A 30/33 Doc ID 022671 Rev 1 L6564T 9 Ordering codes Ordering codes Table 7. Ordering information Order codes Package L6564TD Packing Tube SSO10 L6564TDTR Tape and reel Doc ID 022671 Rev 1 31/33 Revision history 10 L6564T Revision history Table 8. 32/33 Document revision history Date Revision 18-Jan-2012 1 Changes Initial release Doc ID 022671 Rev 1 L6564T Please Read Carefully: Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any time, without notice. All ST products are sold pursuant to ST’s terms and conditions of sale. Purchasers are solely responsible for the choice, selection and use of the ST products and services described herein, and ST assumes no liability whatsoever relating to the choice, selection or use of the ST products and services described herein. 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The ST logo is a registered trademark of STMicroelectronics. All other names are the property of their respective owners. © 2012 STMicroelectronics - All rights reserved STMicroelectronics group of companies Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan Malaysia - Malta - Morocco - Philippines - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States of America www.st.com Doc ID 022671 Rev 1 33/33