L6565DTR

L6565 QUASI-RESONANT SMPS CONTROLLER QUASI-RESONANT (QR) ZERO-VOLTAGESWITCHING (ZVS) TOPOLOGY ■ LINE FEED FORWARD TO DELIVER CONSTANT POWER vs. MAINS CHANGE ■ FREQUENCY FOLDBACK FOR OPTIMUM STANDBY EFFICIENCY ■ PULSE-BY-PULSE & HICCUP-MODE OCP ■ ULTRA-LOW START-UP (< 70µA) AND QUIESCENT CURRENT (< 3.5mA) ■ DISABLE FUNCTION (ON/OFF CONTROL) ■ 1% PRECISION (@ T j = 25°C) INTERNAL REFERENCE VOLTAGE ■ ±400mA TOTEM POLE GATE DRIVER WITH UVLO PULL-DOWN ■ BLUE ANGEL, ENERGY STAR, ENERGY 2000 COMPLIANT APPLICATIONS ■ TV/MONITOR SMPS ■ AC-DC ADAPTERS/CHARGERS ■ DIGITAL CONSUMER ■ PRINTERS, FAX MACHINES, PHOTOCOPIERS AND SCANNERS ■ DIP8(Minidip) SO-8 ORDERING NUMBERS: L6565N L6565D DESCRIPTION The L6565 is a current-mode primary controller IC, specifically designed to build offline Quasi-resonant ZVS (Zero Voltage Switching at switch turn-on) flyback converters. Quasi-resonant operation is achieved by means of a transformer demagnetization sensing input that triggers MOSFET's turn-on. BLOCK DIAGRAM COMP VFF 2 3 1 INV - LINE VOLTAGE FEEDFORWARD + 40K 2.5V 4 CS 2V VOLTAGE REGULATOR - + - 8 VCC 5pF + Hiccup-mode OCP INTERNAL SUPPLY R Q S Q VCC 20V R1 + R2 7 GD UVLO DRIVER - VREF2 Blanking START ZERO CURRENT DETECTOR Starter STOP + BLANKING 2.1V 1.6V Hiccup-mode OCP 5 ZCD January 2003 STARTER - DISABLE 6 GND 1/17 L6565 DESCRIPTION (continued) Converter's power capability variations with the mains voltage are compensated by line voltage feedforward. At light load the device features a special function that automatically lowers the operating frequency still maintaining the operation as close to ZVS as possible. In addition to very low start-up and quiescent currents, this feature helps keep low the consumption from the mains at light load and be Blue Angel and Energy Star compliant. The IC includes also a disable function, an on-chip filter on current sense, an error amplifier with a precise reference voltage for primary regulation and an effective two-level overcurrent protection. PIN CONNECTION (Top view, Minidip and SO8) INV 1 8 Vcc COMP 2 7 GD VFF 3 6 GND CS 4 5 ZCD PIN DESCRIPTION N° Name Function 1 INV Inverting input of the error amplifier. The information on the output voltage is fed into the pin through either a resistor divider (primary regulation) or an optocoupler (secondary feedback). This pin can be grounded in some secondary feedback schemes (see pin 2). 2 COMP Output of the error amplifier. Typically, a compensation network is placed between this pin and the INV pin to achieve stability and good dynamic performance of the voltage control loop. With secondary feedback, the pin can be also driven directly by an optocoupler to control PWM by modulating the current sunk from the pin (with the INV pin grounded). 3 VFF Line voltage feedforward. The information on the converter’s input voltage is fed into the pin through a resistor divider and is used to change the setpoint of the pulse-by-pulse current limitation (the higher the voltage, the lower the setpoint). If this function is not desired the pin will be grounded and the current limitation setpoint will be maximum. 4 CS Input to the PWM comparator. The primary current is sensed through a resistor, the resulting voltage is applied to this pin and compared with an internal reference to determine MOSFET’s turn-off. The internal reference is clamped at a value, which defines the pulse-by-pulse current limitation setpoint, depending on the voltage at pin VFF. If the signal at the pin CS exceeds 2 V, the gate driver will be disabled (Hiccup-mode OCP). 5 ZCD Transformer’s demagnetization sensing input for Quasi-Resonant operation. Alternately, synchronization input for an external signal. A negative-going edge triggers MOSFET’s turn-on. The trigger circuit is blanked for a minimum of 3.5 µs after MOSFET turn-off, for safe operation under short circuit conditions and frequency foldback. If the pin is grounded the IC will be disabled. 6 GND Ground. Current return for both the signal part of the IC and the gate driver. 7 GD Gate driver output. The totem pole output stage is able to drive power MOSFET’s and IGBT’s with a peak current of 400 mA (source and sink). 8 Vcc Supply Voltage of both the signal part of the IC and the gate driver. An electrolytic capacitor is connected between this pin and ground. A resistor connected from this pin to the converter’s input bulk capacitor will be typically used to start up the device. 2/17 L6565 THERMAL DATA Symbol Rth j-amb Parameter Max. Thermal Resistance, Junction-to-ambient SO8 Minidip Unit 150 100 °C/W ABSOLUTE MAXIMUM RATINGS Symbol Pin IVcc 8 ICC + IZ IGD 7 Output Totem Pole Peak Current (2 µs) INV, COMP, VFF, CS Parameter Value Unit 30 mA ±700 mA -0.3 to 7 V 50 (source) -10 (sink) mA 1 0.65 W Junction Temperature Operating range -40 to 150 °C Storage Temperature -55 to 150 °C 1, 2, 3 4 Analog Inputs & Outputs 5 IZCD Zero Current Detector Ptot Power Dissipation @Tamb = 50°C Tj Tstg (Minidip) (SO8) ELECTRICAL CHARACTERISTCS (Tj = -25 to 125°C, VCC = 12V, Co = 1nF; unless otherwise specified) Symbol Parameter Test Condition Min. Typ. Max. Unit SUPPLY VOLTAGE Vcc Operating range VCCOn Turn-on threshold 12.5 13.5 14.5 V VCCOff Turn-off threshold 8.7 9.5 10.3 V 3.65 4 4.3 V 18 20 22 V Hys Hysteresis VZ Zener Voltage After turn-on Icc = 25 mA 10.3 18 SUPPLY CURRENT Istart-up Start-up Current Before turn-on, VCC = 12V 45 70 µA Quiescent Current After turn-on 2.3 3.5 mA Operating Supply Current @ 70 kHz 3.5 5 mA Iq Quiescent Current During Hiccup-mode OCP 3.5 mA Iq Quiescent Current VZCD < VDIS, VCC>VCCOff 1.4 2.1 mA -1 µA Iq ICC 1.6 LINE FEEDFORWARD IVFF Input Bias Current VVFF Operating Range K Gain VVFF = 0 to 3 V 0 to 3 V 0.16 VVFF = 1.5V, VCOMP = 4V ERROR AMPLIFIER VINV Voltage Feedback Input Threshold Line Regulation IINV Input Bias Current Tamb = 25°C 2.465 12V < VCC < 18V 2.44 Vcc = 12 to 18V 2.5 2.535 V 2.56 2 5 mV -0.1 -1 µA 3/17 L6565 ELECTRICAL CHARACTERISTCS (continued) (Tj = -25 to 125°C, VCC = 12V, Co = 1nF; unless otherwise specified) Symbol Parameter Min. Typ. Open loop 60 80 Source Current VCOMP = 4V, VINV = 2.4 V -2 -3.5 Sink Current VCOMP = 4V, VINV = 2.6 V 2.5 4.5 GV Voltage Gain GB Gain-Bandwidth Product ICOMP VCOMP Test Condition Max. dB 1 Upper Clamp Voltage ISOURCE = 0.5 mA Lower Clamp Voltage ISINK = 0.5 mA 5 2.25 VCS = 0 Unit MHz -5 mA mA 5.5 V 2.55 V -0.05 -1 µA 200 450 ns V CURRENT SENSE COMPARATOR ICS Input Bias Current td(H-L) Delay to Output VCSx Current Sense Reference Clamp VCOMP = Upper clamp, VVFF = 0V 1.28 1.4 1.5 VCOMP = Upper clamp, VVFF = 1.5V 0.62 0.7 0.78 0 0.2 1.85 2.0 2.2 V VCOMP = Upper clamp, VVFF = 3V VCSdis Hiccup-mode OCP level ZERO CURRENT DETECTOR/ SYNCHRONIZATION VZCDH Upper Clamp Voltage IZCD = 3mA 4.7 5.2 6.1 V VZCDL Lower Clamp Voltage IZCD = - 3mA 0.3 0.65 1 V VZCDA Arming Voltage (positive-going edge) (1) VZCDT Triggering Voltage (negative-going edge) IZCDb Input Bias Current VZCD = 1 to 4.5 V 2.1 V 1.6 V 2 µA IZCDsrc Source Current Capability -3 -10 mA IZCDsnk Sink Current Capability 3 10 mA VDIS Disable Threshold IZCDr Restart Current After Disable VZCD < VDIS, Vcc > Vccoff Blanking time after pin 7 high-tolow transition VCOMP ≥ 3.2 V 3.5 VCOMP = 2.5 V 18 TBLANK 150 200 250 mV -70 -150 -230 µA µs START TIMER tSTART Start Timer period 250 400 550 µs IGDsource = 200mA 1.2 2 V IGDsource = 20mA 0.7 GATE DRIVER VOL Dropout Voltage VOH 2 IGDsink = 20mA 0.3 V tf Current Fall Time 40 100 ns tr Current Rise Time 40 100 ns IGDoff IGD sink current Vcc = 4 V, VGD = 1 V (1) Parameters guaranteed by design, not tested in production. 4/17 1 IGDsink = 200mA 5 10 mA L6565 Figure 1. Supply current vs. Supply voltage ICC (mA) Figure 4. Line feedforward characteristics Vcsx [V] 1.5 Upper clamp 10 5.0 V 5 1 1 4.5 V 0.5 4.0 V 0.1 0.5 3.5 V 0.05 CL = 1nF f = 70KHz TA = 25°C 0.01 0.005 3.0 V 0 VCOMP = 2.5V 0 0 0 5 10 15 20 0.5 1 VCC(V) Figure 2. Start-up & UVLO vs. Temperature 1.5 2 2.5 3 3.5 VVFF [V] Figure 5. Pin 2 (COMP) V-I characteristics VCOMP [V] 14 VCC-ON (V) 13 6 Tj = 25 °C Vpin1 = 0 5 4 12 3 11 Regulation range 2 10 VCC-OFF (V) 9 -25 1 0 0 25 50 75 100 125 0 1 2 3 4 ICOMP [mA] T (°C) Figure 3. Feedback reference vs. Temperature VREF (V) D94IN048A Figure 6. ZCD blanking time vs. COMP voltage TBLANK [µs] 20 Tj = 25 °C 15 2.50 10 2.48 5 0 2 2.46 -50 0 50 100 T (°C) 3 4 5 6 VCOMP [V] 5/17 L6565 Figure 7. Gate-drive output saturation Figure 10. Zener voltage at Vcc pin vs. Tj Vpin7 [V] Vz [V] 2.5 22 Tj = 25 °C Vcc = 14.5 V SINK 2 21 1.5 20 1 19 0.5 0 0 100 200 300 400 500 18 -50 0 50 100 150 Tj [°C] IGD [mA] Figure 11. Start-up timer period vs. Tj Figure 8. Gate-drive output saturation TSTART [µs] Vpin7 [V] 0 Vcc - 0.5 450 Tj = 25 °C Vcc = 14.5 V SOURCE Vcc --0.5 0.5 Vcc=12V 400 Vcc - 1.0 -1 350 Vcc --1.5 1.5 300 Vcc - 2.0 -2 Vcc - 0.5 -2.5 0 100 200 300 400 500 IGD [mA] Icc [mA] 5 Vcc=12V 2 Quiescent 1 0.5 0.2 0.1 0.02 -50 Before Start-up 0 50 Tj [°C] 6/17 0 50 Tj [°C] Figure 9. IC consumption vs. temperature 0.05 250 -50 100 150 100 150 L6565 APPLICATION INFORMATION Quasi-resonant operation in offline flyback converters lies in synchronizing MOSFET's turn-on to the transformer's demagnetization. Detecting the resulting negative-going edge of the voltage across any winding of the transformer can do this. The L6565 is provided with a dedicated pin that allows doing the job with a very simple interface, just one resistor. Variable frequency operation - as a result of different operating conditions in terms of input voltage and output current - is inherent in such functionality. The system always works close to the boundary between DCM (Discontinuous Conduction Mode) and CCM (Continuous Conduction Mode) operation of the transformer. The operation is then identical to that of the so-called self-oscillating or Ringing Choke Converter (RCC). Detailed Device Description Internal Supply Block (see fig. 12) A linear voltage regulator supplied by Vcc (pin 8) generates an internal 7V rail used for supplying the entire IC, except for the gate driver that is supplied directly from Vcc. In addition, a bandgap circuit generates a precise internal reference (2.5V±1% @ 25°C) used by the control loop to ensure a good regulation with primary feedback technique. In figure 12 it is also shown the undervoltage lockout (UVLO) comparator with hysteresis used to enable the chip as long as the Vcc voltage is high enough to ensure a reliable operation. Figure 12. L6565 internal supply block +Vin Vcc 8 + LIN. REG. UVLO REF. 2.5V 7V bus 7/17 L6565 Zero Current Detection and Triggering Block (see fig. 13): The Zero Current Detection (ZCD) block switches on the external MOSFET if a negative-going edge falling below 1.6 V is applied to the input (pin 5, ZCD). However, to ensure high noise immunity, the triggering block must be armed first: prior to falling below 1.6V, the voltage on pin 5 must experience a positive-going edge exceeding 2.1 V. This feature is typically used to detect transformer demagnetization for QR operation, where the signal for the ZCD input is obtained from the transformer's auxiliary winding used also to supply the IC. Alternatively, this can be used to synchronize MOSFET's turn-on to the negative-going edge of an external clock signal, in case the device is not required to work in QR mode but as a standard PWM controller in a synchronized system (e.g. monitor SMPS). The triggering block is blanked for a certain time after the MOSFET has been turned off. This has two goals: first, to prevent any negative-going edge that follows leakage inductance demagnetization from triggering the ZCD circuit erroneously; second, to realize the Frequency Foldback function (see the relevant description). Figure 13. Zero Current Detection and Triggering Block; Disable and Frequency Foldback Blocks COMP L6565 INV E/A + 2.5V RZCD 5 ZCD 150µA +Vin 5.2V - Q BLANKING TIME 1.6V 2.1V + PWM blanking START 7 R Q MONO STABLE S STARTER 0.2V 0.3V to line FFWD DRIVER GD starter STOP DISABLE + A circuit is needed that turns on the external MOSFET at start-up since no signal is coming from the ZCD pin. This is realized with an internal starter, which forces the driver to deliver a pulse to the gate of the MOSFET. To minimize the external interface with the synchronization source (either the auxiliary winding or an external clock), the voltage at the pin is both top and bottom limited by a double clamp, as illustrated in the internal diagram of the ZCD block of figure 13. The upper clamp is typically located at 5.2 V, while the lower clamp is at one VBE above ground. The interface will then be made by just one resistor that has to limit the current sourced by and sunk from the pin within the rated capability of the internal clamps. Disable Block (see fig. 13): The ZCD pin is used also to activate the Disable Block. If the voltage on the pin is taken below 150 mV the device will be shut down. To do so, it is necessary to override the source capability (10 mA max.) of the internal lower clamp. While in disable, the current consumption of the IC will be reduced. To re-enable device operation, the pull-down on the pin must be released. Frequency Foldback Block (see fig. 13): To prevent the switching frequency from reaching too high values, which is a typical drawback of QR operation, 8/17 L6565 the L6565 puts a limit on the minimum OFF-time of the switch. This is done by blanking the triggering block of the ZCD circuit as mentioned before. The duration of the blanking time (3.5µs min.) is a function of the error amplifier output VCOMP, as shown in the diagram of figure 6. If the load current and the input voltage are such that the switch OFF-time falls below the minimum blanking time of 3.5µs, the system will enter the "Frequency Foldback" mode, a sort of "ringing cycle skipping" illustrated schematically in figure 14. Figure 14. Frequency foldback: ringing cycle skipping as the load is progressively reduced VDS VDS VDS t TFW t t TV TBLANKmin TBLANK Pin = Pin' (limit condition) TBLANK Pin = Pin'' < Pin' Pin = Pin''' < Pin'' In this mode, uneven switching cycles may be observed under some line/load conditions, due to the fact that the OFF-time of the MOSFET is allowed to change with discrete steps (2·Tv), while the OFF-time needed for cycle-by-cycle energy balance may fall in between. Thus one or more longer switching cycles will be compensated by one or more shorter ones and vice versa. However, this mechanism is absolutely normal and there is no appreciable effect on the performance of the converter or on its output voltage. Figure 15. Frequency Foldback: qualitative frequency dependence on power throughput fsw BURST MODE 00 00 00 00 0000 00 0 0 0 00 000 000 000 without frequency foldback Vin fixed with frequency foldback Voltage Feedforward block (see fig. 17b): The power that QR flyback converters with a fixed overcurrent setpoint (like fixed-frequency systems) are able to deliver changes with the input voltage considerably. With wide-range mains, at maximum line it can be more than twice the value at minimum line, as shown by the upper curve in the diagram of figure 16. The L6565 has the Line Feedforward function available to solve this issue. Figure 16. Typical power capability change vs. input voltage in ZVS QR flyback converters 2.5 system not compensated Pin Further load reductions involve lower values for VCOMP, which increases the blanking time. Therefore, more and more ringing cycles will be skipped. When the load is low enough, so many ringing cycles need to be skipped that their amplitude becomes very small and they can no longer trigger the ZCD circuit. In that case the internal starter of the IC will be activated, resulting in burst-mode operation: a series of few switching cycles spaced out by long periods where the MOSFET is in OFF state. Pinlim @ Vin Pinlim @ Vinmin 2 1.5 1 system optimally compensated 0.5 1 1.5 2 2.5 3 3.5 4 Vin Vinmin 9/17 L6565 It acts on the clamp level of the control voltage Vcsx, that is on the overcurrent setpoint, so that it is a function of the converter's input voltage sensed through a dedicated pin (#3, VFF): the higher the input voltage, the lower the setpoint. This is illustrated in the diagram of figure 17a that shows the relationship between the voltage at the pin VFF and Vcsx (with the error amplifier saturated high in the attempt of keeping output voltage regulation). The schematic in figure 17b shows also how the function is included in the control loop. With a proper selection of the external divider R1-R2 it is possible to achieve the optimum compensation described by the lower curve in the diagram of figure 16. In applications where this function is not wanted, e.g. because of a narrow input voltage range, the VFF pin can be simply grounded, thus saving the resistor divider. The overcurrent setpoint will be then fixed at the maximum value of about 1.4V (1.5V max.). Line Feedforward is also beneficial to other characteristics of quasi-resonant converters: it improves their input ripple rejection ability and limits the variation of the power stage's small-signal gain versus the line voltage. Figure 17. a) Overcurrent setpoint vs. VFF voltage; b) Line Feedforward function block Vcsx [V] 1.5 VCOMP = Upper clamp 1 a) 0.5 0 0 0.5 1 1.5 2 2.5 3 3.5 VVFF [V] +Vin R1 R2 Rs COMP 2 VFF CS 3 ZCD 4 5 ZCD PWM 2V Hiccup - 2.5V b) 10/17 S 7 Q DRIVER GD R (reset-dominant) + E/A + - - VOLTAGE FEED FORWARD starter STOP + INV 1 STARTER DISABLE L6565 L6565 Error Amplifier Block (see fig. 17b): The Error Amplifier (E/A) inverting input is used in primary feedback technique to compare a partition of the voltage generated by the auxiliary winding with the internal reference, to achieve converter's output voltage regulation (see "Application Ideas", fig. 24). With secondary feedback (typically using a TL431 at the secondary side and an optocoupler to transfer output voltage information to the primary side through the isolation barrier) the E/A can be used as an inverting level-shifter to achieve negative feedback and shape the loop gain (see "Application Ideas", fig. 23). The E/A output is used typically for control loop compensation, realized with an RC network connected to the inverting input. With other secondary feedback techniques, the output is driven directly by an emitter-grounded optocoupler to modulate the duty cycle (the inverting input will be grounded in that case - see figure 23 in "Application Ideas"). Current Comparator, PWM Latch and Hiccup-mode OCP (see fig. 17b): The current comparator senses the voltage across the current sense resistor (Rs) and, by comparing it with the programming signal delivered by the feedforward block, determines the exact time when the external MOSFET is to be switched off. The PWM latch avoids spurious switching of the MOSFET, which might result from the noise generated ("double-pulse suppression"). A comparator senses the voltage on the current sense input and disables the gate driver if the voltage at the pin exceeds 2 V. Such anomalous condition is typically generated by a short circuit on the secondary rectifier or on the secondary winding. To re-enable the driver, first the IC must be turned off and then can be restarted, that is the Vcc voltage must fall below the UVLO threshold. When the gate driver is disabled the quiescent current of the IC is unchanged and, since no energy is coming from the self-supply circuit, the Vcc capacitor will be discharged below the UVLO threshold after some time. Then the device will initiate a new start-up cycle. In case of failure of the secondary diode the resulting behavior will be a low-frequency intermittent operation (Hiccup-mode operation), with very low stress on the power circuit. Gate Driver (see fig. 18): A totem pole buffer, with 400mA source and sink capability, drives the external MOSFET. It is made up of a high-side NPN Darlington and a low-side MOSFET. In this way there is no need of an external diode clamp to prevent the voltage at the gate drive output (pin 7, GD) from being pulled too negative. An internal pull-down circuit holds the output low when the device is in UVLO conditions, to ensure that the external MOSFET cannot be turned on accidentally (e.g. at power-on). Figure 18. Gate driver with UVLO pull-down Vcc 8 L6565 7 GD Q DRIVER UVLO 6 GND 11/17 L6565 TYPICAL APPLICATIONS Figure 19. 50W Wide Range Mains SMPS for 14" TV C6 4700pF/ 4KV F1 2A fuse NTC1 16R D1 1N4148 C25 C24 1nF 100nF Vin C23 88 to 264 Vac 100nF R9 4.7M 3 B1 2KBP04M L1 15mH C1 150 µF 400 V C26 1nF R1 75k R2 75k R10 4.7M C22 100 pF T1 105 V 0.35 A C2 C8 8.2 nF 180 pF 250 V 630V R5 100 k C7 4700pF/ 4KV N1 C9 220 µF D5 BYT01-400 8 160 V 1 D3 N2 STTA106 9 R8 22 D6 BYW98-100 4 N3 C4 47µF 25V 5 7 R3 3M VFF 3 8 2 C3 1 nF 4 1 COMP R4 16 K 10 5 Q1 STP7NB80FI D2 R7 10 1N4148 CS Vcc 6 INV Naux R6 100 GD IC1 L6565 25 V D4 1N4148 R20 22 k ZCD R11 0.47 C27 220nF GND 1 IC3 PC817 R12 47 k C12 100 µF 25V R15 1.8 k 1 IC4 L7805 2 3 4 R14 1.5 k DZ1 15 V R13 3.3 k C5 2.2 nF 14 V 1A C10 470 µF 3 TRANSFORMER SPECS: CORE: ETD29x16x10, N67 material or equivalent IC2 TL431 ≈ 1 mm air gap for a primary inductance of 285 µH N1: 48 T (24T+24T series connected), 2xAWG28 (∅ 0.37 mm) N2: 31 T, AWG28 N3: 5 T, AWG28 Naux: 5 T, AWG32 (∅ 0.24 mm) P1 100 k R16 220 k 2 C13 100 nF 1 3 R18 150 k R17 4.7 k 2 Figure 20. 40W Wide Range Mains SMPS for inkjet printer 2200pF 4KV 2A fuse 16R 1N4148 BYW100-200 2KBP04M 1nF Vin 88 to 100nF 264 Vac 100nF 28V / 0.7A 75 kΩ 56 kΩ 2W 75 kΩ 15mH 1nF 10 nF 250V N2 2 x 470µF 35V BYW98-100 12V / 1.5A N1 STTA106 N3 2 x 1000µF 16V GND BYW100-50 10 Ω 47 kΩ 47µF 5V / 0.5A 1N4148 N5 5 3 MΩ N4 470µF 16V 8 10 Ω STP4NA80FP 7 L6565 220 Ω 3 10 nF PC817A 4 16 kΩ 2 1 0.39 Ω 1/2 W 3.3 nF PC817 100 nF TL431 TRANSFORMER SPECS: CORE: ETD29x16x10, 3C85 material or equivalent ≈1 mm air gap for a primary inductance of 700 µH N1: 75 T, AWG25 (∅ 0.51 mm) N2: 8 T, AWG25 N3: 7 T, AWG20 (∅ 0.89 mm) N4: 3 T, AWG25 N5: 7 T, AWG32 (∅ 0.24 mm) 12/17 270 kΩ 3.9 kΩ 6 2.7 kΩ 5.1 kΩ +5 V 50 mA C11 47 µF 25V L6565 APPLICATION IDEAS Here follows a series of ideas/suggestions aimed at either improving performance or solving common application issues of L6565-based power supplies. Figure 21. Enhanced turn-off for big MOSFET's drive Vcc 8 7 GD Q DRIVER BC327 L6565 Rs 6 GND Figure 22. Latched shutdown on: a) feedback disconnection; b) overload or short circuit Vcc Vcc 8 8 L6565 L6565 2 2 COMP COMP BC327 1N4148 BC327 1N4148 BC337 BC337 a) b) Figure 23. Secondary Feedback loop configurations Vout Vout Vout L6565 2 1 Vcc 8 INV COMP L6565 2 COMP 1 RA INV 8 RB L6565 ICOMP TL431 Vcc TL431 1 TL431 4 CS INV a) b) Roff Rs c) 13/17 L6565 Figure 24. Primary Feedback loop configurations Vcc COMP Vcc COMP 8 2 RH 8 2 RH 1 1 - INV + - to VFF block E/A INV to VFF block E/A + RL RL 2.5V GND 2.5V GND L6565 6 a) L6565 6 b) Figure 25. Protection against secondary feedback disconnection by primary regulation take-over Figure 27. Remote ON/OFF control L6565 5 Vcc 15 V ZCD 8 INV 1 L6565 OFF 2 BC337 ON COMP 2.2 kΩ Figure 28. Low-consumption start-up circuit Figure 26. Leading edge blanking circuit for enhanced primary regulation BC327 +Vin Vac 1N4148 Vcc R C START 1N4148 Vcc 470 pF L6565 8 1N4148 CSUPPLY L6565 2.7 kΩ 6 GND GND RELATED DOCUMENTATION [1] "L6565, QUASI-RESONANT CONTROLLER” (AN1326) [2] “25W QUASI-RESONANT FLYBACK CONVERTER FOR SET-TOP BOX APPLICATIONS USING THE L6565” (AN1376) [3] “EVAL6565N, 30W AC-DC ADAPTER WITH THE L6565 QUASI-RESONANT PWM CONTROLLER” (AN1439). 14/17 L6565 mm inch DIM. MIN. A TYP. MAX. MIN. 3.32 TYP. MAX. 0.131 a1 0.51 B 1.15 1.65 0.045 0.065 b 0.356 0.55 0.014 0.022 b1 0.204 0.304 0.008 0.012 0.020 D E 10.92 7.95 9.75 0.430 0.313 0.384 e 2.54 0.100 e3 7.62 0.300 e4 7.62 0.300 F 6.6 0.260 I 5.08 0.200 L Z 3.18 OUTLINE AND MECHANICAL DATA 3.81 1.52 0.125 0.150 Minidip 0.060 15/17 L6565 mm DIM. MIN. TYP. A a1 inch MAX. MIN. TYP. 1.75 0.1 0.25 a2 MAX. 0.069 0.004 0.010 1.65 0.065 a3 0.65 0.85 0.026 0.033 b 0.35 0.48 0.014 0.019 b1 0.19 0.25 0.007 0.010 C 0.25 0.5 0.010 0.020 c1 45° (typ.) D (1) 4.8 5.0 0.189 0.197 E 5.8 6.2 0.228 0.244 e 1.27 e3 0.050 3.81 0.150 F (1) 3.8 4.0 0.15 0.157 L 0.4 1.27 0.016 0.050 M S 0.6 0.024 8 ° (max.) (1) D and F do not include mold flash or protrusions. Mold flash or potrusions shall not exceed 0.15mm (.006inch). 16/17 OUTLINE AND MECHANICAL DATA SO8 L6565 Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is a registered trademark of STMicroelectronics © 2003 STMicroelectronics - All Rights Reserved STMicroelectronics GROUP OF COMPANIES Australia - Brazil - Canada - China - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan -Malaysia - Malta - Morocco Singapore - Spain - Sweden - Switzerland - United Kingdom - United States. http://www.st.com 17/17