L6566A

L6566A Multi-mode controller for SMPS with PFC front-end Datasheet − production data Features ■ Selectable multi-mode operation: fixed frequency or quasi-resonant ■ Onboard 700 V high-voltage startup ■ Advanced light load management ■ Low quiescent current (< 3 mA) ■ Adaptive UVLO ■ Line feedforward for constant power capability vs. mains voltage ■ Pulse-by-pulse OCP, shutdown on overload (latched or auto-restart) ■ Transformer saturation detection ■ Switched supply rail for PFC controller ■ Latched or auto-restart OVP ■ SO16N Applications ■ Notebook, TV and LCD monitor adapters ■ High power chargers ■ PDP/LCD TVs ■ Consumer appliances, such as DVD players, VCRs, set-top boxes Brownout protection ■ IT equipment, games, auxiliary power supplies ■ -600/+800 mA totem pole gate-driver with active pull-down during UVLO ■ Power supplies in excess of 150 W ■ SO16N package Block diagram 14 Icharge 5 Vcc_PFC 7.7V LINE VOLTAGE FEEDFORWARD AC_FAIL 400 uA - UVLO_SHF CS LEB + PWM Vth + OCP 7 + - VCC + Hiccup-mode OCP logic 5.7V + Q 1.5 V VCC IC_LATCH OVPL 1 mA UVLO OCP2 6 6.4V OVP OFF2 Reference voltages Internal supply VOLTAGE REGULATOR & ADAPTIVE UVLO VCC 15 LOW CLAMP & DISABLE + HV VFF 9 TIME SOFT-START OUT & FAULT MNGT 1 VCC COMP SS VREF 10 - Figure 1. BURST-MODE 14V OCP2 4 GD OSCILLATOR R Q MODE/SC 50 mV 100 mV ZCD S MODE SELECTION & TURN-ON LOGIC 12 - TIME OUT OVPL ZERO CURRENT DETECTOR + 11 DRIVER OVERVOLTAGE PROTECTION OVP OFF2 LATCH 4.5V + 13 - OSC DIS 8 IC_LATCH 16 AC_OK 3V 15 µA 0.450V 0.485V - AC_FAIL + UVLO DISABLE 3 GND March 2012 This is information on a product in full production. Doc ID 13794 Rev 4 1/52 www.st.com 52 Contents L6566A Contents 1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 2 Pin settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 3 2.1 Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Electrical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 3.1 Maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 3.2 Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 4 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 5 Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 5.1 High-voltage startup generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 5.2 Zero current detection and triggering block; oscillator block . . . . . . . . . . 19 5.3 Burst-mode operation at no load or very light load . . . . . . . . . . . . . . . . . . 22 5.4 Adaptive UVLO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 5.5 PWM control block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 5.6 PWM comparator, PWM latch and voltage feedforward blocks . . . . . . . . 25 5.7 Hiccup-mode OCP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 5.8 PFC interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 5.9 Latched disable function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 5.10 Soft-start and delayed latched shutdown upon overcurrent . . . . . . . . . . . 31 5.11 OVP block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 5.12 Brownout protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 5.13 Slope compensation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 5.14 Summary of L6566A power management functions . . . . . . . . . . . . . . . . 38 6 Application examples and ideas . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 7 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 2/52 Doc ID 13794 Rev 4 L6566A Contents 8 Order codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 9 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 Doc ID 13794 Rev 4 3/52 List of tables L6566A List of tables Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. 4/52 Pin functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Thermal data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 L6566A light load management features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 L6566A protection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 External circuits that determine IC behavior upon OVP and OCP . . . . . . . . . . . . . . . . . . . 44 SO16N dimentions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 Order codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 Doc ID 13794 Rev 4 L6566A List of figures List of figures Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Figure 10. Figure 11. Figure 12. Figure 13. Figure 14. Figure 15. Figure 16. Figure 17. Figure 18. Figure 19. Figure 20. Figure 21. Figure 22. Figure 23. Figure 24. Figure 25. Figure 26. Figure 27. Figure 28. Figure 29. Figure 30. Figure 31. Figure 32. Figure 33. Figure 34. Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Typical system block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Pin connection (through top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Multi-mode operation with QR option active . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 High-voltage startup generator: internal schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Timing diagram: normal power-up and power-down sequences . . . . . . . . . . . . . . . . . . . . 18 Timing diagram showing short-circuit behavior (SS pin clamped at 5 V) . . . . . . . . . . . . . . 19 Zero current detection block, triggering block, oscillator block and related logic . . . . . . . . 19 Drain ringing cycle skipping as the load is gradually reduced . . . . . . . . . . . . . . . . . . . . . . 20 Operation of ZCD, triggering and oscillator blocks (QR option active) . . . . . . . . . . . . . . . . 22 Load-dependent operating modes: timing diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Addition of an offset to the current sense lowers the burst-mode operation threshold . . . . 24 Adaptive UVLO block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Possible feedback configurations that can be used with the L6566A . . . . . . . . . . . . . . . . . 25 Externally controlled burst-mode operation by driving the COMP pin: timing diagram. . . . 26 Typical power capability change vs. input voltage in QR flyback converters . . . . . . . . . . . 27 Left: overcurrent setpoint vs. VFF voltage; right: line feedforward function block. . . . . . . . 28 Hiccup-mode OCP: timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Possible interfaces between the L6566A and a PFC controller . . . . . . . . . . . . . . . . . . . . . 31 Operation after latched disable activation: timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . 32 Soft-start pin operation under different operating conditions and settings . . . . . . . . . . . . . 33 OVP function: internal block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 OVP function: timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Maximum allowed duty cycle vs. switching frequency for correct OVP detection. . . . . . . . 36 Brownout protection: internal block diagram and timing diagram . . . . . . . . . . . . . . . . . . . . 37 AC voltage sensing with the L6566A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Slope compensation waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Typical low-cost application schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 Typical full-feature application schematic (QR operation) . . . . . . . . . . . . . . . . . . . . . . . . . 43 Typical full-feature application schematic (FF operation) . . . . . . . . . . . . . . . . . . . . . . . . . . 44 Frequency foldback at light load (FF operation) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 Latched shutdown upon mains overvoltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 Package drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 Recommended footprint (dimensions are in mm) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 Doc ID 13794 Rev 4 5/52 Description 1 L6566A Description The L6566A is an extremely versatile current-mode primary controller IC specifically designed for high-performance offline flyback converters operated from front-end power factor correction (PFC) stages in applications in compliance with EN61000-3-2 or JEITAMITI regulations. Both fixed-frequency (FF) and quasi-resonant (QR) operation are supported. The user can choose either of the two depending on application needs. The device features an externally programmable oscillator; it defines the converter's switching frequency in FF mode and the maximum allowed switching frequency in QR mode. When FF operation is selected, the IC works like a standard current-mode controller with a maximum duty cycle limited to 70% (min.). QR operation, when selected, occurs and is achieved through a transformer demagnetization sensing input that triggers MOSFET turn-on. Under some conditions, ZVS (zero-voltage switching) can be achieved. The converter's power capability rise with the input voltage is compensated by line voltage feedforward. At medium and light load, as the QR operating frequency equals the oscillator frequency, a function (valley skipping) is activated to prevent further frequency rise and keep the operation as close to ZVS as possible. With either FF or QR operation, at very light load the IC enters a controlled burst-mode operation that, along with the built-in non-dissipative high-voltage startup circuit and a reduced quiescent current, helps keep the consumption from the mains low and meet energy saving recommendations. To allow the meeting of energy saving recommendations in two-stage power-factorcorrected systems as well, the L6566A provides an interface with the PFC controller that enables the re-regulator to be turned off at light load. An innovative adaptive UVLO helps minimize the issues related to fluctuations in the selfsupply voltage due to transformer parasites. The protection functions included in this device are: not-latched input undervoltage (brownout), output OVP (auto-restart or latch-mode selectable), a first-level OCP with delayed shutdown to protect the system during overload or short-circuit conditions (autorestart or latch-mode selectable), and a second-level OCP which is invoked when the transformer saturates or the secondary diode fails short. A latched disable input allows easy implementation of OTP with an external NTC, while an internal thermal shutdown prevents IC overheating. Programmable soft-start, leading-edge blanking on the current sense input for greater noise immunity, slope compensation (in FF mode only), and a shutdown function for externally controlled burst-mode operation or remote ON/OFF control are all features of this device. 6/52 Doc ID 13794 Rev 4 L6566A Description Figure 2. Typical system block diagram PFC PRE-REGULATOR FLYBACK DC-DC CONVERTER Rectified Mains Voltage Voutdc PWM/QR controller is turned off in case of PFC's anomalous operation, for safety L6562A L6563S L6564 L6566A PFC is automatically turned off at light load to ease compliance with energy saving specifications. Doc ID 13794 Rev 4 7/52 Pin settings L6566A 2 Pin settings 2.1 Connections Figure 3. 2.2 HVS 1 16 AC_OK N.C. 2 15 VFF GND 3 14 SS GD 4 13 OSC Vcc 5 12 MODE/SC Vcc_PFC 6 11 ZCD CS 7 10 VREF DIS 8 9 COMP Pin description Table 1. N° 8/52 Pin connection (through top view) Pin functions Pin Function 1 HVS High-voltage startup. The pin, able to withstand 700 V, is to be tied directly to the rectified mains voltage. A 1 mA internal current source charges the capacitor connected between the Vcc pin (5) and GND pin (3) until the voltage on the Vcc pin reaches the turn-on threshold, it is then shut down. Normally, the generator is reenabled when the Vcc voltage falls below 5 V, to ensure a low power throughput during short-circuit. Otherwise, when a latched protection is tripped, the generator is re-enabled 0.5 V below the turn-on threshold, to keep the latch supplied; or, when the IC is turned off by the COMP pin (9) pulled low, the generator is active just below the UVLO threshold to allow a faster restart. 2 N.C. Not internally connected. Provision for clearance on the PCB to meet safety requirements. 3 GND Ground. Current return for both the signal part of the IC and the gate-drive. All of the ground connections of the bias components should be tied to a track going to this pin and kept separate from any pulsed current return. 4 GD Gate driver output. The totem pole output stage is able to drive power MOSFETs and IGBTs with a peak current capability of 800 mA source/sink. Doc ID 13794 Rev 4 L6566A Pin settings Table 1. N° 5 Pin functions (continued) Pin Function Vcc Supply voltage of both the signal part of the IC and the gate-driver. The internal high-voltage generator charges an electrolytic capacitor connected between this pin and GND (pin 3) as long as the voltage on the pin is below the turn-on threshold of the IC, after which it is disabled and the chip is turned on. The IC is disabled as the voltage on the pin falls below the UVLO threshold. This threshold is reduced at light load to counteract the natural reduction of the self-supply voltage. Sometimes a small bypass capacitor (0.1 µF typ.) to GND may be useful in order to get a clean bias voltage for the signal part of the IC. 6 Supply pin output. This pin is intended for supplying the PFC controller IC in systems comprising a PFC pre-regulator or other compatible circuitry. It is internally connected to the Vcc pin (5) via a controlled switch. The switch is closed as the IC Vcc_PFC starts up and opens when the voltage at the COMP pin is lower than a threshold (light load), whenever the IC is shut down (either latched or not) and during UVLO. If not used, the pin is left floating. 7 CS Input to the PWM comparator. The current flowing in the MOSFET is sensed through a resistor, the resulting voltage is applied to this pin and compared with an internal reference to determine MOSFET turn-off. The pin is equipped with 150 ns min. blanking time after the gate-drive output goes high for improved noise immunity. A second comparison level located at 1.5 V latches the device off and reduces its consumption in case of transformer saturation or secondary diode short-circuit. The information is latched until the voltage on the Vcc pin (5) goes below the UVLO threshold, and so resulting in intermittent operation. A logic circuit improves sensitivity to temporary disturbances. DIS IC’s latched disable input. Internally, the pin connects a comparator that, when the voltage on the pin exceeds 4.5 V, latches off the IC and brings its consumption to a lower value. The latch is cleared as the voltage on the Vcc pin (5) goes below the UVLO threshold, but the HV generator keeps the Vcc voltage high (see pin 1 description). It is then necessary to recycle the input power to restart the IC. For a quick restart, pull pin 16 (AC_OK) below the disable threshold (see pin 16 description). Bypass the pin with a capacitor to GND (pin 3) to reduce noise pickup. Ground the pin if the function is not used. COMP Control input for loop regulation. The pin is driven by the phototransistor (emittergrounded) of an optocoupler to modulate its voltage by modulating the current sunk. A capacitor placed between the pin and GND (3), as close to the IC as possible to reduce noise pick-up, sets a pole in the output-to-control transfer function. The dynamic of the pin is in the 2.5 to 5 V range. A voltage below an internally defined threshold activates burst-mode operation. The voltage at the pin is bottom-clamped at about 2 V. If the clamp is externally overridden and the voltage is pulled below 1.4 V, the IC shuts down. VREF An internal generator furnishes an accurate voltage reference (5 V ± 2%) that can be used to supply few mA to an external circuit. A small film capacitor (0.1 µF typ.), connected between this pin and GND (3), is recommended to ensure the stability of the generator and to prevent noise from affecting the reference. This reference is internally monitored by a separate auxiliary reference and any failure or drift causes the IC to latch off. 8 9 10 Doc ID 13794 Rev 4 9/52 Pin settings L6566A Table 1. N° 11 Pin functions (continued) Pin Function ZCD Transformer demagnetization sensing input for quasi-resonant operation and OVP input. The pin is externally connected to the transformer’s auxiliary winding through a resistor divider. A negative-going edge triggers MOSFET turn-on if QR mode is selected. A voltage exceeding 5 V shuts the IC down and brings its consumption to a lower value (OVP). Latch-off or auto-restart mode is selectable externally. This function is strobed and digitally filtered to increase noise immunity. Operating mode selection. If the pin is connected to the VREF pin (7) quasi-resonant operation is selected and the oscillator (pin 13, OSC) determines the maximum allowed operating frequency. Fixed-frequency operation is selected if the pin is not tied to VREF, in which case 12 MODE/SC the oscillator determines the actual operating frequency, the maximum allowed duty cycle is set at 70% min. and the pin delivers a voltage ramp synchronized to the oscillator when the gate-drive output is high; the voltage delivered is zero while the gate-drive output is low. The pin is to be connected to pin CS (7) via a resistor for slope compensation. 13 14 15 16 10/52 OSC Oscillator pin. The pin is an accurate 1 V voltage source, and a resistor connected from the pin to GND (pin 3) defines a current. This current is internally used to set the oscillator frequency that defines the maximum allowed switching frequency of the L6566A, if working in QR mode, or the operating switching frequency if working in FF mode. SS Soft-start current source. At startup, a capacitor Css between this pin and GND (pin 3) is charged with an internal current generator. During the ramp, the internal reference clamp on the current sense pin (7, CS) rises linearly starting from zero to its final value, therefore causing the duty cycle to increase progressively, starting also from zero. During soft-start the adaptive UVLO function and all functions monitoring the COMP pin are disabled. The soft-start capacitor is discharged whenever the supply voltage of the IC falls below the UVLO threshold. The same capacitor is used to delay IC shutdown (latch-off or auto-restart mode selectable) after detecting an overload condition (OLP). VFF Line voltage feedforward input. The information on the converter’s input voltage is fed into the pin through a resistor divider and is used to change the setpoint of the pulse-by-pulse current limitation (the higher the voltage, the lower the setpoint). The linear dynamics of the pin ranges from 0 to 3 V. A voltage higher than 3 V makes the IC stop switching. If feedforward is not desired, tie the pin to GND (pin 3) directly if a latch-mode OVP is not required (see pin 11, ZCD) or through a resistor if a latch-mode OVP is required. Bypass the pin with a capacitor to GND (pin 3) to reduce noise pick-up. AC_OK Brownout protection input. A voltage below 0.45 V shuts down (not latched) the IC, lowers its consumption, opens the Vcc_PFC pin (6), and clears the latch set by latched protection (DIS > 4.5 V, SS > 6.4 V, VFF > 6.4 V). IC operation is reenabled as the voltage exceeds 0.45 V. The comparator is provided with current hysteresis: an internal 15 µA current generator is ON as long as the voltage on the pin is below 0.45 V and is OFF if this value is exceeded. Bypass the pin with a capacitor to GND (pin 3) to reduce noise pick-up. Tie to Vcc with a 220 to 680 kΩ resistor if the function is not used. Doc ID 13794 Rev 4 L6566A Electrical data 3 Electrical data 3.1 Maximum rating Table 2. Absolute maximum ratings Symbol Pin VHVS 1 IHVS Value Unit Voltage range (referred to ground) -0.3 to 700 V 1 Startup current Self-limited VCC 5 IC supply voltage (Icc = 20 mA) Self-limited VVcc_PFC 6 Voltage range -0.3 to Vcc V IVcc_PFC 6 Max. source current (continuous) 30 mA -0.3 to 7 V Vmax 7, 8, 10, 14 Analog inputs and outputs Vmax 9, 15, 16 Maximum pin voltage (Ipin ≤ 1 mA) Self-limited IZCD 11 Zero current detector max. current ±5 mA VMODE/SC 12 Voltage range -0.3 to 5.3 V VOSC 13 Voltage range -0.3 to 3.3 V 0.75 W PTOT Power dissipation @TA = 50 °C TSTG Storage temperature -55 to 150 °C Junction operating temperature range -40 to 150 °C TJ 3.2 Parameter Thermal data Table 3. Symbol RthJA Thermal data Parameter Thermal resistance junction to ambient Doc ID 13794 Rev 4 Value Unit 120 °C/W 11/52 Electrical characteristics 4 L6566A Electrical characteristics (TJ = -25 to 125 °C, VCC = 12 V, CO = 1 nF; MODE/SC = VREF, RT = 20 kΩ from OSC to GND, unless otherwise specified.) Table 4. Electrical characteristics Symbol Parameter Test condition Min. Typ. Max. Unit Supply voltage Vcc VccOn VccOff Operating range after turn-on Turn-on threshold Turn-off threshold VCOMP > VCOMPL 10.6 23 VCOMP = VCOMPO 8 23 (1) (1) (1) V 13 14 15 VCOMP > VCOMPL 9.4 10 10.6 VCOMP = VCOMPO 7.2 7.6 8.0 Hys Hysteresis VCOMP > VCOMPL VZ Zener voltage Icc = 20 mA, IC disabled V V 4 23 V 25 27 V Supply current Startup current Before turn-on, Vcc = 13 V 200 250 µA Iq Quiescent current After turn-on, VZCD = VCS = 1 V 2.6 2.8 mA Icc Operating supply current MODE/SC open 4 4.6 mA Istart-up IC disabled Iqdis (2) 330 2500 Quiescent current µA IC latched off 440 500 High-voltage startup generator Breakdown voltage IHV < 100 µA 700 Start voltage IVcc < 100 µA 65 80 100 V Icharge Vcc charge current VHV > VHvstart, Vcc > 3 V 0.55 0.85 1 mA IHV, ON ON-state current IHV, OFF OFF-state leakage current VHV VHVstart VHV > VHvstart, Vcc > 3 V 1.6 VHV > VHvstart, Vcc = 0 0.8 VHV = 400 V 40 Vcc falling VCCrestart Vcc restart voltage V (1) IC latched off (1) Disabled by VCOMP < VCOMPOFF mA µA 4.4 5 5.6 12.5 13.5 14.5 9.4 10 10.6 4.95 5 5.05 V 5.1 V V Reference voltage VREF Output voltage (1) T J VREF Total variation IREF = 1 to 5 mA, Vcc = 10.6 to 23 V 12/52 = 25 °C; IREF = 1 mA Doc ID 13794 Rev 4 4.9 L6566A Table 4. Electrical characteristics Electrical characteristics (continued) Symbol IREF VOV Parameter Test condition Short-circuit current VREF = 0 Sink capability in UVLO Vcc = 6 V; Isink = 0.5 mA Overvoltage threshold Min. Typ. 10 0.2 5.3 Max. Unit 30 mA 0.5 V 5.7 V Internal oscillator fsw Oscillation frequency Operating range 10 TJ = 25 °C, VZCD = 0, MODE/SC = open 95 100 105 Vcc=12 to 23 V, VZCD = 0, MODE/SC = open 93 100 107 0.97 1 1.03 V 75 % VOSC Voltage reference (1) Dmax Maximum duty cycle MODE/SC = open, VCOMP = 5 V 300 70 kHz Brownout protection Vth IHys Voltage falling (turn-off) 0.432 0.450 0.468 V Voltage rising (turn-on) 0.452 0.485 0.518 V Vcc > 5 V, VVFF = 0.3 V 12 15 18 µA 3 3.15 3.3 V -1 µA Threshold voltage Current hysteresis (1) VAC_OK_CL Clamp level IAC_OK = 100 µA Line voltage feedforward VVFF = 0 to 3 V, VZCD < VZCDth IVFF Input bias current VVFF Linear operation range VOFF IC disable voltage VVFFlatch Kc KFF VZCD > VZCDth 3 Latch-off/clamp level Control voltage gain Feedforward gain -0.7 (3) (3) -1 mA 0 to 3 V 3.15 3.3 V VZCD > VZCDth 6.4 V VVFF = 1 V, VCOMP = 4 V 0.4 V/V VVFF = 1 V, VCOMP = 4 V 0.04 V/V Current sense comparator ICS Input bias current tLEB Leading edge blanking td(H-L) VCSx VCS = 0 150 Delay to output µA 300 ns 100 ns VCOMP = VCOMPHI, VVFF = 0 V 0.92 1 1.08 Overcurrent setpoint VCOMP = VCOMPHI, VVFF = 1.5 V 0.45 0.5 0.55 0 0.1 Hiccup-mode OCP level (1) 1.5 1.6 VCOMP = VCOMPHI, VVFF = 3.0 V VCSdis 250 -1 Doc ID 13794 Rev 4 1.4 V V 13/52 Electrical characteristics Table 4. L6566A Electrical characteristics (continued) Symbol Parameter Test condition Min. Typ. Max. Unit PWM control VCOMPHI Upper clamp voltage ICOMP = 0 5.7 V VCOMPLO Lower clamp voltage ISOURCE = -1 mA 2.0 V Linear dynamics upper limit (1) ICOMP Max. source current VCOMP = 3.3 V RCOMP Dynamic resistance VCOMP = 2.6 to 4.8 V VCOMPSH VVFF = 0 V (1) VCOMPBM Burst-mode threshold Hys Burst-mode hysteresis ICLAMPL Lower clamp capability VCOMPOFF Disable threshold (1) 4.8 5 5.2 V 320 400 480 µA 25 kΩ 2.52 2.65 2.78 2.7 2.85 3 V MODE/SC = open 20 VCOMP = 2 V -3.5 Voltage falling mV -1.5 1.4 mA V Zero current detector/overvoltage protection VZCDH Upper clamp voltage IZCD = 3 mA VZCDL Lower clamp voltage IZCD = - 3 mA Arming voltage (1) Triggering voltage (1) negative-going VZCDA VZCDT IZCD Internal pull-up 5.4 5.7 6 -0.4 positive-going edge edge V 85 100 115 mV 30 50 70 mV VCOMP < VCOMPSH VZCD < 2 V, VCOMP = VCOMPHI V -1 µA -130 -100 -70 IZCDsrc Source current capability VZCD = VZCDL -3 mA IZCDsnk Sink current capability VZCD = VZCDH 3 mA TBLANK1 Turn-on inhibit time After gate-drive going low VZCDth TBLANK2 OVP threshold OVP strobe delay 2.5 4.85 After gate-drive going low 5 µs 5.15 2 V µs Latched shutdown function IOTP Input bias current VDIS = 0 to VOTP VOTP Disable threshold (1) 4.32 4.5 -1 µA 4.68 V Thermal shutdown Vth Shutdown threshold 180 °C Hys Hysteresis 40 °C VCC_PFC function Ileak OFF-state leakage current VCOMP = 2.5 V, VVcc_PFC = 0 VVcc VVcc_PFC ON-state voltage dropout VCOMP = 4 V, I VCC_PFC = 10 mA 14/52 Doc ID 13794 Rev 4 0.15 1 µA 0.3 V L6566A Table 4. Electrical characteristics Electrical characteristics (continued) Symbol Parameter Test condition VCOMPO Level for pin 6 open and lower UVLO off threshold (COMP voltage falling) (1) (1) VCOMPL Level for pin 6 closed and higher UVLO off threshold (COMP voltage rising) Tdelay Pin 6 change of state delay Closed-to-open (1) (1) MODE/SC = open MODE/SC = open Min. Typ. Max. Unit 2.61 2.75 2.89 V 3.02 3.15 3.28 2.9 3.05 3.2 3.41 3.55 3.69 V 10 ms 3 V Mode selection/slope compensation MODEth Threshold for QR operation SCpk Ramp peak (MODE/SC = open) RS-COMP = 3 kΩ to GND, GD pin high, VCOMP = 5 V 1.7 V SCvy Ramp starting value (MODE/SC = open) RS-COMP = 3 kΩ to GND, GD pin high 0.3 V Ramp voltage (MODE/SC = open) GD pin low 0 V Source capability (MODE/SC = open) VS-COMP = VS-COMPpk 0.8 TJ = 25 °C, VSS < 2 V, VCOMP = 4 V 14 20 26 TJ = 25 °C, VSS > 2 V, VCOMP = VCOMPHi 3.5 5 6.5 Discharge current VSS > 2 V 3.5 5 6.5 High saturation voltage VCOMP = 4 V VSSDIS Disable level (1) V COMP VSSLAT Latch-off level VCOMP = VCOMPHi VGDH Output high-voltage IGDsource = 5 mA, Vcc = 12 V VGDL Output low-voltage IGDsink = 100 mA mA Soft-start ISS1 Charge current ISS2 ISSdis VSSclamp = VCOMPHi µA 2 4.85 5 µA V 5.15 V 6.4 V 11 V 0.75 V Gate driver Isourcepk Isinkpk 9.8 Output source peak current -0.6 A Output sink peak current 0.8 A tf Fall time 40 ns tr Rise time 50 ns VGDclamp Output clamp voltage IGDsource = 5 mA; Vcc = 20 V UVLO saturation Vcc = 0 to Vccon, Isink = 1 mA 10 11.3 15 V 0.9 1.1 V 1. Parameters tracking one another. 2. See Table 6 on page 41 and Table 7 on page 45. 3. The voltage feedforward block output is given by: Vcs = Kc (VCOMP − 2.5) − K FF VVFF Doc ID 13794 Rev 4 15/52 Application information 5 L6566A Application information The L6566A is a versatile peak-current-mode PWM controller specific to offline flyback converters. The device allows either fixed-frequency (FF) or quasi-resonant (QR) operation, selectable with the MODE/SC pin (12): forcing the voltage on the pin over 3 V (e.g. by tying it to the 5 V reference externally available at the VREF pin, 10) activates QR operation, otherwise the device is FF-operated. Irrespective of the operating option selected by pin 12, the device is able to work in different modes, depending on the converter's load conditions. If QR operation is selected (see Figure 4): 1. QR mode at heavy load. Quasi-resonant operation lies in synchronizing MOSFET turnon to the transformer's demagnetization by detecting the resulting negative-going edge of the voltage across any winding of the transformer. The system then works close to the boundary between discontinuous (DCM) and continuous conduction (CCM) of the transformer. As a result, the switching frequency is different for different line/load conditions (see the hyperbolic-like portion of the curves in Figure 4). Minimum turn-on losses, low EMI emission, and safe behavior in short-circuit are the main benefits of this kind of operation. 2. Valley-skipping mode at medium/light load. The externally programmable oscillator of the L6566A, synchronized to MOSFET turn-on, enables the designer to define the maximum operating frequency of the converter. As the load is reduced, MOSFET turnon no longer occurs on the first valley but on the second one, the third one, and so on. In this way the switching frequency no longer increases (piecewise linear portion in Figure 4). 3. Burst-mode with no or very light load. When the load is extremely light or disconnected, the converter enters a controlled on/off operation with constant peak current. Decreasing the load then results in frequency reduction, which can go down even to a few hundred hertz, therefore minimizing all frequency-related losses and making it easier to comply with energy saving regulations or recommendations. Having the peak current very low, no issue of audible noise arises. Figure 4. Multi-mode operation with QR option active fosc Input voltage Valley-skipping mode f sw Burst-mode Quasi-resonant mode 0 0 16/52 P in Doc ID 13794 Rev 4 Pinmax L6566A Application information If FF operation is selected: 1. FF mode from heavy to light load. The system operates exactly like a standard current mode, at a frequency fsw determined by the externally programmable oscillator: both DCM and CCM transformer operations are possible, depending on whether the power that it processes is greater or less than: Equation 1 ⎛ Vin VR ⎞ ⎜⎜ ⎟⎟ ⎝ Vin + VR ⎠ Pin T = 2 fsw Lp 2 where Vin is the input voltage to the converter, VR the reflected voltage (i.e. the regulated output voltage times the primary-to-secondary turn ratio) and Lp the inductance of the primary winding. PinT is the power level that marks the transition from continuous to discontinuous operation mode of the transformer. 2. Burst-mode with no or very light load. This kind of operation is activated in the same way and results in the same behavior as previously described for QR operation. The L6566A is specifically designed for flyback converters operated from front-end power factor correction (PFC) stages in applications in compliance with EN61000-3-2 or JEITAMITI regulations. Pin 6 (Vcc_PFC) provides the supply voltage to the PFC control IC. 5.1 High-voltage startup generator Figure 5 shows the internal schematic of the high-voltage startup generator (HV generator). It is made up of a high-voltage N-channel FET, with a gate biased by a 15 MΩ resistor, with a temperature-compensated current generator connected to its source. Figure 5. High-voltage startup generator: internal schematic HV L6566A 1 15 MΩ Vcc_OK HV_EN I HV 5 Vcc CONTROL I charge 3 GND Doc ID 13794 Rev 4 17/52 Application information L6566A With reference to the timing diagram of Figure 6, when power is first applied to the converter the voltage on the bulk capacitor (Vin) builds up and, at about 80 V, the HV generator is enabled to operate (HV_EN is pulled high) so that it draws about 1 mA. This current, minus the device’s consumption, charges the bypass capacitor connected from pin Vcc (5) to ground and causes its voltage to rise almost linearly. Figure 6. Timing diagram: normal power-up and power-down sequences Vin VHVstart regulation is lost here Vcc (pin 5) t VccON VccOFF Vccrestart t Vcc_PFC (pin 6) light load heavy load GD (pin 4) t HV_EN t Vcc_OK Icharge t 0.85 mA Power-on Normal operation Power-off t As the Vcc voltage reaches the startup threshold (14 V typ.) the low-voltage chip starts operating and the HV generator is cut off by the Vcc_OK signal asserted high. The device is powered by the energy stored in the Vcc capacitor until the self-supply circuit (typically an auxiliary winding of the transformer and a steering diode) develops a voltage high enough to sustain the operation. The residual consumption of this circuit is just the one on the 15 MΩ resistor (≈ 10 mW at 400 Vdc), typically 50-70 times lower, under the same conditions, as compared to a standard startup circuit made with external dropping resistors. At converter power-down the system loses regulation as soon as the input voltage is so low that either peak current or maximum duty cycle limitation is tripped. Vcc then drops and stops IC activity as it falls below the UVLO threshold (10 V typ.). The Vcc_OK signal is deasserted as the Vcc voltage goes below a threshold Vccrestart located at about 5 V. The HV generator can now restart. However, if Vin < Vinstart, as illustrated in Figure 6, HV_EN is deasserted too and the HV generator is disabled. This prevents converter restart attempts and ensures monotonic output voltage decay at power-down in systems where brownout protection (see Section 5.12) is not used. The low restart threshold Vccrestart ensures that, during short-circuits, the restart attempts of the device have a very low repetition rate, as shown in the timing diagram of Figure 7 on page 19, and that the converter works safely with extremely low power throughput. 18/52 Doc ID 13794 Rev 4 L6566A Application information Figure 7. Timing diagram showing short-circuit behavior (SS pin clamped at 5 V) Short circuit occurs here Vcc (pin 5) VccON Vcc OFF Vccrestart Trep GD (pin 4) t < 0.03Trep Vcc_OK t Icharge t 0.85 mA t Figure 8. Zero current detection block, triggering block, oscillator block and related logic COMP VFF 9 15 L6566A ZCD 11 RZ1 +Vin line FFWD 5.7V PWM blanking START BLANKING TIME 7 CS 4 GD RZ2 R 100 mV 50 mV + TURN-ON LOGIC MONO STABLE S Q OSCILLATOR Strobe Q DRIVER Rs Reset + - S/H 4:1 Counter FAULT 5V 13 OSC RT Doc ID 13794 Rev 4 19/52 Application information 5.2 L6566A Zero current detection and triggering block; oscillator block The zero current detection (ZCD) and triggering blocks switch on the external MOSFET if a negative-going edge falling below 50 mV is applied to the input (pin 11, ZCD). To do so the triggering block must be previously armed by a positive-going edge exceeding 100 mV. This feature is typically used to detect transformer demagnetization for QR operation, where the signal for the ZCD input is obtained from the transformer’s auxiliary winding used also to supply the L6566A. The triggering block is blanked for TBLANK = 2.5 µs after MOSFET turnoff to prevent any negative-going edge that follows leakage inductance demagnetization from triggering the ZCD circuit erroneously. The voltage at the pin is both top and bottom limited by a double clamp, as illustrated in the internal diagram of the ZCD block of Figure 8. The upper clamp is typically located at 5.7 V, while the lower clamp is located at -0.4 V. The interface between the pin and the auxiliary winding is a resistor divider. Its resistance ratio is properly chosen (see Section 5.11) and the individual resistance values (RZ1, RZ2) are such that the current sourced and sunk by the pin be within the rated capability of the internal clamps (± 3 mA). At converter power-up, when no signal is coming from the ZCD pin, the oscillator starts up the system. The oscillator is programmed externally by means of a resistor (RT) connected from pin OSC (13) to ground. With good approximation the oscillation frequency fosc is: Equation 2 fosc ≈ 2 ⋅ 10 3 RT (with fosc in kHz and RT in kW). As the device is turned on, the oscillator starts immediately; at the end of the first oscillator cycle, the voltage on the ZCD pin being zero, the MOSFET is turned on, therefore starting the first switching cycle right at the beginning of the second oscillator cycle. At any switching cycle, the MOSFET is turned off as the voltage on the current sense pin (CS, 7) hits an internal reference set by the line feedforward block, and the transformer starts demagnetization. If this completes (so a negative-going edge appears on the ZCD pin) after a time exceeding one oscillation period Tosc=1/fosc from the previous turnon, the MOSFET is turned on again - with some delay to ensure minimum voltage at turn-on – and the oscillator ramp is reset. If, instead, the negative-going edge appears before Tosc has elapsed, it is ignored and only the first negative-going edge after Tosc turns on the MOSFET and synchronizes the oscillator. In this way one or more drain ringing cycles are skipped (“valley-skipping mode”, Figure 9) and the switching frequency is prevented from exceeding fosc. Figure 9. Drain ringing cycle skipping as the load is gradually reduced VDS VDS VDS t TON TFW Tosc Pin = Pin' (limit condition) 20/52 t t TV Tosc Tosc Pin = Pin'' < Pin' Doc ID 13794 Rev 4 Pin = Pin''' < P in'' L6566A Note: Application information When the system operates in valley skipping-mode, uneven switching cycles may be observed under some line/load conditions, due to the fact that the OFF-time of the MOSFET is allowed to change with discrete steps of one ringing cycle, while the OFF-time needed for cycle-by-cycle energy balance may fall in between. Therefore one or more longer switching cycles is compensated by one or more shorter cycles, and vice versa. However, this mechanism is absolutely normal and there is no appreciable effect on the performance of the converter or on its output voltage. If the MOSFET is enabled to turn on but the amplitude of the signal on the ZCD pin is smaller than the arming threshold for some reason (e.g. a heavy damping of drain oscillations, like in some single-stage PFC topologies, or when a turn-off snubber is used), MOSFET turn-on cannot be triggered. This case is identical to what happens at startup: at the end of the next oscillator cycle the MOSFET is turned on, and a new switching cycle takes place after skipping no more than one oscillator cycle. The operation described so far does not consider the blanking time TBLANK after MOSFET turn-off, and actually TBLANK does not come into play as long as the following condition is met: Equation 3 D ≤ 1− TBLANK Tosc where D is the MOSFET duty cycle. If this condition is not met, nothing changes substantially: the time during which MOSFET turn-on is inhibited is extended beyond Tosc by a fraction of TBLANK. As a consequence, the maximum switching frequency is a little lower than the programmed value fosc and valley-skipping mode may take place slightly earlier than expected. However this is quite unusual: setting fosc = 150 kHz, the phenomenon can be observed at duty cycles higher than 60%. See Section 5.11 for further implications of TBLANK. If the voltage on the COMP pin (9) saturates high, which reveals an open control loop, an internal pull-up keeps the ZCD pin close to 2 V during MOSFET OFF-time to prevent noise from false triggering the detection block. When this pull-up is active, the ZCD pin may not be able to go below the triggering threshold, which would stop the converter. To allow autorestart operation, while ensuring minimum operating frequency in these conditions, the oscillator frequency that retriggers MOSFET turn-on is that of the external oscillator divided by 128. Additionally, to prevent malfunction at converter startup, the pull-up is disabled during the initial soft-start (see Section 5.10). However, to ensure a correct startup, at the end of the soft-start phase, the output voltage of the converter must meet the condition: Equation 4 Vout > Ns R Z1 I ZCD Naux where Ns is the turn number of the secondary winding, Naux the turn number of the auxiliary winding, and IZCD the maximum pull-up current (130 μA). Doc ID 13794 Rev 4 21/52 Application information L6566A The operation described so far under different operating conditions for the converter is illustrated in the timing diagrams of Figure 10. If the FF option is selected, the operation is exactly equal to that of a standard current-mode PWM controller. It works at a frequency fsw = fosc; both DCM and CCM transformer operations are possible, depending on the operating conditions (input voltage and output load) and on the design of the power stage. The MOSFET is turned on at the beginning of each oscillator cycle and is turned off as the voltage on the current sense pin reaches an internal reference set by the line feedforward block. The maximum duty cycle is limited at 70% minimum. The signal on the ZCD pin in this case is used only for detecting feedback loop failures (see Section 5.11). Figure 10. Operation of ZCD, triggering and oscillator blocks (QR option active) ZCD (pin 11) ZCD (pin 11) ZCD (pin 11) 100 mV 100 mV 50 mV 100 mV 50 mV 50 mV Oscillator ramp Oscillator ramp Oscillator ramp ZCD blanking time ZCD blanking time ZCD blanking time Arm/Trigger Arm/Trigger Arm/Trigger ON-enable ON-enable ON-enable PWM latch Set PWM latch Set PWM latch Set PWM latch Reset PWM latch Reset PWM latch Reset GD (pin 4) GD (pin 4) GD (pin 4) armed trigger a) full load 22/52 b) light load Doc ID 13794 Rev 4 c) start-up L6566A 5.3 Application information Burst-mode operation at no load or very light load When the voltage at the COMP pin (9) falls 20 mV below a threshold fixed internally at a value, VCOMPBM, depending on the selected operating mode, the L6566A is disabled with the MOSFET kept in OFF-state and its consumption reduced at a lower value to minimize Vcc capacitor discharge. The control voltage now increases as a result of the feedback reaction to the energy delivery stop (the output voltage is slowly decaying), the threshold is exceeded and the device restarts switching again. In this way the converter works in burst-mode with a nearly constant peak current defined by the internal disable level. A load decreases and then causes a frequency reduction, which can go down even to a few hundred hertz, therefore minimizing all frequency-related losses and making it easier to comply with energy saving regulations. This kind of operation, shown in the timing diagrams of Figure 11 along with the others previously described, is noise-free since the peak current is low. If it is necessary to decrease the intervention threshold of the burst-mode operation, this can be done by adding a small DC offset on the current sense pin as shown in Figure 12. Note: The offset reduces the available dynamics of the current signal; thereby, the value of the sense resistor must be determined taking this offset into account. Figure 11. Load-dependent operating modes: timing diagrams COMP (pin 9) 20 mV hyster. VCOMPBM t fosc MODE/SC=Open fsw MODE/SC=VREF t GD (pin 4) MODE/SC=Open MODE/SC=VREF FF Mode QR Mode Burst-mode Burst-mode FF Mode t QR Mode Valley-skipping Mode Doc ID 13794 Rev 4 23/52 Application information L6566A Figure 12. Addition of an offset to the current sense lowers the burst-mode operation threshold Vcso = Vref R R + Rc Vref 10 4 Rc L6566A R 7 3 Rs 5.4 Adaptive UVLO A major problem when optimizing a converter for minimum no-load consumption is that the voltage generated by the auxiliary winding under these conditions falls considerably as compared even to few mA load. This very often causes the supply voltage Vcc of the control IC to drop and go below the UVLO threshold so that the operation becomes intermittent, which is undesired. Furthermore, this must be traded off against the need of generating a voltage not exceeding the maximum allowed by the control IC at full load. To help the designer overcome this problem, the device, besides reducing its own consumption during burst-mode operation, also features a proprietary adaptive UVLO function. It consists of shifting the UVLO threshold downwards at light load, namely when the voltage at the COMP pin falls below a threshold VCOMPO internally fixed (see Section 5.8), so as to have more headroom. To prevent any malfunction during transients from minimum to maximum load, the normal (higher) UVLO threshold is re-established when the voltage at the COMP pin exceeds VCOMPL (see Section 5.8) and Vcc has exceeded the normal UVLO threshold (see Figure 13). The normal UVLO threshold ensures that at full load the MOSFET is driven with a proper gate-to-source voltage. Figure 13. Adaptive UVLO block VCOMP (pin 9) Vcc_PFC Vcc 6 V C OMPL V C OMPO 5 Vcc_PFC logic + Vcc (pin 5) COMP t R 9 - UVLO Q Vcc OFF1 Vcc OFF2 + S + SW VCOMPL VCOMPO - VccOFF1 t Q VccOFF2 (*) L6566A Vcc_PFC (pin 6) t Tdelay (*) VccOFF2 < VccOFF1 is selected when Q is high t 24/52 Doc ID 13794 Rev 4 L6566A 5.5 Application information PWM control block The device is specific to secondary feedback. Typically, there is a TL431 on the secondary side and an optocoupler that transfers output voltage information to the PWM control on the primary side, crossing the isolation barrier. The PWM control input (pin 9, COMP) is driven directly by the phototransistor’s collector (the emitter is grounded to GND) to modulate the duty cycle (Figure 14, left-hand side circuit). In applications where a tight output regulation is not required, it is possible to use a primarysensing feedback technique. In this approach the voltage generated by the self-supply winding is sensed and regulated. This solution, shown in Figure 14, right-hand side circuit, is cheaper because no optocoupler or secondary reference is needed, but output voltage regulation, especially as a result of load changes, is quite poor. Ideally, the voltage generated by the self-supply winding and the output voltage should be related by the Naux/Ns turn ratio only. In fact, numerous non-idealities, mainly transformer parasitics, cause the actual ratio to deviate from the ideal one. Line regulation is quite good, in the range of ± 2%, whereas load regulation is about ± 5% and output voltage tolerance is in the range of ±10%. The dynamic of the pin is in the 2.5 to 5 V range. The voltage at the pin is clamped downwards at about 2 V. If the clamp is externally overridden and the voltage on the pin is pulled below 1.4 V, the L6566A shuts down. This condition is latched as long as the device is supplied. While the device is disabled, however, no energy is coming from the self-supply circuit, therefore the voltage on the Vcc capacitor decays and crosses the UVLO threshold after some time, which clears the latch and lets the HV generator restart. This function is intended for an externally controlled burst-mode operation at light load with a reduced output voltage, a technique typically used in multi-output SMPS, such as those for CRT TVs or monitors (see the timing diagram Figure 15). Figure 14. Possible feedback configurations that can be used with the L6566A Vout L6566A 5 Vcc L6566A 9 Cs 9 COMP Naux COMP TL431 Secondary feedback Primary feedback Doc ID 13794 Rev 4 25/52 Application information L6566A Figure 15. Externally controlled burst-mode operation by driving the COMP pin: timing diagram Vcc (pin 5) VccON Standby is commanded here VccOFF Vcc restart COMP (pin 9) t GD (pin 4) t Vcc_OK t Icharge t 0.85 mA Vcc_PFC (pin 6) t Vout t t 5.6 PWM comparator, PWM latch and voltage feedforward blocks The PWM comparator senses the voltage across the current sense resistor Rs and, by comparing it to the programming signal delivered by the feedforward block, determines the exact instant when the external MOSFET must be switched off. Its output resets the PWM latch, previously set by the oscillator or the ZCD triggering block, which asserts the gatedriver output low. The use of PWM latch avoids spurious switching of the MOSFET that may result from the noise generated (“double-pulse suppression”). Cycle-by-cycle current limitation is realized with a second comparator (OCP comparator) that also senses the voltage across the current sense resistor Rs and compares this voltage to a reference value VCSX. Its output is OR-ed with that of the PWM comparator (see the circuit schematic in Figure 17). In this way, if the programming signal delivered by the feedforward block and sent to the PWM comparator exceeds VCSX, it is the OCP comparator that first resets the PWM latch instead of the PWM comparator. The value of Vcsx, thereby, determines the overcurrent setpoint along with the sense resistor Rs. The power that QR flyback converters with a fixed overcurrent setpoint (like fixed-frequency systems) are able to deliver changes considerably with the input voltage. Obviously, this is not a problem if the flyback converter runs off a fixed voltage bus generated by the PFC preregulator; however, with a tracking boost PFC (a “boost follower” PFC), the regulated output voltage at maximum mains voltage can be even twice the value at minimum mains voltage. In this case the issue remains, although it is not as great as without PFC and wide-range mains. With a 1: 2 voltage change, the maximum transferable power at maximum line can 26/52 Doc ID 13794 Rev 4 L6566A Application information be 50% higher than at minimum line, as shown by the upper curve in the diagram of Figure 16. The L6566A has the line feedforward function available to solve this issue. Figure 16. Typical power capability change vs. input voltage in QR flyback converters 2.5 k=0 system not compensated Pinlim @ Vin Pinlim @ Vinmin 2 k 1.5 1 system optimally compensated k = kopt 0.5 1 1.5 2 2.5 3 3.5 4 Vin Vinmin It acts on the overcurrent setpoint Vcsx, so that it is a function of the converter’s input voltage Vin (output of the PFC pre-regulator) sensed through a dedicated pin (15, VFF): the higher the input voltage, the lower the setpoint. This is illustrated in the diagram on the left-hand side of Figure 17: it shows the relationship between the voltage on the VFF and Vcsx pin (with the error amplifier saturated high in an attempt to maintain the output voltage regulation): Equation 5 Vcsx = 1 − Note: VVFF k = 1 − Vin 3 3 If the voltage on the pin exceeds 3 V, switching ceases but the soft-start capacitor is not discharged. The schematic in Figure 17 also shows how the function is included in the control loop. With a proper selection of the external divider R1-R2, i.e. of the ratio k = R2 / (R1+R2), it is possible to achieve the optimum compensation described by the lower curve in the diagram of Figure 16. The optimum value of k, kopt, which minimizes the power capability variation over the input voltage range, is the one that provides equal power capability at the extremes of the range. The exact calculation is complex, and non-idealities shift the real-world optimum value from the theoretical one. It is therefore more practical to provide a first cut value, easily calculated, and then to fine-tune experimentally. Assuming that the system operates exactly at the boundary between DCM and CCM, and neglecting propagation delays, the following expression for kopt can be found: Doc ID 13794 Rev 4 27/52 Application information L6566A Equation 6 k opt = 3 ⋅ VR Vin min ⋅ Vin max + (Vin min + Vin max ) ⋅ VR Experience shows that this value is typically lower than the real one. Once the maximum peak primary current, IPKpmax, occurring at minimum input voltage Vinmin has been found, the value of Rs can be determined from (2): Equation 7 Rs = k opt 1− 3 Vin min IPKp max The converter is then bench tested to find the output power level Poutlim where regulation is lost (because overcurrent is being tripped) both at Vin = Vinmin and Vin = Vinmax. Figure 17. Left: overcurrent setpoint vs. VFF voltage; right: line feedforward function block PFC Output Bus Vcsx [V] To PFC's OV sensing 1.2 R1A Optional for OVP settings VCOMP = Upper clamp 1 R1B 0.8 R2 Rs VFF CS 15 7 VOLTAGE FEED FORWARD COMP 0.2 9 PWM - 0.4 + 0.6 Q + DRIVER S GD 0.5 1 1.5 2 VVFF [V] 2.5 3 3.5 Clock/ZCD Hiccup L6566A 1.5 V DISABLE - 0 Vcsx + 0 4 R OCP If Poutlim @ Vinmax > Poutlim @ Vinmin the system is still undercompensated and k needs to increase; if Poutlim @ Vinmax < Poutlim @ Vinmin the system is overcompensated and k needs to decrease. This continues until the difference between the two values is acceptably low. Once the true kopt is found in this way, it is possible that Poutlim turns out slightly different from the target; to correct this, the sense resistor Rs needs adjusting and the above tuning process is repeated with the new Rs value. Typically, a satisfactory setting is achieved in no more than a couple of iterations. In applications where this function is not wanted, e.g. because the PFC stage regulates at a fixed voltage, the VFF pin can be simply grounded, directly or through a resistor, depending on whether one wants the OVP function to be auto-restart or latched mode (see Section 5.11). The overcurrent setpoint is then fixed at the maximum value of 1 V. If a lower setpoint is desired to reduce the power dissipation on Rs, the pin can be also biased at a fixed voltage using a divider from VREF (pin 10). 28/52 Doc ID 13794 Rev 4 L6566A Application information If the FF option is selected, the line feedforward function can be still used to compensate for the total propagation delay Td of the current sense chain (internal propagation delay td(H-L) plus the turn-off delay of the external MOSFET), which in standard current mode PWM controllers is done by adding an offset on the current sense pin proportional to the input voltage. In that case, the divider ratio k, which is much smaller when compared to that used with the QR option selected, can be calculated with the following equation: Equation 8 k opt = 3 Td Rs Lp where Lp is the inductance of the primary winding. In case a constant maximum power capability vs. the input voltage is not required, the VFF pin can be grounded, directly or through a resistor (see Section 5.11), therefore fixing the overcurrent setpoint at 1 V, or biased at a fixed voltage through a divider from VREF to get a lower setpoint. It is possible to bypass the pin to ground with a small film capacitor (e.g. 1-10 nF) to ensure a clean operation of the IC even in a noisy environment. The pin is internally forced to ground during UVLO, after activating any latched protection and when the COMP pin is pulled below its low clamp voltage (see Section 5.5). 5.7 Hiccup-mode OCP A third comparator senses the voltage on the current sense input and shuts down the device if the voltage on the pin exceeds 1.5 V, a level well above that of the maximum overcurrent setpoint (1 V). Such an anomalous condition is typically generated by either a short-circuit of the secondary rectifier or a shorted secondary winding, or a hard-saturated flyback transformer. To distinguish an actual malfunction from a disturbance (e.g. induced during ESD tests), the first time the comparator is tripped, the protection circuit enters a “warning state”. If, in the next switching cycle, the comparator is not tripped, a temporary disturbance is assumed and the protection logic is reset in its idle state; if the comparator is tripped again a real malfunction is assumed and the L6566A is stopped. Depending on the time relationship between the detected event and the oscillator, occasionally the device may stop after the third detection. This condition is latched as long as the device is supplied. While it is disabled, however, no energy is coming from the self-supply circuit; so the voltage on the Vcc capacitor decays and crosses the UVLO threshold after some time, which clears the latch. If the internal startup generator is still off, then the Vcc voltage still needs to go below its restart voltage before the Vcc capacitor is charged again and the device restarted. Ultimately, this results in a low-frequency intermittent operation (hiccup-mode operation), with very low stress on the power circuit. This special condition is illustrated in the timing diagram of Figure 18. Doc ID 13794 Rev 4 29/52 Application information L6566A Figure 18. Hiccup-mode OCP: timing diagram Vcc (pin 5) Secondary diode is shorted here Vcc ON Vcc OFF Vcc restart VCS (pin 7) t 1.5 V t GD (pin 4) OCP latch t Vcc_OK t Vcc_PFC (pin 6) t t 5.8 PFC interface The device is specifically designed to minimize converter losses under light or no-load conditions, and a special function has been provided to help the designer meet energy saving requirements even in power-factor-corrected systems where a PFC pre-regulator precedes the isolated DC-DC converter. In fact, EMC regulations require compliance with low-frequency harmonic emission limits at nominal load; no limit is envisaged when the converter operates with a light load. Then the PFC pre-regulator can be turned off, therefore saving the no-load consumption of this stage (0.5÷1 W). To do so, the L6566A provides the Vcc_PFC pin (6): this pin is internally connected to the Vcc pin (5) via a PNP transistor, normally closed, that opens when the voltage VCOMP falls below VCOMPO, a threshold internally set at a value depending on whether QR operation or FF operation is selected. This pin is intended for supplying the PFC controller of the preregulator as shown in Figure 16. The switch is thermally protected, so that the IC stops if an external failure causes the pin to be overloaded for too long a time or shorted to ground. 30/52 Doc ID 13794 Rev 4 L6566A Application information Figure 19. Possible interfaces between the L6566A and a PFC controller Vcc Vcc 5 6 L6561 L6562 L6563 Vcc_PFC L6566A 22 kΩ Vcc 5 6 Vcc_PFC L6566A 4.7kΩ RUN 10 L6563 To prevent intermittent operation of the PFC stage, some hysteresis is provided: if the internal switch is open, it is closed (which re-enables the PFC pre-regulator) when VCOMP exceeds VCOMPL > VCOMPO. Additionally, to reject VCOMP undershoots during transients, VCOMP must stay below VCOMPO for more than 1024 oscillator cycles in order for the Vcc_PFC pin to open. Entering burst-mode (VCOMP < VCOMPBM) opens Vcc_PFC immediately. Besides pin 6 going open, when VCOMP falls below VCOMPO the UVLO threshold is set 2.4 V below to compensate for the drop of the voltage delivered by the self-supply circuit that occurs at light load (see Section 5.4). 5.9 Latched disable function The device is equipped with a comparator having the non-inverting input externally available at the DIS pin (8) and with the inverting input internally referenced to 4.5 V. As the voltage on the pin exceeds the internal threshold, the device is immediately shut down and its consumption reduced to a low value. The information is latched and it is necessary to let the voltage on the Vcc pin go below the UVLO threshold to reset the latch and restart the device. To keep the latch supplied as long as the converter is connected to the input source, the HV generator is activated periodically so that Vcc oscillates between the startup threshold VccON and VccON - 0.5 V. Activating the HV generator in this way cuts its power dissipation approximately by three (as compared to the case of continuous conduction) and keeps peak silicon temperature close to the average value. To let the L6566A restart it is then necessary to disconnect the converter from the input source. Pulling pin 16 (AC_OK) below the disable threshold (see Section 5.12) stops the HV generator until Vcc falls below Vccrestart, so that the latch can be cleared and a quicker restart is allowed as the input source is removed. This operation is shown in the timing diagram of Figure 20. This function is useful to easily implement a latched overtemperature protection by biasing the pin with a divider from VREF, where the upper resistor is an NTC physically located close to a heating element like the MOSFET, or the transformer. The DIS pin is a highimpedance input, it is therefore prone to pick-up noise, which might give origin to undesired latch-off of the device. It is possible to bypass the pin to ground with a small film capacitor (e.g. 1-10 nF) to prevent any malfunctioning of this kind. Doc ID 13794 Rev 4 31/52 Application information L6566A Figure 20. Operation after latched disable activation: timing diagram DIS (pin 8) 4.5V Vcc (pin 5) HV generator is turned on Restart is quicker t Vcc ON Vcc ON -0.5 VccOFF Disable latch is reset here Vcc restart GD (pin 4) HV generator turn-on is disabled here t t Vcc_PFC (pin 6) Input source is removed here Vin t VHVstart t AC_OK (pin 16) Vth t 5.10 Soft-start and delayed latched shutdown upon overcurrent At device startup, a capacitor (Css) connected between the SS pin (14) and ground is charged by an internal current generator, ISS1, from zero up to about 2 V where it is clamped. During this ramp, the overcurrent setpoint progressively rises from zero to the value imposed by the voltage on the VFF pin 15, (see Section 5.6); MOSFET conduction time increases gradually, therefore controlling the startup inrush current. The time needed for the overcurrent setpoint to reach its steady-state value, referred to as soft-start time, is approximately: Equation 9 TSS = V ⎞ Css ⎛ Css ⎜1 − VFF ⎟⎟ Vcsx (VVFF ) = 3 ⎠ I SS1 ⎜⎝ I SS1 During the ramp (i.e. until VSS = 2 V) all the functions that monitor the voltage on the COMP pin are disabled. The soft-start pin is also invoked whenever the control voltage (COMP) saturates high, which reveals an open-loop condition for the feedback system. This condition very often occurs at startup, but may be also caused by either a control loop failure or a converter overload/short-circuit. A control loop failure results in an output overvoltage that is handled by the OVP function of the L6566A (see Section 5.11). In the case of QR operation, a shortcircuit causes the converter to run at a very low frequency, then with very low power capability. This causes the self-supply system that powers the device to switch off, so that 32/52 Doc ID 13794 Rev 4 L6566A Application information the converter works intermittently, which is very safe. In case of overload the system has a power capability lower than that at nominal load but the output current may be quite high and overstressing the output rectifier. In the case of FF operation the capability is almost unchanged and both short-circuit and overload conditions are more critical to handle. The L6566A, regardless of the operating option selected, makes it easier to handle such conditions: the 2 V clamp on the SS pin is removed and a second internal current generator ISS2 = ISS1 /4 keeps on charging Css. As the voltage reaches 5 V, the device is disabled, if it is allowed to reach 2 VBE over 5 V, the device is latched off. In the former case the resulting behavior is identical to that under short-circuit illustrated in Figure 6; in the latter case the result is identical to that of Figure 20. See Section 5.9 for additional details. A diode, with the anode to the SS pin and the cathode connected to the VREF pin (10) is the simplest way to select either auto-restart mode or latch-mode behavior upon overcurrent. If the overload disappears before the Css voltage reaches 5 V, the ISS2 generator is turned off and the voltage gradually brought back down to 2 V. Refer to Section 6 (Figure 7) for additional hints. If latch-mode behavior is desired also for converter short-circuit, make sure that the supply voltage of the device does not fall below the UVLO threshold before activating the latch. Figure 21 shows soft-start pin behavior under different operating conditions and with different settings (latch-mode or auto-restart). Figure 21. Soft-start pin operation under different operating conditions and settings Vcc (pin 5) UVLO Vcc falls below UVLO before latching off SS (pin 14) t 5V+2Vbe 5V here the IC shuts down 2V COMP (pin 9) here the IC latches off t GD (pin 4) t Vcc_PFC (pin 6) t START-UP Note: NORMAL OPERATION TEMPORARY OVERLOAD NORMAL OPERATION OVERLOAD SHUTDOWN RESTART t LATCHED AUTORESTART Unlike other PWM controllers provided with a soft-start pin, in the L6566A, grounding the SS pin does not guarantee that the gate-driver is disabled. Doc ID 13794 Rev 4 33/52 Application information 5.11 L6566A OVP block The OVP function of the L6566A monitors the voltage on the ZCD pin (11) in the MOSFET OFF-time, during which the voltage generated by the auxiliary winding tracks the converter output voltage. If the voltage on the pin exceeds an internal 5 V reference, a comparator is triggered, an overvoltage condition is assumed and the device is shut down. An internal current generator is activated that sources 1 mA out of the VFF pin (15). If the VFF voltage is allowed to reach 2 Vbe over 5 V, the L6566A is latched off. See Section 5.9 for more details on the IC’s behavior under these conditions. If the impedance externally connected to pin 15 is so low that the 5+2 VBE threshold cannot be reached or if some means is provided to prevent that, the device is able to restart after the Vcc has dropped below 5 V. Refer to Section 6 (Table 7) for additional hints. Figure 22. OVP function: internal block diagram ZCD 11 to triggering block L6566A 5V - 40kΩ + PWM latch R Q S Q COUT 5pF OVP Monostable M1 Monostable M2 2 µs 2-bit counter STROBE 0.5 µs FF Fault Counter reset R Q1 S Figure 23. OVP function: timing diagram GD (pin 4) t Vaux 0 ZCD (pin 11) t 5V t COUT 2 µs STROBE t 0.5 µs t OVP t COUNTER RESET COUNTER STATUS t 0 0 0 0 →1 1 →2 2 →0 0 0 →1 1 →2 2 →3 FAULT t Vcc_PFC (pin 6) t NORMAL OPERATION 34/52 3 →4 TEMPORARY DISTURBANCE Doc ID 13794 Rev 4 FEEDBACK LOOP FAILURE t L6566A Application information The ZCD pin is connected to the auxiliary winding through a resistor divider RZ1, RZ2 (see Figure 8). The divider ratio kOVP = RZ2 / (RZ1 + RZ2) is chosen equal to: Equation 10 k OVP = 5 Ns Vout OVP Naux where VoutOVP is the output voltage value that is to activate the protection, Ns is the turn number of the secondary winding and Naux is the turn number of the auxiliary winding. The value of RZ1 is such that the current sourced by the ZCD pin be within the rated capability of the internal clamp: Equation 11 R Z1 ≥ 1 3 ⋅ 10 −3 Naux Vin max Np where Vinmax is the maximum DC input voltage and Ns the turn number of the primary winding. See Section 5.2 for additional details. To reduce sensitivity to noise and prevent the latch from being erroneously activated, first the OVP comparator is active only for a small time window (typically, 0.5 µs), starting 2 µs after MOSFET turn-off, to reject the voltage spike associated to the positive-going edges of the voltage across the auxiliary winding Vaux; secondly, to stop the L6566A, the OVP comparator must be triggered for four consecutive switching cycles. A counter, which is reset every time the OVP comparator is not triggered in one switching cycle, is provided for this purpose. Figure 22 shows the internal block diagram, while the timing diagrams in Figure 23 illustrate the operation. Note: To use the OVP function effectively, i.e. to ensure that the OVP comparator is always interrogated during MOSFET OFF-time, the duty cycle D under open-loop conditions must fulfill the following inequality: Equation 12 D + TBLANK 2 fsw ≤ 1 where TBLANK2 = 2 µs; this is also illustrated in the diagram of Figure 24. Doc ID 13794 Rev 4 35/52 Application information L6566A Figure 24. Maximum allowed duty cycle vs. switching frequency for correct OVP detection 0.8 0.725 0.7 0.6 Dmax 0.5 0.4 0.3 0.2 5 .10 4 1 . 10 5 1.5 .10 5 2 . 10 5 2.5 .10 fsw [Hz] 36/52 Doc ID 13794 Rev 4 5 3 .10 5 3.5 .10 5 4 . 10 5 L6566A 5.12 Application information Brownout protection Brownout protection is basically a not-latched device shutdown function activated when a condition of mains undervoltage is detected. There are several reasons why it may be desirable to shut down a converter during a brownout condition, which occurs when the mains voltage falls below the minimum specification of normal operation. Firstly, a brownout condition may cause overheating of the PFC front-end due to an excess of RMS current. Secondly, brownout can also cause the PFC pre-regulator to work open loop. This could be dangerous to the PFC itself and the downstream converter, should the input voltage return abruptly to its rated value, given the slow response of PFC to transient events. Finally, spurious restarts may occur during converter power-down, therefore causing the output voltage not to decay to zero monotonically. The L6566A shutdown upon brownout is accomplished by means of an internal comparator, as shown in the block diagram of Figure 25, which shows the basic circuit usage. The inverting input of the comparator, available on the AC_OK pin (16), is supposed to sense a voltage proportional to either the RMS or the peak mains voltage; the non-inverting input is internally referenced to 0.485 V with 35 mV hysteresis. If the voltage applied on the AC_OK pin before the device starts operating does not exceed 0.485 V or if it falls below 0.45 V while the device is running, The AC_OK signal goes high, the Vcc_PFC pin is open and the device shuts down, with the soft-start capacitor discharged and the gate-drive output low. Additionally, in case the device has been latched off by some protection function (in which case Vcc is oscillating between VccON and VccON - 0.5 V), the AC_OK voltage falling below 0.45 V clears the latch. This feature can be used to allow a quicker restart as the input source is removed. Figure 25. Brownout protection: internal block diagram and timing diagram Sensed voltage VsenON VsenOFF VAC_OK (pin 16) t 0.485V 0.45V Sensed voltage t AC_FAIL Vcc IHYS 5 L6566A t 15 µA RH AC_OK 16 15 µA 0.485V 0.45V Vcc (pin 5) AC_FAIL t + RL GD (pin 4) t t Vout Vcc_PFC (pin 6) t t Doc ID 13794 Rev 4 37/52 Application information L6566A While the brownout protection is active the startup generator keeps on working but, there being no PWM activity, the Vcc voltage continuously oscillates between the startup and the HV generator restart thresholds, as shown in the timing diagram of Figure 25. The brownout comparator is provided with current hysteresis in addition to voltage hysteresis: an internal 15 µA current sink is ON as long as the voltage applied on the AC_OK pin is such that the AC_FAIL signal is high. This approach provides an additional degree of freedom: it is possible to set the ON threshold and the OFF threshold separately by properly choosing the resistors of the external divider (see Equation 13 and 14 below). With just voltage hysteresis, instead, fixing one threshold automatically fixes the other one depending on the built-in hysteresis of the comparator. With reference to Figure 25, the following relationships can be established for the ON (VsenON) and OFF (VsenOFF) thresholds of the sensed voltage: Equation 13 Vsen ON − 0.485 0.485 = 15 ⋅ 10 − 6 + RH RL Vsen OFF − 0.45 0.45 = RH RL which, solved for RH and RL, yield: Equation 14 RH = Vsen ON − 1.078 ⋅ Vsen OFF 15 ⋅ 10 −6 RL = RH ; 0.45 Vsen OFF − 0.45 Figure 26. AC voltage sensing with the L6566A Rectified input voltage For minimum temperature drift Q L6561 L6562/A L6563 Sensed voltage: Vsen < 7V 5 CF MULT RH 3 Q Vcc L6566A AC_OK 16 RL It is usually convenient to not use additional dividers connected to high-voltage rails because this could make it difficult to meet no-load consumption targets envisaged by energy-saving regulations. Figure 26 shows a simple voltage sensing technique that makes use of the divider already used by the PFC control chip to sense the AC mains voltage with just the addition of an extra tap. The small-signal NPN Q and the capacitor CF create a peak detector, so that the information of the RMS mains voltage can be found across CF. The tap position determines the DC voltage to be sensed by the AC_OK pin. It is convenient to use a level as high as possible to minimize the effect of VBE changes with temperature. However, it may be necessary to limit the maximum sensed voltage below 7 V to prevent Q’s emitter reverse breakdown; it would not be destructive because the reverse current would be quite small (the resistors seen by 38/52 Doc ID 13794 Rev 4 L6566A Application information the base terminal are several ten kW) but this could distort the signal on the MULT pin of the PFC chip and adversely affect the operation of the pre-regulator. CF needs to be quite a big capacitor (in the μF) to have small residual ripple superimposed on the DC level; as a ruleof-thumb, use a time constant (RL + RH)·CF at least 4-5 times the maximum line cycle period, then fine-tune if needed, considering also transient conditions such as mains missing cycles. If temperature effects are critical, the NPN Q can be replaced by a PNP-NPN pair arranged as shown in Figure 26 on the right-hand side; other sensing techniques may also be adopted. The voltage on the pin is clamped upwards at about 3.15 V; then, if the function is not used, the pin must be connected to Vcc through a resistor (220 to 680 kΩ). 5.13 Slope compensation The MODE/SC pin (12), when not connected to VREF, provides a voltage ramp during MOSFET ON-time synchronous to that of the internal oscillator sawtooth, with 0.8 mA minimum current capability. This ramp is intended for implementing additive slope compensation on current sense. This is needed to avoid the sub-harmonic oscillation that arises in all peak-current-mode-controlled converters working at fixed frequency in continuous conduction mode with a duty cycle close to or exceeding 50%. Figure 27. Slope compensation waveforms Internal oscillator GD (pin 4) t MODE/SC (pin 12) t t The compensation is realized by connecting a programming resistor between this pin and the current sense input (pin 7, CS). The CS pin must be connected to the sense resistor with another resistor to make a summing node on the pin. Since no ramp is delivered during MOSFET OFF-time (see Figure 27), no external component other than the programming resistor is needed to ensure a clean operation at light loads. Note: The addition of the slope compensation ramp reduces the available dynamics of the current signal; therefore, the value of the sense resistor must be determined taking this into account. Note also that the burst-mode threshold (in terms of power) changes slightly. If slope compensation is not required with FF operation, the pin is left floating. Doc ID 13794 Rev 4 39/52 Application information 5.14 L6566A Summary of L6566A power management functions It has been seen that the device is provided with a number of power management functions: multiple operating mode upon loading conditions, protection functions, as well as interaction with the PFC pre-regulator. To help the user familiarize themselves with these functions, in the following tables all of the themes are summarized with their respective activation mechanisms and the resulting status of the most important pins. This may be useful not only for the correct use of the IC but also for diagnostic purposes: especially at the prototyping/debugging stage, it is quite common to bump into unwanted activation of some functions, and the following tables can be used as a sort of quick troubleshooting guide. Table 5. L6566A light load management features Feature Description Burst mode IC Caused by behavior Controlled ON-OFF VCOMP operation for Pulse< low power skipping VCOMPB consumptio operation M - Hys n at light load PFC OFF at PFC light load, manage ON at heavy ment load VCOMP < VCOMP VCC_PFC =0 Vcc_restar Consump. VREF t (Iqdis,mA) (V) (V) N.A. 1.34 mA N.A. VCOMP OSC (V) (V) VCOMPBM -HYS to VCOMPBM 0/1 0 1 0 5 Unchang ed 5 Unchang unchange ed d FMOD O VCOMP VCC_PFC < = VCC VCOMPL 40/52 SS VCC Doc ID 13794 Rev 4 L6566A protection Protection OVP Doc ID 13794 Rev 4 OLP Short-circuit protection Description Output overvoltage protection Output overload protection Output shortcircuit protection Transformer saturation or shorted secondary diode protection Caused by IC behavior Vcc restart IC Iq (V) (mA) (V) VREF VCOMP OSC SS FMOD VFF (V) (V) 6) 0 0 0 Unchanged VZCD>VZCDth for 4 consecutive switching cycles Auto restart(1) 5 2.2 5(6) VFF > VFFlatch Latched 13.5 0.33 0 0 0 0 0 0 VCOMP =VCOMPHi VSS > VSSDIS Auto restart(2) 5 1.46 5(6) VSS VSSLAT Latched 13.5 0.33 0 0 0 0 0 0 VCOMP =VCOMPHi VSS > VSSDIS(4) Auto restart 5 1.46 0 VSS VSSLAT(6) Latched 13.5 0.33 0 0 0 0 0 0 VCS > VCSDIS for 2-3 consecutive switching cycles Latched 5 0.33 0 0 0 0 0 0 Unchanged( 41/52 Application information 2nd OCP L6566A Table 6. L6566A protection (continued) Protection Description Caused by IC behavior Vcc restart IC Iq (V) (mA) (V) 13.5 0.33 0 VREF VCOMP OSC SS FMOD VFF (V) (V) 0 0 0 0 0 Externally settable overtemperature protection VDIS>VOTP Latched Internal thermal shutdown Tj > 160 oC restart(5) 5 0.33 0 0 0 0 0 0 Brownout Mains undervoltage protection VAC_OK < Vth Auto restart 5 0.33 0 0 0 0 0 Unchanged Reference drift VREF drift protection VREF > Vov Latched 13.5 0.33 0 0 0 0 0 0 Shutdown1 Gate driver disable VFF > Voff Auto restart 5 2.5 5 1 Unchanged Unchanged Shutdown2 Shutdown by VCOMP low VCOMP < VCOMPOFF Latched 10 0.33 0 0 0 0 0 0 Auto restart 5V 0.18 0 0 0 0 0 0 OTP Doc ID 13794 Rev 4 Shutdown by Vcc going below Vccoff Adaptive UVLO (lowering of Vccoff threshold at light load) Vcc < 9.4 V (VCOMP > VCOMPL) Auto Unchanged Unchanged L6566A Table 6. Vcc < 7.2 V (VCOMP > VCOMPO) 2. Use one external diode from SS (#14) to VREF (#10), cathode to VREF 3. If Css and the Vcc capacitor are such that Vcc falls below UVLO before latch tripping (Figure 21 on page 33) 4. If Css and the Vcc capacitor are such that the latch is tripped before Vcc falls below UVLO (Figure 21 on page 33) 5. When TJ < 110 oC 6. Discharged to zero by Vcc going below UVLO 42/52 Application information 1. Use One external diode from VFF (#15) to AC_OK (#16), cathode to AC_OK2 L6566A Application information It is worth remembering that “auto-restart” means that the device works intermittently as long as the condition that is activating the function is not removed; “latched” means that the device is stopped as long as the unit is connected to the input power source and the unit must be disconnected for some time from the source in order for the device (and the unit) to restart. Optionally, a restart can be forced by pulling the voltage of pin 16 (AC_OK) below 0.45 V. Doc ID 13794 Rev 4 43/52 Application examples and ideas 6 L6566A Application examples and ideas Figure 28. Typical low-cost application schematic PFC Pre-regulator Output bus T1 Output capacitor of boost PFC Pre-regulator R1 C2 D4 Vout D1 C8A,B R3 470k R2 D2 C3 AC_OK FMOD DIS 6 16 C7 2.2 nF Y1 Vcc HVS 1 5 8 VFF 4 GD D3 L6566A 12 10 MODE/SC 13 VREF 7 14 OSC C4 R6 Optional f or QR operation R7 Q1 IC1 15 R4 9 3 COMP SS C5 11 1 IC3 CS 4 ZCD R5 R9 GND 3 2 Optional f or QR operation C6 C9 R8 TL431 R10 Figure 29. Typical full-feature application schematic (QR operation) PFC Pre-regulator Output bus C1 T1 Output capacitor of boost PFC Pre-regulator R1 C2 D4 Vout D1 C8A,B R2 to mains v oltage sensing AC_OK to Vcc pin of PFC controller Vcc_PFC R14 16 6 VFF 1 C7 2.2 nF Y1 11 5 4 15 ZCD R3 R4 GD R7 Q1 IC1 D3 1N4148 L6566A DIS D2 1N4148 C3 Vcc HVS 7 IC3 PC817A CS 8 1 4 10 12 13 14 9 R5 3 R9 R18 R13 NTC2 R12 C4 VREF MODE/SC R6 OSC SS COMP GND 3 C5 C6 2 C9 R8 TL431 R10 44/52 Doc ID 13794 Rev 4 L6566A Application examples and ideas Figure 30. Typical full-feature application schematic (FF operation) PFC Pre-regulator Output bus C1 T1 Output capacitor of boost PFC Pre-regulator R1 C2 D4 Vout D1 C8A,B R2 R15 to mains v oltage sensing AC_OK to Vcc pin of PFC controller Vcc_PFC 6 VFF 16 1 C7 2.2 nF Y1 11 5 4 15 R3 ZCD R4 GD D3 1N4148 L6566A IC3 PC817A CS MODE/SC NTC2 R12 7 8 13 10 R13 VREF C4 R6 14 OSC SS R7 Q1 IC1 DIS D2 1N4148 C3 Vcc HVS 3 9 COMP R17 12 R5 R9 R16 GND R18 3 2 C6 C5 1 4 C9 R8 TL431 R10 Table 7. External circuits that determine IC behavior upon OVP and OCP OVP latched SS OVP auto-restart VREF 14 AC_OK 10 RH RH OCP latched SS RFF VFF 14 L6566A L6566A RL RFF needed if RL < 4.7 kΩ VFF 15 Diode needed if RL > 4.7 kΩ 1N4148 1N4148 SS RFF VFF SS VREF 14 RH 10 16 15 RL OCP auto-restart VREF 10 AC_OK RH 14 VREF 10 16 L6566A L6566A 15 RL RL RFF needed if RL < 4.7 kΩ Doc ID 13794 Rev 4 VFF 15 Diode needed if RL > 4.7 k Ω 45/52 Application examples and ideas L6566A Figure 31. Frequency foldback at light load (FF operation) R1 MODE/SC R2 Vref 12 10 COMP L6566A BC857 9 13 OSC RT Figure 32. Latched shutdown upon mains overvoltage Vin Vin BC857 Vcc BC847 5 Vref L6566A 8 DIS 15 VFF DIS 8 >10 Rq 46/52 10 Doc ID 13794 Rev 4 L6566A Rq 15 VFF L6566A 7 Package mechanical data Package mechanical data In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK® packages, depending on their level of environmental compliance. ECOPACK specifications, grade definitions and product status are available at: www.st.com. ECOPACK is an ST trademark. Table 8. SO16N mechanical data mm Dim. Min. Typ. A Max. 1.75 A1 0.10 0.25 A2 1.25 b 0.31 0.51 c 0.17 0.25 D 9.80 9.90 10.00 E 5.80 6.00 6.20 E1 3.80 3.90 4.00 e 1.27 h 0.25 0.50 L 0.40 1.27 k 0 8° ccc 0.10 Doc ID 13794 Rev 4 47/52 Package mechanical data L6566A Figure 33. Package drawing 0016020_F 48/52 Doc ID 13794 Rev 4 L6566A Package mechanical data Figure 34. Recommended footprint (dimensions are in mm) Doc ID 13794 Rev 4 49/52 Order codes 8 Order codes Table 9. 50/52 L6566A Order codes Order codes Package Packaging L6566A SO16N Tube L6566ATR SO16N Tape and reel Doc ID 13794 Rev 4 L6566A 9 Revision history Revision history Table 10. Document revision history Date Revision 20-Aug-2007 1 First release 29-May-2008 2 Updated VMODE/SC value Table 2 on page 11 02-Dec-2008 3 Updated Figure 1 on page 1 and Section 5.6 on page 27 4 Modified: Table 4: Electrical characteristics and Table 8: SO16N mechanical data; replaced Figure 33: Package drawing with a more detailed version; added Figure 34: Recommended footprint (dimensions are in mm) 14-Mar-2012 Changes Doc ID 13794 Rev 4 51/52 L6566A Please Read Carefully: Information in this document is provided solely in connection with ST products. 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