L6599ATDTR

L6599AT Improved high voltage resonant controller Datasheet - production data Applications  LCD and PDP TV  Desktop PC, entry-level server  Telecom SMPS  High efficiency industrial SMPS 61  AC-DC adapter, open frame SMPS Features Table 1. Device summary  50% duty cycle, variable frequency control of resonant half bridge  High accuracy oscillator Order code L6599ATD L6599ATDTR  Up to 500 kHz operating frequency Package SO16N Packaging Tube Tape and reel  Two-level OCP: frequency-shift and latched shutdown  Interface with PFC controller  Latched disable input  Burst mode operation at light load  Input for power-ON/OFF sequencing or brownout protection  Non-linear soft-start for monotonic output voltage rise  600 V - rail compatible high-side gate driver with integrated bootstrap diode and high dv/dt immunity  -300/700 mA high-side and low-side gate drivers with UVLO pull-down  Guaranteed for extreme temperature ranges June 2017 This is information on a product in full production. DocID15534 Rev 8 1/32 www.st.com Contents L6599AT Contents 1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 2 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 3 Pin connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 4 Electrical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 4.1 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 4.2 Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 5 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 6 Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 7 6.1 Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 6.2 Operation at no load or very light load . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 6.3 Soft-start . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 6.4 Current sense, OCP and OLP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 6.5 Latched shutdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 6.6 Line sensing function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 6.7 Bootstrap section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 7.1 8 2/32 SO16N package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 DocID15534 Rev 8 L6599AT 1 Description Description The L6599AT is an improved revision of the previous L6599A. It is a double-ended controller specific to series-resonant half bridge topology. It provides 50% complementary duty cycle: the high-side switch and the low-side switch are driven ON/OFF 180° out-of-phase for exactly the same time. Output voltage regulation is obtained by modulating the operating frequency. A fixed deadtime inserted between the turn-off of one switch and the turn-on of the other guarantees soft-switching and enables high-frequency operation. To drive the high-side switch with the bootstrap approach, the IC incorporates a high voltage floating structure able to withstand more than 600 V with a synchronous-driven high voltage DMOS that replaces the external fast-recovery bootstrap diode. The IC enables the designer to set the operating frequency range of the converter by means of an externally programmable oscillator. At startup, to prevent uncontrolled inrush current, the switching frequency starts from a programmable maximum value and progressively decays until it reaches the steady-state value determined by the control loop. This frequency shift is non-linear to minimize output voltage overshoots; its duration is programmable as well. At light load the IC may enter a controlled burst mode operation that keeps the converter input consumption to a minimum. IC functions include a not-latched active-low disable input with current hysteresis useful for power sequencing or for brownout protection, a current sense input for OCP with frequency shift and delayed shutdown with automatic restart. A higher level OCP latches off the IC if the first-level protection is not sufficient to control the primary current. Their combination offers complete protection against overload and short-circuits. An additional latched disable input (DIS) allows easy implementation of OTP and/or OVP. An interface with the PFC controller is provided that enables the pre-regulator to be switched off during fault conditions, such as OCP shutdown and DIS high, or during burst mode operation. DocID15534 Rev 8 3/32 32 4/32    5)PLQ &VV &)     DocID15534 Rev 8 ',6 67$1'%< 9 5 64 9&2   89/2 ',6$%/( ,IPLQ 9  9   '(/$< &21752/ /2*,& 9  /,1(B2. 2&3 ,6(1B',6 '($' 7,0( 9 89/2 89 '(7(&7,21  /,1(  —$ 9   5 46 '5,9,1* /2*,& 6 6 V, DIS > 1.85 V, ISEN > 1.5 V, DELAY > 2 V) to make sure it is soft-started next, and when the voltage on the current sense pin (ISEN) exceeds 0.8 V, as long as it stays above 0.75 V. 2 DELAY Delayed shutdown upon overcurrent. A capacitor and a resistor are connected from this pin to GND to set the maximum duration of an overcurrent condition before the IC stops switching and the delay after which the IC restarts switching. Every time the voltage on the ISEN pin exceeds 0.8 V, the capacitor is charged by an internal 150 µA current generator and is slowly discharged by the external resistor. If the voltage on the pin reaches 2 V, the soft-start capacitor is completely discharged so that the switching frequency is pushed to its maximum value and the 150 µA is kept always on. As the voltage on the pin exceeds 3.5 V the IC stops switching and the internal generator is turned off, so that the voltage on the pin decays because of the external resistor. The IC is soft-restarted as the voltage drops below 0.3 V. In this way, under short-circuit conditions, the converter works intermittently with very low input average power. 3 CF Timing capacitor. A capacitor connected from this pin to GND is charged and discharged by internal current generators programmed by the external network connected to pin 4 (RFmin) and determines the switching frequency of the converter. RFmin Minimum oscillator frequency setting. This pin provides a precise 2 V reference and a resistor connected from this pin to GND defines a current that is used to set the minimum oscillator frequency. To close the feedback loop that regulates the converter output voltage by modulating the oscillator frequency, the phototransistor of an optocoupler is connected to this pin through a resistor. The value of this resistor sets the maximum operating frequency. An R-C series connected from this pin to GND sets frequency shift at startup to prevent excessive energy inrush (soft-start). 1 4 DocID15534 Rev 8 5/32 32 Pin connection L6599AT Table 2. Pin description (continued) Pin no. 5 6 7 8 9 Type Function STBY Burst mode operation threshold. The pin senses some voltage related to the feedback control, which is compared to an internal reference (1.24 V). If the voltage on the pin is lower than the reference, the IC enters an idle state and its quiescent current is reduced. The chip restarts switching as the voltage exceeds the reference by 50 mV. Soft-start is not invoked. This function realizes burst mode operation when the load falls below a level that can be programmed by properly choosing the resistor connecting the optocoupler to pin RFmin (see block diagram). Tie the pin to RFmin if burst mode is not used. ISEN Current sense input. The pin senses the primary current though a sense resistor or a capacitive divider for lossless sensing. This input is not intended for a cycle-by-cycle control; therefore the voltage signal must be filtered to get average current information. As the voltage exceeds a 0.8 V threshold (with 50 mV hysteresis), the soft-start capacitor connected to pin 1 is internally discharged: the frequency increases, so limiting the power throughput. Under output short-circuit, this normally results in a nearly constant peak primary current. This condition is allowed for a maximum time set at pin 2. If the current keeps on building up despite this frequency increase, a second comparator referenced at 1.5 V latches the device off and brings its consumption almost to a “before startup” level. The information is latched and it is necessary to recycle the supply voltage of the IC to enable it to restart: the latch is removed as the voltage on the Vcc pin goes below the UVLO threshold. Tie the pin to GND if the function is not used. LINE Line sensing input. The pin is to be connected to the high voltage input bus with a resistor divider to perform either AC or DC (in systems with PFC) brownout protection. A voltage below 1.24 V shuts down (not latched) the IC, lowers its consumption and discharges the soft-start capacitor. IC operation is re-enabled (soft-started) as the voltage exceeds 1.24 V. The comparator is provided with current hysteresis: an internal 13 µA current generator is ON as long as the voltage applied at the pin is below 1.24 V and is OFF if this value is exceeded. Bypass the pin with a capacitor to GND to reduce noise pick-up. The voltage on the pin is top-limited by an internal Zener diode. Activating the Zener diode causes the IC to shut down (not latched). Bias the pin between 1.24 and 6 V if the function is not used. DIS Latched device shutdown. Internally, the pin connects a comparator that, when the voltage on the pin exceeds 1.85 V, shuts the IC down and brings its consumption almost to a “before startup” level. The information is latched and it is necessary to recycle the supply voltage of the IC to enable it to restart: the latch is removed as the voltage on the VCC pin goes below the UVLO threshold. Tie the pin to GND if the function is not used. Open-drain ON/OFF control of PFC controller. This pin, normally open, is intended for stopping the PFC controller, for protection purposes or during burst mode operation. It goes low when the IC is shut down by DIS>1.85 V, ISEN > 1.5 V, LINE > 6 V and STBY < 1.24 V. PFC_STOP The pin is pulled low also when the voltage on the DELAY exceeds 2 V and goes back open as the voltage falls below 0.3 V. During UVLO, it is open. Leave the pin unconnected if not used. 10 GND Chip ground. Current return for both the low-side gate-drive current and the bias current of the IC. All of the ground connections of the bias components should be tied to a track going to this pin and kept separate from any pulsed current return. 11 LVG Low-side gate-drive output. The driver is capable of 0.3 A min. source and 0.7 A min. sink peak current to drive the lower MOSFET of the half bridge leg. The pin is actively pulled to GND during UVLO. 12 Vcc Supply voltage of both the signal part of the IC and the low-side gate driver. Sometimes a small bypass capacitor (0.1 µF typ.) to GND may be useful to get a clean bias voltage for the signal part of the IC. 6/32 DocID15534 Rev 8 L6599AT Pin connection Table 2. Pin description (continued) Pin no. Type 13 N.C. high voltage spacer. The pin is not internally connected to isolate the high voltage pin and ease compliance with safety regulations (creepage distance) on the PCB. 14 OUT High-side gate-drive floating ground. Current return for the high-side gate-drive current. Layout carefully the connection of this pin to avoid too large spikes below ground. 15 HVG High-side floating gate-drive output. The driver is capable of 0.3 A min. source and 0.7 A min. sink peak current to drive the upper MOSFET of the half bridge leg. A resistor internally connected to pin 14 (OUT) ensures that the pin is not floating during UVLO. VBOOT High-side gate-drive floating supply voltage. The bootstrap capacitor connected between this pin and pin 14 (OUT) is fed by an internal synchronous bootstrap diode driven in-phase with the low-side gate drive. This patented structure replaces the normally used external diode. 16 Function DocID15534 Rev 8 7/32 32 Electrical data L6599AT 4 Electrical data 4.1 Absolute maximum ratings Table 3. Absolute maximum rating Symbol Pin Parameter Value Unit VBOOT 16 Floating supply voltage -1 to 618 V HVG 15 HVG voltage VOUT -0.3 to VBOOT +0.3 V VOUT 14 Floating ground voltage -3 up to a value included in the range VBOOT -18 and VBOOT V dVOUT /dt 14 Floating ground max. slew rate 50 V/ns Vcc 12 IC supply voltage (Icc = 25 mA) Self-limited V LVG 11 LVG voltage -0.3 to VCC +0.3 V VPFC_STOP 9 Maximum voltage (pin open) -0.3 to Vcc V IPFC_STOP 9 Maximum sink current (pin low) Self-limited A VLINEmax 7 Maximum pin voltage (Ipin  1 mA) Self-limited V IRFmin 4 Maximum source current 2 mA - 1 to 6, 8 Analog inputs and outputs -0.3 to 5 V Ptot - Power dissipation at TA = 70 °C (DIP16) 1 W - - Power dissipation at TA = 50 °C (SO16) 0.83 - Tj - Junction temperature operating range -40 to 150 °C Tstg - Storage temperature -55 to 150 °C Note: ESD immunity for pins 14, 15 and 16 is guaranteed up to 900 V. 4.2 Thermal data Table 4. Thermal data Symbol Rth(JA) 8/32 Parameter Max. thermal resistance junction to ambient (SO16) DocID15534 Rev 8 Value Unit 120 °C/W L6599AT 5 Electrical characteristics Electrical characteristics TJ = - 40 to 125 °C, VCC = 15 V, VBOOT = 15 V, CHVG = CLVG = 1 nF; CF = 470 pF; RRFmin = 12 k; unless otherwise specified. Table 5. Electrical characteristics Symbol Parameter Test condition Min. Typ. Max. Unit 8.85 - 16 V IC supply voltage Vcc Operating range After device turn-on VccOn Turn-on threshold Voltage rising 10 10.7 11.4 V VccOff Turn-off threshold Voltage falling 7.45 8.15 8.85 V Hys Hysteresis - - 2.55 - V VZ Vcc clamp voltage Iclamp = 15 mA 16 17 - V Supply current Startup current Before device turn-on Vcc = VccOn- 0.2 V - 200 250 µA Iq Quiescent current Device on, VSTBY = 1 V - 1.5 2 mA Iop Operating current Device on, VSTBY = VRFmin - 3.5 5 mA Iq Residual consumption VDIS > 1.85 V or VDELAY > 3.5 V or VLINE < 1.24 V or VLINE = Vclamp - 300 400 µA Istart-up High-side floating gate-drive supply ILKBOOT VBOOT pin leakage current VBOOT = 580 V - - 5 µA ILKOUT OUT pin leakage current VOUT = 562 V - - 5 µA RDS(on) Synchronous bootstrap diode on-resistance VLVG = HIGH - 150 -  Overcurrent comparator IISEN Input bias current VISEN = 0 to VISENdis - - -1 µA tLEB Leading edge blanking After VHVG and VLVG low-to-high transition - 250 - ns Frequency shift threshold Voltage rising(1) 0.76 0.8 0.84 V Hysteresis Voltage falling - 50 - mV 1.44 1.5 1.56 V 300 400 ns VISENx VISENdis td(H-L) Latch-off threshold Voltage Delay to output - rising(1) Line sensing Vth Threshold voltage Voltage rising or falling(1) 1.2 1.24 1.28 V IHys Current hysteresis VLINE = 1.1 V 10 13 16 µA Clamp level ILINE = 1 mA 6 - 8 V Vclamp DocID15534 Rev 8 9/32 32 Electrical characteristics L6599AT Table 5. Electrical characteristics (continued) Symbol Parameter Test condition Min. Typ. Max. Unit - - -1 µA 1.78 1.85 1.92 V 48 50 52 % 58.2 60 61.8 RRFmin = 2.7 k 240 250 260 0.2 0.3 0.4 µs DIS function IDIS Vth Input bias current VDIS = 0 to Vth (1) Disable threshold Voltage rising Output duty cycle Both HVG and LVG Oscillator D fosc Oscillation frequency TD Deadtime Between HVG and LVG VCFp Peak value - - 3.9 - V VCFv Valley value - - 0.9 - V 1.93 2 2.07 1.8 2 2.2 - - 1 VPFC_STOP = Vcc, VDIS = 0 V - - 1 µA IPFC_STOP = 1 mA, VDIS = 1.5 V - 130 200  IPFC_STOP = 1 mA, VDIS = 1.5 V - - 0.2 V Open-state current V(Css) = 2 V - - 0.5 µA Discharge resistance VISEN > VISENx - 120 -  VDIS = 0 to Vth - - -1 µA 1.2 1.24 1.28 V (1) VREF KM Voltage reference at pin 4 Current mirroring ratio (1) IREF = -2 mA kHz V -A/A PFC_STOP function Ileak High level leakage current RPFC_STOP ON-state resistance VL Low saturation level Soft-start function Ileak R Standby function IDIS Input bias current falling(1) Vth Disable threshold Voltage Hys Hysteresis Voltage rising - 50 - mV Open-state current V(DELAY) = 0 - - 0.5 µA Charge current VDELAY = 1 V, VISEN = 0.85 V 100 150 200 µA Vth1 Threshold for forced operation at max. frequency Voltage rising(1) 1.98 2.05 2.12 V Vth2 Shutdown threshold Voltage rising(1) 3.35 3.5 3.65 V 0.3 0.33 0.36 V Delayed shutdown function Ileak ICHARGE Vth3 10/32 Restart threshold Voltage falling (1) DocID15534 Rev 8 L6599AT Electrical characteristics Table 5. Electrical characteristics (continued) Symbol Parameter Test condition Min. Typ. Max. Unit Low-side gate driver (voltages referred to GND) VLVGL Output low voltage Isink = 200 mA - - 1.8 V VLVGH Output high voltage Isource = 5 mA 12.8 13.3 - V Isourcepk Peak source current - -0.3 - - A Peak sink current - 0.7 - - A tf Fall time - - 30 - ns tr Rise time - - 60 - ns - UVLO saturation Vcc = 0 to VccOn, Isink = 2 mA - - 1.1 V Isinkpk High-side gate driver (voltages referred to OUT) VLVGL Output low voltage Isink = 200 mA - - 1.8 V VLVGH Output high voltage Isource = 5 mA 12.8 13.3 - V Isourcepk Peak source current - -0.3 - - A Peak sink current - 0.7 - - A tf Fall time - - 30 - ns tr Rise time - - 60 - ns - HVG-OUT pull-down - - 25 - k Isinkpk 1. Values tracking each other. DocID15534 Rev 8 11/32 32 Application information 6 L6599AT Application information The L6599AT is an advanced double-ended controller specific for resonant half bridge topology (see Figure 4). In these converters the switches (MOSFETs) of the half bridge leg are alternately switched on and off (180° out-of-phase) for exactly the same time. This is commonly referred to as operation at “50% duty cycle”, although the real duty cycle, that is the ratio of the ON-time of either switch to the switching period, is actually less than 50%. The reason is that there is an internally fixed deadtime TD inserted between the turn-off of either MOSFET and the turn-on of the other one, where both MOSFETs are off. This deadtime is essential in order for the converter to work correctly: it ensures soft-switching and enables high-frequency operation with high efficiency and low EMI emissions. To perform converter output voltage regulation the device is able to operate in different modes (Figure 3), depending on the load conditions: 1. Variable frequency at heavy and medium/light load. A relaxation oscillator (see Section 6.1: Oscillator for more details) generates a symmetrical triangular waveform, which the MOSFET switching is locked to. The frequency of this waveform is related to a current that is modulated by the feedback circuitry. As a result, the tank circuit driven by the half bridge is stimulated at a frequency dictated by the feedback loop to keep the output voltage regulated, therefore exploiting its frequency-dependent transfer characteristics. 2. Burst mode control with no or very light load. When the load falls below a value, the converter enters a controlled intermittent operation, where a series of a few switching cycles at a nearly fixed frequency are spaced out by long idle periods where both MOSFETs are in OFF-state. A further load decrease is translated into longer idle periods and then in a reduction of the average switching frequency. When the converter is completely unloaded, the average switching frequency can go down even to few hundred hertz, therefore minimizing magnetizing current losses as well as all frequency-related losses and making it easier to comply with energy saving recommendations. Figure 3. Multi-mode operation of the L6599AT %XUVWPRGH  9LQ IVZ 9DULDEOHIUHTXHQF\PRGH   3LQ 3LQPD[  $0Y 12/32 DocID15534 Rev 8 L6599AT Application information Figure 4. Typical system block diagram 3)&35(5(*8/$725237,21$/ 5(621$17+$/)%5,'*( 9RXWGF 9LQDF 5HVRQDQW+%LVWXUQHGRIILQFDVHRI 3)& VDQRPDORXVRSHUDWLRQIRUVDIHW\ //$ /6/+ '$3 / / /$7 '$3$ '$3 /$ 3)&FDQEHWXUQHGRIIDWOLJKW ORDGWRHDVHFRPSOLDQFHZLWK HQHUJ\VDYLQJUHJXODWLRQV  $0Y 6.1 Oscillator The oscillator is programmed externally by means of a capacitor (CF), connected from the pin 3 (CF) to ground, that is alternately charged and discharged by the current defined with the network connected to pin 4 (RFmin). The pin provides an accurate 2 V reference with about 2 mA source capability and the higher the current sourced by the pin is, the higher the oscillator frequency is. The block diagram of Figure 5 shows a simplified internal circuit that explains the operation. The network that loads the RFmin pin is generally made up of three branches: 1. A resistor RFmin connected between the pin and ground that determines the minimum operating frequency. 2. A resistor RFmax connected between the pin and the collector of the (emitter-grounded) phototransistor that transfers the feedback signal from the secondary side back to the primary side; while in operation, the phototransistor modulates the current through this branch - therefore modulating the oscillator frequency - to perform output voltage regulation; the value of RFmax determines the maximum frequency the half bridge is operated at when the phototransistor is fully saturated. 3. An R-C series circuit (CSS+RSS) connected between the pin and ground that enables a frequency shift to be set up at startup (see Section 6.3: Soft-start on page 18). Note that the contribution of this branch is zero during steady-state operation. DocID15534 Rev 8 13/32 32 Application information L6599AT Figure 5. Oscillator internal block diagram  /$ /$7 9 .0ā,5  5)PLQ 5)PLQ 5VV   5)PD[ ā.0ā,5 ,5 9     &VV .0ā,5 &) &) 6 4 5 9 $0Y The following approximate relationships hold for the minimum and the maximum oscillator frequency respectively: Equation 1 fmin  1 3  CF RFmin ; fmax  1 3  CF   RFmin // RFmax  After fixing CF in the hundred pF or in the nF (consistently with the maximum source capability of the RFmin pin and trading this off against the total consumption of the device), the value of RFmin and RFmax is selected so that the oscillator frequency is able to cover the entire range needed for regulation, from the minimum value fmin (at minimum input voltage and maximum load) to the maximum value fmax (at maximum input voltage and minimum load): Equation 2 RFmin  1 3  CF  fmin ; RFmax  RFmin fmax 1 fmin A different selection criterion is given for RFmax in case burst mode operation at no load is used (see Section 6.2: Operation at no load or very light load). 14/32 DocID15534 Rev 8 L6599AT Application information Figure 6. Oscillator waveforms and their relationship with gate-driving signals  &) +9* 7' 7' W /9* W +% W W $0Y In Figure 6 the timing relationship between the oscillator waveform and the gate-drive signal, as well as the swinging node of the half bridge leg (HB), is shown. Note that the lowside gate drive is turned on while the oscillator triangle is ramping up and the high-side gate drive is turned on while the triangle is ramping down. In this way, at startup, or as the IC resumes switching during burst mode operation, the low-side MOSFET is switched on first to charge the bootstrap capacitor. As a result, the bootstrap capacitor is always charged and ready to supply the high-side floating driver. 6.2 Operation at no load or very light load When the resonant half bridge is lightly loaded or not loaded at all, its switching frequency is at its maximum value. To keep the output voltage under control in these conditions and to avoid losing soft-switching, there must be some significant residual current flowing through the transformer’s magnetizing inductance. This current, however, produces some associated losses that prevent converter no load consumption from achieving very low values. To overcome this issue, the L6599AT enables the designer to make the converter operate intermittently (burst mode operation), with a series of a few switching cycles spaced out by long idle periods where both MOSFETs are in OFF-state, so that the average switching frequency can be substantially reduced. As a result, the average value of the residual magnetizing current and the associated losses are considerably cut down, therefore facilitating the converter to comply with energy saving recommendations. The L6599AT can be operated in burst mode by using pin 5 (STBY): if the voltage applied to this pin falls below 1.24 V, the IC enters an idle state where both gate-drive outputs are low, the oscillator is stopped, the soft-start capacitor CSS keeps its charge and only the 2 V reference at the RFmin pin stays alive to minimize IC consumption and Vcc capacitor discharge. The IC resumes normal operation as the voltage on the pin exceeds 1.24 V by 50 mV. To implement burst mode operation the voltage applied to the STBY pin needs to be related to the feedback loop. Figure 7 (a) shows the simplest implementation, suitable with a narrow input voltage range (e.g. when there is a PFC front-end). DocID15534 Rev 8 15/32 32 Application information L6599AT Figure 7. Burst mode implementation: a) narrow input voltage range; b) wide input voltage range % 5)PLQ 5)PLQ   5)PLQ 5)PD[ 67%< /$7 /$ '$3 5)PLQ 5' '$3 /$7 /$ 5)PD[ 67%< /,1(    5$ 5& 5% 5$ 5%!!5& D E $0Y Essentially, RFmax defines the switching frequency fmax above which the L6599AT enters burst mode operation. Once fmax is fixed, RFmax is found from the relationship: Equation 3 RFmax  3 RFmin 8 fmax 1 fmin Note that, unlike the fmax considered in the previous section (Section 6.1: Oscillator), here fmax is associated to some load PoutB greater than the minimum one. PoutB is such that the transformer peak currents are low enough not to cause audible noise. Resonant converter switching frequency, however, depends also on the input voltage; therefore, in the case of quite a large input voltage range with the circuit of Figure 7a, the value of PoutB would change considerably. In this case it is recommended to use the arrangement shown in Figure 7b, where the information on the converter input voltage is added to the voltage applied to the STBY pin. Due to the strongly non-linear relationship between switching frequency and input voltage, it is more practical to find empirically the right amount of correction RA / (RA + RB) needed to minimize the change of PoutB. Make sure to choose the total value RA + RB much greater than RC to minimize the effect on the LINE pin voltage (see Section 6.6: Line sensing function on page 23). Whichever circuit is in use, its operation can be described as follows. As the load falls below the value PoutB the frequency tries to exceed the maximum programmed value fmax and the voltage on the STBY pin (VSTBY) goes below 1.24 V. The IC then stops with both gate-drive outputs low, so that both MOSFETs of the half bridge leg are in OFF-state. The voltage VSTBY now increases as a result of the feedback reaction to the energy delivery stop and, as it exceeds 1.29 V, the IC restarts switching. After a while, VSTBY goes down again in response to the energy burst and stops the IC. In this way, the converter works in a burst mode fashion with a nearly constant switching frequency. A further load decrease then causes a frequency reduction, which can go down even to few hundred hertz. The timing diagram of Figure 8 illustrates this kind of operation, showing the most significant signals. A small capacitor (typically in the hundred pF) from the STBY pin to ground, placed as close to the IC as possible to reduce switching noise pick-up, helps obtain clean operation. To help the designer meet energy saving requirements even in power-factor-corrected systems, where a PFC pre-regulator precedes the DC-DC converter, the L6599AT allows that the PFC pre-regulator can be turned off during burst mode operation, therefore 16/32 DocID15534 Rev 8 L6599AT Application information eliminating the no load consumption of this stage (0.51 W). There is no compliance issue in that, because EMC regulations on low-frequency harmonic emissions refer to nominal load, no limit is envisaged when the converter operates with light or no load. To do so, the L6599AT provides pin 9 (PFC_STOP): it is an open collector output, normally open, that is asserted low when the IC is idle during burst mode operation. This signal is externally used for switching off the PFC controller and the pre-regulator, as shown in Figure 9. When the L6599AT is in UVLO, the pin is kept open to let the PFC controller start first. Figure 8. Load-dependent operating modes: timing diagram 67%< P9 K\VWHU 9 W IRVF W /9* +9* W 3)&B6723 3)& *$7('5,9( 5HVRQDQW0RGH %XUVWPRGH 5HVRQDQW0RGH $0Y Figure 9. How the L6599AT can switch off a PFC controller at light load  ,19 /$ /$7 9FF NŸ  NŸ /$ /$7  3)&B6723 /$ %& %&  3)&B2. 3)&B6723 /$6+ $&B2. $0Y DocID15534 Rev 8 17/32 32 Application information 6.3 L6599AT Soft-start Generally speaking, the purpose of soft-start is to progressively increase converter power capability when it is started up, so as to avoid excessive inrush current. In resonant converters the deliverable power depends inversely on frequency, soft-start is then done by sweeping the operating frequency from an initial high value until the control loop takes over. With the L6599AT converter, soft-startup is simply realized with the addition of an R-C series circuit from pin 4 (RFmin) to ground (see Figure 10, left). Initially, the capacitor CSS is totally discharged, so that the series resistor RSS is effectively in parallel to RFmin and the resulting initial frequency is determined by RSS and RFmin only, since the optocoupler phototransistor is cut off (as long as the output voltage is not too far away from the regulated value): Equation 4 fstart  1 3  CF   RFmin // R SS  The CSS capacitor is progressively charged until its voltage reaches the reference voltage (2 V) and, consequently, the current through RSS goes to zero. This conventionally is imposed 5 times by selecting the constants RSS·CSS. Before reaching 2 V on Css, the output voltage should be already close to the regulated value and the feedback loop already taken over, so that it is the optocoupler phototransistor to determine the operating frequency from that moment onwards. During this frequency sweep phase the operating frequency decays following the exponential charge of CSS, that is, initially it changes relatively quickly but the rate of change gets slower and slower. This counteracts the non-linear frequency dependence of the tank circuit that makes the converter power capability change little as frequency is away from resonance and change very quickly as frequency approaches resonance frequency (see Figure 10, right). Figure 10. Soft-start circuit (left) and power vs. frequency curve in a resonant half bridge (right)  _=I_  5(621$1&( )5(48(1&< 5)PLQ  5)PLQ 566 /$7 &VV  &66 I 6WHDG\VWDWH IUHTXHQF\ ,QLWLDO IUHTXHQF\ $0Y As a result, the average input current smoothly increases, without the peaking that occurs with linear frequency sweep, and the output voltage reaches the regulated value with almost no overshoot. 18/32 DocID15534 Rev 8 L6599AT Application information Typically, RSS and CSS are selected based on the following relationships: Equation 5 R SS  RFmin 3  10 3 ; CSS  fstart R SS 1 fmin where fstart is recommended to be at least 4 times fmin. The proposed criterion for CSS is quite empirical and is a compromise between an effective soft-start action and an effective OCP (see next section). Please refer to the timing diagram of Figure 10 to see some significant signals during the soft-start phase. 6.4 Current sense, OCP and OLP The resonant half bridge is essentially voltage-mode controlled; therefore a current sense input only serves as an overcurrent protection (OCP). Unlike PWM-controlled converters, where energy flow is controlled by the duty cycle of the primary switch (or switches), in a resonant half bridge the duty cycle is fixed and energy flow is controlled by its switching frequency. This impacts on the way current limitation can be realized. While in PWM-controlled converters energy flow can be limited simply by terminating switch conduction beforehand when the sensed current exceeds a preset threshold (this is commonly known as cycle-by-cycle limitation), in a resonant half bridge the switching frequency, that is, its oscillator frequency must be increased and this cannot be done as quickly as turning off a switch: it takes at least the next oscillator cycle to see the frequency change. This implies that, to have an effective increase able to change the energy flow significantly, the rate of change of the frequency must be slower than the frequency itself. This, in turn, implies that cycle-by-cycle limitation is not feasible and that, therefore, the information on the primary current fed to the current sensing input must be somehow averaged. Of course, the averaging time must not be too long to prevent the primary current from reaching too high values. In Figure 11 a couple of current sensing methods are illustrated and are described in the following. The circuit of Figure 11 a is simpler but the dissipation on the sense resistor Rs might not be negligible, damaging efficiency; the circuit of Figure 11 b is more complex but virtually lossless and recommended when the efficiency target is very high. DocID15534 Rev 8 19/32 32 Application information L6599AT Figure 11. Current sensing techniques: a) with sense resistor, b) “lossless”, with capacitive shunt  W|  9&USN IPLQ &U  ,6(1 '$3 /$7 /$  ,6(1 , &U W|  IPLQ 5V 1 &$ 5$ '$3 /$ /$7 9VSN 5% &%  D 1 , &U &U E $0Y The L6599AT is equipped with a current sensing input (pin 6, ISEN) and a sophisticated overcurrent management system. The ISEN pin is internally connected to the input of a first comparator, referenced to 0.8 V, and to that of a second comparator referenced to 1.5 V. If the voltage externally applied to the pin by either circuit in Figure 11 exceeds 0.8 V, the first comparator is tripped and this causes an internal switch to be turned on and discharge the soft-start capacitor CSS (see Section 6.3: Soft-start). This quickly increases the oscillator frequency and thereby limits energy transfer. The discharge goes on until the voltage on the ISEN pin has dropped by 50 mV; this, with an averaging time in the range of 10/fmin, ensures an effective frequency rise. Under output short-circuit, this operation results in a nearly constant peak primary current. It is normal that the voltage on the ISEN pin may overshoot above 0.8 V; however, if the voltage on the ISEN pin reaches 1.5 V, the second comparator is triggered, the L6599AT shuts down and latches off with both the gate drive outputs and the PFC_STOP pin low, therefore turning off the entire unit. The supply voltage of the IC must be pulled below the UVLO threshold and then again above the startup level in order to restart. Such an event may occur if the soft-start capacitor CSS is too large, so that its discharge is not fast enough or in the case of transformer magnetizing inductance saturation or a shorted secondary rectifier. In the circuit shown in Figure 11a, where a sense resistor Rs in series to the source of the low-side MOSFET is used, note the particular connection of the resonant capacitor. In this way the voltage across Rs is related to the current flowing through the high-side MOSFET and is positive most of the switching period, except for the time needed for the resonant current to reverse after the low-side MOSFET has been switched off. Assuming that the time constant of the RC filter is at least ten times the minimum switching frequency fmin, the approximate value of Rs can be found using the empirical equation: Equation 6 Rs  Vs pkx ICrpkx  5  0 .8 4  ICrpkx ICrpkx where ICrpkx is the maximum desired peak current flowing through the resonant capacitor and the primary winding of the transformer, which is related to the maximum load and the minimum input voltage. 20/32 DocID15534 Rev 8 L6599AT Application information The circuit shown in Figure 11 b can be operated in two different ways. If the resistor RA in series to CA is small (not above some hundred , just to limit current spiking), the circuit operates like a capacitive current divider; CA is typically selected equal to Cr/100 or less and is a low-loss type, the sense resistor RB is selected as: Equation 7 RB  C  0 .8   1  r  ICrpkx  C A  and CB is such that RB·CB is in the range of 10 /fmin. If the resistor RA in series to CA is not small (in this case it is typically selected in the ten k), the circuit operates like a divider of the ripple voltage across the resonant capacitor Cr, which, in turn, is related to its current through the reactance of Cr. Again, CA is typically selected equal to Cr/100 or less, not necessarily a low-loss type this time, while RB (provided it is