L6599E
Improved high-voltage resonant controller
Datasheet − production data
Features
■
50% duty cycle, variable frequency control of
resonant half-bridge
■
High-accuracy oscillator
■
Up to 500 kHz operating frequency
■
Two-level OCP: frequency-shift and latched
shutdown
■
Interface with PFC controller
■
Latched disable input
■
Burst-mode operation at light load
■
Input for power-ON/OFF sequencing or
brownout protection
■
Non-linear soft-start for monotonic output
voltage rise
■
600 V-rail compatible high-side gate driver with
integrated bootstrap diode and high dv/dt
immunity
■
-300/800 mA high-side and low-side gate
drivers with UVLO pull-down
■
SO16N package
SO16 Narrow
Application
■
LCD and PDP TV
■
Desktop PC, entry-level server
■
Telecom SMPS
■
High efficiency industrial SMPS
■
AC-DC adapter, open frame SMPS
Table 1.
Device summary
Order codes
Package
Packaging
L6599ED
SO16N
Tube
L6599EDTR
SO16N
Tape and reel
May 2012
This is information on a product in full production.
Doc ID 023238 Rev 1
1/39
www.st.com
39
Contents
L6599E
Contents
1
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
3
Pin connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
4
Electrical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
4.1
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
4.2
Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
5
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
6
Typical electrical performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
7
Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
7.1
Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
7.2
Operation at no load or very light load . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
7.3
Soft-start . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
7.4
Current sense, OCP and OLP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
7.5
Latched shutdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
7.6
Line sensing function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
7.7
Bootstrap section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
8
Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
9
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
2/39
Doc ID 023238 Rev 1
L6599E
List of tables
List of tables
Table 1.
Table 2.
Table 3.
Table 4.
Table 5.
Table 6.
Table 7.
Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Absolute maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Thermal data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
SO16N dimentions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Doc ID 023238 Rev 1
3/39
List of figures
L6599E
List of figures
Figure 1.
Figure 2.
Figure 3.
Figure 4.
Figure 5.
Figure 6.
Figure 7.
Figure 8.
Figure 9.
Figure 10.
Figure 11.
Figure 12.
Figure 13.
Figure 14.
Figure 15.
Figure 16.
Figure 17.
Figure 18.
Figure 19.
Figure 20.
Figure 21.
Figure 22.
Figure 23.
Figure 24.
Figure 25.
Figure 26.
Figure 27.
Figure 28.
Figure 29.
Figure 30.
Figure 31.
Figure 32.
Figure 33.
Figure 34.
4/39
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Pin connection (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Device consumption vs supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
IC consumption vs junction temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
VCC clamp voltage vs junction temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
UVLO thresholds vs junction temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Oscillator frequency vs junction temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Dead-time vs junction temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Oscillator frequency vs timing components . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Oscillator ramp vs junction temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Reference voltage vs junction temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Current mirroring ratio vs junction temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
OCP delay source current vs junction temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
OCP delay thresholds vs junction temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Standby thresholds vs junction temperature. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Current sense thresholds vs junction temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Line thresholds vs junction temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Line source current vs junction temperature. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Latched disable threshold vs junction temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Multi-mode operation of the L6599E. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Typical system block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Oscillator's internal block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Oscillator waveforms and their relationship with gate-driving signals. . . . . . . . . . . . . . . . . 22
Burst-mode implementation: a) narrow input voltage range; b) wide input voltage range . 23
Load-dependent operating modes: timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
How the L6599E can switch off a PFC controller at light load . . . . . . . . . . . . . . . . . . . . . . 24
Soft-start circuit (left) and power vs. frequency curve in an resonant half-bridge (right). . . 25
Current sensing techniques: a) with sense resistor, b) “lossless”,with capacitive shunt. . . 27
Soft-start and delayed shutdown upon overcurrent timing diagram . . . . . . . . . . . . . . . . . . 29
Line sensing function: internal block diagram and timing diagram . . . . . . . . . . . . . . . . . . . 31
Bootstrap supply: a) standard circuit; b) internal bootstrap synchronous diode . . . . . . . . 32
Application example: 90 W AC/DC adapter using L6563H, L6599E and SRK2000 . . . . . . 34
SO16N drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Recommended footprint (dimensions are in mm) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Doc ID 023238 Rev 1
L6599E
1
Description
Description
The L6599E is an improved revision of the previous L6599. It is a double-ended controller
specific for the series-resonant half-bridge topology. It provides 50% complementary duty
cycle: the high-side switch and the low-side switch are driven ON/OFF 180° out-of-phase for
exactly the same time. Output voltage regulation is obtained by modulating the operating
frequency. A fixed dead-time inserted between the turn-off of one switch and the turn-on of
the other one guarantees soft-switching and enables high-frequency operation.
To drive the high-side switch with the bootstrap approach, the IC incorporates a high-voltage
floating structure able to withstand more than 600 V with a synchronous-driven high-voltage
DMOS that replaces the external fast-recovery bootstrap diode.
The IC enables the designer to set the operating frequency range of the converter by means
of an externally programmable oscillator.
At start-up, to prevent uncontrolled inrush current, the switching frequency starts from a
programmable maximum value and progressively decays until it reaches the steady-state
value determined by the control loop. This frequency shift is non linear to minimize output
voltage overshoots; its duration is programmable as well.
At light load the IC may enter a controlled burst-mode operation that keeps the converter
input consumption to a minimum.
IC’s functions include a not-latched active-low disable input with current hysteresis useful for
power sequencing or for brownout protection, a current sense input for OCP with frequency
shift and delayed shutdown with automatic restart. A higher level OCP latches off the IC if
the first-level protection is not sufficient to control the primary current. Their combination
offers complete protection against overload and short circuits. An additional latched disable
input (DIS) allows easy implementation of OTP and/or OVP.
An interface with the PFC controller is provided that enables to switch off the pre-regulator
during fault conditions, such as OCP shutdown and DIS high, or during burst-mode
operation.
Doc ID 023238 Rev 1
5/39
Block diagram
2
L6599E
Block diagram
Figure 1.
Block diagram
Vcc
8
DISABLE
DIS
1.85V
STBY
+
-
5
1.24V +
DIS
S
R
UV
17V DETECTION
Q
UVLO
+
-
HVG
DRIVER
SYNCHRONOUS
BOOTSTRAP DIODE
15
HVG
2V
LEVEL
SHIFTER
DRIVING
LOGIC
DEAD
TIME
CBOOT
14
V cc
LVG DRIVER
11
LC TANK
CIRCUIT
LVG
10
Q
S
R
UVLO
+
-
1.5V
+
-
0.8V
GND
Css 1
6
CONTROL
LOGIC
3
VBOOT
OUT
ISEN_DIS
CF
16
UVLO
STANDBY
Ifmin
RFmin 4
H.V.
12
OCP
LINE_OK
1.24V
6.3V
VCO
13
µA
9
+
ISEN
PFC_STOP
ISEN_DIS
DIS
STANDBY
7
2
DELAY
LINE
AM01128v1
6/39
Doc ID 023238 Rev 1
L6599E
3
Pin connection
Pin connection
Figure 2.
Pin connection (top view)
Css
1
16
VBOOT
DELAY
2
15
HVG
CF
3
14
OUT
RFmin
4
13
N.C.
STBY
5
12
Vcc
ISEN
6
11
LVG
LINE
7
10
GND
DIS
8
9
PFC_STOP
AM01129v1
Table 2.
Pin N#
1
2
3
Pin description
Type
Function
Css
Soft-start. This pin connects an external capacitor to GND and a resistor to
RFmin (pin 4) that set both the maximum oscillator frequency and the time
constant for the frequency shift that occurs as the chip starts up (softstart). An internal switch discharges this capacitor every time the chip turns
off (Vcc < UVLO, LINE < 1.24 V or > 6 V, DIS > 1.85 V, ISEN > 1.5 V,
DELAY > 2 V) to make sure it will be soft-started next, and when the
voltage on the current sense pin (ISEN) exceeds 0.8 V, as long as it stays
above 0.75 V.
DELAY
Delayed shutdown upon overcurrent. A capacitor and a resistor are
connected from this pin to GND to set the maximum duration of an
overcurrent condition before the IC stops switching and the delay after
which the IC restarts switching. Every time the voltage on the ISEN pin
exceeds 0.8 V the capacitor is charged by an internal 150 µA current
generator and is slowly discharged by the external resistor. If the voltage
on the pin reaches 2 V, the soft start capacitor is completely discharged so
that the switching frequency is pushed to its maximum value and the
150 µA is kept always on. As the voltage on the pin exceeds 3.5 V the IC
stops switching and the internal generator is turned off, so that the voltage
on the pin will decay because of the external resistor. The IC will be softrestarted as the voltage drops below 0.3 V. In this way, under short circuit
conditions, the converter will work intermittently with very low input
average power.
CF
Timing capacitor. A capacitor connected from this pin to GND is charged
and discharged by internal current generators programmed by the external
network connected to pin 4 (RFmin) and determines the switching
frequency of the converter.
Doc ID 023238 Rev 1
7/39
Pin connection
L6599E
Table 2.
Pin N#
4
5
6
7
8
8/39
Pin description (continued)
Type
Function
RFmin
Minimum oscillator frequency setting. This pin provides a precise 2 V
reference and a resistor connected from this pin to GND defines a current
that is used to set the minimum oscillator frequency. To close the feedback
loop that regulates the converter output voltage by modulating the
oscillator frequency, the phototransistor of an optocoupler will be
connected to this pin through a resistor. The value of this resistor will set
the maximum operating frequency. An R-C series connected from this pin
to GND sets frequency shift at start-up to prevent excessive energy inrush
(soft-start).
STBY
Burst-mode operation threshold. The pin senses some voltage related to
the feedback control, which is compared to an internal reference (1.24 V).
If the voltage on the pin is lower than the reference, the IC enters an idle
state and its quiescent current is reduced. The chip restarts switching as
the voltage exceeds the reference by 50 mV. Soft-start is not invoked. This
function realizes burst-mode operation when the load falls below a level
that can be programmed by properly choosing the resistor connecting the
optocoupler to pin RFmin (see block diagram). Tie the pin to RFmin if
burst-mode is not used.
ISEN
Current sense input. The pin senses the primary current though a sense
resistor or a capacitive divider for lossless sensing. This input is not
intended for a cycle-by-cycle control; hence the voltage signal must be
filtered to get average current information. As the voltage exceeds a 0.8 V
threshold (with 50 mV hysteresis), the soft-start capacitor connected to pin
1 is internally discharged: the frequency increases hence limiting the
power throughput. Under output short circuit, this normally results in a
nearly constant peak primary current. This condition is allowed for a
maximum time set at pin 2. If the current keeps on building up despite this
frequency increase, a second comparator referenced at 1.5 V latches the
device off and brings its consumption almost to a “before start-up” level.
The information is latched and it is necessary to recycle the supply voltage
of the IC to enable it to restart: the latch is removed as the voltage on the
Vcc pin goes below the UVLO threshold. Tie the pin to GND if the function
is not used.
LINE
Line sensing input. The pin is to be connected to the high-voltage input bus
with a resistor divider to perform either AC or DC (in systems with PFC)
brownout protection. A voltage below 1.24 V shuts down (not latched) the
IC, lowers its consumption and discharges the soft-start capacitor. IC’s
operation is re-enabled (soft-started) as the voltage exceeds 1.24 V. The
comparator is provided with current hysteresis: an internal 13 µA current
generator is ON as long as the voltage applied at the pin is below 1.24 V
and is OFF if this value is exceeded. Bypass the pin with a capacitor to
GND to reduce noise pick-up. The voltage on the pin is top-limited by an
internal zener. Activating the zener causes the IC to shut down (not
latched). Bias the pin between 1.24 and 6 V if the function is not used.
DIS
Latched device shutdown. Internally the pin connects a comparator that,
when the voltage on the pin exceeds 1.85 V, shuts the IC down and brings
its consumption almost to a “before start-up” level. The information is
latched and it is necessary to recycle the supply voltage of the IC to enable
it to restart: the latch is removed as the voltage on the Vcc pin goes below
the UVLO threshold. Tie the pin to GND if the function is not used.
Doc ID 023238 Rev 1
L6599E
Pin connection
Table 2.
Pin N#
9
Pin description (continued)
Type
Function
Open-drain ON/OFF control of PFC controller. This pin, normally open, is
intended for stopping the PFC controller, for protection purpose or during
burst-mode operation. It goes low when the IC is shut down by DIS>1.85 V,
PFC_STOP ISEN > 1.5 V, LINE > 6 V and STBY < 1.24 V. The pin is pulled low also
when the voltage on pin DELAY exceeds 2 V and goes back open as the
voltage falls below 0.3 V. During UVLO, it is open. Leave the pin
unconnected if not used.
10
GND
Chip ground. Current return for both the low-side gate-drive current and
the bias current of the IC. All of the ground connections of the bias
components should be tied to a track going to this pin and kept separate
from any pulsed current return.
11
LVG
Low-side gate-drive output. The driver is capable of 0.3 A min. source and
0.8 A min. sink peak current to drive the lower MOSFET of the half-bridge
leg. The pin is actively pulled to GND during UVLO.
12
Vcc
Supply voltage of both the signal part of the IC and the low-side gate
driver. Sometimes a small bypass capacitor (0.1 µF typ.) to GND might be
useful to get a clean bias voltage for the signal part of the IC.
13
N.C.
High-voltage spacer. The pin is not internally connected to isolate the highvoltage pin and ease compliance with safety regulations (creepage
distance) on the PCB.
14
OUT
High-side gate-drive floating ground. Current return for the high-side gatedrive current. Layout carefully the connection of this pin to avoid too large
spikes below ground.
HVG
High-side floating gate-drive output. The driver is capable of 0.3 A min.
source and 0.8 A min. sink peak current to drive the upper MOSFET of the
half-bridge leg. A resistor internally connected to pin 14 (OUT) ensures
that the pin is not floating during UVLO.
VBOOT
High-side gate-drive floating supply voltage. The bootstrap capacitor
connected between this pin and pin 14 (OUT) is fed by an internal
synchronous bootstrap diode driven in-phase with the low-side gate-drive.
This patented structure replaces the normally used external diode.
15
16
Doc ID 023238 Rev 1
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Electrical data
L6599E
4
Electrical data
4.1
Absolute maximum ratings
Table 3.
Absolute maximum rating
Symbol
Pin
VBOOT
16
VOUT
Value
Unit
Floating supply voltage
-1 to 618
V
14
Floating ground voltage
-3 to VBOOT-18
V
dVOUT /dt
14
Floating ground max. slew rate
50
V/ns
Vcc
12
IC supply voltage (Icc = 25 mA)
Self-limited
V
VPFC_STOP
9
Maximum voltage (pin open)
-0.3 to Vcc
V
IPFC_STOP
9
Maximum sink current (pin low)
Self-limited
A
VLINEmax
7
Maximum pin voltage (Ipin ≤1 mA)
Self-limited
V
IRFmin
4
Maximum source current
2
mA
---
1 to 6, 8
-0.3 to 5
V
Power dissipation @TA = 70 °C (DIP16)
1
W
Power dissipation @TA = 50 °C (SO16)
0.83
Ptot
Tj
Parameter
Analog inputs and Outputs
Junction temperature operating range
-40 to 150
°C
Storage temperature
-55 to 150
°C
Value
Unit
Max. thermal resistance junction to ambient (DIP16)
80
°C/W
Max. thermal resistance junction to ambient (SO16)
120
°C/W
Tstg
Note:
ESD immunity for pins 14, 15 and 16 is guaranteed up to 900 V.
4.2
Thermal data
Table 4.
Symbol
Rth(JA)
10/39
Thermal data
Parameter
Doc ID 023238 Rev 1
L6599E
5
Electrical characteristics
Electrical characteristics
TJ = 0 to 105 °C, Vcc = 15 V, VBOOT = 15 V, CHVG = CLVG = 1 nF; CF = 470 pF; RRFmin = 12
kΩ; unless otherwise specified.
Table 5.
Electrical characteristics
Symbol
Parameter
Test condition
Min.
Typ.
Max.
Unit
16
V
IC supply voltage
Vcc
Operating range
After device turn-on
VccOn
Turn-on threshold
Voltage rising
10
10.7
11.4
V
VccOff
Turn-off threshold
Voltage falling
7.45
8.15
8.85
V
Hys
Hysteresis
VZ
Vcc clamp voltage
8.85
2.55
Iclamp = 15 mA
16
V
17
17.9
V
Supply current
Start-up current
Before device turn-on
Vcc = VccOn- 0.2 V
200
250
µA
Iq
Quiescent current
Device on, VSTBY = 1 V
1.5
2
mA
Iop
Operating current
Device on, VSTBY = VRFmin
3.5
5
mA
Iq
Residual consumption
VDIS > 1.85 V or VDELAY >
3.5 V or VLINE < 1.24 V or
VLINE = Vclamp
300
400
µA
Istart-up
High-side floating gate-drive supply
ILKBOOT
VBOOT pin leakage current
VBOOT = 580 V
5
µA
ILKOUT
OUT pin leakage current
VOUT = 562 V
5
µA
RDS(on)
Synchronous bootstrap
diode on-resistance
VLVG = HIGH
Ω
150
Overcurrent comparator
IISEN
Input bias current
VISEN = 0 to VISENdis
tLEB
Leading edge blanking
After VHVG and VLVG lowto-high transition
Frequency shift threshold
Voltage rising (1)
Hysteresis
Voltage falling
Latch off threshold
Voltage rising (1)
VISENx
VISENdis
td(H-L)
-1
250
0.77
0.8
ns
0.83
50
1.45
Delay to output
µA
V
mV
1.5
1.55
V
300
400
ns
Line sensing
Vth
Threshold voltage
Voltage rising or falling (1)
1.2
1.24
1.28
V
IHys
Current hysteresis
VLINE = 1.1 V
10
13
16
µA
Clamp level
ILINE = 1 mA
6
8
V
Vclamp
Doc ID 023238 Rev 1
11/39
Electrical characteristics
Table 5.
L6599E
Electrical characteristics (continued)
Symbol
Parameter
Test condition
Min.
Typ.
Max.
Unit
-1
µA
DIS function
IDIS
Vth
Input bias current
VDIS = 0 to Vth
(1)
Disable threshold
Voltage rising
Output duty cycle
Both HVG and LVG
1.78
1.85
1.92
V
48
50
52
%
58.2
60
61.8
RRFmin = 2.7 kΩ
240
250
260
Between HVG and LVG
0.2
0.3
0.4
Oscillator
D
fosc
Oscillation frequency
TD
Dead-time
VCFp
Peak value
VCFv
Valley value
kHz
(1)
VREF
KM
Voltage reference at pin 4
IREF = - 2 mA
(1)
µs
3.9
V
0.9
V
1.93
2
2.07
1.93
2
2.07
V
Current mirroring ratio
1
A/A
PFC_STOP function
Ileak
High level leakage current
1
µA
200
Ω
IPFC_STOP = 1 mA, VDIS =
1.5 V
0.2
V
Open-state current
V(Css) = 2 V
0.5
µA
Discharge resistance
VISEN > VISENx
IPFC_STOP = 1 mA, VDIS = 1.5
RPFC_STOP ON-state resistance
VL
VPFC_STOP =Vcc, VDIS = 0
V
130
V
Low saturation level
Soft-start function
Ileak
R
Ω
120
Standby function
IDIS
Input bias current
VDIS = 0 to Vth
Vth
Disable threshold
Voltage falling
Hys
Hysteresis
Voltage rising
(1)
1.2
1.24
-1
µA
1.28
V
50
mV
Delayed shutdown function
Ileak
Open-state current
V(DELAY) = 0
Charge current
VDELAY = 1 V, VISEN = 0.85
V
100
Vth1
Threshold for forced
operation at max.
frequency
Voltage rising (1)
Vth2
Shutdown threshold
Voltage rising (1)
ICHARGE
12/39
Doc ID 023238 Rev 1
0.5
µA
150
200
µA
1.98
2.05
2.12
V
3.35
3.5
3.65
V
L6599E
Electrical characteristics
Table 5.
Vth3
Symbol
Electrical characteristics (continued)
Voltage falling (1)
Restart threshold
Parameter
Test condition
0.3
0.33
0.36
V
Min.
Typ.
Max.
Unit
1.5
V
Low-side gate driver (voltages referred to GND)
VLVGL
Output low voltage
Isink = 200 mA
VLVGH
Output high voltage
Isource = 5 mA
Isourcepk
Peak source current
-0.3
A
Peak sink current
0.8
A
Isinkpk
12.8
13.3
V
tf
Fall time
30
ns
tr
Rise time
60
ns
Vcc= 0 to VccOn, Isink = 2
mA
UVLO saturation
1.1
V
1.5
V
High-side gate driver (voltages referred to OUT)
VLVGL
Output low voltage
Isink = 200 mA
VLVGH
Output high voltage
Isource = 5 mA
Isourcepk
Peak source current
-0.3
A
Peak sink current
0.8
A
Isinkpk
12.8
13.3
V
tf
Fall time
30
ns
tr
Rise time
60
ns
HVG-OUT pull-down
25
kΩ
1. Values tracking each other
Doc ID 023238 Rev 1
13/39
Typical electrical performance
L6599E
6
Typical electrical performance
Figure 3.
Device consumption vs supply
voltage
Figure 4.
IC consumption vs junction
temperature
Pin 12 [mA]
Pin 12 Icc [mA ]
50
5
Operating @ 50 kHz
10
3
5
2
1
Vcc=15 V
Quiescent
1
0.5
0.5
0.1
0.05
0.3
0.01
0
Figure 5.
5
10
Vcc [ V]
15
Start-up
0.2
CHVG =CLVG = 1nF
f = 50 kHz
Tj = 25 °C
0.005
0
Latched off
20
0.1
-20
0
20
AM12930v1
VCC clamp voltage vs junction
temperature
Pin 12 [V]
Figure 6.
40
60
Tj [°C]
80
100
120
AM12931v1
UVLO thresholds vs junction
temperature
Pin 12 [V]
11
18
Turn-on
10.5
17.5
10
9.5
17
9
16.5
8.5
16
-20
14/39
0
20
40
60
Tj [°C]
80
100
120
8
-20
AM12932v1
Doc ID 023238 Rev 1
Turn-off
0
20
40
60
Tj [°C]
80
100
120
AM12933v1
L6599E
Typical electrical performance
Figure 7.
Oscillator frequency vs junction
temperature
Pin 3
Figure 8.
Dead-time vs junction temperature
Pins 11 & 15
1.05
1.15
Normalized to fsw @ 25 °C
50 kHz < fsw < 250 kHz
Vcc=15 V
1.1
1.025
Normalized to fsw @ 25 °C
50 kHz < fsw < 250 kHz
Vcc=15 V
1.05
1
1
0.975
0.95
0.95
-20
Figure 9.
0
20
40
60
Tj [°C]
80
100
120
500
200
0
20
AM12934v1
Oscillator frequency vs timing
components
40
60
Tj [°C]
80
100
120
AM12935v1
Figure 10. Oscillator ramp vs junction
temperature
Pin 3 [V]
Pin 3 fsw [Hz]
1,000
0.9
-20
4
CF =
220 pF
330 pF
470 pF
680 pF
Vcc=15 V
3.5
Peak
50 kHz < fsw < 250 kHz
Vcc=15 V
3
1.0 nF
2.5
100
2.2 nF
2
50
1.5
20
10
1
5
0.5
-20
Valley
1
2
3
5
RFmin [ k ]
10
20
AM12936v1
Doc ID 023238 Rev 1
0
20
40
60
Tj [°C]
80
100
120
AM12937v1
15/39
Typical electrical performance
L6599E
Figure 11. Reference voltage vs junction
temperature
Pin 4 [V]
Pins 3 & 4
1.015
2.08
2.06
Figure 12. Current mirroring ratio vs junction
temperature
Vcc=15 V
2.04
1.005
2.02
1
2
0.995
1.98
0.99
1.96
0.985
1.94
0.98
1.92
-20
0
Normalized to KM @ 25°C
50 kHz < fsw < 250 kHz
Vcc=15 V
1.01
20
40
60
Tj [°C]
80
100
120
0.975
-20
0
20
AM12938v1
Figure 13. OCP delay source current vs
junction temperature
40
60
Tj [°C]
80
100
120
AM12939v1
Figure 14. OCP delay thresholds vs junction
temperature
Pin 2 [V]
4
Pin 2 [uA]
200
Vcc=15 V
Vcc=15 V
Stop
3.5
180
3
2.5
160
CSS always ON
2
140
1.5
1
120
Restart
0.5
100
-20
16/39
0
20
40
60
Tj [°C]
80
100
120
0
-20
AM12940v1
Doc ID 023238 Rev 1
0
20
40
60
Tj [°C]
80
100
120
AM12941v1
L6599E
Typical electrical performance
Figure 15. Standby thresholds vs junction
temperature
Figure 16. Current sense thresholds vs
junction temperature
Pin 6 [V]
Pin 5 [V]
1.6
1.4
Latch-off
Vcc=15 V
1.4
Vcc=15 V
1.35
Restart
1.2
1.3
1
CSS low
1.25
0.8
Stop
CSS open
1.2
-20
0
20
40
60
Tj [°C]
80
100
120
0.6
-20
0
AM12942v1
Figure 17. Line thresholds vs junction
temperature
40
60
Tj [°C]
80
100
120
AM12943v1
Figure 18. Line source current vs junction
temperature
Pin 7 [V]
Pin 7 [uA]
7
18
Clamp
Vcc=15 V
6
17
Stop
5
20
Vcc=15 V
16
4
15
3
14
2
1
0
-20
13
Stop
0
20
40
60
Tj [°C]
80
100
120
12
-20
AM12944v1
Doc ID 023238 Rev 1
0
20
40
60
Tj [°C]
80
100
120
AM12945v1
17/39
Typical electrical performance
L6599E
Figure 19. Latched disable threshold vs
junction temperature
Pin 8 [V]
1.92
Vcc=15 V
1.88
1.84
1.8
1.76
-20
18/39
0
20
40
60
Tj [°C]
80
100
120
AM12946v1
Doc ID 023238 Rev 1
L6599E
Application information
The L6599E is an advanced double-ended controller specific for resonant half-bridge
topology (see Figure 21.). In these converters the switches (MOSFETs) of the half-bridge
leg are alternately switched on and off (180° out-of-phase) for exactly the same time. This is
commonly referred to as operation at “50% duty cycle”, although the real duty cycle, that is
the ratio of the on-time of either switch to the switching period, is actually less than 50%.
The reason is that there is an internally fixed dead-time TD inserted between the turn-off of
either MOSFET and the turn-on of the other one, where both MOSFETs are off. This deadtime is essential in order for the converter to work correctly: it will ensure soft-switching and
enable high-frequency operation with high efficiency and low EMI emissions.
To perform converter's output voltage regulation the device is able to operate in different
modes (Figure 20 ), depending on the load conditions:
1.
Variable frequency at heavy and medium/light load. A relaxation oscillator (see
Section 7.1: Oscillator for more details) generates a symmetrical triangular waveform,
which MOSFETs' switching is locked to. The frequency of this waveform is related to a
current that will be modulated by the feedback circuitry. As a result, the tank circuit
driven by the half-bridge will be stimulated at a frequency dictated by the feedback loop
to keep the output voltage regulated, thus exploiting its frequency-dependent transfer
characteristics.
2.
Burst-mode control with no or very light load. When the load falls below a value, the
converter will enter a controlled intermittent operation, where a series of a few
switching cycles at a nearly fixed frequency are spaced out by long idle periods where
both MOSFETs are in OFF-state. A further load decrease will be translated into longer
idle periods and then in a reduction of the average switching frequency. When the
converter is completely unloaded, the average switching frequency can go down even
to few hundred hertz, thus minimizing magnetizing current losses as well as all
frequency-related losses and making it easier to comply with energy saving
recommendations.
Figure 20. Multi-mode operation of the L6599E
Burst-mode
7
Application information
Vin
fsw
Variable-frequency mode
0
0
Pin
Pinmax
AM01131v1
Doc ID 023238 Rev 1
19/39
Application information
L6599E
Figure 21. Typical system block diagram
PFC PRE-REGULATOR (OPTIONAL)
RESONANT HALF-BRIDGE
Voutdc
Vinac
Resonant HB is turned off in case of
PFC's anomalous operation, for safety
L6562, L6562A,
L6563S,
L6563H,
DAP005
L6564
L6563
DAP015A
DAP015
L6599A
L6599E
PFC can be turned off at light
load to ease compliance with
energy saving regulations.
AM01130v1
7.1
Oscillator
The oscillator is programmed externally by means of a capacitor (CF), connected from pin 3
(CF) to ground, that will be alternately charged and discharged by the current defined with
the network connected to pin 4 (RFmin). The pin provides an accurate 2 V reference with
about 2 mA source capability and the higher the current sourced by the pin is, the higher the
oscillator frequency will be. The block diagram of Figure 22 shows a simplified internal
circuit that explains the operation.
The network that loads the RFmin pin generally comprises three branches:
20/39
1.
A resistor RFmin connected between the pin and ground that determines the minimum
operating frequency;
2.
a resistor RFmax connected between the pin and the collector of the (emittergrounded) phototransistor that transfers the feedback signal from the secondary side
back to the primary side; while in operation, the phototransistor will modulate the
current through this branch - hence modulating the oscillator frequency - to perform
output voltage regulation; the value of RFmax determines the maximum frequency the
half-bridge will be operated at when the phototransistor is fully saturated;
3.
an R-C series circuit (CSS+RSS) connected between the pin and ground that enables
to set up a frequency shift at start-up (see Section 7.3: Soft-start ). Note that the
contribution of this branch is zero during steady-state operation.
Doc ID 023238 Rev 1
L6599E
Application information
Figure 22. Oscillator's internal block diagram
L6599E
L6599
2V
KM·IR
+
RFmin
RFmin
Rss
RFmax
4
+
+
-
Css
CF
2·KM·IR
IR
1V
KM·IR
3
CF
S
Q
R
4V
AM01132v1
The following approximate relationships hold for the minimum and the maximum oscillator
frequency respectively:
Equation 1
1
fmin = ------------------------------------------- ;
3 ⋅ CF ⋅ RF min
1
f max = --------------------------------------------------------------------3 ⋅ CF ⋅ ( RF min //RFmax )
After fixing CF in the hundred pF or in the nF (consistently with the maximum source
capability of the RFmin pin and trading this off against the total consumption of the device),
the value of RFmin and RFmax will be selected so that the oscillator frequency is able to
cover the entire range needed for regulation, from the minimum value fmin (at minimum input
voltage and maximum load) to the maximum value fmax (at maximum input voltage and
minimum load):
Equation 2
1
RFmin = ------------------------------------ ;
3 ⋅ CF ⋅ f min
RF min
RF max = -------------------fmax
----------- – 1
f min
A different selection criterion will be given for RFmax in case burst-mode operation at no-load
will be used (see Section 7.2: Operation at no load or very light load ).
Doc ID 023238 Rev 1
21/39
Application information
L6599E
Figure 23. Oscillator waveforms and their relationship with gate-driving signals
CF
HVG
TD
TD
t
LVG
t
HB
t
t
AM01133v1
In Figure 23 the timing relationship between the oscillator waveform and the gate-drive
signal, as well as the swinging node of the half-bridge leg (HB) is shown. Note that the lowside gate-drive is turned on while the oscillator's triangle is ramping up and the high-side
gate-drive is turned on while the triangle is ramping down. In this way, at start-up, or as the
IC resumes switching during burst-mode operation, the low-side MOSFET will be switched
on first to charge the bootstrap capacitor. As a result, the bootstrap capacitor will always be
charged and ready to supply the high-side floating driver.
7.2
Operation at no load or very light load
When the resonant half-bridge is lightly loaded or unloaded at all, its switching frequency will
be at its maximum value. To keep the output voltage under control in these conditions and to
avoid losing soft-switching, there must be some significant residual current flowing through
the transformer's magnetizing inductance. This current, however, produces some
associated losses that prevent converter's no-load consumption from achieving very low
values.
To overcome this issue, the L6599E enables the designer to make the converter operate
intermittently (burst-mode operation), with a series of a few switching cycles spaced out by
long idle periods where both MOSFETs are in OFF-state, so that the average switching
frequency can be substantially reduced. As a result, the average value of the residual
magnetizing current and the associated losses will be considerably cut down, thus
facilitating the converter to comply with energy saving recommendations.
The L6599E can be operated in burst-mode by using pin 5 (STBY): if the voltage applied to
this pin falls below 1.24 V the IC will enter an idle state where both gate-drive outputs are
low, the oscillator is stopped, the soft-start capacitor CSS keeps its charge and only the 2 V
reference at RFmin pin stays alive to minimize IC's consumption and Vcc capacitor's
discharge. The IC will resume normal operation as the voltage on the pin exceeds 1.24 V by
50 mV.
To implement burst-mode operation the voltage applied to the STBY pin needs to be related
to the feedback loop. Figure 24a shows the simplest implementation, suitable with a narrow
input voltage range (e.g. when there is a PFC front-end).
22/39
Doc ID 023238 Rev 1
L6599E
Application information
Figure 24. Burst-mode implementation: a) narrow input voltage range; b) wide input
voltage range
B+
RFmin
RFmin
RFmax
STBY
RFmin
4
L6599E
L6599A
DAP015
RFmin
5
RFmax
STBY
RA
4
DAP015
L6599E
L6599A
5
RD
7
LINE
RC
RB
RA + RB >> RC
a)
b)
AM01134v1
Essentially, RFmax will define the switching frequency fmax above which the L6599E will
enter burst-mode operation. Once fixed fmax, RFmax will be found from the relationship:
Note that, unlike the fmax considered in the previous section (Section 7.1: Oscillator ), here
3 RF min
RFmax = --- --------------------8 f max
----------- – 1
f min
fmax is associated to some load PoutB greater than the minimum one. PoutB will be such that
the transformer's peak currents are low enough not to cause audible noise.
Resonant converter's switching frequency, however, depends also on the input voltage;
hence, in case there is quite a large input voltage range with the circuit of Figure 24a the
value of PoutB would change considerably. In this case it is recommended to use the
arrangement shown in Figure 24b, where the information on the converter's input voltage is
added to the voltage applied to the STBY pin. Due to the strongly non-linear relationship
between switching frequency and input voltage, it is more practical to find empirically the
right amount of correction RA / (RA + RB) needed to minimize the change of PoutB. Just be
careful in choosing the total value RA + RB much greater than RC to minimize the effect on
the LINE pin voltage (see Section 7.6: Line sensing function).
Whichever circuit is in use, its operation can be described as follows. As the load falls below
the value PoutB the frequency will try to exceed the maximum programmed value fmax and
the voltage on the STBY pin (VSTBY) will go below 1.24 V. The IC will then stop with both
gate-drive outputs low, so that both MOSFETs of the half-bridge leg are in OFF-state. The
voltage VSTBY will now increase as a result of the feedback reaction to the energy delivery
stop and, as it exceeds 1.29 V, the IC will restart switching. After a while, VSTBY will go down
again in response to the energy burst and stop the IC. In this way the converter will work in a
burst-mode fashion with a nearly constant switching frequency. A further load decrease will
then cause a frequency reduction, which can go down even to few hundred hertz. The timing
diagram of Figure 25 illustrates this kind of operation, showing the most significant signals.
A small capacitor (typically in the hundred pF) from the STBY pin to ground, placed as close
to the IC as possible to reduce switching noise pick-up, will help get clean operation.
To help the designer meet energy saving requirements even in power-factor-corrected
systems, where a PFC pre-regulator precedes the DC-DC converter, the L6599E allows that
the PFC pre-regulator can be turned off during burst-mode operation, hence eliminating the
no-load consumption of this stage (0.5 1 W). There is no compliance issue in that because
Doc ID 023238 Rev 1
23/39
Application information
L6599E
EMC regulations on low-frequency harmonic emissions refer to nominal load, no limit is
envisaged when the converter operates with light or no load.
To do so, the L6599E provides pin 9 (PFC_STOP): it is an open collector output, normally
open, that is asserted low when the IC is idle during burst-mode operation. This signal will
be externally used for switching off the PFC controller and the pre-regulator as shown in
Figure 26. When the L6599E is in UVLO the pin is kept open, to let the PFC controller start
first
Figure 25. Load-dependent operating modes: timing diagram
STBY
50 mV
hyster.
1.24 V
t
fosc
t
LVG
HVG
t
PFC_STOP
PFC
GATE-DRIVE
Burst-mode
Resonant Mode
Resonant Mode
AM01135v1
Figure 26. How the L6599E can switch off a PFC controller at light load
INV
L6599A
L6599E
Vcc
22 k
12
100 k
L6599A
L6599E
9
PFC_STOP
L6562A
BC547
BC547
9
PFC_OK
PFC_STOP
L6563/A/S/H
(AC_OK)
AM01136v1
24/39
Doc ID 023238 Rev 1
L6599E
7.3
Application information
Soft-start
Generally speaking, purpose of soft-start is to progressively increase converter's power
capability when it is started up, so as to avoid excessive inrush current. In resonant
converters the deliverable power depends inversely on frequency, then soft- start is done by
sweeping the operating frequency from an initial high value until the control loop takes over.
With the L6599E converter's soft start-up is simply realized with the addition of an R-C
series circuit from pin 4 (RFmin) to ground (see Figure 27, left).
Initially, the capacitor CSS is totally discharged, so that the series resistor RSS is effectively
in parallel to RFmin and the resulting initial frequency is determined by RSS and RFmin
only, since the optocoupler's phototransistor is cut off (as long as the output voltage is not
too far away from the regulated value):
Equation 3
1
f start = ------------------------------------------------------------3 ⋅ CF ⋅ ( RF min //R ss )
The CSS capacitor is progressively charged until its voltage reaches the reference voltage (2
V) and, consequently, the current through RSS goes to zero. This conventionally takes 5
times constants RSS·CSS but, before that time, the output voltage will have got close to the
regulated value and the feedback loop taken over, so that it will be the optocoupler's
phototransistor to determine the operating frequency from that moment onwards.
During this frequency sweep phase the operating frequency will decay following the
exponential charge of CSS, that is, initially it will change relatively quickly but the rate of
change will get slower and slower. This counteract the non-linear frequency dependence of
the tank circuit that makes converter's power capability change little as frequency is away
from resonance and change very quickly as frequency approaches resonance frequency
(see Figure 27, right).
Figure 27. Soft-start circuit (left) and power vs. frequency curve in an resonant halfbridge (right)
| Z ( f ) |- 1
RESONANCE
FREQUENCY
RFmin
4
RFmin
RSS
L6599E
Css
1
CSS
f
Steady-state
frequency
Initial
frequency
AM01137v1
As a result, the average input current will smoothly increase, without the peaking that occurs
with linear frequency sweep, and the output voltage will reach the regulated value with
almost no overshoot.
Typically, RSS and CSS will be selected based on the following relationships:
Doc ID 023238 Rev 1
25/39
Application information
L6599E
Equation 4
RFmin
R ss = ---------------------- ;
f start
------------ – 1
fmin
–3
⋅ 10 --------------------C ss = 3
R ss
where fstart is recommended to be at least 4 times fmin. The proposed criterion for CSS is
quite empirical and is a compromise between an effective soft-start action and an effective
OCP (see next section). Please refer to the timing diagram of Figure 27 to see some
significant signals during the soft-start phase.
7.4
Current sense, OCP and OLP
The resonant half-bridge is essentially voltage-mode controlled; hence a current sense input
will only serve as an overcurrent protection (OCP).
Unlike PWM-controlled converters, where energy flow is controlled by the duty cycle of the
primary switch (or switches), in a resonant half-bridge the duty cycle is fixed and energy flow
is controlled by its switching frequency. This impacts on the way current limitation can be
realized. While in PWM-controlled converters energy flow can be limited simply by
terminating switch conduction beforehand when the sensed current exceeds a preset
threshold (this is commonly now as cycle-by-cycle limitation), in a resonant half-bridge the
switching frequency, that is, its oscillator’s frequency must be increased and this cannot be
done as quickly as turning off a switch: it takes at least the next oscillator cycle to see the
frequency change. This implies that to have an effective increase, able to change the energy
flow significantly, the rate of change of the frequency must be slower than the frequency
itself. This, in turn, implies that cycle-by-cycle limitation is not feasible and that, therefore,
the information on the primary current fed to the current sensing input must be somehow
averaged. Of course, the averaging time must not be too long to prevent the primary current
from reaching too high values.
In Figure 28 a couple of current sensing methods are illustrated that will be described in the
following. The circuit of Figure 28a is simpler but the dissipation on the sense resistor Rs
might not be negligible, hurting efficiency; the circuit of Figure 28b is more complex but
virtually lossless and recommended when the efficiency target is very high.
26/39
Doc ID 023238 Rev 1
L6599E
Application information
Figure 28. Current sensing techniques: a) with sense resistor, b) “lossless”,with
capacitive shunt
τ
6
Cr
ISEN
DAP015
L6599E
L6599A
6
I Cr
τ
10
fmin
Rs
Vspk
10
fmin
ISEN
VCrpk
1N4148 CA RA
DAP015
L6599E
L6599A
RB
0
CB
a)
1N4148
I Cr
Cr
b)
AM01138v1
The L6599E is equipped with a current sensing input (pin 6, ISEN) and a sophisticated
overcurrent management system. The ISEN pin is internally connected to the input of a first
comparator, referenced to 0.8 V, and to that of a second comparator referenced to 1.5 V. If
the voltage externally applied to the pin by either circuit in Figure 28 exceeds 0.8 V the first
comparator is tripped and this causes an internal switch to be turned on and discharge the
soft-start capacitor CSS (see Section 7.3: Soft-start ). This will quickly increase the oscillator
frequency and thereby limit energy transfer. The discharge will go on until the voltage on the
ISEN pin has dropped by 50 mV; this, with an averaging time in the range of 10/fmin, ensures
an effective frequency rise. Under output short circuit, this operation results in a nearly
constant peak primary current.
It is normal that the voltage on the ISEN pin may overshoot above 0.8 V; however, if the
voltage on the ISEN pin reaches 1.5 V, the second comparator will be triggered, the L6599E
will shutdown and latch off with both the gate-drive outputs and the PFC_STOP pin low,
hence turning off the entire unit. The supply voltage of the IC must be pulled below the
UVLO threshold and then again above the start-up level in order to restart. Such an event
may occur if the soft-start capacitor CSS is too large, so that its discharge is not fast enough
or in case of transformer’s magnetizing inductance saturation or a shorted secondary
rectifier.
In the circuit shown in Figure 28a, where a sense resistor Rs in series to the source of the
low-side MOSFET is used, note the particular connection of the resonant capacitor. In this
way the voltage across Rs is related to the current flowing through the high-side MOSFET
and is positive most of the switching period, except for the time needed for the resonant
current to reverse after the low-side MOSFET has been switched off. Assuming that the time
constant of the RC filter is at least ten times the minimum switching frequency fmin, the
approximate value of Rs can be found using the empirical equation:
Equation 5
V Spkx
--------------I Crpkx
5 ⋅ 0.8
4
≈ ------------------ ≈ --------------ICrpkx
I Crpkx
where ICrpkx is the maximum desired peak current flowing through the resonant capacitor
and the primary winding of the transformer, which is related to the maximum load and the
minimum input voltage.
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Application information
L6599E
The circuit shown in Figure 28b can be operated in two different ways. If the resistor RA in
series to CA is small (not above some hundred Ω, just to limit current spiking) the circuit
operates like a capacitive current divider; CA will be typically selected equal to Cr/100 or
less and will be a low-loss type, the sense resistor RB will be selected as:
Equation 6
C
0.8π
R B = --------------- ⎛ 1 + ------r-⎞
I Crpkx ⎝
C A⎠
and CB will be such that RB·CB is in the range of 10 /fmin.
If the resistor RA in series to CA is not small (in this case it will be typically selected in the ten
kΩ), the circuit operates like a divider of the ripple voltage across the resonant capacitor Cr,
which, in turn, is related to its current through the reactance of Cr. Again, CA will be typically
selected equal to Cr/100 or less, this time not necessarily a low-loss type, while RB
(provided it is 150 kHz), so that they run at high frequency also at full load. Otherwise, the converter will
run at high frequency at light load, where the current flowing in the MOSFETs of the halfbridge leg is low, so that, generally, an R(DS)ON rise is not an issue. However, it is wise to
check this point anyway and the following equation is useful to compute the drop on the
bootstrap driver:
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Application information
Equation 12
Qg
V Drop = Ich arg e R ( DS )on + V F = ------------------- R ( DS )on + V F
Tch arg e
where Qg is the gate charge of the external power MOS, R(DS)ON is the on-resistance of the
bootstrap DMOS (150 W, typ.) and Tcharge is the ON-time of the bootstrap driver, which
equals about half the switching period minus the dead time TD. For example, using a
MOSFET with a total gate charge of 30nC, the drop on the bootstrap driver is about 3 V at a
switching frequency of 200 kHz:
Equation 13
–9
30 ⋅ 10
- 150+0.6=2.7 V
VDrop = --------------------------------------------------------------–6
–6
2.5 ⋅ 10 – 0.27 ⋅ 10
If a significant drop on the bootstrap driver is an issue, an external ultra-fast diode can be
used, thus saving the drop on the R(DS)ON of the internal DMOS.
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Application information
L6599E
Figure 32. Application example: 90 W AC/DC adapter using L6563H, L6599E and SRK2000
AM01142v1
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Doc ID 023238 Rev 1
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8
Package mechanical data
Package mechanical data
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK® packages, depending on their level of environmental compliance. ECOPACK®
specifications, grade definitions and product status are available at: www.st.com.
ECOPACK® is an ST trademark.
Table 6.
SO16N dimentions
mm
Dim.
Min.
Typ.
A
Max.
1.75
A1
0.10
0.25
A2
1.25
b
0.31
0.51
c
0.17
0.25
D
9.80
9.90
10.00
E
5.80
6.00
6.20
E1
3.80
3.90
4.00
e
1.27
h
0.25
0.50
L
0.40
1.27
k
0
8°
ccc
0.10
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Package mechanical data
L6599E
Figure 33. SO16N drawing
0016020_F
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Package mechanical data
Figure 34. Recommended footprint (dimensions are in mm)
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Revision history
9
L6599E
Revision history
Table 7.
38/39
Document revision history
Date
Revision
29-May-2012
1
Changes
Initial release
Doc ID 023238 Rev 1
L6599E
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