L6615
HIGH/LOW SIDE LOAD SHARE CONTROLLER
■
■
■
■
■
■
■
SSI SPECS COMPLIANT
HIGH/LOW SIDE CURRENT SENSING
FULLY COMPATIBLE WITH REMOTE
OUTPUT VOLTAGE SENSING
FULL DIFFERENTIAL LOW OFFSET
CURRENT SENSE
2.7V TO 22V VCC OPERATING RANGE
32kΩ SHARE SENSE AMPLIFIER INPUT
IMPEDANCE
HYSTERETIC UVLO
BCD TECHNOLOGY
DIP8
SO8
ORDERING NUMBERS:
L6615N
APPLICATION
DISTRIBUTED POWER SYSTEMS
■ HIGH DENSITY DC-DC CONVERTERS
■ (N+1) REDUNDANT SYSTEMS, N UP TO 20
■ SMPS FOR (WEB) SERVERS
L6615D
L6615DTR(T & Reel)
■
achieve load sharing of paralleled and independent power supply modules in distributed power
systems, by adding only few external components.
Current sharing is achieved through a single wire
connection (share bus) common to all of the paralleled modules.
DESCRIPTION
This controller IC is specifically designed to
TYPICAL APPLICATION DIAGRAM
RSENSE
(*)
+OUT
+OUT_S
RADJ
-OUT_S
-OUT
PS #1
RG1
RG2
1
GND
VCC
8
2
CS-
CGA
7
3
CS+
SHARE
6
4
ADJ
COMP
5
L6615
CC
RCGA
RC
(*)
RSENSE
+OUT
+OUT_S
+OUT
RADJ
-OUT_S
LOAD
-OUT
PS #N
GND
RG1
RG2
1
GND
VCC
8
2
CS-
CGA
7
3
CS+
SHARE
6
4
ADJ
COMP
5
L6615
SHARE BUS
CC
RC
July 2003
RCGA
(*) OR-ing FET can
be used to reduce
power dissipation
1/20
L6615
DESCRIPTION (continued)
Load sharing is a technique used in all the systems in which the load requires low voltage, high current
and/or redundancy; for this reason a modular power system is necessary in which two or more power supplies or DC-DC converters are paralleled.
The device is able to perform both high side and low side current sensing, that is the sense current resistor
can be placed either in series to the power supplies output or on the ground return.
The L6615 then drives the share bus to a voltage proportional to the output current of the master that is
to the highest amongst the output currents delivered by the paralleled power supplies.
The share bus dynamics is independent of the power supply output voltage and is clamped only by the
device supply voltage (VCC).
The output voltage of the other paralleled power supplies (slaves) is then trimmed by the ADJ pin so that
they can support their amount of load current. The slave power supplies work as current-controlled current
sources.
Sharing the output currents is useful for equalizing also the thermal stress of the different modules and
providing an advantage in term of reliability.
Moreover the paralleled supplies architecture allows achieving redundancy; the failure of one of the modules can be tolerated until the capability of the remaining power supplies is enough to provide the required
load current.
PIN DESCRIPTION
N°
Pin
1
GND
Ground.
2
CS-
Input of current sense amplifier; it is connected to the negative side of the sense resistor through
a resistor (RG2).
3
CS+
Input of current sense amplifier. A resistor (RG1, of the same value as RG2) is placed between
this pin and the positive side of the sense resistor: its value defines the transconductance gain
between ICGA and VSENSE.
4
ADJ
Output of Adjust amplifier; it is connected to both the load (through a resistor RADJ) and to the
positive remote sense pin of the power system. This pin is an open collector diverting (from the
feedback path) a current proportional to the difference between the current supplied to the load
by the relevant power supply and the current supplied by the master.
5
COMP
Output of the current sharing (transconductance) error amplifier and input of ADJ amplifier.
Typically, a compensation network is placed between this pin and ground. The maximum voltage
is internally clamped to 1.5V (typ.)
6
SH
Share bus pin. During the power supply slave operation, this pin acts as positive input from
share bus. During power supply master operation, it drives the share bus to a voltage
proportional to the load current.
The share bus connects the SH pins of all the paralleled modules. A capacitor between this pin
and GND could be useful to reduce the noise present on the share bus.
7
CGA
Current Gain Adjust pin; current sense amplifier output. A resistor connected between this pin
and ground defines the maximum voltage on the share bus and sets the gain of the current
sharing system.
8
VCC
Supply voltage of the IC.
2/20
Function
L6615
ABSOLUTE MAXIMUM RATINGS
Symbol
Pin
VCC
8
ICS+, ICS2, 3, 6, 4, 7
VCOMP
5
Ptot
Value
Unit
selflimit
V
10
mA
-0.3 to VCC
V
Error amplifier output
-0.3 to 1.5
V
Differential input voltage (VCS+ from 0V to 22V)
-0.7 to 0.7
V
0.45
0.6
W
Junction temperature range
-40 to +125
°C
Storage temperature
-55 to +150
°C
Supply Voltage (*) (ICC --- ⋅ --------------
2 10mA
in this way no fault will cause ICS+ (or ICS-) to overcome its absolute maximum ratings.
At full load, ∆VSENSE(MAX) = IOUT(MAX) · RSENSE(MAX) is the maximum voltage drop across the resistor
RSENSE (typically few hundreds of millivolt).
IOUT(MAX) is the maximum current carried by each of the paralleled power supply; in non redundant systems composed by N power supplies, each of them works at its nominal current, so:
I LOAD
I OUT ( MAX ) = --------------N
This relationship is true also in N+M redundant system, even if under normal condition each power supply
provides ILOAD/(N+M).
For example in a system composed by two paralleled power supplies 100% redundant (N=M=1), each
module is sized to sustain the entire load current (in normal operation it carries only one half): for this reason the sense resistor must be sized considering the whole load current.
The temperature variation of the sense resistor (hence of its resistance value) has to be taken into account, so RSENSE(MAX) is the value at maximum operating temperature to avoid saturating the share bus.
Once fixed VSENSE(MAX), the ratio RCGA/RG (gain from the sensing section to the share bus) can be calculated:
R CGA
V SH ( MAX )
--------------= ------------------------------------RG
V SENSE ( MAX )
where VSH(MAX) is defined by the application.
A small capacitor in parallel to R CGA is useful to reduce the noise.
The effect of current sharing feedback loop is to force the voltages of the slave's CGA pins to be equal to
VSH (that is to reduce the voltage difference at the inputs of the L6615 error amplifier). For the sake of
simplicity we consider 2 paralleled power supplies (as in fig. 11): under closed loop condition:
R SNS ( 1 )
R SNS ( 2 )
I OUT ( 1 ) ⋅ ---------------------- ⋅ R CGA ( 1 ) = I OUT ( 2 ) ⋅ ---------------------- ⋅ R CGA ( 2 )
RG ( 1 )
RG( 2)
Ideally all the external component and α are matched so:
I LOAD
I OUT ( 1 ) = I OUT ( 2 ) = --------------2
Any mismatch will have repercussion on the sharing precision: in particular the maximum difference between the output currents (sharing error) will be given by the sum of the mismatches amongst the relevant
values.
11/20
L6615
Figure 12. ADJ network
VOUT
RADJ
VOUT
RADJ
IADJ
to L6615
ADJ pin
R1
E/A
Off the shelf
POWER SUPPLY
IADJ
to L6615
ADJ pin
E/A
R2
VREF
VREF
a)
b)
To set the RADJ value it is necessary to know the tolerance required of the power supply output voltage
(VOUT±∆VO); the maximum difference between master and slave output voltage is 2*∆VO and this amount
represents the voltage that the L6615 must be able to correct.
Now two different approaches are feasible depending on whether the SMPS (whose output current must
be shared) has to be completely designed or it is an "off the shelf" component and only the current sharing
section must be designed.
In the first case, the adjustment resistor (RADJ) can be considered as a fraction of the high resistor of the
feedback divider RH (see fig.12.a): typically the first step consist of fixing the current flowing, under steady
state condition, through the feedback divider IFB; by choosing the value for R2:
V REF
I FB = ------------R2
we will have:
R H = R 1 + R ADJ =
V OUT
-------------- V REF
– 1 ⋅ R 2
It can be an useful rule of thumb to use RADJ lower than (or equal to) one tenth of R1, considering that, in
worst case condition, it will be:
∆V OUT
I ADJ ( max ) = -----------------R ADJ
This value must not exceed the one indicated in the "Electrical characteristic section" but this is very easy
to meet, as one can easily see by using sensible values for ∆VOUT and R 2.
In the second case (fig 12.b), the feedback divider has been already designed by the SMPS manufacturer
and it is not possible to modify it: the design of RADJ must be done to make the L6615 able to correct the
maximum spread without significantly shifting the SMPS regulation point. A minimum RADJ value can be
found by:
∆V OUT
R ADJ ( min ) = ------------------------I ADJ ( max )
where IADJ(max) is 8mA.
Especially for low voltage output buses it is important to avoid adjustment network saturation; the design
must satisfy the following relationship:
V OUT – R ADJ ⋅ ( I ADJ + I FB ) > V A DJ( MIN )
where VADJ(MIN) can be found in the "Electrical characteristic section" for different IADJ values.
12/20
L6615
The last point is the design of the compensation network ZC(s) connected between the COMP pin and
ground.
Besides the power supply feedback loop, the current sharing system introduces another, outer loop. To
avoid interaction between them it is important to design the bandwidth of the sharing loop at least one order of magnitude lower than the bandwidth of the power supply loop.
For the total system, the loop gain is:
R CGA
R ADJ
1
G LOOP ( s ) = R SENSE ⋅ --------------- ⋅ G M ⋅ Z C ( s ) ⋅ -------------- ⋅ A PWR ( s ) ⋅ -----------------R
R
R
G
A
LOA D
where
APWR(s) is the transfer function of PWM controller and power stage (see fig. 11)
RLOAD is the equivalent load resistance
Typically the compensation network is built by a R-C series.
A resistor in series with CC is required to boost the phase margin of the load share loop. The zero is placed
at the load share loop crossover frequency, fC(SH).
If fC(SH) is the share loop crossover frequency, then:
R CGA ⋅ G M R ADJ R SENSE
1
C C = -------------------------------- ⋅ ----------------------------- ⋅ -------------- ⋅ ---------------------- ⋅ A PWR ( f
RA
R LOAD
2 ⋅ π ⋅ f C ( SH )
RG
C ( SH ) )
1
R C = --------------------------------------------2 ⋅ π ⋅ f C ( SH ) ⋅ C C
5
CURRENT SENSE METHODS
Several are the methods to sense the power supply output current; the simplest one is to use a power
resistor (fig. 13a) but increasing load current could require expensive resistor to support the inherent power dissipation, imposing the use of several paralleled resistor.
Other methods to sense the output current are showed in fig. 13b and 13c:
1. RDS(ON): a power MOS is placed in series to the output and its channel resistance (RDS(ON)) is used
as sense resistor (fig 13a): the L6615 sense pins will be connected, through RG resistors to the drain
and to the source of the MOS. Besides providing the sense resistor, the FET is used as "ORing" element: driving properly its gate, it is possible isolate the power supply output from the load (the body
diode is reversed biased so it doesn't conduct).
This is useful whenever features like hot swap or hot plug are required; compared with the well-known
solution using ORing diode, the ORing FET greatly reduces the power dissipation, in particular:
2
P ( DIO DE ) = VF ⋅ IOUT + R SE NSE ⋅ IOUT
2
P( MOS ) = R DS ( O N ) ⋅ I OUT
where VF is the forward drop across the diode.
2. Current transformer: in case of very high load currents, a transformer allows sensing a smaller current, obtained through a scaling factor equal to the transformer turn ratio. In this way, the sense resistor power dissipation requirements can be less tight: obviously this is paid with the cost of the
transformer.
In fig. 13c it is showed the simplified output stage of a power supply in forward configuration: through
two current transformers the load current is reproduced in the sensing circuit scaled by a factor N.
RSENSE will read a ripple (at the switching frequency) superimposed on the average current value
that doesn't affect the correct behaviour of the current sharing system because its loop gain is designed with a low bandwidth - at least 2 order of magnitude lower than the switching frequency - that
will cut this high frequency.
13/20
L6615
Figure 13. Current sense methods.
L6615
CS+
CS-
CS+
RG
RG
RG
L6615
ORing FET
CS-
RG
CS+
RG
CS-
L6615
RSNS
1:N
RG
1:N
SENSING
CIRCUIT
RSNS
IOUT
L
O
A
D
POWER
SUPPLY
IOUT
POWER
SUPPLY
GATE
CONTROL
a)
IOUT
L
O
A
D
L
O
A
D
b)
c)
6
APPLICATION IDEAS
In fig. 14 is showed a single section of a system in which several DC to DC modules can be paralleled,
typical solution whenever the load requires high current at low voltage; the converter is designed for a step
down configuration using a synchronous rectification controller (for example L6910 [1] or L6911 [2] ST device).
The L6615 reads the drop across the Rds(ON) of the OR-ing FET and the LM293 drives its gate, pulling
it down whenever a fault condition (e.g. short on the low side) appears.
A charge pump could be necessary to be sure that the ORing FET VGS is higher than VGS(TH) (depending
on the input and output voltage).
Figure 14. 0.9 to 5V DC-Dc converter with Current Sharing and output hot-pluggability
VIN
4
8
LM293
7
5
6
BOOT
UGATE
VCC
VOUT
PHASE
GND
LGATE
SS
CS+
PGND
L6910
VIN
COMP
VFB
R1
GND
+S_OUT
CSVcc
ADJ
L6615
COMP
CGA
SH
SH
Q1
-SOUT
P_GND
14/20
L6615
Figure 15. Distributed power system for +48V bus
00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00
00000000000000
00 00 00 00 00 00 00 00 00 00 00 00 00 00
+48V
+48V
+48V (*)
feedback
AC
Mains
IOUT1
L
O
A
D
RSNS
+48V (*)
feedback
IOUT2
RSNS
AC
Mains
+48V GND
+48V GND
+12V
+12V
RG
RG
RG
RG
DPS2
DPS1
(*) the center of the
output feedback divider
is usually connected to
a voltage compatible
with L6615 AMR
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
000000000000000
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
ADJ
CS-
CS+
SH
Vcc
GND
L6615
SH bus
CS+
SH
GND
CSADJ
Vcc
L6615
In this application is inserted also a circuit for the square current limit protection in case of overcurrent (R1Q1): being the voltage at the CGA pin directly proportional to the current carried by the relevant section,
it is possible to set the CGA resistor such that, until the output current is in the right range, the CGA voltage
is lower than VREF+0.7. As soon as this value is overcome, then the bipolar pushes current in the feedback
path, reducing the duty cycle and consequently the output voltage.
Current sharing can be required in AC to DC application like distributed power system (DPS) for telecom
applications: if the output voltage is higher than the absolute maximum rating for the current sense pins
(CS+ and CS-) high side sensing can not be performed unless adding other components; the current
sense is performed on the ground return.
To maintain high side sensing two resistor dividers (between the edge of R SENSE and ground) could be
introduced to translate the sense signal in the L6615 input pin common mode range.
In fig.15 two AC-DC converters supply the same load through a +48V bus; these converters usually exhibit
also a +12V auxiliary output useful to supply the L6615 whose ADJ pin works on the +48V feedback section (COMP pin and CGA pin connections are not showed) in figure 15.
7
LOW VOLTAGE BUSES
The L6615 has a "doubled" sense structure, designed to perform both high side and low side sensing: the
first solution is usually considered more convenient. Actually low side sensing means to split the ground
return as many times as the power supplies paralleled are: on each of these paths it is then necessary to
place the sense resistor introducing a drop between the power supply ground and the common load negative reference.
The voltage at CS+ pin is read by an internal comparator and compared with a reference corresponding
to the switchover threshold VTHcs+ whose value is typically 1.6V. If such value is overcome, then the comparator triggers the High Side Amplifier (HSA); being the threshold provided by hysteresis, then the Low
Side Amplifier (LSA) will be triggered as VCS+ is lower than 1.44V (typ.).
Hence VTHcs+ defines the threshold between the operating range of LSA, (referring to fig.10) and the operating range of HSA; usually LSA is operating when the sense resistor is placed on the ground return,
between the negative load terminal and the negative power supply output (fig 10.b) and HSA when the
sense resistor is placed between the power supply positive output and the load.
It is however possible to perform high side sensing for applications whose output voltage is close to VTHcs+
threshold (or even lower) exploiting the low sense internal structure (LSA).
15/20
L6615
Consider, for example an application with VOUT = 1.2V and the sense resistor placed high side; the voltage
at CS+:
VCS+ = VOUT - ∆VSENSE
is lower than 1.6V so the internal comparator triggers on the LSA structure and the pin CS- sources the
current ICS (see paragraph "2. CURRENT SENSE SECTION"). The IC works properly because the dynamics of LSA spreads down to zero: in this case it is necessary to pay attention to the design of ADJ
network.
Now consider, for example, an application with VOUT =1.5V where, because of the drop across RSNS, the
voltage at CS+ pin could be very close to the threshold: if such voltage is overcome (start-up, load regulation, overvoltage,…) , then the HSA structure will be activated; as nominal conditions are restored, the
hysteresis will then keep HSA active (unless VCS+ falls under the lower threshold).
8
OFFSET TRIMMING
The current sharing accuracy strongly depends on the unbalance between the relevant parameters of the
paralleled sections. Each percentage point on the relevant parameters tolerance introduces a maximum
error equal to the double of the tolerance.The L6615 introduces an inherent error in current sharing due
to the 40mV offset at the negative input of the error amplifier; this offset is necessary to guarantee the low
value of the master COMP pin.
Considering perfectly matched all other parameters, the offset introduces a percentage error equal to 4%
divided by the voltage on the share bus. In particular:
40mA
I SLAV E = I MAST ER ⋅ 1 – ----------------
VS H
Being VSH directly proportional to the load current and fixed the ratio R CGA/RG, higher are the currents
involved in the sharing, lower is the error.
Another error is introduced by the current sense amplifier due to its input offset whose amplitude can be
±1mV: being typically the drop across RSNS about one hundred mV at full load, the offset could lead to an
error of some percentage point.
Whenever the application requires very high current sharing accuracy, it is possible to correct these offsets
through a triggering process, introducing a trimmer (RK) between current sense input pins.
Referring to fig. 16, in case of high side sensing, the equations governing the circuit are:
V OUT – V M
VM
---------------------------- = ---------------------------( 1 – δ) ⋅ RK
RG
V OUT + V SENSE – V P
VP
- = IG
--------------------------------------------------------- – -------------δ ⋅ RK
RG
VP = VM + VO
where VO is the current sense amplifier input offset.
Solving for IG, we get:
V SENSE δ ⋅ R K + R G
2⋅δ–1
I G = --------------------- – ------------------------------ ⋅ V O + V OUT ⋅ -------------------------------------------------------δ ⋅ [ RK ⋅ ( 1 – δ ) + R G ]
δ ⋅ R K ⋅ RG
RG
Ideally IG should be equal only to the first term: this current will be sunk by CS+ pin, internally mirrored
with 1:1 ratio and sent to CGA pin.
Imposing that the sum of two latter terms is zero it is possible to find the value of δ deleting the effect of
the offset:
2
2
2
2
2
1 2 ⋅ V OUT ⋅ R G – 4 ⋅ V OUT ⋅ R G + V O ⋅ R K + 4 ⋅ V O ⋅ R G ⋅ R K
δ OPT = --- – ----------------------------------------------------------------------------------------------------------------------------------------------------------2
2 ⋅ VO ⋅ RK
16/20
L6615
Figure 16. Offset Trimming
ILOAD
VOUT+VSENSE
VOUT
_
+
RSNS
RG
RG
δ RK
IG
(1-δ) RK
VP
VM
CS+
CS-
CGA
RCGA
L6615
Because of the tolerance of the output voltage, it is not possible to delete completely the effect of the offset
on CGA pin on all the allowed output voltage range: if the trimming operation is performed at VOUT(MIN),
then on pin CGA the maximum residual voltage will be present at VOUT(MAX) and its value will be:
1 – 2 ⋅ δ OPT
R CGA ⋅ ( V OUT (MAX ) – V OUT ( MIN ) ) ⋅ ----------------------------------------------------------------------------δ OPT ⋅ ( R K ⋅ δ OPT – R K – R G )
To simplify the procedure, the following step-by step process can be used:
■ a trimmer has to be placed between sense pins of each section: the value of the trimmer resistance
must be at least one order of magnitude higher than RG and it has to be set at one half of its range
(δ=0.5);
■ once the application is running at a load defined by the designer based on the required sharing
accuracy, the master section has to be located;
■ on the slave sections it is then necessary to operate on the trimmer to make equal the output currents.
REFERENCE
[1] "L6910 - Adjustable step down controller with synchronous rectification" (Datasheet)
[2] "L6911 - 5 bit programmable step down controller with synchronous rectification" (Datasheet
17/20
L6615
mm
inch
DIM.
MIN.
A
TYP.
MAX.
MIN.
3.32
TYP.
MAX.
0.131
a1
0.51
B
1.15
1.65
0.045
0.065
b
0.356
0.55
0.014
0.022
b1
0.204
0.304
0.008
0.012
0.020
D
E
10.92
7.95
9.75
0.430
0.313
0.384
e
2.54
0.100
e3
7.62
0.300
e4
7.62
0.300
F
6.6
0.260
I
5.08
0.200
L
Z
18/20
3.18
OUTLINE AND
MECHANICAL DATA
3.81
1.52
0.125
0.150
0.060
Minidip
L6615
mm
DIM.
MIN.
TYP.
A
a1
inch
MAX.
MIN.
TYP.
1.75
0.1
0.25
a2
MAX.
0.069
0.004
0.010
1.65
0.065
a3
0.65
0.85
0.026
0.033
b
0.35
0.48
0.014
0.019
b1
0.19
0.25
0.007
0.010
C
0.25
0.5
0.010
0.020
D (1)
4.8
5.0
0.189
0.197
E
5.8
6.2
0.228
0.244
c1
45° (typ.)
e
1.27
0.050
e3
3.81
0.150
F (1)
3.8
4.0
0.15
0.157
L
0.4
1.27
0.016
0.050
M
S
OUTLINE AND
MECHANICAL DATA
0.6
0.024
SO8
8 ° (max.)
(1) D and F do not include mold flash or protrusions. Mold flash or
potrusions shall not exceed 0.15mm (.006inch).
19/20
L6615
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences
of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted
by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject
to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not
authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics.
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20/20
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