L6668

L6668 SMART PRIMARY CONTROLLER 1 ■ ■ General Features MULTIPOWER BCD TECHNOLOGY LOAD-DEPENDENT CURRENT-MODE CONTROL: FIXED-FREQUENCY (HEAVY LOAD), FREQUENCY FOLDBACK (LIGHT LOAD), BURST-MODE (NO-LOAD) ON-BOARD HIGH-VOLTAGE START-UP IMPROVED STANDBY FUNCTION LOW QUIESCENT CURRENT (< 2 mA) SLOPE COMPENSATION PULSE-BY-PULSE & HICCUP-MODE OCP INTERFACE WITH PFC CONTROLLER DISABLE FUNCTION (ON/OFF CONTROL) LATCHED DISABLE FOR OVP/OTP FUNCTION PROGRAMMABLE SOFT-START 2% PRECISION REFERENCE VOLTAGE EXTERNALLY AVAILABLE ±800 mA TOTEM POLE GATE DRIVER WITH INTERNAL CLAMP AND UVLO PULL-DOWN BLUE ANGEL, ENERGY STAR, EU CODE OF CONDUCT COMPLIANT Figure 1. Package SO-16 (Narrow) ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ Table 1. Order Codes Part Number L6668 L6668TR ■ Package SO-16 SO-16 in Tape & Reel SO16 PACKAGE ECOPACK® 1.1 APPLICATIONS ■ ■ ■ HI-END AC-DC ADAPTERS/CHARGERS FOR NOTEBOOKS. LCD/CRT MONITORS, LCD/CRT TV DIGITAL CONSUMER Figure 2. Block Diagram S-COMP 15 1 HV 5 V CC SLOPE COMP. 16 RCT CLK 25V HV generator ON/OFF and UVLO management Vcc_OK VREG Vref 8 VREF TIMING DIS + 7 2.2V R S Q DIS 15V 4 OUT BLANKING + PWM OCP Q + S R Q N.C. 6 12 ISEN 1.5V HICCUP + - R S Vcc_OK DIS VREG 3 GND HYST. CTRL 0.4mA 13 STANDBY ST-BY PFC_STOP 14 DIS OCP + 2.2/2.7V 0.8V 9 SKIPADJ SS 4R 11R SOFT-START 11 10 COMP January 2006 Rev. 4 1/23 L6668 2 Description L6668 is a current-mode primary controller IC, designed to build single-ended converters. The IC drives the system at fixed frequency at heavy load and an improved Standby function causes a smooth frequency reduction as the load is progressively reduced. At very light load the device enters a special operating mode (burst-mode with fixed, externally programmed peak current) that, in addition to the on-board high-voltage start-up and the very low quiescent current, helps keep low the consumption from the mains and be compliant with energy saving regulations. To allow meeting compliance with these standards in power-factor-corrected systems too, an interface with the PFC controller is provided that enables to turn off the pre-regulator when the load level falls below a threshold. The IC includes also a programmable soft-start, slope compensation for stable operation at duty cycles greater then 50%, a disable function, a leading edge blanking on current sense to improve noise immunity, latched disable for OVP or OTP shutdown and an effective two-level OCP able to protect the system even in case the secondary diode fails short. Table 2. Absolute Maximum Ratings Symbol Vcc VHV IHV --IPFC_STOP VPFC_STOP Ptot Tj Tstg 14 14 Pin 5 1 1 1 Parameter IC Supply voltage (Icc = 20 mA) High-voltage start-up generator voltage range High-voltage start-up generator current Analog Inputs & Outputs, except pin 14 Max. sink current (low state) Max. voltage (open state) Power Dissipation @Tamb = 50°C Junction Temperature Operating range Storage Temperature Value Self-limited -0.3 to 700 Self-limited -0.3 to 8 2 16 0.75 -25 to 150 -55 to 150 Unit V V A V mA V W °C °C Note: 1. ESD immunity for pin 1 is guaranteed up to 900V (Human Body Model). Table 3. Thermal Data Symbol Rth j-amb Parameter Thermal Resistance Junction to AmbientMax Value 120 Unit °C/W Figure 3. Pin Connection (Top view) HV HVS GND OUT Vcc N.C. DIS VREF RCT S-COMP PFC_STOP STBY ISEN SS COMP SKIPADJ 2/23 L6668 Table 4. Pin Description Pin Number 1 Pin Name HV Function High-voltage start-up. The pin is to be connected directly to the rectified mains voltage. A 0.8 mA internal current source charges the capacitor connected between pin Vcc and GND to start up the IC. When the voltage on the Vcc pin reaches the start-up threshold the generator is shut down. Normally it is re-enabled when the voltage on the Vcc pin falls below 5V, except under latched shutdown conditions, when it is re-enabled as the Vcc voltage falls 0.5V below the start-up threshold. High-voltage spacer. The pin is not connected internally to isolate the high-voltage pin and comply with safety regulations (creepage distance) on the PCB. Chip ground. Current return for both the gate-drive current and the bias current of the IC. All of the ground connections of the bias components should be tied to a track going to this pin and kept separate from any pulsed current return. Gate-drive output. The driver is capable of 0.8A min. source/sink peak current to drive MOSFET’s. The voltage delivered to the gate is clamped at about 15V so as to prevent too high values when the IC is supplied with a voltage close to or exceeding 20V. Supply Voltage of both the signal part of the IC and the gate driver. The internal high voltage generator charges an electrolytic capacitor connected between this pin and GND as long as the voltage on the pin is below the start-up threshold of the IC, after that it is disabled. Sometimes a small bypass capacitor (0.1µF typ.) to GND might be useful to get a clean bias voltage for the signal part of the IC. Connect the pin to GND. Latched device shutdown. Internally the pin connects a comparator that, when the voltage on the pin exceeds 2.2V, shuts the IC down and brings its consumption to a value barely higher than before start-up. The information is latched and it is necessary to recycle the input power to restart the IC: the latch is removed as the voltage on the Vcc pin goes below the UVLO threshold. Connect the pin to GND if the function is not used. Voltage reference. An internal generator furnishes an accurate voltage reference (5V±4%, all inclusive) that can be used to supply up to 5 mA to an external circuit. A small film capacitor (0.1µF typ.), connected between this pin and GND is recommended to ensure the stability of the generator and to prevent noise from affecting the reference. Burst-mode control threshold. A voltage is applied to this pin, derived from the reference voltage VREF via a resistor divider. When the control voltage at pin COMP falls 50 mV below the voltage on this pin the IC is shutdown and the consumption is reduced. The chip is re-enabled as the voltage on pin COMP exceeds the voltage on the pin. The high-voltage start-up generator is not invoked. The function is disabled during the soft-start ramp. The pin must always be biased between 0.8 and 2.5V. A voltage between 0.8 and 1.4V disables the function, if the pin is pulled below 0.8V the IC is shut down. Control input for PWM regulation. The pin is to be driven by the phototransistor (emittergrounded) of an optocoupler to modulate the voltage by modulating the current sunk from (sourced by) the pin (0.4 mA typ.). It is recommended to place a small filter capacitor between the pin and GND, as close to the IC as possible to reduce switching noise pick up, to set a pole in the output-to-control transfer function. A voltage 50 mV lower than that on pin SKIPADJ shuts down the IC and reduces its current consumption. Soft start. An internal 20µA generator charges an external capacitor connected between the pin and GND generating a voltage ramp across it. This ramp clamps the voltage at pin COMP during start-up, thus the duty cycle of the power switch starts from zero. During the ramp all functions monitoring the voltage at pin COMP are disabled. The SS capacitor is quickly discharged as the chip goes into UVLO. Current sense (PWM comparator) input. The voltage on this pin is internally compared with an internal reference derived from the voltage on pin COMP and when they are equal the gate drive output (previously asserted high by the clock signal generated by the oscillator) is driven low to turn off the power MOSFET. The pin is equipped with 200 ns. min. blanking time for improved noise immunity. A second comparison level located at 1.5V shuts the device down and brings its consumption almost to a “before start-up” level. 2 3 HVS GND 4 OUT 5 Vcc 6 7 N.C. DIS 8 VREF 9 SKIPADJ 10 COMP 11 SS 12 ISEN 3/23 L6668 Table 4. Pin Description (continued) Pin Number 13 Pin Name STBY Function Standby function. This pin is a high-impedance one as long as the voltage on pin COMP is higher than 3V. When the voltage on pin COMP falls below 3V, the voltage on the pin tracks that on pin COMP and is capable of sinking current. A resistor connected from the pin to the oscillator allows programming frequency foldback at light load. Open-drain ON/OFF control of PFC controller. This pin is intended for driving the base of a PNP transistor in systems comprising a PFC pre-regulator, to stop the PFC controller at light load by cutting its supply. The pin, normally low, opens if the voltage on COMP is lower than 2.2V and goes back low when the voltage on pin COMP exceeds 2.7V. Whenever the IC is shutdown, either latched (DIS >2.2V, ISEN >1.5V) or not (UVLO, SKIPADJ 2.2, or VISEN > 1.5 VSKIPADJ 3V VHV > VHvstart, Vcc > 3V VHV > VHvstart, Vcc = 0 VHV = 400 V 700 60 0.55 80 0.85 105 1 1.6 0.8 40 4.4 5 13 5.6 14 12 V mA mA µA V V After DIS tripping 4/23 L6668 Table 5. Electrical Characteristcs (continued) (Tj = 0 to 105°C, Vcc=15V, Co=1nF; RT =13.3k , CT =1nF; unless otherwise specified) Symbol VREF VREF IREF Parameter Output voltage Total variation Short circuit current Sink capability in UVLO PWM CONTROL VCOMPH ICOMP RCOMP Dmax Dmin IISEN tLEB td(H-L) VISENx VISENdis Vdrop Vth Maximum level Max. source current Dynamic resistance Maximum duty cycle Minimum duty cycle Input Bias Current Leading Edge Blanking Delay to Output Gain Maximum signal Hiccup-mode OCP level VCOMP - VSTBY Threshold on VCOMP Hysteresis LATCHED DISABLE FUNCTION IDIS Vth Input Bias Current Disable threshold VDIS = 0 to Vth (2) (2) Test Condition Min. 4.925 4.8 10 Typ. 5 Max. 5.075 5.13 30 Unit V V mA V V REFERENCE VOLTAGE Tj = 25 °C; IREF = 1 mA Vcc= 9.4 to 22 V, IREF = 1 to 5 mA VREF = 0 Vcc = 6V; Isink = 0.5 mA ICOMP =0 VCOMP = 1 V VCOMP = 2 to 4 V VCOMP = 5 V VCOMP = 1 V VISEN = 0 After gate drive low-to-high transition 0.2 5.5 320 70 400 22 0.5 480 75 0 -1 µA kΩ % % µA ns ns V/V V V mV V mV CURRENT SENSE COMPARATOR 160 225 290 100 3.56 VCOMP = 5 V (2) 3.75 0.8 1.5 35 3 3.94 0.875 1.65 0.725 1.35 STANDBY FUNCTION ISTBY = 0.8 mA, VCOMP2.2V” in the table 4 pin 14. 22/23 L6668 Information furnished is believed to be accurate and reliable. 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