L6711TR

L6711 3 Phase controller with dynamic VID and selectable DACs Features ■ 2A integrated gate drivers ■ Fully differential current reading across inductor or LS MOSFET ) s ( t c u d ) ro s Description P ( t c e t u e d l o o r s P b e O t e l ) o s ( s t b c u O d o ) r s P ( t c e t u e l d o o r s Applications P b O e t e l o s b OOrder codes ■ 0.5% Output voltage accuracy ■ 6 bit programmable output from 0.8185V to 1.5810V in 12.5mV steps ■ 5 bit programmable output from 0.800V to 1.550V in 25mV steps ■ Dynamic VID management ■ Adjustable reference voltage offset ■ 3% active current sharing accuracy ■ Digital 2048 step soft-start ■ Programmable over voltage protection ■ Integrated temperature sensor ■ Constant over current protection ■ Oscillator internally fixed at 150kHz (450kHz ripple) externally adjustable ■ Output enable ■ Integrated remote sense buffer ■ TQFP48 7x7 Package with exposed pad TQFP48 (Exposed Pad) The device implements a three phase step-down controller with a 120° phase-shift between each phase with integrated high current drivers in a compact 7x7mm body package with exposed pad. The device embeds selectable DAC: the output voltage ranges from 0.8185V to 1.5810V with 12.5mV steps (VID_SEL = OPEN) or from 0.800V to 1.550V with 25mV steps (VID_SEL = GND; VID5 drives an optional +25mV offset) managing dynamic VID with 0.5% accuracy over line and temp variations. Additional programmable offset can be added to the voltage reference with a single external resistor. The device assures a fast protection against load over current and load over/under voltage. An internal crowbar is provided turning on the low side mosfet if an over-voltage is detected. ■ High current VRM/VRD for desktop / Server / Workstation CPUs In case of over-current, the system works in Constant Current mode until UVP. ■ High density DC/DC Converters Selectable current reading adds flexibility in system design. April 2006 Part Number Package Packing L6711 TQFP48 Tube L6711TR TQFP48 Tape & Reel Rev 4 1/50 www.st.com 50 Contents L6711 Contents 1 2 Typical application circuit and block diagram . . . . . . . . . . . . . . . . . . . . 4 1.1 Application circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 1.2 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Pins description and connection diagrams . . . . . . . . . . . . . . . . . . . . . . 7 2.1 Pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 ) s ( t c u d o ) r s ( P t c e t u e d l o o r s P b e O t e l ) o s ( s t b c u O d o ) r s P ( t c e t u e l d o o r s P b O e t e l o s b O 3 Maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 3.1 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 3.2 Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 4 Electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 5 VID Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 6 Device description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 7 Current reading and current sharing control loop . . . . . . . . . . . . . . . . 19 7.1 Low-side current reading . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 7.2 Inductor current reading . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 8 DAC Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 9 Remote voltage sense . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 10 Voltage positioning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 11 2/50 10.1 Droop function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 10.2 Offset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 10.3 Integrated thermal sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Dynamic VID transitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 11.1 VID_SEL = OPEN. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 11.2 VID_SEL = GND. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 L6711 Contents 12 Enable and disable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 13 Soft start . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 14 Output voltage monitor and protections . . . . . . . . . . . . . . . . . . . . . . . . 33 14.1 UVP protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 14.2 Programmable OVP protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 14.3 Preliminary OVP protection (Pre-OVP) . . . . . . . . . . . . . . . . . . . . . . . . . . 33 14.4 Over current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 14.5 Low side sense overcurrent (CS_SEL=OPEN) . . . . . . . . . . . . . . . . . . . . 35 ) s ( t c u d o ) r s ( P t c e t u e d l o o r s P b e O t e l ) o s ( s t b c u O d o ) r s P ( t c e t u e l d o o r s P b O e t e l o s b O 14.6 14.5.1 TON Limited output voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 14.5.2 Constant current operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Inductor sense over current (CS_SEL = SGND) . . . . . . . . . . . . . . . . . . . 37 15 Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 16 Driver section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 16.1 Power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 17 System control loop compensation . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 18 Layout guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 18.1 Power connections. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 18.2 Power connections related. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 18.3 Current sense connections. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 19 Embedding L6711-based VRDs... . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 20 TQFP48 Mechanical data & package dimensions . . . . . . . . . . . . . . . . 48 21 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 3/50 Typical application circuit and block diagram L6711 1 Typical application circuit and block diagram 1.1 Application circuit Figure 1. Typical application circuit for LS MOSFET current sense VIN LIN 1 GNDIN 41 38 CIN VCCDR1 VCCDR2 VCCDR3 BOOT1 45 ) s ( t c u d o ) r s ( P t c e t u e d l o o r s P b e O t e l ) o s ( s t b c u O d o ) r s P ( t c e t u e l d o o r s P b O e t e l o s b O 4 5,31 22 6 UGATE1 VCC PHASE1 SGND LGATE1 OSC/FAULT OFFSET PGND1 CS1- 20 21 9 TC CS1+ CS_SEL BOOT2 OVP 23 VID5 28 VID4 27 VID3 26 VID2 25 VID1 24 VID0 29 VID_SEL 13 OUTEN L6711 UGATE2 VID5 VID4 VID3 VID2 VID1 PHASE2 LGATE2 PGND2 VID0 CS2- VID_SEL OUTEN CS2+ BOOT3 7 COMP UGATE3 CF RF PHASE3 8 FB LGATE3 PGND3 RFB 10 11 12 L6711 REF. SCH. (MOSFET) 4/50 CS3- VSEN CS3+ FBR FBG SS_END N.C. 37 N.C. 48 46 HS1 L1 47 2 LS1 3 14 Rg 15 Rg 44 43 HS2 42 Vcc_core L2 40 COUT LS2 LOAD 39 16 Rg 17 Rg 34 33 HS3 32 L3 36 LS3 35 18 Rg 19 Rg 30 SS_END L6711 Typical application circuit and block diagram Figure 2. Typical application circuit for inductor DCR current sense VIN LIN 1 GNDIN 41 38 4 5,31 22 6 CIN VCCDR1 VCCDR2 VCCDR3 BOOT1 UGATE1 VCC PHASE1 SGND LGATE1 OSC/FAULT OFFSET 45 46 HS1 47 L1 2 LS1 Rg(RC) 3 ) s ( t c u d o ) r s ( P t c e t u e d l o o r s P b e O t e l ) o s ( s t b c u O d o ) r s P ( t c e t u e l d o o r s P b O e t e l o s b O PGND1 CS1- 20 21 9 TC CS1+ CS_SEL BOOT2 OVP 23 VID5 28 VID4 27 VID3 26 VID2 25 VID1 24 VID0 29 VID_SEL 13 OUTEN L6711 UGATE2 VID5 VID4 VID3 VID2 VID1 PHASE2 LGATE2 PGND2 VID0 CS2- VID_SEL OUTEN CS2+ BOOT3 7 COMP UGATE3 CF RF PHASE3 8 FB LGATE3 PGND3 RFB 10 11 12 L6711 REF. SCH. (INDUCTOR) CS3- VSEN CS3+ FBR FBG SS_END N.C. 37 Cg 14 Rg 15 Rg(a) 44 43 HS2 42 Vcc_core L2 40 LS2 Rg(RC) COUT LOAD 39 Cg 16 Rg 17 Rg(a) 34 33 HS3 32 L3 36 LS3 Rg(RC) 35 Cg 18 R 19 Rg(a) SS_END 30 N.C. 48 5/50 Typical application circuit and block diagram Block diagram OUTEN OUTEN HS1 HS1 3 PHASE OSCILLATOR LS2 PGND3 LGATE3 LS3 12.5µA LOGIC PWM ADAPTIVE ANTI CROSS CONDUCTION CURRENT SHARING CORRECTION PWM1 VCCDR3 PHASE3 HS3 LOGIC PWM ADAPTIVE ANTI CROSS CONDUCTION CURRENT SHARING CORRECTION UGATE3 BOOT3 PGND2 LGATE2 VCCDR2 PHASE2 UGATE2 HS2 LOGIC PWM ADAPTIVE ANTI CROSS CONDUCTION OSC BOOT2 PGND1 LGATE1 PHASE1 VCCDR1 Block diagram BOOT1 Figure 3. UGATE1 1.2 L6711 OVP OVP VCC CURRENT SHARING CORRECTION PWM2 VCC SGND PWM3 ) s ( t c u d o ) r s ( P t c e t u e d l o o r s P b e O t e l ) o s ( s t b c u O d o ) r s P ( t c e t u e l d o o r s P b O e t e l o s b O CS_SEL PWM1 PWM2 AVERAGE CURRENT TC PWM3 DIGITAL SOFT START OUTEN VCC TEMPERATURE COMPENSATION VCCDR CS_SEL L6711 CONTROL LOGIC AND PROTECTIONS OCP1 OCP2 CH3 CURRENT READING DAC WITH DYNAMIC VID CONTROL CH2 CURRENT READING OCP3 VID5 OFFSET CH1 CURRENT READING TOTAL CURRENT IDROOP VID4 IOS VID3 CS2- CS2+ OCP2 ITC VID2 CS3+ OCP3 VID0 VID1 CS3- OVP 115% / OVP CS1- CS1+ OCP1 64k VID_SEL 64k SS_END ERROR AMPLIFIER IOS REMOTE BUFFER 64k 6/50 FBG FBR VSEN COMP FB OFFSET IFB 1.240V 64k L6711 Pins description and connection diagrams VID1 VID2 VID3 VID4 VID_SEL SS_END SGND PHASE3 UGATE3 Pins connection (top view) BOOT3 Figure 4. PGND3 Pins description and connection diagrams LGATE3 2 36 35 34 33 32 31 30 29 28 27 26 25 37 24 VID0 VCCDR3 38 23 VID5 PGND2 39 22 OSC / FAULT LGATE2 40 21 CS_SEL VCCDR2 41 20 TC PHASE2 42 19 CS3+ UGATE2 43 18 CS3- BOOT2 44 17 CS2+ BOOT1 45 16 CS2- UGATE1 46 15 CS1+ PHASE1 47 14 CS1- N.C. 48 13 OUTEN N.C. ) s ( t c u d o ) r s ( P t c e t u e d l o o r s P b e O t 2.1 Pin descriptions e l ) o s ( s t b c u O d o ) r s P ( t c e t u e l d o o r s P b O e t e l o s b O Table 1. 5 6 7 8 LGATE1 PGND1 VCC SGND OFFSET COMP FB 9 10 11 12 FBG 4 FBR 3 VSEN 2 OVP 1 VCCDR1 L6711 Pins description N° Name 1 VCCDR1 Channel 1 LS driver supply: it can be varied from 5V to 12V buses. It must be connected together with other VCCDRx pins. Filter locally with at least 1µF ceramic cap vs. PGND1. 2 LGATE1 Channel 1 LS driver output. A little series resistor helps in reducing device-dissipated power. 3 PGND1 Channel 1 LS driver return path. Connect to Power Ground Plane. 4 VCC 5 SGND 6 OFFSET 7 COMP Description Device supply voltage. The operative supply voltage is 12V ±15%. Filter with 1µF capacitor (Typ.) vs. SGND. All the internal references are referred to this pin. Connect it to the PCB signal ground. Offset programming pin, internally fixed at 1.240V. Short to SGND to disable the offset generation or connect through a resistor ROFFSET to SGND to program an offset (positive or negative, depending on TC status) to the regulated output voltage as reported in the relative section. This pin is connected to the error amplifier output and is used to compensate the control feedback loop. 7/50 Pins description and connection diagrams Table 1. L6711 Pins description (continued) N° Name 8 FB This pin is connected to the error amplifier inverting input and is used to compensate the voltage control feedback loop. Connecting a resistor between this pin and VSEN pin allows programming the droop effect. OVP Over Voltage protection setup pin: it allows programming the OVP intervention. Internally pulled-up to 5V, it sources a constant 12.5µA current. Leaving the pin floating the OVP threshold is set to 115% (Typ.) of the programmed voltage Connecting a resistor ROVP to SGND, it sets the OVP threshold to a fixed programmable voltage (see relevant section for further details). Filter with 10nF vs. SGND in this case. 9 Description Manages Over&Under-voltage conditions. It is internally connected with the output of the Remote Sense Buffer for Remote Sense of the regulated voltage. If no Remote Sense is implemented, connect it directly to the regulated voltage in order to manage OVP and UVP. ) s ( t c u d o ) r s ( P t c e t u e d l o o r s P b e O t e l ) o s ( s t b c u O d o ) r s P ( t c e t u e l d o o r s P b O e t e l o s b O 10 VSEN 11 FBR Remote sense buffer non-inverting input. It has to be connected to the positive side of the load to perform a remote sense. 12 FBG Remote sense buffer inverting input. It has to be connected to the negative side of the load to perform a remote sense. 13 14 15 16 8/50 OUTEN Output Enable pin; internally 3V pulled-up, it can be pulled-up with a resistor up to 3.3V. If forced to a voltage lower than 0.3V, the device stops operation with all mosfets OFF: all the protections are disabled in this condition except pre-OVP. Cycle this pin to recover latch from protections; filter with 1nF (Typ.) capacitor vs. SGND. CS1- Channel 1 Current Sense Negative Input pin. It must be connected through an Rg resistor to the LS mosfet drain (or to the LS-side of the sense resistor placed in series to the LS mosfet) if LS mosfet sense is performed (CS_SEL=OPEN). Otherwise (CS_SEL=SGND), it must be connected to the output-side of the output inductor (or the output-side of the sense resistor used and placed between the channel 1 inductor and the output of the converter) through Rg resistor. The net connecting the pin to the sense point must be routed as close as possible to the CS1+ net in order to couple in common mode any picked-up noise. CS1+ Channel 1 Current Sense Positive Input pin. It must be connected through an Rg resistor to the LS mosfet source (or to the GND-side of the sense resistor placed in series to the LS mosfet) if LS mosfet sense is performed (CS_SEL=OPEN). Otherwise (CS_SEL=SGND), it must be connected to the phase-side of the output inductor (or the inductor-side of the sense resistor used and placed between the channel 1 inductor and the output of the converter) through Rg resistor and an R-C network across the inductor. The net connecting the pin to the sense point must be routed as close as possible to the CS1net in order to couple in common mode any picked-up noise. CS2- Channel 2 Current Sense Negative Input pin. It must be connected through an Rg resistor to the LS mosfet drain (or to the LS-side of the sense resistor placed in series to the LS mosfet) if LS mosfet sense is performed (CS_SEL=OPEN). Otherwise (CS_SEL=SGND), it must be connected to the output-side of the output inductor (or the output-side of the sense resistor used and placed between the channel 2 inductor and the output of the converter) through Rg resistor. The net connecting the pin to the sense point must be routed as close as possible to the CS2+ net in order to couple in common mode any picked-up noise. L6711 Table 1. N° 17 Pins description and connection diagrams Pins description (continued) Name Description CS2+ Channel 2 Current Sense Positive Input pin. It must be connected through an Rg resistor to the LS mosfet source (or to the GND-side of the sense resistor placed in series to the LS mosfet) if LS mosfet sense is performed (CS_SEL=OPEN). Otherwise (CS_SEL=SGND), it must be connected to the phase-side of the output inductor (or the inductor-side of the sense resistor used and placed between the channel 2 inductor and the output of the converter) through Rg resistor and an R-C network across the inductor. The net connecting the pin to the sense point must be routed as close as possible to the CS2net in order to couple in common mode any picked-up noise. CS3- Channel 3 Current Sense Negative Input pin. It must be connected through an Rg resistor to the LS mosfet drain (or to the LS-side of the sense resistor placed in series to the LS mosfet) if LS mosfet sense is performed (CS_SEL=OPEN). Otherwise (CS_SEL=SGND), it must be connected to the output-side of the output inductor (or the output-side of the sense resistor used and placed between the channel 3 inductor and the output of the converter) through Rg resistor. The net connecting the pin to the sense point must be routed as close as possible to the CS3+ net in order to couple in common mode any picked-up noise. CS3+ Channel 3 Current Sense Positive Input pin. It must be connected through an Rg resistor to the LS mosfet source (or to the GND-side of the sense resistor placed in series to the LS mosfet) if LS mosfet sense is performed (CS_SEL=OPEN). Otherwise (CS_SEL=SGND), it must be connected to the phase-side of the output inductor (or the inductor-side of the sense resistor used and placed between the channel 3 inductor and the output of the converter) through Rg resistor and an R-C network across the inductor. The net connecting the pin to the sense point must be routed as close as possible to the CS3net in order to couple in common mode any picked-up noise. ) s ( t c u d o ) r s ( P t c e t u e d l o o r s P b e O t e l ) o s ( s t b c u O d o ) r s P ( t c e t u e l d o o r s P b O e t e l o s b O 18 19 20 21 22 TC Temperature Compensation pin. Connect through a resistor RTC and filter with 10nF vs. SGND to program the temperature compensation effect. Short to SGND to disable the compensation effect. CS_SEL Current Reading Selection pin, internally 5V pulled-up. Leave floating to sense current across low-side mosfets or a sense resistor placed in series to the LS mosfet source. Maximum duty cycle is dynamically limited and Track&Hold is enabled to assure proper reading of the current. Short to SGND to read current across inductors or a sense resistor placed in series to the output inductors. No duty cycle limitation and no Track&Hold performed in this case. OSC / FAULT Oscillator pin. It allows programming the switching frequency of each channel: the equivalent switching frequency at the load side results in being tripled. Internally fixed at 1.24V, the frequency is varied proportionally to the current sunk (forced) from (into) the pin with an internal gain of 6kHz/µA (See relevant section for details). If the pin is not connected, the switching frequency is 150kHz for each channel (450kHz on the load). The pin is forced high (5V Typ.) when an Over/Under Voltage is detected; to recover from this condition, cycle VCC or the OUTEN pin. 9/50 Pins description and connection diagrams Table 1. N° 23, 24 to 28 29 L6711 Pins description (continued) Name Description VID5, VID0-4 Voltage IDentification pins. Internally pulled-up to 3V, connect to SGND to program a logic ‘0’ while leave floating (as well as pull-up with a resistor up to 3.3V) to program a logic ‘1’. They are used to program the output voltage as specified in Table 5 and Table 6 together with VID_SEL and to set the OVP/UVP protection thresholds accordingly. See relevant section for details about DAC selection. VID_SEL VID_SELect pin. Through this pin it is possible to select the DAC table used for the regulation. Leave floating to use a VRD10.x compliant DAC (See Table 1) while short to SGND to use a VRM-Hammer compliant DAC (See Table 3). See relevant section for details about DAC selection. ) s ( t c u d o ) r s ( P t c e t u e d l o o r s P b e O t e l ) o s ( s t b c u O d o ) r s P ( t c e t u e l d o o r s P b O e t e l o s b O 30 SS_END Soft start end signal. It is an open collector output, set free after finishing the soft start. Pull-up with a resistor to a voltage lower than 5V, if not used may be left floating. 31 SGND All the internal references are referred to this pin. Connect it to the PCB signal ground. 32 PHASE3 Channel 3 HS driver return path. It must be connected to the HS3 mosfet source and provides the return path for the HS driver of channel 3. 33 UGATE3 Channel 3 HS driver output. A little series resistor helps in reducing device-dissipated power. 34 BOOT3 Channel 3 HS driver supply. This pin supplies the relative high side driver. Connect through a capacitor (100nF Typ.) to the PHASE3 pin and through a diode to VCC (cathode vs. boot). 35 PGND3 Channel 3 LS driver return path. Connect to Power Ground Plane. 36 LGATE3 Channel 3 LS driver output. A little series resistor helps in reducing device-dissipated power. 37 N.C. 38 VCCDR3 39 PGND2 Channel 2 LS driver return path. Connect to Power Ground Plane. 40 LGATE2 Channel 2 LS driver output. A little series resistor helps in reducing device-dissipated power. 41 VCCDR2 Channel 2 LS driver supply: it can be varied from 5V to 12V buses. It must be connected together with other VCCDRx pins. Filter locally with at least 1µF ceramic cap vs. PGND2. 42 PHASE2 Channel 2 HS driver return path. It must be connected to the HS2 mosfet source and provides the return path for the HS driver of channel 2. 43 UGATE2 Channel 2 HS driver output. A little series resistor helps in reducing device-dissipated power. 44 BOOT2 Channel 2 HS driver supply. This pin supplies the relative high side driver. Connect through a capacitor (100nF Typ.) to the PHASE2 pin and through a diode to VCC (cathode vs. boot). 10/50 Not internally connected. Channel 3 LS driver supply: it can be varied from 5V to 12V buses. It must be connected together with other VCCDRx pins. Filter locally with at least 1µF ceramic cap vs. PGND3. L6711 Pins description and connection diagrams Table 1. Pins description (continued) N° Name Description 45 BOOT1 Channel 1 HS driver supply. This pin supplies the relative high side driver. Connect through a capacitor (100nF Typ.) to the PHASE1 pin and through a diode to VCC (cathode vs. boot). 46 UGATE1 Channel 1 HS driver output. A little series resistor helps in reducing device-dissipated power. 47 PHASE1 Channel 1 HS driver return path. It must be connected to the HS1 mosfet source and provides the return path for the HS driver of channel 1. 48 N.C. Not internally connected. ) s ( t c u d o ) r s ( P t c e t u e d l o o r s P b e O t e l ) o s ( s t b c u O d o ) r s P ( t c e t u e l d o o r s P b O e t e l o s b O PAD Thermal pad connects the silicon substrate and makes a good thermal contact with the PCB to THERMAL dissipate the power necessary to drive the external mosfets. Connect to the GND plane with PAD several vias to improve thermal conductivity. 11/50 Maximum ratings L6711 3 Maximum ratings 3.1 Absolute maximum ratings Table 2. Absolute maximum ratings Symbol Parameter Value Unit 15 V 15 V VCC, VCCDRx To PGNDx VBOOTxVPHASEx Boot Voltage VUGATExVPHASEx All other pins to PGNDx ete Pr ol Maximum Withstanding Voltage Range Test Condition: CDF-AEC-Q100-002”Human Body Model” OTHER PINS Acceptance Criteria: “Normal Performance” bs Thermal data e t e l o s b O s b O 12/50 s ( t c u d o Pr ) s ( ct o s b O Parameter du TMAX Maximum junction temperature TSTG Storage temperature range TJ PTOT e t le Thermal Resistance Junction to Ambient (Device soldered on 2s2p PC Board) o r P e t e l o O ) Thermal data Symbol RthJA -0.3 to 5 -0.3 to 7 uc Sustainable Positive Peak Voltage. T>R L; ESR