L6713A

L6713A 2/3 phase controller with embedded drivers for Intel VR10, VR11 and AMD 6 bit CPUs Features ■ Load transient boost LTB Technology™ to minimize the number of output capacitors (patent pending) Dual-edge asynchronous PWM Selectable 2 or 3 phase operation 0.5 % output voltage accuracy 7/8 bit programmable output up to 1.60000 V Intel VR10.x, VR11 DAC 6 bit programmable output up to 1.5500 V AMD 6 bit DAC High current integrated gate drivers Full differential current sensing across inductor Embedded VRD thermal monitor Differential remote voltage sensing Dynamic VID management Adjustable voltage offset Low-side-less startup Programmable soft-start Programmable over voltage protection Preliminary over voltage protection Programmable over current protection Adjustable switching frequency Output enable SS_END / PGOOD signal TQFP64 10x10 mm package with exposed pad TQFP64 (Exposed pad) ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ Description L6713A implements a two/three phase step-down controller with 180º/120º phase-shift between each phase with integrated high current drivers in a compact 10x10 mm body package with exposed pad.The 2 or 3 phase operation can be easily selected through PHASE_SEL pin. Load transient boost LTB Technology™ (patent pending) reduces system cost by providing the fastest response to load transition therefore requiring less bulk and ceramic output capacitors to satisfy load transient requirements. LTB Technology™ can be disabled and in this condition the device works as a dual-edge asynchronous PWM. The device embeds selectable DACs: the output voltage ranges up to 1.60000 V (both Intel VR10.x and VR11 DAC) or up to 1.5500 V (AMD 6BIT DAC) managing D-VID with ± 0.5% output voltage accuracy over line and temperature variations. The controller assures fast protection against load over current and under / over voltage (in this last case also before UVLO). In case of over-current the device turns off all MOSFET and latches the condition. System thermal monitor is also provided allowing system protection from over-temperature conditions. Package Packaging Tube Applications ■ ■ ■ High current VRD for desktop CPUs Workstation and server CPU power supply VRM modules Table 1. Device summary Order codes L6713A TQFP64 (Exposed pad) L6713ATR August 2008 Rev 3 Tape and reel 1/64 www.st.com 64 Contents L6713A Contents 1 2 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Pin settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2.1 2.2 Pin connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 3 Electrical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 3.1 3.2 Maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 4 5 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 VID Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 5.1 5.2 5.3 5.4 5.5 Mapping for the Intel VR11 mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Voltage identification (VID) for Intel VR11 mode . . . . . . . . . . . . . . . . . . . 16 Voltage identifications (VID) for Intel VR10 mode + 6.25 mV . . . . . . . . . . 18 Mapping for the AMD 6 bit mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Voltage identifications (VID) codes for AMD 6 bit mode . . . . . . . . . . . . . . 20 6 7 8 Reference schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Device description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Configuring the device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 8.1 8.2 Number of phases selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 DAC selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 9 10 11 Power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Current reading and current sharing loop . . . . . . . . . . . . . . . . . . . . . . 32 Differential remote voltage sensing . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 2/64 L6713A Contents 12 Voltage positioning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 12.1 12.2 Offset (Optional) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Droop function (Optional) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 13 Load transient boost technology™ . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 13.1 LTB™ gain modification (Optional) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 14 15 16 Dynamic VID transitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Enable and disable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 Soft-start . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 16.1 Intel mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 16.1.1 16.1.2 SS/LTB/AMD connections when using LTB™ gain = 2 . . . . . . . . . . . . . 43 SS/LTB/AMD connections when using LTB™ gain < 2 . . . . . . . . . . . . . 44 16.2 16.3 AMD mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 Low-side-less startup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 17 Output voltage monitor and protections . . . . . . . . . . . . . . . . . . . . . . . . 47 17.1 17.2 17.3 17.4 Under voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 Preliminary over voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 Over voltage and programmable OVP . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 PGOOD (only for AMD mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 18 19 20 21 22 Over current protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 Driver section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 System control loop compensation . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 Thermal monitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 3/64 Contents L6713A 23 Tolerance band (TOB) definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 23.1 23.2 23.3 23.4 Controller tolerance (TOBController) . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 Ext. current sense circuit tolerance (TOBCurrSense) . . . . . . . . . . . . . . . 56 Time constant matching error tolerance (TOBTCMatching) . . . . . . . . . . 56 Temperature measurement error (VTC) . . . . . . . . . . . . . . . . . . . . . . . . . . 57 24 Layout guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 24.1 24.2 Power components and connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 Small signal components and connections . . . . . . . . . . . . . . . . . . . . . . . 59 25 26 27 Embedding L6713A - based VR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 4/64 L6713A Block diagram 1 Block diagram Figure 1. Block diagram VCCDR1 VCCDR2 VCCDR3 PHASE1 PHASE2 PHASE3 UGATE1 UGATE2 UGATE3 LGATE1 LGATE2 LGATE3 PGND1 PGND2 PGND3 BOOT1 BOOT2 BOOT3 SS_END / PGOOD HS1 LS1 LOGIC PWM ADAPTIVE ANTI CROSS CONDUCTION CURRENT SHARING CORRECTION VR_HOT HS2 LS2 LOGIC PWM ADAPTIVE ANTI CROSS CONDUCTION CURRENT SHARING CORRECTION HS3 LS3 VR_FAN LOGIC PWM ADAPTIVE ANTI CROSS CONDUCTION CURRENT SHARING CORRECTION 3.600V 2/3 PHASE OSCILLATOR OSC / FAULT LTB LTB LTB PWM1 PWM2 PWM3 3.200V TM SS/ LTBG/ AMD PWM1 DIGITAL SOFT START VCC VCCDR OUTEN SSOSC/AMD PWM2 PWM3 AVERAGE CURRENT CH1 CURRENT READING CS1CS1+ VID0 VID1 VID2 VID3 VID4 VID5 VID6 VID7 / D-VID VID_SEL 12.5μA L6713A CONTROL LOGIC AND PROTECTIONS OCP CH2 CURRENT READING CS2CS2+ DAC WITH DYNAMIC VID CONTROL IDROOP TOTAL DELIVERED CURRENT +175mV / 1.800V / OVP OVP COMPARATOR TO OCP IOFFSET IOCSET CH3 CURRENT READING VCC CS3CS3+ VCC 12.5μA VREF OUTEN GND DROP RECOVERY ERROR AMPLIFIER LTB OCP COMPARATOR 12.5μA +.1240V SGND OVP PHASE_SEL VSEN LTB FB PHASE _SEL DROOP COMP FBG OUTEN OCSET OVP 5/64 Pin settings L6713A 2 2.1 Pin settings Pin connection Figure 2. Pin connection (top view) VR_FAN VR_HOT SS_END / PGOOD VID0 VID1 VID2 VID3 VID4 VID5 VID6 VID7 / D-VID OSC / FAULT FBG OCSET VID_SEL OVP TM SGND N.C. N.C. N.C. PGND2 LGATE2 VCCDR2 VCCDR3 LGATE3 PGND3 PGND1 LGATE1 VCCDR1 PHASE1 N.C. 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 31 30 29 28 27 26 L6713A 25 24 23 22 21 20 19 18 17 SS / LTBG / AMD CS1CS1+ CS3CS3+ CS2CS2+ N.C. N.C. COMP FB DROOP VSEN SGND LTB OUTEN 6/64 UAGTE1 BOOT1 N.C. PHASE3 UGATE3 BOOT3 N.C. PHASE2 UGATE2 BOOT2 N.C. N.C. N.C. N.C. VCC PHASE_SEL L6713A Pin settings 2.2 Pin description Table 2. N° 1 Pin description Pin UGATE1 Function Channel 1 HS driver output. A small series resistors helps in reducing device-dissipated power. Channel 1 HS driver supply. Connect through a capacitor (100 nF typ.) to PHASE1 and provide necessary Bootstrap diode. A small resistor in series to the boot diode helps in reducing Boot capacitor overcharge. Not internally connected. Channel 3 HS driver return path. It must be connected to the HS3 MOSFET source and provides return path for the HS driver of channel 3. Channel 3 HS driver output. A small series resistors helps in reducing device-dissipated power. Channel 3 HS driver supply. Connect through a capacitor (100 nF typ.) to PHASE3 and provide necessary Bootstrap diode. A small resistor in series to the boot diode helps in reducing Boot capacitor overcharge. Not internally connected. Channel 2 HS driver return path. It must be connected to the HS2 MOSFET source and provides return path for the HS driver of channel 2. Leave floating when using 2 phase operation. Channel 2 HS driver output. A small series resistors helps in reducing device-dissipated power. Leave floating when using 2 phase operation. Channel 2 HS driver supply. Connect through a capacitor (100 nF typ.) to PHASE2 and provide necessary Bootstrap diode. A small resistor in series to the boot diode helps in reducing Boot capacitor overcharge.Leave floating when using 2 phase operation. Not internally connected. Not internally connected. Not internally connected. Not internally connected. Device supply voltage. The operative voltage is 12 V ±15 %. Filter with 1 µF (typ) MLCC vs. SGND. Phase selection pin. Internally pulled up by 12.5 µA(typ) to 5 V. It allows selecting between 2 phase and 3 phase operation. See Table 11 for details. 2 BOOT1 3 4 N.C. PHASE3 5 UGATE3 6 BOOT3 7 8 N.C. PHASE2 9 UGATE2 10 BOOT2 11 12 13 14 15 N.C. N.C. N.C. N.C. VCC PHASE_ SEL 16 7/64 Pin settings Table 2. N° L6713A Pin description (continued) Pin Function Output enable pin. Internally pulled up by 12.5 µA(typ) to 5 V. Forced low, the device stops operations with all MOSFETs OFF: all the protections are disabled except for Preliminary over voltage. Leave floating, the device starts-up implementing soft-start up to the selected VID code. Cycle this pin to recover latch from protections; filter with 1 nF (typ) vs. SGND. Load transient boost pin. Internally fixed at 1 V, connecting a RLTB - CLTB vs. VOUT allows to enable the Load transient boost technology™: as soon as the device detects a transient load it turns on all the PHASEs at the same time. Short to SGND to disable the function. All the internal references are referred to this pin. Connect to the PCB Signal Ground. It manages OVP and UVP protections and PGOOD (when applicable). See “Output voltage monitor and protections” Section. 100 µA constant current (IOFFSET, See Table 5) is sunk by VSEN pin in order to generate a positive offset in according to the ROFFSET resistor between VSEN pin and VOUT. See “Offset (Optional)” Section for details. A current proportional to the total current read is sourced from this pin according to the current reading gain. Short to FB to implement droop function or short to SGND to disable the function. Connecting to SGND through a resistor and filtering with a capacitor, the current info can be used for other purposes. Error amplifier inverting input. Connect with a resistor RFB vs. VSEN and with an RF - CF vs. COMP. Error amplifier output. Connect with an RF - CF vs. FB. The device cannot be disabled by pulling down this pin. Not internally connected. Not internally connected. Channel 2 current sense positive input. Connect through an R-C filter to the phase-side of the channel 2 inductor. Short to SGND or to VOUT when using 2 Phase operation. See “Layout guidelines” Section for proper layout of this connection. Channel 2 current sense negative input. Connect through a Rg resistor to the output-side of the channel 2 inductor. Leave floating when using 2 Phase operation. See “Layout guidelines” Section for proper layout of this connection. Channel 3 current sense positive input. Connect through an R-C filter to the phase-side of the channel 3 inductor. See “Layout guidelines” Section for proper layout of this connection. Channel 3 current sense negative input. Connect through a Rg resistor to the output-side of the channel 3 inductor. See “Layout guidelines” Section for proper layout of this connection. 17 OUTEN 18 LTB 19 SGND 20 VSEN 21 DROOP 22 23 24 25 FB COMP N.C. N.C. 26 CS2+ 27 CS2- 28 CS3+ 29 CS3- 8/64 L6713A Table 2. N° Pin settings Pin description (continued) Pin Function Channel 1 current sense positive input. Connect through an R-C filter to the phase-side of the channel 1 inductor. See “Layout guidelines” Section for proper layout of this connection. Channel 1 current sense negative input. Connect through a Rg resistor to the output-side of the channel 1 inductor. See “Layout guidelines” Section for proper layout of this connection. Soft-start oscillator, LTB gain and AMD selection pin. It allows selecting between INTEL DACs and AMD DAC. Short to SGND to select AMD DAC otherwise INTEL mode is selected. When INTEL mode is selected trough this pin it is possible to select the softstart time and also the gain of LTB Technology™. See “Soft-start” Section” and See “Load transient boost technologyTM” Section for details. Over voltage programming pin. Internally pulled up by 12.5 µA (typ) to 5 V. Leave floating to use built-in protection thresholds as reported into Table 12. Connect to SGND through a ROVP resistor and filter with 100 pF (max) to set the OVP threshold to a fixed voltage according to the ROVP resistor. See “Over voltage and programmable OVP” Section Section for details. Intel mode. Internally pulled up by 12.5 µA (typ) to 5 V. It allows selecting between VR10 (short to SGND, Table 8) or VR11 (floating, See Table 7) DACs. See “Configuring the device” Section for details. AMD mode. Not applicable. Needs to be shorted to SGND. Over current set pin. Connect to SGND through a ROCSET resistor to set the OCP threshold. Connect also a COCSET capacitor to set a delay for the OCP intervention. See “Over current protection” Section for details. Connect to the negative side of the load to perform remote sense. See “Layout guidelines” Section for proper layout of this connection. Oscillator pin. It allows programming the switching frequency FSW of each channel: the equivalent switching frequency at the load side results in being multiplied by the phase number N. Frequency is programmed according to the resistor connected from the pin vs. SGND or VCC with a gain of 8 kHz/µA (see relevant section for details). Leaving the pin floating programs a switching frequency of 200kHz per phase. The pin is forced high (5 V) to signal an OVP FAULT: to recover from this condition, cycle VCC or the OUTEN pin. See “Oscillator” Section for details. 30 CS1+ 31 CS1- 32 SS/ LTBG/ AMD 33 OVP 34 VID_SEL 35 OCSET 36 FBG 37 OSC/ FAULT 38 VID7 - Intel mode. See VID5 to VID0 section. DVID - AMD mode. DVID output. VID7/DVID CMOS output pulled high when the controller is performing a D-VID transition (with 32 clock cycle delay after the transition has finished). See “Dynamic VID transitions” Section Section for details. VID6 Intel mode. See VID5 to VID0 section. AMD mode. Not applicable. Needs to be shorted to SGND. 39 9/64 Pin settings Table 2. N° L6713A Pin description (continued) Pin Function Intel mode. Voltage identification pins (also applies to VID6, VID7). Internally pulled up by 25 µA to 5 V, connect to SGND to program a '0' or leave floating to program a '1'. They allow programming output voltage as specified in Table 7 and Table 8 according to VID_SEL status. OVP and UVP protection comes as a consequence of the programmed code (See Table 12). AMD mode. Voltage identification pins. Internally pulled down by 12.5 µA, leave floating to program a '0' while pull up to more than 1.4 V to program a '1'. They allow programming the output voltage as specified in Table 10 (VID7 doesn’t care). OVP and UVP protection comes as a consequence of the programmed code (See Table 12). Note. VID6 not used, need to be shorted to SGND. SSEND - Intel mode. soft-start end signal. Open drain output sets free after SS has finished and pulled low when triggering any protection. Pull up to a voltage lower than 5 V (typ), if not used it can be left floating. PGOOD - AMD mode. Open drain output set free after SS has finished and pulled low when VSEN is lower than the relative threshold. Pull up to a voltage lower than 5 V (typ), if not used it can be left floating. Voltage regulator hot. Over temperature alarm signal. Open drain output, set free when TM overcomes the alarm threshold. Thermal monitoring output enabled if Vcc > UVLOVCC. See “Thermal monitor” Section for details and typical connections. Voltage regulator fan. Over temperature warning signal. Open drain output, set free when TM overcomes the warning threshold. Thermal monitoring output enabled if Vcc > UVLOVCC. See “Thermal monitor” Section for details and typical connections. Thermal monitor input. It senses the regulator temperature through apposite network and drives VR_FAN and VR_HOT accordingly. Short TM pin to SGND if not used. See “Thermal monitor” Section for details and typical connections. All the internal references are referred to this pin. Connect to the PCB signal Ground. Not internally connected. Not internally connected. Not internally connected. Channel 2 LS driver return path. Connect to power ground plane. It must be connected to power ground plane also when using 2-phase operation. Channel 2 LS driver output. A small series resistor helps in reducing devicedissipated power. Leave floating when using 2 phase operation. 40 to 45 VID5 to VID0 46 SS_END/ PGOOD 47 VR_HOT 48 VR_FAN 49 TM 50 51 52 53 54 SGND N.C. N.C. N.C. PGND2 55 LGATE2 10/64 L6713A Table 2. N° Pin settings Pin description (continued) Pin Function Channel 2 LS driver supply. It must be connected to others VCCDRx pins also when using 2-phase operation. LS driver supply can range from 5 Vbus up to 12 Vbus, filter with 1 µF MLCC cap vs. PGND2. Channel 3 LS driver supply. It must be connected to others VCCDRx pins. LS driver supply can range from 5 Vbus up to 12 Vbus, filter with 1 µF MLCC cap vs. PGND3. Channel 3 LS driver output. A small series resistor helps in reducing devicedissipated power. Channel 3 LS driver return path. Connect to power ground plane. Channel 1 LS driver return path. Connect to power ground plane. Channel 1 LS driver output. A small series resistor helps in reducing devicedissipated power. Channel 1 LS driver supply. It must be connected to others VCCDRx pins. LS driver supply can range from 5 Vbus up to 12 Vbus, filter with 1 µF MLCC cap vs. PGND1. Channel 1 HS driver return path. It must be connected to the HS1 MOSFET source and provides return path for the HS driver of channel 1. Not internally connected. Thermal pad connects the silicon substrate and makes good thermal contact with the PCB to dissipate the power necessary to drive the external MOSFETs. Connect to the PGND plane with several VIAs to improve thermal conductivity. 56 VCCDR2 57 VCCDR3 58 59 60 61 LGATE3 PGND3 PGND1 LGATE1 62 VCCDR1 63 64 PAD PHASE1 N.C. Thermal pad 11/64 Electrical data L6713A 3 3.1 Electrical data Maximum ratings Table 3. Symbol VCC, VCCDRx to PGNDx Absolute maximum ratings Parameter Value 15 15 15 7.5 LGATEx, PHASEx, to PGNDx VID0 to VID7, VID_SEL All other pins to PGNDx Static condition to PGNDx, VCC = 14 V, BOOTx = 7 V, PHASEx = -7.5 V Positive peak voltage to PGNDx; T < 20 ns @ 600 kHz -0.3 to VCC + 0.3 -0.3 to 5 -0.3 to 7 -7.5 Unit V V V V V V V V VBOOTx - VPHASEx Boot voltage VUGATEx - VPHASEx VCC - VBOOTx VPHASEx 26 V 3.2 Thermal data Table 4. Symbol RthJA TMAX TSTG TJ PTOT Thermal data Parameter Thermal resistance junction to ambient (Device soldered on 2s2p PC board) Maximum junction temperature Storage temperature range Junction temperature range Maximum power dissipation at TA = 25 °C Value 40 150 -40 to 150 0 to 125 2.5 Unit °C/W °C °C °C W 12/64 L6713A Electrical characteristics 4 Electrical characteristics VCC = 12 V ± 15 %, TJ = 0 °C to 70 °C, unless otherwise specified Table 5. Symbol Electrical characteristics Parameter Test condition Min. Typ. Max. Unit Supply current ICC ICCDRx IBOOTx Power-ON VCC turn-ON UVLOVCC VCC turn-OFF VCCDR turn-ON UVLOVCCDR VCCDR turn-OFF Pre-OVP turn-ON UVLOOVP Pre-OVP turn-OFF VCC Rising; VCCDRx = 5 V VCC Falling; VCCDRx = 5 V VCCDRx Rising; VCC = 12 V VCCDRx Falling; VCC = 12 V VCC Rising; VCCDRx = 5 V VCC Falling; VCCDRx = 5 V 3.05 3.9 7.3 8.9 7.7 4.5 4.3 3.6 3.3 4.2 4.8 9.3 V V V V V V VCC supply current VCCDRx supply current BOOTx supply current HGATEx and LGATEx = OPEN VCCDRx = BOOTx = 12 V LGATEx = OPEN; VCCDRx = 12 V HGATEx = OPEN; PHASEx to PGNDx VCC = BOOTx = 12 V 17 1 0.75 mA mA mA Oscillator and inhibit FOSC T1 T2 T3 Main oscillator accuracy SS delay time SS time T2 SS time T3 Output enable intel mode Hysteresis OUTEN Output enable AMD mode Input high OUTEN pull-up current ΔVOSC FAULT PWMx ramp amplitude Voltage at pin OSC OVP active OUTEN to SGND 1.40 12.5 3 5 V μA V V Input low 100 0.80 mV V OSC = OPEN OSC = OPEN; TJ = 0 °C to 125 °C Intel mode Intel mode; RSSOSC = 25 kΩ Intel mode Rising thresholds voltage 50 0.80 0.85 0.90 180 175 1 500 200 220 225 kHz ms μs μs V 13/64 Electrical characteristics Table 5. Symbol Reference and DAC Intel mode VID = 1.000 V to VID = 1.600 V FB = VOUT; FBG = GNDOUT kVID Output voltage accuracy AMD mode VID = 1.000 V to VID = 1.550 V FB = VOUT; FBG = GNDOUT Boot voltage VID pull-up current IVID VIDIL VID thresholds VIDIH VID_SEL threshold (Intel mode) VID_SEL pull-up current Error amplifier A0 SR EA DC gain EA slew rate COMP = 10 pF to SGND 80 20 Intel mode; Input high AMD mode; Input high Input low Input high VIDSEL to SGND 0.8 1.35 0.3 0.8 12.5 VID pull-down current Intel mode Intel mode; VIDx to SGND AMD mode; VIDx to 5.4 V Intel mode; Input low AMD mode; Input low -0.6 1.081 25 12.5 0.3 0.8 0.6 L6713A Electrical characteristics (continued) Parameter Test condition Min. Typ. Max. Unit -0.5 - 0.5 % % V μA μA V V V μA VBOOT VID_SEL dB V/μs Differential current sensing and offset ICSx+ I –I INFOx AVG ----------------------------------------I AVG Bias current Current sense mismatch Over current threshold OCSET current accuracy Inductor sense Rg = 1 kΩ; IINFOx = 25 μA VOCSET (OCP) Rg = 1 kΩ 2-PHASE, IOCSET = 60 μA; 3-PHASE, IOCSET = 90 μA; Rg = 1kΩ 2-PHASE, IDROOP = 0 to 40 μA; 3-PHASE, IDROOP = 0 to 60 μA; VSEN = 0.500 V to 1.600 V -3 1.215 -5 0 1.240 3 1.265 5 μA % V % VOCTH KIOCSET kIDROOP IOFFSET Gate driver Droop current deviation from nominal value Offset current -1 90 100 1 110 μA μA tRISE_UGATEx HS rise time IUGATEx RUGATEx HS source current HS sink resistance BOOTx - PHASEx = 10 V; CUGATEx to PHASEx = 3.3 nF BOOTx - PHASEx = 10 V BOOTx - PHASEx = 12 V 1.5 15 2 2 30 ns A 2.5 Ω 14/64 L6713A Table 5. Symbol Electrical characteristics Electrical characteristics (continued) Parameter Test condition VCCDRx = 10 V; CLGATEx to PGNDx = 5.6 nF VCCDRx = 10 V VCCDRx = 12 V 0.7 Min. Typ. 30 1.8 1.1 1.5 Max. 55 Unit ns A Ω tRISE_LGATEx LS rise time ILGATEx RLGATEx Protections LS source current LS sink resistance Intel mode; Before VBOOT OVP Over voltage protection (VSEN rising) Intel mode; Above VID AMD mode Program- IOVP current mable OVP Comparator offset voltage OVP = SGND OVP = 1.8 V UVLOOVP < VCC < UVLOVCC VCC > UVLOVCC & OUTEN = SGND Hysteresis UVP PGOOD VSSEND/ PGOOD 1.300 150 1.700 11.5 -20 175 1.740 12.5 0 1.800 350 -750 -300 200 1.780 13.5 20 V mV V μA mV V mV mV mV Pre-OVP Preliminary over voltage protection Under voltage protection PGOOD threshold SSEND / PGOOD voltage low VSEN falling; Below VID AMD mode; VSEN falling; Below VID I = -4 mA 0.4 V Thermal monitor TM warning (VR_FAN) VTM TM alarm (VR_HOT) TM hysteresis VVR_HOT; VVR_FAN VR_HOT voltage low; VR_FAN voltage low I = -4 mA VTM rising VTM rising 3.420 3.2 3.6 100 0.4 0.4 3.770 V V mV V V 15/64 VID Tables L6713A 5 5.1 VID Tables Mapping for the Intel VR11 mode Table 6. VID7 800 mV Voltage identification (VID) mapping for Intel VR11 mode VID6 400 mV VID5 200 mV VID4 100 mV VID3 50 mV VID2 25 mV VID1 12.5 mV VID0 6.25 mV 5.2 Voltage identification (VID) for Intel VR11 mode Table 7. HEX code 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 0 1 2 3 4 5 6 7 8 9 A B C D E F 0 1 2 3 4 5 6 Voltage identification (VID) for Intel VR11 mode (See Note) Output voltage (1) HEX code 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 5 5 5 5 5 5 5 0 1 2 3 4 5 6 7 8 9 A B C D E F 0 1 2 3 4 5 6 Output voltage (1 ) HEX code 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 9 9 9 9 9 9 9 0 1 2 3 4 5 6 7 8 9 A B C D E F 0 1 2 3 4 5 6 Output voltage (1) HEX code C C C C C C C C C C C C C C C C D D D D D D D 0 1 2 3 4 5 6 7 8 9 A B C D E F 0 1 2 3 4 5 6 Output voltage (1) OFF OFF 1.60000 1.59375 1.58750 1.58125 1.57500 1.56875 1.56250 1.55625 1.55000 1.54375 1.53750 1.53125 1.52500 1.51875 1.51250 1.50625 1.50000 1.49375 1.48750 1.48125 1.47500 1.21250 1.20625 1.20000 1.19375 1.18750 1.18125 1.17500 1.16875 1.16250 1.15625 1.15000 1.14375 1.13750 1.13125 1.12500 1.11875 1.11250 1.10625 1.10000 1.09375 1.08750 1.08125 1.07500 0.81250 0.80625 0.80000 0.79375 0.78750 0.78125 0.77500 0.76875 0.76250 0.75625 0.75000 0.74375 0.73750 0.73125 0.72500 0.71875 0.71250 0.70625 0.70000 0.69375 0.68750 0.68125 0.67500 0.41250 0.40625 0.40000 0.39375 0.38750 0.38125 0.37500 0.36875 0.36250 0.35625 0.35000 0.34375 0.33750 0.33125 0.32500 0.31875 0.31250 0.30625 0.30000 0.29375 0.28750 0.28125 0.27500 16/64 L6713A Table 7. HEX code 1 1 1 1 1 1 1 1 1 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 3 3 3 3 3 3 3 3 7 8 9 A B C D E F 0 1 2 3 4 5 6 7 8 9 A B C D E F 0 1 2 3 4 5 6 7 VID Tables Voltage identification (VID) for Intel VR11 mode (See Note) (continued) Output voltage (1) HEX code 5 5 5 5 5 5 5 5 5 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 7 7 7 7 7 7 7 7 7 8 9 A B C D E F 0 1 2 3 4 5 6 7 8 9 A B C D E F 0 1 2 3 4 5 6 7 Output voltage (1 ) HEX code 9 9 9 9 9 9 9 9 9 A A A A A A A A A A A A A A A A B B B B B B B B 7 8 9 A B C D E F 0 1 2 3 4 5 6 7 8 9 A B C D E F 0 1 2 3 4 5 6 7 Output voltage (1) HEX code D D D D D D D D D E E E E E E E E E E E E E E E E F F F F F F F F 7 8 9 A B C D E F 0 1 2 3 4 5 6 7 8 9 A B C D E F 0 1 2 3 4 5 6 7 Output voltage (1) 1.46875 1.46250 1.45625 1.45000 1.44375 1.43750 1.43125 1.42500 1.41875 1.41250 1.40625 1.40000 1.39375 1.38750 1.38125 1.37500 1.36875 1.36250 1.35625 1.35000 1.34375 1.33750 1.33125 1.32500 1.31875 1.31250 1.30625 1.30000 1.29375 1.28750 1.28125 1.27500 1.26875 1.06875 1.06250 1.05625 1.05000 1.04375 1.03750 1.03125 1.02500 1.01875 1.01250 1.00625 1.00000 0.99375 0.98750 0.98125 0.97500 0.96875 0.96250 0.95625 0.95000 0.94375 0.93750 0.93125 0.92500 0.91875 0.91250 0.90625 0.90000 0.89375 0.88750 0.88125 0.87500 0.86875 0.66875 0.66250 0.65625 0.65000 0.64375 0.63750 0.63125 0.62500 0.61875 0.61250 0.60625 0.60000 0.59375 0.58750 0.58125 0.57500 0.56875 0.56250 0.55625 0.55000 0.54375 0.53750 0.53125 0.52500 0.51875 0.51250 0.50625 0.50000 0.49375 0.48750 0.48125 0.47500 0.46875 0.26875 0.26250 0.25625 0.25000 0.24375 0.23750 0.23125 0.22500 0.21875 0.21250 0.20625 0.20000 0.19375 0.18750 0.18125 0.17500 0.16875 0.16250 0.15625 0.15000 0.14375 0.13750 0.13125 0.12500 0.11875 0.11250 0.10625 0.10000 0.09375 0.08750 0.08125 0.07500 0.06875 17/64 VID Tables Table 7. HEX code 3 3 3 3 3 3 3 3 8 9 A B C D E F L6713A Voltage identification (VID) for Intel VR11 mode (See Note) (continued) Output voltage (1) HEX code 7 7 7 7 7 7 7 7 8 9 A B C D E F Output voltage (1 ) HEX code B B B B B B B B 8 9 A B C D E F Output voltage (1) HEX code F F F F F F F F 8 9 A B C D E F Output voltage (1) 1.26250 1.25625 1.25000 1.24375 1.23750 1.23125 1.22500 1.21875 0.86250 0.85625 0.85000 0.84375 0.83750 0.83125 0.82500 0.81875 0.46250 0.45625 0.45000 0.44375 0.43750 0.43125 0.42500 0.41875 0.06250 0.05625 0.05000 0.04375 0.03750 0.03125 OFF OFF 1. According to VR11 specs, the device automatically regulates output voltage 19 mV lower to avoid any external offset to modify the built-in 0.5 % accuracy improving TOB performances. Output regulated voltage is than what extracted from the table lowered by 19 mV built-in offset. 5.3 Voltage identifications (VID) for Intel VR10 mode + 6.25 mV (VID7 does not care) Table 8. Voltage identifications (VID) for Intel VR10 mode + 6.25 mV (See Note) Output voltage (1) VID VID VID VID VID VID VID 4 3 2 1 0 5 6 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 VID VID VID VID VID VID VID 4 3 2 1 0 5 6 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 Output voltage (1) 1.60000 1.59375 1.58750 1.58125 1.57500 1.56875 1.56250 1.55625 1.55000 1.54375 1.53750 1.53125 1.52500 1.51875 1.51250 1.50625 1.20000 1.19375 1.18750 1.18125 1.17500 1.16875 1.16250 1.15625 1.15000 1.14375 1.13750 1.13125 1.12500 1.11875 1.11250 1.10625 18/64 L6713A Table 8. VID Tables Voltage identifications (VID) for Intel VR10 mode + 6.25 mV (See Note) Output voltage (1) VID VID VID VID VID VID VID 4 3 2 1 0 5 6 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 VID VID VID VID VID VID VID 4 3 2 1 0 5 6 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Output voltage (1) 1.50000 1.49375 1.48750 1.48125 1.47500 1.46875 1.46250 1.45625 1.45000 1.44375 1.43750 1.43125 1.42500 1.41875 1.41250 1.40625 1.40000 1.39375 1.38750 1.38125 1.37500 1.36875 1.36250 1.35625 1.35000 1.34375 1.33750 1.33125 1.32500 1.31875 1.31250 1.30625 1.30000 1.10000 1.09375 OFF OFF OFF OFF 1.08750 1.08125 1.07500 1.06875 1.06250 1.05625 1.05000 1.04375 1.03750 1.03125 1.02500 1.01875 1.01250 1.00625 1.00000 0.99375 0.98750 0.98125 0.97500 0.96875 0.96250 0.95625 0.95000 0.94375 0.93750 0.93125 0.92500 19/64 VID Tables Table 8. L6713A Voltage identifications (VID) for Intel VR10 mode + 6.25 mV (See Note) Output voltage (1) VID VID VID VID VID VID VID 4 3 2 1 0 5 6 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 VID VID VID VID VID VID VID 4 3 2 1 0 5 6 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 Output voltage (1) 1.29375 1.28750 1.28125 1.27500 1.26875 1.26250 1.25625 1.25000 1.24375 1.23750 1.23125 1.22500 1.21875 1.21250 1.20625 0.91875 0.91250 0.90625 0.90000 0.89375 0.88750 0.88125 0.87500 0.86875 0.86250 0.85625 0.85000 0.84375 0.83750 0.83125 1. According to VR10.x specs, the device automatically regulates output voltage 19 mV lower to avoid any external offset to modify the built-in 0.5 % accuracy improving TOB performances. Output regulated voltage is than what extracted from the table lowered by 19mVbuilt-in offset. VID7 doesn’t care. 5.4 Mapping for the AMD 6 bit mode Table 9. VID4 400 mV Voltage identifications (VID) mapping for AMD 6 bit mode VID3 200 mV VID2 100 mV VID1 50 mV VID0 25 mV 5.5 Table 10. VID5 0 0 0 0 VID4 0 0 0 0 Voltage identifications (VID) codes for AMD 6 bit mode Voltage identifications (VID) codes for AMD 6 bit mode (See Note) VID3 0 0 0 0 VID2 0 0 0 0 VID1 0 0 1 1 VID0 0 1 0 1 Output voltage (1) 1.5500 1.5250 1.5000 1.4750 VID5 1 1 1 1 VID4 0 0 0 0 VID3 0 0 0 0 VID2 0 0 0 0 VID1 0 0 1 1 VID0 0 1 0 1 Output voltage (1) 0.7625 0.7500 0.7375 0.7250 20/64 L6713A Table 10. VID5 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VID4 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 VID Tables Voltage identifications (VID) codes for AMD 6 bit mode (See Note) (continued) VID3 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 VID2 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 VID1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 VID0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Output voltage (1) 1.4500 1.4250 1.4000 1.3750 1.3500 1.3250 1.3000 1.2750 1.2500 1.2250 1.2000 1.1750 1.1500 1.1250 1.1000 1.0750 1.0500 1.0250 1.0000 0.9750 0.9500 0.9250 0.9000 0.8750 0.8500 0.8250 0.8000 0.7750 VID5 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 VID4 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 VID3 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 VID2 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 VID1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 VID0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Output voltage (1) 0.7125 0.7000 0.6875 0.6750 0.6625 0.6500 0.6375 0.6250 0.6125 0.6000 0.5875 0.5750 0.5625 0.5500 0.5375 0.5250 0.5125 0.5000 0.4875 0.4750 0.4625 0.4500 0.4375 0.4250 0.4125 0.4000 0.3875 0.3750 1. VID6 not applicable, need to be left unconnected. 21/64 Reference schematic L6713A 6 Reference schematic Figure 3. VIN Reference schematic - Intel VR10.x, VR11 - 3-phase operation LIN to BOOT1 to BOOT2 62 56 VCCDR1 VCCDR2 UGATE1 VCCDR3 PHASE1 BOOT1 2 VIN CIN to BOOT3 GNDIN 1 57 HS1 L1 63,64 15 VCC LGATE1 61 LS1 R 19,50 PGND1 SGND CS1CS1+ 60 C 31 30 Rg 33 OVP 16 35 PHASE_SEL OCSET BOOT2 10 VIN UGATE2 9 HS2 L2 37 OSC/FAULT PHASE2 7,8 to SSEND RSSOSC 32 SS/LTBG/AMD VID7 / DVID LGATE2 55 LS2 R PGND2 54 C 27 26 Rg 39 L6713A VID bus from CPU 40 41 42 43 44 45 34 17 VID6 VID5 VID4 VID3 VID2 VID1 VID0 CS2CS2+ Vcc_core BOOT3 6 VIN COUT LOAD GND_core UGATE3 VID_SEL OUTEN PHASE3 5 HS3 L3 VID_SEL OUTEN 3,4 LGATE3 18 LTB 58 LS3 R PGND3 CS3- 59 C 29 28 Rg CLTB RLTB CF CP RF 23 COMP CS3+ 22 21 SS_END / PGOOD FB DROOP VR_HOT VR_FAN 46 SS_END 47 48 49 NTC +5V CI RI RFB 20 VSEN TM RTM ROFFSET 36 FBG L6713A REF.SCH: Intel Mode - 3-Phase Operation 22/64 L6713A Figure 4. Reference schematic Reference schematic - Intel VR10.x, VR11 - 2-phase operation VIN LIN to BOOT1 to BOOT3 GNDIN 62 56 VCCDR1 VCCDR2 BOOT1 2 VIN CIN 57 UGATE1 VCCDR3 PHASE1 1 HS1 L1 63,64 15 VCC LGATE1 61 LS1 R 19,50 PGND1 SGND CS1CS1+ 60 C 31 30 Rg 33 OVP 16 35 PHASE_SEL OCSET BOOT2 10 UGATE2 9 37 OSC/FAULT PHASE2 7,8 to SSEND RSSOSC 32 SS/LTBG/AMD VID7 / DVID LGATE2 55 PGND2 54 27 26 Short to SGND (or to VOUT) 39 L6713A VID bus from CPU 40 41 42 43 44 45 34 17 VID6 VID5 VID4 VID3 VID2 VID1 VID0 CS2CS2+ Vcc_core BOOT3 6 VIN COUT LOAD GND_core HS3 L3 UGATE3 VID_SEL OUTEN PHASE3 5 VID_SEL OUTEN 3,4 LGATE3 18 LTB 58 LS3 R PGND3 CS3- 59 C 29 28 Rg CLTB RLTB CF CP RF 23 COMP CS3+ 22 21 SS_END / PGOOD FB DROOP VR_HOT VR_FAN 46 SS_END 47 48 49 NTC +5V CI RI RFB TM 20 VSEN RTM ROFFSET 36 FBG L6713A REF.SCH: Intel Mode -2-Phase Operation 23/64 Reference schematic Figure 5. Reference schematic - AMD 6 bit - 3-phase operation L6713A VIN LIN to BOOT1 to BOOT2 GNDIN 62 56 VCCDR1 VCCDR2 BOOT1 2 VIN CIN to BOOT3 57 UGATE1 VCCDR3 PHASE1 1 HS1 L1 63,64 15 VCC LGATE1 61 LS1 R 19,50 PGND1 SGND CS1CS1+ 60 C 31 30 Rg 33 OVP 16 35 PHASE_SEL OCSET OSC/FAULT SS/LTBG/AMD BOOT2 10 VIN UGATE2 9 HS2 L2 37 32 PHASE2 7,8 LGATE2 55 LS2 R 38 39 40 VID bus from CPU VID7 / DVID PGND2 54 C 27 26 Rg L6713A VID6 VID5 VID4 VID3 VID2 VID1 VID0 CS2CS2+ 41 42 43 44 45 34 Vcc_core BOOT3 6 VIN COUT LOAD GND_core HS3 L3 UGATE3 VID_SEL OUTEN PHASE3 5 OUTEN 17 3,4 LGATE3 18 LTB 58 LS3 R PGND3 CS3- 59 C 29 28 Rg CLTB RLTB CF CP RF 23 COMP CS3+ 22 21 SS_END / PGOOD FB DROOP VR_HOT VR_FAN 46 PGOOD 47 48 49 NTC +5V CI RI RFB TM 20 VSEN RTM ROFFSET 36 FBG L6713A REF.SCH: AMD Mode - 3-Phase Operation 24/64 L6713A Figure 6. Reference schematic Reference schematic - AMD 6 bit - 2-phase operation VIN LIN to BOOT1 to BOOT3 GNDIN 62 56 VCCDR1 VCCDR2 BOOT1 2 VIN CIN 57 UGATE1 VCCDR3 PHASE1 1 HS1 L1 63,64 15 VCC LGATE1 61 LS1 R 19,50 PGND1 SGND CS1CS1+ 60 C 31 30 Rg 33 OVP 16 35 PHASE_SEL OCSET OSC/FAULT SS/LTBG/AMD BOOT2 10 UGATE2 9 37 32 PHASE2 7,8 LGATE2 55 38 39 40 VID bus from CPU VID7 / DVID PGND2 54 27 26 Short to SGND (or to VOUT) L6713A VID6 VID5 VID4 VID3 VID2 VID1 VID0 CS2CS2+ 41 42 43 44 45 34 Vcc_core BOOT3 6 VIN COUT LOAD GND_core HS3 L3 UGATE3 VID_SEL OUTEN PHASE3 5 OUTEN 17 3,4 LGATE3 18 LTB 58 LS3 R PGND3 CS3- 59 C 29 28 Rg CLTB RLTB CF CP RF 23 COMP CS3+ 22 21 SS_END / PGOOD FB DROOP VR_HOT VR_FAN 46 PGOOD 47 48 49 NTC +5V CI RI RFB 20 VSEN TM RTM ROFFSET 36 FBG L6713A REF.SCH: AMD Mode - 2-Phase Operation 25/64 Device description L6713A 7 Device description L6713A is two/three phase PWM controller with embedded high current drivers providing complete control logic and protections for a high performance step-down DC-DC voltage regulator optimized for advanced microprocessor power supply. Multi phase buck is the simplest and most cost-effective topology employable to satisfy the increasing current demand of newer microprocessors and modern high current VRM modules. It allows distributing equally load and power between the phases using smaller, cheaper and most common external power MOSFETs and inductors. Moreover, thanks to the equal phase shift between each phase, the input and output capacitor count results in being reduced. Phase interleaving causes in fact input RMS current and output ripple voltage reduction and show an effective output switching frequency increase: the 200kHz freerunning frequency per phase, externally adjustable through a resistor, results multiplied on the output by the number of phases. L6713A is a dual-edge asynchronous PWM controller featuring load transient boost LTB Technology™ (patent pending): the device turns on simultaneously all the phases as soon as a load transient is detected allowing to minimize system cost by providing the fastest response to load transition. Load transition is detected (through LTB pin) measuring the derivate dV/dt of the output voltage and the dV/dt can be easily programmed extending the system design flexibility. Moreover, load transient boost LTB Technology™ gain can be easily modified in order to keep under control the output voltage ring back. LTB Technology™ can be disabled and in this condition the device works as a dual-edge asynchronous PWM. The controller allows to implement a scalable design: a three phase design can be easily downgraded to two phase simply by leaving one phase not mounted and leaving PHASE_SEL pin floating. The same design can be used for more than one project saving development and debug time. In the same manner, a two phase design can be further upgraded to three phase facing with newer and highly-current-demanding applications. L6713A permits easy system design by allowing current reading across inductor in fully differential mode. Also a sense resistor in series to the inductor can be considered to improve reading precision. The current information read corrects the PWM output in order to equalize the average current carried by each phase limiting the error to ±3 % over static and dynamic conditions unless considering the sensing element spread. The controller includes multiple DACs, selectable through an apposite pin, allowing compatibility with both Intel VR10,VR11 and AMD 6BIT processors specifications, also performing D-VID transitions accordingly. Low-side-less start-up allows soft-start over pre-biased output avoiding dangerous current return through the main inductors as well as negative spike at the load side. 26/64 L6713A Device description L6713A provides a programmable over-voltage protection to protect the load from dangerous over stress. It can be externally set to a fixed voltage through an apposite resistor, or it can be set internally, latching immediately by turning ON the lower driver and driving high the FAULT pin. Furthermore, preliminary OVP protection also allows the device to protect load from dangerous OVP when VCC is not above the UVLO threshold. The over-current protection is on the total delivered current and causes the device turns OFF all MOSFETs and latches the condition. L6713A provides also system Thermal Monitoring: through an apposite pin the device senses the temperature of the hottest component in the application driving the Warning and the Alarm signal as a consequence. A compact 10 x 10 mm body TQFP64 package with exposed thermal pad allows dissipating the power to drive the external MOSFET through the system board. 27/64 Configuring the device L6713A 8 Configuring the device Number of phases and multiple DACs need to be configured before the system starts-up by programming the apposite pin PHASE_SEL and SS/LTBG/AMD pin. The configuration of this pin identifies two main working areas (See Table 12) distinguishing between compliancy with Intel VR10,VR11 or AMD 6BIT specifications. According to the main specification considered, further customizations can be done: main differences are regarding the DAC table, soft-start implementation, protection management and Dynamic VID Transitions. See Table 13 and See Table 14 for further details about the device configuration. 8.1 Number of phases selection L6713A allows to select between two and three phase operation simply using the PHASE_SEL pin, as shown in the following table. Table 11. Number of phases setting Number of phases 2-PHASE 3-PHASE Phases used Phase1, Phase3 Phase1, Phase2, Phase3 PHASE_SEL pin Floating Short to SGND 8.2 DAC selection L6713A embeds a selectable DAC (through SS/LTBG/AMD pin, See Table 12) that allows to regulate the output voltage with a tolerance of ±0.5% (±0.6% for AMD DAC) recovering from offsets and manufacturing variations. In case of selecting Intel mode, the device automatically introduces a -19 mV (both VRD10.x and VR11) offset to the regulated voltage in order to avoid any external offset circuitry to worsen the guaranteed accuracy and, as a consequence, the calculated system TOB. Table 12. DAC settings (See note) DAC Soft-start time LTB™ gain OVP UVP SS / LTBG / AMD Resistor (RSSOSC) vs. SGND 0 (Short) AMD Not programmable Fixed (LTB™ gain = 2) 1.800 V (typ) or Programmable VID + 175 mV (typ) or programmable -750 mV (typ) > 2.4 kΩ Intel Programmable trough RSSOSC Programmable trough RSSOSC (LTB™ gain ≤ 2) -750 mV (typ) Note: When selecting Intel mode, SS/LTBG/AMD pin is used to select both soft-start time and LTB™ gain (see dedicated sections). 28/64 L6713A Configuring the device Output voltage is programmed through the VID pins: they are inputs of an internal DAC that is realized by means of a series of resistors providing a partition of the internal voltage reference. The VID code drives a multiplexer that selects a voltage on a precise point of the divider. The DAC output is delivered to an amplifier obtaining the voltage reference (i.e. the set-point of the error amplifier, VREF). Table 13. Pin SS / LTBG / AMD Intel mode configuration (See Note) Function (1) Typical connection It allows programming the soft-start time TSS RSSOSC resistor in series to and also the LTB Technology™ gain. See “Soft- signal diode vs. SSEND pin. start” Section and See “Load transient boost (LTB™ gain = 2, default value). technologyTM” Section for details. It allows selecting between VR11 DAC or VR10.x + 6.25 mV extended DAC. Static info, no dynamic changes allowed. They allow programming the output voltage according to Table 7 and Table 8. Dynamic transitions managed, See “Dynamic VID transitions” Section for details. Open: VR11 (Table 7 ). short to SGND: VR10.x (Table 8 ). Open: Logic “1” (25 μA pull-up) Short to SGND: “0” VID_SEL VID7 to VID0 SSEND / PGOOD Soft-start end signal set free after soft-start has Pull-up to anything lower finished. It only indicates soft-start has finished. than 5 V. Note: VID pull-ups / pull-downs, VID voltage thresholds and OUTEN thresholds changes according to the selected DAC: See Table 5 for details. Table 14. Pin SS / LTBG / AMD VID_SEL VID7 / DVID VID6 AMD mode configuration (See Note) Function It allows programming AMD 6 BIT DAC. Not applicable Pulled high when performing a D-VID transition. The pin is kept high with a 32 clock cycles delay. Not applicable They allow programming the output voltage according to Table 10. Dynamic transitions managed, See “Dynamic VID transitions” Section for details. Power good signal set free after soft-start has finished whenever the output voltage is within limits. Typical connection Short to SGND. Need to be shorted to SGND. Not applicable Need to be shorted to SGND. Open: “0” (12.5 μA pull-down) Pull-up to V > 1.4 V: “1” VID5 to VID0 SSEND / PGOOD Pull-up to anything lower than 5 V. Note: VID pull-ups / pull-downs, VID voltage thresholds and OUTEN thresholds changes according to the selected DAC: See Table 5 for details. 29/64 Power dissipation L6713A 9 Power dissipation L6713A embeds high current MOSFET drivers for both high side and low side MOSFETs: it is then important to consider the power the device is going to dissipate in driving them in order to avoid overcoming the maximum junction operative temperature. In addition, since the device has an exposed pad to better dissipate the power, the thermal resistance between junction and ambient consequent to the layout is also important: thermal pad needs to be soldered to the PCB ground plane through several VIAs in order to facilitate the heat dissipation. Two main terms contribute in the device power dissipation: bias power and drivers' power. The first one (PDC) depends on the static consumption of the device through the supply pins and it is simply quantifiable as follow (assuming to supply HS and LS drivers with the same VCC of the device): P DC = V CC ⋅ ( I CC + N ⋅ I CCDRx + N ⋅ I BOOTx ) where N is the number of phases. Drivers' power is the power needed by the driver to continuously switch on and off the external MOSFETs; it is a function of the switching frequency and total gate charge of the selected MOSFETs. It can be quantified considering that the total power PSW dissipated to switch the MOSFETs (easy calculable) is dissipated by three main factors: external gate resistance (when present), intrinsic MOSFET resistance and intrinsic driver resistance. This last term is the important one to be determined to calculate the device power dissipation. The total power dissipated to switch the MOSFETs results: P SW = N ⋅ F SW ⋅ ( Q GHS ⋅ V BOOT + Q GLS ⋅ V CCDRx ) External gate resistors helps the device to dissipate the switching power since the same power PSW will be shared between the internal driver impedance and the external resistor resulting in a general cooling of the device. When driving multiple MOSFETs in parallel, it is suggested to use one gate resistor for each MOSFET. 30/64 L6713A Figure 7. L6713A dissipated power (quiescent + switching) 2-PHASE Operation; Rgate=0; Rmosfet=0 4500 Power dissipation 2-PHASE Operation; Rhs=2.2; Rls=3.3; Rmosfet=1 4000 Controller Dissipated Power [mW] Controller Dissipated Power [mW] 4000 3500 3000 2500 2000 1500 1000 500 0 50 HS=1xSTD38NH02L; LS=1xSTD90NH02L HS=2xSTD38NH02L; LS=2xSTD90NH02L HS=1xSTD55NH2LL; LS=1xSTD95NH02L HS=2xSTD55NH2LL; LS=2xSTD95NH02L HS=3xSTD55NH22L; LS=3xSTD95NH02L 3500 3000 2500 2000 1500 1000 500 0 HS=1xSTD38NH02L; LS=1xSTD90NH02L HS=2xSTD38NH02L; LS=2xSTD90NH02L HS=1xSTD55NH2LL; LS=1xSTD95NH02L HS=2xSTD55NH2LL; LS=2xSTD95NH02L HS=3xSTD55NH22L; LS=3xSTD95NH02L 150 250 350 450 550 650 750 850 950 1050 50 150 250 350 450 550 650 750 850 950 1050 Switching frequency [kHz] per phase 3-PHASE Operation; Rgate=0; Rmosfet=0 7000 Switching frequency [kHz] per phase 3-PHASE Operation; Rhs=2.2; Rls=3.3; Rmosfet=1 4000 Controller Dissipated Power [mW] Controller Dissipated Power [mW] 6000 5000 4000 3000 2000 1000 0 50 HS=1xSTD38NH02L; LS=1xSTD90NH02L HS=2xSTD38NH02L; LS=2xSTD90NH02L HS=1xSTD55NH2LL; LS=1xSTD95NH02L HS=2xSTD55NH2LL; LS=2xSTD95NH02L HS=3xSTD55NH22L; LS=3xSTD95NH02L 3500 3000 2500 2000 1500 1000 500 0 HS=1xSTD38NH02L; LS=1xSTD90NH02L HS=2xSTD38NH02L; LS=2xSTD90NH02L HS=1xSTD55NH2LL; LS=1xSTD95NH02L HS=2xSTD55NH2LL; LS=2xSTD95NH02L HS=3xSTD55NH22L; LS=3xSTD95NH02L 150 250 350 450 550 650 750 850 950 1050 50 150 250 350 450 550 650 750 850 950 1050 Switching frequency [kHz] per phase Switching frequency [kHz] per phase 31/64 Current reading and current sharing loop L6713A 10 Current reading and current sharing loop L6713A embeds a flexible, fully-differential current sense circuitry that is able to read across inductor parasitic resistance or across a sense resistor placed in series to the inductor element. The fully-differential current reading rejects noise and allows placing sensing element in different locations without affecting the measurement's accuracy. Reading current across the inductor DCR, the current flowing trough each phase is read using the voltage drop across the output inductor or across a sense resistor in its series and internally converted into a current. The trans-conductance ratio is issued by the external resistor Rg placed outside the chip between CSx- pin toward the reading points. The current sense circuit always tracks the current information, no bias current is sourced from the CSx+ pin: this pin is used as a reference keeping the CSx- pin to this voltage. To correctly reproduce the inductor current an R-C filtering network must be introduced in parallel to the sensing element. The current that flows from the CSx- pin is then given by the following equation (See Figure 8): DCR 1 + s ⋅ L ⁄ ( DCR ) I CSx- = ------------ ⋅ ------------------------------------------ ⋅ I Rg 1+s⋅R⋅C PHASEx Where IPHASEx is the current carried by the relative phase. Figure 8. Current reading connections IPHASEx PHASEx Lx R DCRx CSx+ NO Bias ICSx-=IINFOx CSxRg C Inductor DCR Current Sense Considering now to match the time constant between the inductor and the R-C filter applied (Time constant mismatches cause the introduction of poles into the current reading network causing instability. In addition, it is also important for the load transient response and to let the system show resistive equivalent output impedance), it results: L------------ = R ⋅ C DCR ⇒ DCR I CSx- = ------------ ⋅ I PHASEx = I INFOx ⇒ Rg DCR I INFOX = ------------ ⋅ I PHASEx Rg Where IINFOx is the current information reproduced internally. 32/64 L6713A Current reading and current sharing loop The Rg trans-conductance resistor has to be selected using the following formula, in order to guarantee the correct functionality of internal current reading circuitry: DCR ( MAX ) I OUT ( MAX ) Rg = ------------------------------- ⋅ -----------------------------N 20 μ A Current sharing control loop reported in Figure 9: it considers a current IINFOx proportional to the current delivered by each phase and the average current AVG = Σ I INFOx ⁄ N. The error between the read current IINFOx and the reference IAVG is then converted into a voltage that with a proper gain is used to adjust the duty cycle whose dominant value is set by the voltage error amplifier in order to equalize the current carried by each phase. Details about connections are shown in Figure 8. Figure 9. Current sharing loop IINFO1 PWM1 Out AVG IAVG IINFO2 From EA PWM2 Out IINFO3 PWM3 Out (PHASE2 Only when using 3-PHASE Operation) 33/64 Differential remote voltage sensing L6713A 11 Differential remote voltage sensing The output voltage is sensed in fully-differential mode between the FB and FBG pin. The FB pin has to be connected through a resistor to the regulation point while the FBG pin has to be connected directly to the remote sense ground point. In this way, the output voltage programmed is regulated between the remote sense point compensating motherboard or connector losses. Keeping the FB and FBG traces parallel and guarded by a power plane results in common mode coupling for any picked-up noise. Figure 10. Differential remote voltage sensing connections VPROG GND DROP RECOVERY VREF ERROR AMPLIFIER IOFFSET IDROOP FBG VSEN DROOP FB COMP ROFFSET RFB RF CP CF To GND_core (Remote Sense) To VCC_core (Remote Sense) 34/64 L6713A Voltage positioning 12 Voltage positioning Output voltage positioning is performed by selecting the reference DAC and by programming the droop function and offset to the reference (See Figure 11). The currents sourced from DROOP and sunk from VSEN pins cause the output voltage to vary according to the external RFB and ROFFSET resistor. The output voltage is then driven by the following relationship: V OUT = V REF – ( R FB + R OFFSET ) ⋅ ( I DROOP ) + ( R OFFSET ) ⋅ ( I OFFSET ) ⎧ V REF = ⎨ VID – 19mV VR10 - VR11 AMD 6BIT ⎩ VID DROOP function can be disabled as well as the OFFSET: connecting DROOP pin and FB pin together implements the load regulation dependence while, if this effect is not desired, by shorting DROOP pin to SGND it is possible for the device to operate as a classic voltage mode buck converter. The DROOP pin can also be connected to SGND through a resistor obtaining a voltage proportional to the delivered current usable for monitoring purposes. OFFSET can be disabled by using ROFFSET equal to zero. Figure 11. Voltage positioning (left) and droop function (right) VPROG GND DROP RECOVERY VREF ERROR AMPLIFIER ESR Drop VMAX IOFFSET IDROOP VNOM FB COMP FBG VSEN DROOP VMIN RESPONSE WITHOUT DROOP RESPONSE WITH DROOP ROFFSET RFB RF CP CF To GND_core (Remote Sense) To VCC_core (Remote Sense) 12.1 Offset (Optional) The IOFFSET current (See Table 5) sunk from the VSEN pin allows programming a positive offset (VOS) for the output voltage by connecting a resistor ROFFSET between VSEN pin and VOUT, as shown in the Figure 11; this offset has to be considered in addition to the one already introduced during the production stage for the Intel VR10,VR11 mode. The output voltage is then programmed as follow: V OUT = V REF – ( R FB + R OFFSET ) ⋅ ( I DROOP ) + ( R OFFSET ) ⋅ ( I OFFSET ) Offset resistor can be designed by considering the following relationship: V OS R OFFSET = --------------------I OFFSET Offset automatically given by the DAC selection differs from the offset implemented through the IOFFSET current: the built-in feature is trimmed in production and assures ± 0.5 % error (± 0.6 % for the AMD DAC) over load and line variations. 35/64 Voltage positioning L6713A 12.2 Droop function (Optional) This method "recovers" part of the drop due to the output capacitor ESR in the load transient, introducing a dependence of the output voltage on the load current: a static error proportional to the output current causes the output voltage to vary according to the sensed current. As shown in Figure 11, the ESR drop is present in any case, but using the droop function the total deviation of the output voltage is minimized. Moreover, more and more highperformance CPUs require precise load-line regulation to perform in the proper way. DROOP function is not then required only to optimize the output filter, but also beacomes a requirement of the load. Connecting DROOP pin and FB pin together, the device forces a current IDROOP, proportional to the read current, into the feedback resistor (RFB+ROFFSET) implementing the load regulation dependence. Since IDROOP depends on the current information about the N phases, the output characteristic vs. load current is then given by (neglecting the OFFSET voltage term): V OUT = V REF – ( R FB + R OFFSET ) ⋅ I DROOP DCR V REF – ( R FB + R OFFSET ) ⋅ ------------ ⋅ I OUT = V REF – R DROOP ⋅ I OUT Rg Where DCR is the inductor parasite resistance (or sense resistor when used) and IOUT is the output current of the system. The whole power supply can be then represented by a "real" voltage generator with an equivalent output resistance RDROOP and a voltage value of VREF. RFB resistor can be also designed according to the RDROOP specifications as follow: Rg R FB = R DROOP ⋅ ------------ – R OFFSET DCR Droop function is optional, in case it is not desired, the DROOP pin can be disconnected from the FB and an information about the total delivered current becomes available for debugging, and/or current monitoring. When not used, the pin can be shorted to SGND. 36/64 L6713A Load transient boost technologyTM 13 Load transient boost technologyTM Load transient boost LTB Technology™ (patent pending) is a L6713A feature to minimize the count of output filter capacitors (MLCC and bulk capacitors) to respect the load transient specifications. The device turns on simultaneously all the phases as soon as a load transient is detected and keep them on for the necessary time to supply the extra energy to the load. This time depends on the COMP pin voltage and on a internal gain, in order to keep under control the output voltage ring back. Load transition is detected through LTB™ pin connecting a RLTB-CLTB vs. VOUT: the device measures the derivate dV/dt of the output voltage and so it is able to turns on all the phases immediately after a load transition detection, minimizing the delay intervention. Modifying the RLTB-CLTB values the dV/dt can be easily programmed, extending the system design flexibility dV OUT R LTB = ----------------50 μ A 1 C LTB = ----------------------------------------------------2 ⋅ π ⋅ R LTB ⋅ N ⋅ F SW where dVOUT is the output voltage drop due to load transition. Moreover, load transient boost LTB Technology™ gain can be easily modified in order to keep under control the output voltage ring back. Figure 12. LTB connections (left) and waveform (right) LTB To VCC_Core RLTB CLTB Short LTB pin to SGND to disable the LTB Technology™: in this condition the device works as a dual-edge asynchronous PWM controller. 37/64 Load transient boost technologyTM L6713A 13.1 LTB™ gain modification (Optional) The internal gain can be modified through the SS/LTBG/AMD pin, as shown in the Figure 13. The SS/LTBG/AMD pin is also used to set the soft-start time, so the current flowing from SS/LTBG/AMD pin has to be modified only after the soft-start has been finished. Using the D diode and R3 resistor (red square in Figure 13), after the soft-start the current flowing from SS/LTBG/AMD pin versus SGND is zero, so the internal gain is not modified.As a consequence the LTB™ gain is the default value (LTB™ gain = 2). To decrease the LTB™ gain it is necessary to use the circuit composed by Q, R1 and R2 (blue square in Figure 13.) After the soft-start the current flowing from SS/LTBG/AMD pin depends only on R1 resistor, so reducing the R1 resistor value the LTB™ gain can be reduced. The sum of R1 and R2 resistors have to be selected to have the desiderated soft-start time. Figure 13. SS/OSC/LTB connections to modify LTB™ gain when using INTEL mode SS_END VPull-Up(1.2V) D SS/LTBG/ AMD R3 LTB GAIN=2 LTB GAIN V BOOT ) if ( V SS < V BOOT ) where TSS is the time spent to reach the programmed voltage VSS and RSSOSC the resistor connected between SS/LTBG/AMD and SSEND (through a signal diode) in kΩ. 43/64 Soft-start L6713A Figure 17. Soft-start time for Intel mode when using RSSOSC, diode versus SSEND 7 6 Time to Vboot Time to 1.6000V Soft Start Time Tss [ms] 5 4 3 2 1 0 1 10 100 1000 Rssosc [kOhms] vs. SSEND through sognal diode 16.1.2 SS/LTB/AMD connections when using LTB™ gain < 2 When using LTB™ gain V BOOT ) if ( V SS < V BOOT ) where TSS is the time spent to reach the programmed voltage VSS and RSSOSC the resistor connected between SS/LTBG/AMD and SGND (RSSOSC = R1 + R2) in kΩ. 44/64 L6713A Figure 19. Soft-start time for Intel mode when using RSSOSC versus SGND 5 4.5 Time to Vboot Time to 1.6000V Soft-start Soft Start Time Tss [ms] 4 3.5 3 2.5 2 1.5 1 0.5 0 1 10 100 1000 Rssosc [kOhms] vs. SGND 16.2 AMD mode Once L6713A receives all the correct supplies and enables, and AMD mode has been selected, it initiates the soft-start by stepping the reference from zero up to the programmed VID code (See Figure 15); the clock now used to step the reference is the same as the main oscillator programmed by the OSC pin, SSOSC pin is not applicable in this case. The softstart time results then (See Figure 20): dV OUT V SS ----------------- = 3.125 ⋅ F SW [ kkHz ] ⇒ T SS = ---------------------------------------------dT 3.125 ⋅ F SW [ kHz ] where TSS is the time spent to reach VSS and FSW is the main switching frequency programmed by OSC pin. Protections are active during soft-start, UVP is enabled after the reference reaches 0.6 V while OVP is always active with the fixed 1.800 V threshold (or the programmed VOVP). Figure 20. Soft-start time for AMD mode 4 3.5 550 500 4 3.5 550 500 450 400 350 Time to 1.6000V Time to 1.1000V Switching Frequency per phase 300 250 200 150 0 200 400 600 800 1000 SoftStart Time Tss [msec] SoftStart Time Tss [msec] 3 2.5 2 1.5 1 0.5 0 0 200 400 600 800 Time to 1.6000V Time to 1.1000V Switching Frequency per phase 450 400 350 300 250 200 150 1000 3 2.5 2 1.5 1 0.5 0 Rosc [kOhms] to SGND Rosc [kOhms] to SGND 45/64 Switching Freqency [kHz] Switching Freqency [kHz] Soft-start L6713A 16.3 Low-side-less startup In order to avoid any kind of negative undershoot on the load side during start-up, L6713A performs a special sequence in enabling LS driver to switch: during the soft-start phase, the LS driver results disabled (LS = OFF) until the HS starts to switch. This avoid the dangerous negative spike on the output voltage that can happen if starting over a pre-biased output (See Figure 21). This particular feature of the device masks the LS turn-ON only from the control loop point of view: protections are still allowed to turn-ON the LS MOSFET in case of over voltage if needed. Figure 21. Low-side-less start-up comparison 46/64 L6713A Output voltage monitor and protections 17 Output voltage monitor and protections L6713A monitors through pin VSEN the regulated voltage in order to manage the OVP, UVP and PGOOD (when applicable) conditions. The device shows different thresholds when programming different operation mode (Intel or AMD, See Table 12) but the behavior in response to a protection event is still the same as described below. When using OFFSET functionality the OVP, UVP and PGOOD thresholds change in according to the OFFSET voltage: V SEN = V OUT – ( R OFFSET ) ⋅ ( I OFFSET ) ⇒ V OUT [ TH ] = V SEN [ TH ] + ( R OFFSET ) ⋅ I OFFSET Protections are active also during soft-start (See “Soft-start” Section) while are masked during D-VID transitions with an additional 32 clock cycle delay after the transition has finished to avoid false triggering. 17.1 Under voltage If the output voltage monitored by VSEN drops more than -750 mV below the programmed reference for more than one clock period, L6713A turns OFF all MOSFETs and latches the condition: to recover it is required to cycle Vcc or the OUTEN pin. This is independent of the selected operative mode. 17.2 Preliminary over voltage To provide a protection while VCC is below the UVLOVCC threshold is fundamental to avoid damage to the CPU in case of failed HS MOSFETs. In fact, since the device is supplied from the 12 V bus, it is basically “blind” for any voltage below the turn-ON threshold (UVLOVCC). In order to give full protection to the load, a preliminary-OVP protection is provided while VCC is within UVLOVCC and UVLOOVP. This protection turns-ON the low side MOSFETs as long as the VSEN pin voltage is greater than 1.800 V with a 350 mV hysteresis. When set, the protection drives the LS MOSFET with a gate-to-source voltage depending on the voltage applied to VCCDRx and independently by the turn-ON threshold across these pins (UVLOVCCDR). This protection depends also on the OUTEN pin status as detailed in Figure 22. A simple way to provide protection to the output in all conditions when the device is OFF (then avoiding the unprotected red region in Figure 22-Left) consists in supplying the controller through the 5 VSB bus as shown in Figure 22-Right: 5 VSB is always present before +12 V and, in case of HS short, the LS MOSFET is driven with 5 V assuring a reliable protection of the load. Preliminary OVP is always active before UVLOVCC for both Intel and AMD modes. 47/64 Output voltage monitor and protections Figure 22. Output voltage protections and typical principle connections BAT54C +5VSB Vcc UVLOVCC (OUTEN = 0) Preliminary OVP VSEN Monitored (OUTEN = 1) Programmable OVP VSEN Monitored L6713A 2.2Ω +12V 2.2Ω 1μF VCCDR1 VCCDR2 VCC Preliminary OVP Enabled VSEN Monitored UVLOOVP No Protection Provided VCCDR3 17.3 Over voltage and programmable OVP Once VCC crosses the turn-ON threshold and the device is enabled (OUTEN = 1), L6713A provides an over voltage protection: when the voltage sensed by VSEN overcomes the OVP threshold, the controller permanently switches on all the low-side MOSFETs and switches OFF all the high-side MOSFETs in order to protect the load. The OSC/ FAULT pin is driven high (5 V) and power supply or OUTEN pin cycling is required to restart operations.The OVP Threshold varies according to the operative mode selected (See Table 12). The OVP threshold can be also programmed through the OVP pin: leaving the pin floating, it is internally pulled-up and the OVP threshold is set according to Table 12. Connecting the OVP pin to SGND through a resistor ROVP, the OVP threshold becomes the voltage present at the pin. Since the OVP pin sources a constant IOVP = 12.5 μA current(See Table 5), the programmed voltage becomes: OVP TH = R OVP ⋅ 12.5 μ A ⇒ OVP TH R OVP = ------------------12.5 μ A Filter OVP pin with 100 pF(max) vs. SGND. 17.4 PGOOD (only for AMD mode) It is an open-drain signal set free after the soft-start sequence has finished. It is pulled low when the output voltage drops below -300 mV of the programmed voltage. 48/64 L6713A Over current protection 18 Over current protection The device limits the total delivered current turning OFF all the MOSFETs as soon as the delivery current is higher than an adjustable thresholds.This condition is lathed and power supply or OUTEN pin cycling is required to restart operations. The device sources a copy of IDROOP current from the OCSET pin: connecting a resistor ROCP between OCSET pin and SGND the voltage at the OCSET pin depends on the total delivery output current, as shown in the following relationships: DCR V OCSET = R OCP ⋅ I DROOP = R OCP ⋅ ------------ ⋅ I OUT RG Figure 23. OCP connections (left) and waveforms (right) VOUT IDROOP OCP COMPARATOR OCSET OCSET UGATE ROCP COCP VOCTH=1.240V LGATE As soon as the OCSET pin voltage is higher than the internal fixed thresholds VOCTH (1.24 V TYP, See Table 5), the device turns OFF all the MOSFETs and latches the condition. The OCP threshold can be easily programmed through the ROCP resistor: V OCTH RG R OCP = ------------ ⋅ -------------------------DCR I OUT ( OCP ) The output over current threshold has to be programmed, by designing the ROCP resistors, to a safe value, in order to be sure that the device doesn't enter OCP during normal operation of the device. This value must take into consideration also the extra current needed during the dynamic VID transition ID-VID and, since the device reads across inductor DCR, the process spread and temperature variations of these sensing elements. Moreover, since also the internal threshold spreads, the ROCP design has to consider the minimum value VOCTH(min) of the threshold as follow: V OCTH ( min ) RG R OCP = ------------------------------ ⋅ --------------------------------DCR ( max ) I OUT ( OCP ) where IOUT(OCP) is the total delivery current for the over current condition and it must be calculated considering the maximum delivery current and ID-VID (when D-VID are implemented): I OUT ( OCP ) > I OUT MAX + I D –VID When it is necessary, filter OCSET pin to introduce a small delay in the over current intervention. 49/64 Oscillator L6713A 19 Oscillator L6713A embeds two/three phase oscillator with optimized phase-shift (180º/120º phaseshift) in order to reduce the input rms current and optimize the output filter definition. The internal oscillator generates the triangular waveform for the PWM charging and discharging with a constant current an internal capacitor. The switching frequency for each channel, FSW, is internally fixed at 200 kHz so that the resulting switching frequency at the load side results in being multiplied by N (number of phases). The current delivered to the oscillator is typically 25 μA (corresponding to the free running frequency FSW = 200 kHz) and it may be varied using an external resistor (ROSC) connected between the OSC pin and SGND or VCC (or a fixed voltage greater than 1.24 V). Since the OSC pin is fixed at 1.24 V, the frequency is varied proportionally to the current sunk (forced) from (into) the pin considering the internal gain of 6 KHz/μA. In particular connecting ROSC to SGND the frequency is increased (current is sunk from the pin), while connecting ROSC to VCC = 12 V the frequency is reduced (current is forced into the pin), according the following relationships: ROSC vs. SGND 1.240V kHz 7.422 ⋅ 10 F SW = 200 ( kHz ) + --------------------------- ⋅ 6 ---------- = 200 ( kHz ) + ---------------------------- ⇒ R OSC ( k Ω ) = R OSC ( k Ω ) R OSC ( k Ω ) μA 3 kHz 7.422 ⋅ 10 7.422 ⋅ 10 6 ---------- = 200 ( kHz ) + ---------------------------- ⇒ R OSC ( k Ω ) = ----------------------------------------------------------- [ k Ω ] μA R OSC ( k Ω ) F SW ( kHz ) – 200 ( kHz ) 3 3 ROSC vs. +12V 4 12V – 1.240V 8kHz 8.608 ⋅ 10 F SW = 200 ( kHz ) – ----------------------------------- ⋅ ------------- = 200 ( kHz ) – ---------------------------- ⇒ R OSC ( k Ω ) = -μA R OSC ( k Ω ) R OSC ( k Ω ) 2 4 4 kHz 8.608 ⋅ 10 6.456 ⋅ 10 ---------- = 200 ( kHz ) – ---------------------------- ⇒ R OSC ( k Ω ) = ----------------------------------------------------------- [ k Ω ] μA R OSC ( k Ω ) 200 ( kHz ) – F SW ( kHz ) Maximum programmable switching frequency per phase must be limited to 1 MHz to avoid minimum Ton limitation. Anyway, device power dissipation must be checked prior to design high switching frequency systems. Figure 24. ROSC vs. switching frequency 7000 6000 400 350 Rosc [kOhms] to SGND Rosc [kOhms] to +12V 5000 4000 3000 2000 1000 0 25 50 75 100 125 150 175 200 300 250 200 150 100 50 0 150 250 350 450 550 650 750 850 950 1050 Fsw [kHz] Programmed Fsw [kHz] Programmed 50/64 L6713A Driver section 20 Driver section The integrated high-current drivers allow using different types of power MOS (also multiple MOS to reduce the equivalent RDS(on)), maintaining fast switching transition. The drivers for the high-side MOSFETs use BOOTx pins for supply and PHASEx pins for return. The drivers for the low-side MOSFETs use VCCDRx pin for supply and PGNDx pin for return. A minimum voltage at VCCDRx pin is required to start operations of the device. VCCDRx pins must be connected together. The controller embodies a sophisticated anti-shoot-through system to minimize low side body diode conduction time maintaining good efficiency saving the use of Schottky diodes: when the high-side MOSFET turns OFF, the voltage on its source begins to fall; when the voltage reaches 2 V, the low-side MOSFET gate drive is suddenly applied. When the lowside MOSFET turns OFF, the voltage at LGATEx pin is sensed. When it drops below 1 V, the high-side MOSFET gate drive is suddenly applied. If the current flowing in the inductor is negative, the source of high-side MOSFET will never drop. To allow the turning on of the low-side MOSFET even in this case, a watchdog controller is enabled: if the source of the high-side MOSFET doesn't drop, the low side MOSFET is switched on so allowing the negative current of the inductor to recirculate. This mechanism allows the system to regulate even if the current is negative. The BOOTx and VCCDRx pins are separated from IC's power supply (VCC pin) as well as signal ground (SGND pin) and power ground (PGNDx pin) in order to maximize the switching noise immunity. The separated supply for the different drivers gives high flexibility in MOSFET choice, allowing the use of logic-level MOSFET. Several combination of supply can be chosen to optimize performance and efficiency of the application. Power conversion input is also flexible; 5 V, 12 V bus or any bus that allows the conversion (See maximum duty cycle limitations) can be chosen freely. 51/64 System control loop compensation L6713A 21 System control loop compensation The control loop is composed by the current sharing control loop (See Figure 9) and the average current mode control loop. Each loop gives, with a proper gain, the correction to the PWM in order to minimize the error in its regulation: the current sharing control loop equalize the currents in the inductors while the average current mode control loop fixes the output voltage equal to the reference programmed by VID. Figure 25 shows the block diagram of the system control loop. The system control loop is reported in Figure 26. The current information IDROOP sourced by the DROOP pin flows into RFB implementing the dependence of the output voltage from the read current. Figure 25. Main control loop L3 PWM3 1/5 L2 PWM2 1/5 L1 PWM1 1/5 ERROR AMPLIFIER 4/5 IDROOP COMP FB DROOP VREF COUT ROUT CURRENT SHARING DUTY CYCLE CORRECTION IINFO1 IINFO2 IINFO3 ZF(s) ZFB(s) (PHASE2 Only applies when using 3-PHASE Operation) The system can be modeled with an equivalent single phase converter which only difference is the equivalent inductor L/N (where each phase has an L inductor). The control loop gain results (obtained opening the loop after the COMP pin): PWM ⋅ Z F ( s ) ⋅ ( R DROOP + Z P ( s ) ) G LOOP ( s ) = – ------------------------------------------------------------------------------------------------------------------ZF ( s ) 1[ Z P ( s ) + Z L ( s ) ] ⋅ -------------- + ⎛ 1 + -----------⎞ ⋅ R FB A(s) ⎝ A ( s )⎠ Where: ● ● ● ● ● ● ● DCR is the Inductor parasitic resistance; function; DCR R DROOP = ------------ ⋅ R F B is the equivalent output resistance determined by the droop Rg ZP(s) is the impedance resulting by the parallel of the output capacitor (and its ESR) and the applied load RO; ZF(s) is the compensation network impedance; ZL(s) is the parallel of the N inductor impedance; A(s) is the error amplifier gain; V IN 4 PWM = -- ⋅ -----------------5 Δ V OSC is the PWM transfer function where ΔVOSC is the oscillator ramp amplitude and has a typical value of 3 V. 52/64 L6713A System control loop compensation Removing the dependence from the error amplifier gain, so assuming this gain high enough, and with further simplifications, the control loop gain results: G LOOP 1 + s ⋅ C ⋅ (R //R + ESR ) V Z ( s ) R O + R DROOP O DROOP O 4 IN F ( s ) = – -- ⋅ --------------------- ⋅ --------------- ⋅ ------------------------------------------- ⋅ -------------------------------------------------------------------------------------------------------------------------------------------R R R 5 ΔV 2 L FB L L OSC LR + ------s ⋅ C ⋅ ---- + s ⋅ ------------------ + C ⋅ ESR + C ⋅ ------- + 1 ON ON ON N ⋅ RO O The system control loop gain (See Figure 26) is designed in order to obtain a high DC gain to minimize static error and to cross the 0dB axes with a constant -20dB/dec slope with the desired crossover frequency ωT. Neglecting the effect of ZF(s), the transfer function has one zero and two poles; both the poles are fixed once the output filter is designed (LC filter resonance ωLC) and the zero (ωESR) is fixed by ESR and the Droop resistance. Figure 26. Equivalent control loop block diagram (left) and bode diagram (right) PWM d VOUT L / N ESR IDROOP VOUT dB RO GLOOP(s) K CO VREF DROOP FB RF COMP CF CP VSEN FBG RF[dB] ZF(s) ZF(s) ω RFB ωLC = ωF ωESR ωT ZFB(s) To obtain the desired shape an RF-CF series network is considered for the ZF(s) implementation. A zero at ωF=1/RFCF is then introduced together with an integrator. This integrator minimizes the static error while placing the zero ωF in correspondence with the LC resonance assures a simple -20dB/dec shape of the gain. In fact, considering the usual value for the output filter, the LC resonance results to be at frequency lower than the above reported zero. Compensation network can be simply designed placing ωF = ωLC and imposing the crossover frequency ωT as desired obtaining (always considering that ωT might be not higher than 1/10th of the switching frequency FSW): R FB ⋅ Δ V OSC 5 L -R F = --------------------------------- ⋅ -- ⋅ ω T ⋅ ------------------------------------------------------V IN 4 N ⋅ ( R DROOP + ESR ) L C O ⋅ --N = -------------------RF CF Moreover, it is suggested to filter the high frequency ripple on the COMP pin adding also a capacitor between COMP pin and FB pin (it does not change the system bandwidth: 1 C P = ----------------------------------------------2 ⋅ π ⋅ R F ⋅ N ⋅ FSW 53/64 Thermal monitor L6713A 22 Thermal monitor L6713A continuously senses the system temperature through TM pin: depending on the voltage sensed by this pin, the device sets free the VR_FAN pin as a warning and, after further temperature increase, also the VR_HOT pin as an alarm condition. These signals can be used to give a boost to the system fan (VR_FAN) and improve the VR cooling, or to initiate the CPU low power state (VR_HOT) in order to reduce the current demand from the processor so reducing also the VR temperature. In a different manner, VR_FAN can be used to initiate the CPU low power state so reducing the processor current requirements and VR_HOT to reset the system in case of further dangerous temperature increase. Thermal sensors is external to the PWM control IC since the controller is normally not located near the heat generating components: it is basically composed by a NTC resistor and a proper biasing resistor RTM. NTC must be connected as close as possible at the system hot-spot in order to be sure to control the hottest point of the VR. Typical connection is reported in Figure 27 that also shows how the trip point can be easily programmed by modifying the divider values in order to cross the VR_FAN and VR_HOT thresholds at the desired temperatures. Both VR_HOT and VR_FAN are active high and open drain outputs. Thermal Monitor function is enabled if VCC>>UVLOVCC. Figure 27. System thermal monitor typical connections TM Voltage - NTC=3300/4250K 4.00 +5V (Place remotely, near Hot Spot) 3.80 3.60 TM Voltage[V] Sense Element TM RTM 3.40 3.20 3.00 2.80 2.60 2.40 2.20 2.00 80 85 90 95 100 105 Rtm = 330 Rtm = 390 Rtm = 470 110 115 120 Temperature [degC] 54/64 L6713A Tolerance band (TOB) definition 23 Tolerance band (TOB) definition Output voltage load-line varies considering component process variation, system temperature extremes, and age degradation limits. Moreover, individual tolerance of the components also varies among designs: it is then possible to define a manufacturing tolerance band (TOBManuf) that defines the possible output voltage spread across the nominal load line characteristic. TOBManuf can be sliced into different three main categories: Controller tolerance, external current sense circuit tolerance and time constant matching error tolerance. All these parameters can be composed thanks to the RSS analysis so that the manufacturing variation on TOB results to be: TOB Manuf = TOB Controller + TOB CurrSense + TOB TCMatching 2 2 2 Output voltage ripple (VP=VPP/2) and temperature measurement error (VTC) must be added to the manufacturing TOB in order to get the system tolerance band as follow: TOB = TOB Manuf + V P + V TC All the component spreads and variations are usually considered at 3σ. Here follows an explanation on how to calculate these parameters for a reference L6713A application. 23.1 Controller tolerance (TOBController) It can be further sliced as follow: ● Reference tolerance. L6713A is trimmed during the production stage to ensure the output voltage to be within kVID = ± 0.5 % (± 0.6 % for AMD DAC) over temperature and line variations. In addition, the device automatically adds a -19 mV offset (Only for Intel mode) avoiding the use of any external component. This offset is already included during the trimming process in order to avoid the use of any external circuit to generate this offsets and, moreover, avoiding the introduction of any further error to be considered in the TOB calculation. Current reading circuit. The device reads the current flowing across the inductor DCR by using its dedicated differential inputs. The current sourced by the VRD is then reproduced and sourced from the DROOP pin scaled down by a proper designed gain as follow: DCR I DROOP = ------------ ⋅ I OUT Rg ● This current multiplied by the RFB resistor connected from FB pin vs. the load allows programming the droop function according to the selected DCR/Rg gain and RFB resistor. Deviations in the current sourced due to errors in the current reading, impacts on the output voltage depending on the size of RFB resistor. The device is trimmed during the production stage in order to guarantee a maximum deviation of kIFB = ± 1 μA from the nominal value. Controller tolerance results then to be: TOB Controller = [ ( VID – 19mV ) ⋅ k VID ] + ( k IDROOP ⋅ R FB ) 2 2 55/64 Tolerance band (TOB) definition L6713A 23.2 Ext. current sense circuit tolerance (TOBCurrSense) It can be further sliced as follow: ● Inductor DCR Tolerance (kDCR). Variations in the inductor DCR impacts on the output voltage since the device reads a current that is different from the real current flowing into the sense element. As a results, the controller will source a IDROOP current different from the nominal. The results will be an AVP different from the nominal in the same percentage as the DCR is different from the nominal. Since all the sense elements results to be in parallel, the error related to the inductor DCR has to be divided by the number of phases (N). Trans-conductance resistors tolerance (kRg). Variations in the Rg resistors impacts in the current reading circuit gain and so impacts on the output voltage. The results will be an AVP different from the nominal in the same percentage as the Rg is different from the nominal. Since all the sense elements results to be in parallel, and so the three current reading circuits, the error related to the Rg resistors has to be divided by the number of phases (N). NTC initial accuracy (kNTC_0). Variations in the NTC nominal value at room temperature used for the thermal compensation impacts on the AVP in the same percentage as before. In addition, the benefit of the division by the number of phases N cannot be applied in this case. NTC temperature accuracy (kNTC). NTC variations from room to hot also impacts on the output voltage positioning. The impact is bigger as big is the temperature variation from room to hot (ΔT). ● ● ● All these parameters impacts the AVP, so they must be weighted on the maximum voltage swing from zero load up to the maximum electrical current (VAVP). Total error from external current sense circuit results: TOB CurrSense = α ⋅ Δ T ⋅ k NTC 2 k DCR k Rg 2 2 V AVP ⋅ ------------- + -------- + k NTC0 + ⎛ ---------------------------------⎞ ⎝ ⎠ DCR N N 2 2 23.3 Time constant matching error tolerance (TOBTCMatching) ● Inductance and capacitance tolerance (kL, kC). Variations in the inductance value and in the value of the capacitor used for the time constant matching causes over/under shoots after a load transient appliance. This impacts the output voltage and then the TOB. Since all the sense elements results to be in parallel, the error related to the time constant mismatch has to be divided by the number of phases (N). Capacitance temperature variations (kCt). The capacitor used for time constant matching also vary with temperature (ΔTC) impacting on the output voltage transients ad before. Since all the sense elements results to be in parallel, the error related to the time constant mismatch has to be divided by the number of phases (N). ● All these parameters impact the dynamic AVP, so they must be weighted on the maximum dynamic voltage swing (Idyn). Total error due to time constant mismatch results: TOB TCMatching = k L + k C + ( k Ct ⋅ Δ TC ) 2 V AVPDyn ⋅ --------------------------------------------------------N 2 2 2 56/64 L6713A Tolerance band (TOB) definition 23.4 Temperature measurement error (VTC) Error in the measured temperature (for thermal compensation) impacts on the output regulated voltage since the correction form the compensation circuit is not what required to keep the output voltage flat. The measurement error (εTemp) must be multiplied by the copper temp coefficient (α) and compared with the sensing resistance (RSENSE): this percentage affects the AVP voltage as follow: α ⋅ ε Temp V TC = ----------------------- ⋅ V AVP R SENSE 57/64 Layout guidelines L6713A 24 Layout guidelines Since the device manages control functions and high-current drivers, layout is one of the most important things to consider when designing such high current applications. A good layout solution can generate a benefit in lowering power dissipation on the power paths, reducing radiation and a proper connection between signal and power ground can optimize the performance of the control loops. Two kind of critical components and connections have to be considered when layouting a VRM based on L6713A: power components and connections and small signal components connections. 24.1 Power components and connections These are the components and connections where switching and high continuous current flows from the input to the load. The first priority when placing components has to be reserved to this power section, minimizing the length of each connection and loop as much as possible. To minimize noise and voltage spikes (EMI and losses) these interconnections must be a part of a power plane and anyway realized by wide and thick copper traces: loop must be anyway minimized. The critical components, i.e. the power transistors, must be close one to the other. The use of multi-layer printed circuit board is recommended. Figure 28 shows the details of the power connections involved and the current loops. The input capacitance (CIN), or at least a portion of the total capacitance needed, has to be placed close to the power section in order to eliminate the stray inductance generated by the copper traces. Low ESR and ESL capacitors are preferred, MLCC are suggested to be connected near the HS drain. Use proper VIAs number when power traces have to move between different planes on the PCB in order to reduce both parasitic resistance and inductance. Moreover, reproducing the same high-current trace on more than one PCB layer will reduce the parasitic resistance associated to that connection. Connect output bulk capacitor as near as possible to the load, minimizing parasitic inductance and resistance associated to the copper trace also adding extra decoupling capacitors along the way to the load when this results in being far from the bulk capacitor bank. Gate traces must be sized according to the driver RMS current delivered to the power MOSFET. The device robustness allows managing applications with the power section far from the controller without losing performances. External gate resistors help the device to dissipate power resulting in a general cooling of the device. When driving multiple MOSFETs in parallel, it is suggested to use one resistor for each MOSFET. 58/64 L6713A Layout guidelines 24.2 Small signal components and connections These are small signal components and connections to critical nodes of the application as well as bypass capacitors for the device supply (See Figure 28). Locate the bypass capacitor (VCC, VCCDRx and Bootstrap capacitor) close to the device and refer sensible components such as frequency set-up resistor ROSC, over current resistor ROCP and OVP resistor ROVP to SGND. Star grounding is suggested: connect SGND to PGND plane in a single point to avoid that drops due to the high current delivered causes errors in the device behavior. Warning: Boot capacitor extra charge. Systems that do not use Schottky diodes might show big negative spikes on the phase pin. This spike can be limited as well as the positive spike but has an additional consequence: it causes the bootstrap capacitor to be over-charged. This extra-charge can cause, in the worst case condition of maximum input voltage and during particular transients, that boot-to-phase voltage overcomes the abs. max. ratings also causing device failures. It is then suggested in this cases to limit this extracharge by adding a small resistor in series to the boot diode (one resistor can be enough for all the three diodes if placed upstream the diode anode, See Figure 28) and by using standard and low-capacitive diodes. Figure 28. Power connections and related connections layout (same for all phases) To limit CBOOT Extra-Charge VIN BOOTx VIN CBOOT UGATEx PHASEx CIN L CIN L PHASEx VCC LGATEx PGNDx LOAD SGND +Vcc LOAD Remote sensing connection must be routed as parallel nets from the FB/VSEN pins to the load in order to avoid the pick-up of any common mode noise. Connecting these pins in points far from the load will cause a non-optimum load regulation, increasing output tolerance. Locate current reading components close to the device. The PCB traces connecting the reading point must use dedicated nets, routed as parallel traces in order to avoid the pick-up of any common mode noise. It's also important to avoid any offset in the measurement and, to get a better precision, to connect the traces as close as possible to the sensing elements. Symmetrical layout is also suggested. Small filtering capacitor can be added, near the controller, between VOUT and SGND, on the CSx- line to allow higher layout flexibility. 59/64 Embedding L6713A - based VR L6713A 25 Embedding L6713A - based VR When embedding the VRD into the application, additional care must be taken since the whole VRD is a switching DC/DC regulator and the most common system in which it has to work is a digital system such as MB or similar. In fact, latest MB has become faster and powerful: high speed data bus are more and more common and switching-induced noise produced by the VRD can affect data integrity if not following additional layout guidelines. Few easy points must be considered mainly when routing traces in which high switching currents flow (high switching currents cause voltage spikes across the stray inductance of the trace causing noise that can affect the near traces): Keep safe guarding distance between high current switching VRD traces and data buses, especially if high-speed data bus to minimize noise coupling. Keep safe guard distance or filter properly when routing bias traces for I/O sub-systems that must walk near the VRD. Possible causes of noise can be located in the PHASE connections, MOSFET gate drive and Input voltage path (from input bulk capacitors and HS drain). Also PGND connections must be considered if not insisting on a power ground plane. These connections must be carefully kept far away from noise-sensitive data bus. Since the generated noise is mainly due to the switching activity of the VRM, noise emissions depend on how fast the current switches. To reduce noise emission levels, it is also possible, in addition to the previous guidelines, to reduce the current slope by properly tuning the HS gate resistor and the PHASE snubber network. 60/64 L6713A Package mechanical data 26 Package mechanical data In order to meet environmental requirements, ST offers these devices in ECOPACK® packages. These packages have a lead-free second level interconnect. The category of second level interconnect is marked on the package and on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. ECOPACK is an ST trademark. ECOPACK specifications are available at: www.st.com 61/64 Package mechanical data L6713A Table 15. Dim. TQFP64 mechanical data mm. Min. Typ. Max. 1.20 0.05 0.95 0.17 0.09 11.80 9.80 3.50 7.50 11.80 9.80 3.50 7.50 0.50 0.45 0.60 1.00 0° 3.5° 7° 0.080 0° 0.75 0.0177 12.00 10.00 12.20 10.20 6.10 0.464 0.386 0.1378 0.295 0.0197 0.0236 0.0393 3.5° 7° 0.0031 0.0295 12.00 10.00 1.00 0.22 0.15 1.05 0.27 0.20 12.20 10.20 6.10 0.002 0.0374 0.0066 0.0035 0.464 0.386 0.1378 0.295 0.472 0.394 0.480 0.401 0.2402 0.472 0.394 0.0393 0.0086 Min. inch Typ. Max. 0.0472 0.006 0.0413 0.0086 0.0078 0.480 0.401 0.2402 A A1 A2 b c D D1 D2 D3 E E1 E2 E3 e L L1 k ccc Figure 29. Package dimensions 62/64 L6713A Revision history 27 Revision history Table 16. Date 03-Mar-2006 07-Nov-2006 04-Aug-2008 Document revision history Revision 1 2 3 Initial release. Updated D2 and E2 exposed tab measures in Table 15: TQFP64 mechanical data Updated Table 2 on page 7, Table 4 on page 12, Figure 22 on page 48, Section 19 on page 50, Changes 63/64 L6713A Please Read Carefully: Information in this document is provided solely in connection with ST products. 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