L6714

L6714 4 phase controller with embedded drivers for Intel VR10, VR11 and AMD 6Bit CPUs Features ■ 0.5% output voltage accuracy ■ 7/8 bit programmable output up to 1.60000V Intel VR10.x, VR11 DAC ■ 6 bit programmable output up to 1.5500V AMD 6Bit DAC ■ High current integrated gate drivers ■ Full differential current sensing across inductor or low side MOSFET ■ Embedded VRD thermal monitor ■ Integrated remote sense buffer ■ Dynamic VID management ■ Adjustable reference voltage offset ■ Programmable Soft-Start ■ Low-Side-Less startup ■ Programmable over voltage protection ■ Preliminary over voltage ■ Constant over current protection ■ Oscillator internally fixed at 150kHz externally adjustable ■ Output enable ■ SS_END / PGOOD signal Description ) s ( ct u d o r P Application e t e l o s b O ■ TQFP64 10mm x 10mm package with Exposed Pad ■ High current VRD for desktop CPUs ■ Workstation and server CPU power supply ■ VRM modules Order codes TQFP64 (Exposed Pad) c u d ) s t( L6714 implements a four phase step-down controller with 90º phase-shift between each phase with integrated high current drivers in a compact 10mm x 10mm body package with exposed pad. e t le o r P The device embeds selectable DACs: the output voltage ranges up to 1.60000V (both Intel VR10.x and VR11 DAC) or up to 1.5500V (AMD 6Bit DAC) managing D-VID with ±0.5% output voltage accuracy over line and temperature variations. Additional programmable offset can be added to the reference voltage with a single external resistor. o s b O - The controller assures fast protection against load over current and under / over voltage (in this last case also before UVLO). In case of over-current the system works in Constant Current mode until UVP. Selectable current reading adds flexibility to the design allowing current sense across inductor or LS MOSFET. System Thermal Monitor is also provided allowing system protection from over-temperature conditions. Part number Package Packaging L6714 TQFP64 Tube L6714TR TQFP64 Tape and reel November 2006 Rev 3 1/70 www.st.com 70 Contents L6714 Contents 1 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 2 Pin settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 3 2.1 Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2.2 Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Electrical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 3.1 Maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 3.2 Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 ) s t( 4 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 5 VID Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 c u d o r P 5.1 Mapping for the Intel VR11 mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 5.2 Voltage Identification (VID) for Intel VR11 mode . . . . . . . . . . . . . . . . . . . 17 5.3 Voltage Identifications (VID) for Intel VR10 mode + 6.25mV . . . . . . . . . . 19 5.4 Mapping for the AMD 6BIT mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 5.5 Voltage identifications (VID) codes for AMD 6BIT mode . . . . . . . . . . . . . 21 e t le ) s ( ct o s b O - 6 Reference schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 7 Device description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 8 Configuring the device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 u d o 8.1 9 t e l o s b O 10 11 2/70 r P e DAC selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Current reading and current sharing loop . . . . . . . . . . . . . . . . . . . . . . 32 10.1 Low side current reading . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 10.2 Inductor current reading . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Remote voltage sense . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 L6714 12 Contents Voltage positioning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 12.1 Droop function (Optional) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 12.2 Offset (Optional) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 13 Dynamic VID transitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 14 Enable and disable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 15 Soft start . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 16 15.1 Intel mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 15.2 AMD mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 15.3 Low-Side-Less startup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 ) s t( Output voltage monitor and protections . . . . . . . . . . . . . . . . . . . . . . . . 47 c u d 16.1 Under voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 16.2 Preliminary over voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 16.3 Over voltage and programmable OVP . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 16.4 PGOOD (Only for AMD mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 e t le o r P o s b O - 17 Maximum Duty-cycle limitation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 18 Over current protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 ) s ( ct 18.1 Low side MOSFET sense over current . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 18.2 Inductor sense over current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 u d o 19 Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 20 Driver section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 21 t e l o s b O 22 r P e System control loop compensation . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 21.1 Compensation network guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 Thermal monitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 3/70 Contents 23 L6714 24 Tolerance band (TOB) definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 23.1 Controller tolerance (TOB controller) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 23.2 Ext. current sense circuit tolerance (TOB CurrSense - Inductor Sense) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 23.3 Time constant matching error tolerance (TOB TCMatching) . . . . . . . . . . 63 23.4 Temperature measurement error (VTC) . . . . . . . . . . . . . . . . . . . . . . . . . . 63 Layout guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 24.1 Power components and connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 24.2 Small signal components and connections . . . . . . . . . . . . . . . . . . . . . . . 65 25 Embedding L6714 - Based VR... . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 26 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 27 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 c u d e t le ) s ( ct u d o r P e t e l o s b O 4/70 o s b O - o r P ) s t( L6714 Block diagram PGND4 LGATE4 VCCDR4 PHASE4 BOOT4 UGATE4 PGND3 LGATE3 VCCDR3 PHASE3 UGATE3 BOOT3 PGND2 LGATE2 VCCDR2 PHASE2 UGATE2 BOOT2 PGND1 LGATE1 PHASE1 VCCDR1 L6714 block diagram BOOT1 Figure 1. UGATE1 1 Block diagram VR_HOT SS_END / PGOOD HS1 HS1 HS2 LS2 HS3 LS3 HS4 LS4 VR_FAN CURRENT SHARING CORRECTION CS_SEL PWM4 AVERAGE CURRENT PWM3 OCP2 OCP1 OCP3 CS_SEL 64k 64k e t le 12.5µA ERROR AMPLIFIER ) s ( ct CS1CS1+ CS_SEL CS2- CS3- OCP3 CH4 CURRENT READING CS3+ CS_SEL CS4CS4+ VCC OVP SGND DAC / CS_SEL VCC OVP CS2+ CS_SEL OCP4 64k o s b O - OCP2 CH3 CURRENT READING 64k FBG REMOTE BUFFER VSEN FB DROOP OUTEN OFFSET IOFFSET 1.240V Pr DAC / CS_SEL OVP COMPARATOR VID7 / D-VID od 12.5µA OFFSET TOTAL DELIVERED CURRENT COMP uc OCP4 +150mV / 1.800V / OVP VID_SEL ) s t( CH1 CURRENT READING CH2 CURRENT READING IDROOP DAC WITH DYNAMIC VID CONTROL IOFFSET VID1 OUTEN TM PWM4 OCP1 DAC/CS_SEL VID0 VID5 PWM2 L6714 CONTROL LOGIC AND PROTECTIONS OUTEN VID4 CURRENT SHARING CORRECTION PWM3 VCC VCCDR VID6 CURRENT SHARING CORRECTION PWM2 PWM1 VID3 LOGIC PWM ADAPTIVE ANTI CROSS CONDUCTION 3.200V PWM1 DIGITAL SOFT START VID2 LOGIC PWM ADAPTIVE ANTI CROSS CONDUCTION FBR SS_OSC / REF CURRENT SHARING CORRECTION 4 PHASE OSCILLATOR OSC / FAULT LOGIC PWM ADAPTIVE ANTI CROSS CONDUCTION 3.600V LOGIC PWM ADAPTIVE ANTI CROSS CONDUCTION u d o r P e t e l o s b O 5/70 Pin settings L6714 2 Pin settings 2.1 Connections Pin connection (Through top view) VR_FAN VR_HOT SS_END / PGOOD VID0 VID1 VID2 VID3 VID4 VID5 VID6 VID7 / D-VID OSC / FAULT FBG FBR VID_SEL OVP Figure 2. TM SGND VCCDR4 LGATE4 PGND4 PGND2 LGATE2 VCCDR2 VCCDR3 LGATE3 PGND3 PGND1 LGATE1 VCCDR1 PHASE1 N.C. 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 49 32 50 31 51 30 52 29 53 28 54 27 55 26 56 e t le 59 60 so 61 62 63 64 1 2 3 4 u d o t e l o s b O 6/70 5 b O 6 7 8 23 22 21 20 19 18 17 9 10 11 12 13 14 15 16 UAGTE1 BOOT1 N.C. PHASE3 UGATE3 BOOT3 N.C. PHASE2 UGATE2 BOOT2 N.C. PHASE4 UGATE4 BOOT4 VCC DAC / CS_SEL ) s ( ct r P e 24 58 c u d o r P 25 L6714 57 OFFSET CS1CS1+ CS3CS3+ CS2CS2+ CS4CS4+ COMP FB DROOP VSEN SGND SSOSC / REF OUTEN ) s t( L6714 2.2 Pin settings Functions Table 1. Pin functions N° Pin 1 UGATE1 Channel 1 HS driver output. A small series resistors helps in reducing device-dissipated power. 2 BOOT1 Channel 1 HS driver supply. Connect through a capacitor (100nF typ.) to PHASE1 and provide necessary Bootstrap diode. A small resistor in series to the boot diode helps in reducing Boot capacitor overcharge. 3 N.C. 4 PHASE3 Channel 3 HS driver return path. It must be connected to the HS3 mosfet source and provides return path for the HS driver of channel 3. 5 UGATE3 Channel 3 HS driver output. A small series resistors helps in reducing device-dissipated power. 6 BOOT3 Channel 3 HS driver supply. Connect through a capacitor (100nF typ.) to PHASE3 and provide necessary Bootstrap diode. A small resistor in series to the boot diode helps in reducing Boot capacitor overcharge. 7 N.C. Not internally connected. c u d Not internally connected. e t le ) s t( o r P o s b O - 8 PHASE2 Channel 2 HS driver return path. It must be connected to the HS2 mosfet source and provides return path for the HS driver of channel 2. 9 UGATE2 Channel 2 HS driver output. A small series resistors helps in reducing device-dissipated power. 10 t e l o ) s ( ct Channel 2 HS driver supply. Connect through a capacitor (100nF typ.) to PHASE2 and provide necessary Bootstrap diode. A small resistor in series to the boot diode helps in reducing Boot capacitor overcharge. u d o BOOT2 r P e s b O Function 11 N.C. 12 PHASE4 Channel 4 HS driver return path. It must be connected to the HS4 mosfet source and provides return path for the HS driver of channel 4. 13 UGATE4 Channel 4 HS driver output. A small series resistors helps in reducing device-dissipated power. BOOT4 Channel 4 HS driver supply. Connect through a capacitor (100nF typ.) to PHASE4 and provide necessary Bootstrap diode. A small resistor in series to the boot diode helps in reducing Boot capacitor overcharge. 14 Not internally connected. 7/70 Pin settings L6714 Table 1. Pin functions N° Pin Function 15 VCC Device supply voltage. The operative voltage is 12V ±15%. Filter with 1µF (typ) MLCC vs. SGND. DAC/ CS_SEL DAC and Current Sense SELection Pin. This pin sources a constant 12.5µA current. By connecting a resistor vs. SGND it is possible to select between Intel and AMD integrated DACs and Current Sense methods. Filter with 100pF(max) vs. SGND. DACs and Current Sense methods cannot be changed dynamically. See “DAC selection” Section and See Table 10 for details. OUTEN OUTput ENable Pin. Forced low, the device stops operations with all MOSFET OFF: all the protections are disabled except for Section 16.2: Preliminary over voltage on page 47. Set free, the device starts-up implementing soft-start up to the selected VID code. Cycle this pin to recover latch from protections; filter with 1nF (typ) vs. SGND. 16 17 c u d 18 SSOSC/ REF e t le o r P o s b O - SGND All the internal references are referred to this pin. Connect to the PCB Signal Ground. 20 VSEN Remote Buffer Output, it manages OVP and UVP protections and PGOOD (when applicable). See “Output voltage monitor and protections” Section and See Table 10 for details. ) s ( ct u d o DROOP A current proportional to the total current read is sourced from this pin according to the Current Reading Gain. Short to FB to implement Droop Function or Short to SGND to disable the function.Connecting to SGND through a resistor and filtering with a capacitor, the current info can be used for other purposes. See “Droop function (Optional)” Section 22 FB Error Amplifier Inverting Input. Connect with a resistor RFB vs. VSEN and with an RF - CF vs. COMP. 23 COMP Error Amplifier Output. Connect with an RF - CF vs. FB. The device cannot be disabled by pulling down this pin. CS4+ Channel 4 Current Sense Positive Input. LS Mosfet Sense: connect through a resistor Rg to the LS mosfet Source. Inductor DCR Sense: connect through an R-C filter to the phase-side of the channel 4 inductor. See “Layout guidelines” Section for proper layout of this connection. r P e t e l o 24 8/70 Intel Mode. Soft Start OSCillator Pin. By connecting a resistor RSSOSC vs. SGND, it allows programming the frequency FSS of an internal additional oscillator that drives the reference during Soft-Start. Setting this frequency allows programming the Soft-Start time TSS proportionally to the RSSOSC connected with a gain of 20.1612 [µs / kΩ]. The same slope implemented to reach VBOOT has to be considered also when the reference moves from VBOOT to the programmed VID code. See “Soft start” Section for details. AMD Mode. REFerence Output. Filter with 47Ω - 4.7nF vs. SGND. 19 21 s b O ) s t( L6714 Pin settings Table 1. N° 25 26 27 28 29 30 Pin functions Pin Function CS4- Channel 4 Current Sense Negative Input. LS Mosfet Sense: connect through a resistor Rg to the LS mosfet Drain. Inductor DCR Sense: connect through a Rg resistor to the output-side of the channel 4 inductor. See “Layout guidelines” Section for proper layout of this connection. CS2+ Channel 2 Current Sense Positive Input. LS Mosfet Sense: connect through a resistor Rg to the LS mosfet Source. Inductor DCR Sense: connect through an R-C filter to the phase-side of the channel 2 inductor. See “Layout guidelines” Section for proper layout of this connection. CS2- Channel 2 Current Sense Negative Input. LS Mosfet Sense: connect through a resistor Rg to the LS mosfet Drain. Inductor DCR Sense: connect through a Rg resistor to the output-side of the channel 2 inductor. See “Layout guidelines” Section for proper layout of this connection. c u d ) s t( CS3+ Channel 3 Current Sense Positive Input. LS Mosfet Sense: connect through a resistor Rg to the LS mosfet Source. Inductor DCR Sense: connect through an R-C filter to the phase-side of the channel 3 inductor. See “Layout guidelines” Section for proper layout of this connection. CS3- Channel 3 Current Sense Negative Input. LS Mosfet Sense: connect through a resistor Rg to the LS mosfet Drain. Inductor DCR Sense: connect through a Rg resistor to the output-side of the channel 3 inductor. See “Layout guidelines” Section for proper layout of this connection. CS1+ Channel 1 Current Sense Positive Input. LS Mosfet Sense: connect through a resistor Rg to the LS mosfet Source. Inductor DCR Sense: connect through an R-C filter to the phase-side of the channel 1 inductor. See “Layout guidelines” Section for proper layout of this connection. e t le ) s ( ct o r P o s b O - u d o r P e 31 t e l o O bs 32 CS1- OFFSET Channel 1 Current Sense Negative Input. LS Mosfet Sense: connect through a resistor Rg to the LS mosfet Drain. Inductor DCR Sense: connect through a Rg resistor to the output-side of the channel 1 inductor. See “Layout guidelines” Section for proper layout of this connection. Offset Programming Pin. Internally fixed at 1.240V, connecting a ROFFSET resistor vs. SGND allows setting a current that is mirrored into FB pin in order to program a positive offset according to the selected RFB. Short to SGND to disable the function. See “Offset (Optional)” Section for details. 9/70 Pin settings L6714 Table 1. N° 33 34 Pin functions Pin Function OVP Over Voltage Programming Pin. Internally pulled up by 12.5µA(typ) to 5V. Set free to use built-in protection thresholds as reported into Table 10. Connect to SGND through a ROVP resistor and filter with 100pF (max) to set the OVP threshold to a fixed voltage according to the ROVP resistor. See “Over voltage and programmable OVP” Section Section for details. VID_SEL Intel Mode. It allows selecting between VR10 (short to SGND, Table 7) or VR11 (floating,Table 6 ) DACs ,internally pulled up by 12.5µA (typ.).. See “Configuring the device” Section for details. AMD Mode. Not Applicable. Needs to be shorted to SGND. 35 FBR Remote Buffer Non Inverting Input. Connect to the positive side of the load to perform remote sense. See “Layout guidelines” Section for proper layout of this connection. 36 FBG Remote Buffer Inverting Input. Connect to the negative side of the load to perform remote sense. See “Layout guidelines” Section for proper layout of this connection. c u d 37 38 OSC/ FAULT VID7/ DVID VID6 t e l o s b O 10/70 40 to 45 Oscillator Pin. It allows programming the switching frequency FSW of each channel: the equivalent switching frequency at the load side results in being multiplied by the phase number N. Frequency is programmed according to the resistor connected from the pin vs. SGND or VCC with a gain of 6kHz/µA (see relevant section for details). Leaving the pin floating programs a switching frequency of 150kHz per phase. The pin is forced high (5V) to signal an OVP FAULT: to recover from this condition, cycle VCC or the OUTEN pin. See “Oscillator” Section for details. e t le o r P o s b O - VID7 - Intel Mode. See VID5 to VID0 Section. DVID - AMD Mode. DVID Output. CMOS output pulled high when the controller is performing a D-VID transition (with 32 clock cycle delay after the transition has finished). See “Dynamic VID transitions” Section Section for details. ) s ( ct u d o r P e 39 ) s t( VID5 to VID0 Intel Mode. See VID5 to VID0 Section. AMD Mode. Not Applicable. Need to be shorted to SGND. Intel Mode. Voltage IDentification Pins (also applies to VID6, VID7). Internally pulled up by 25µA to 5V, connect to SGND to program a '0' or leave floating to program a '1'. They allow programming output voltage as specified in Table 6 and Table 7 according to VID_SEL status. OVP and UVP protection comes as a consequence of the programmed code (See Table 10). AMD Mode. Voltage IDentification Pins. Internally pulled down by 12.5µA, leave floating to program a '0' while pull up to more than 1.4V to program a '1'. They allow programming the output voltage as specified in Table 9 on page 21 (VID7 doesn’t care). OVP and UVP protection comes as a consequence of the programmed code (See Table 10). Note. VID6 not used, need to be shorted to SGND. L6714 Pin settings Table 1. N° Pin functions Pin Function SS_END/ PGOOD SSEND - Intel Mode. Soft Start END Signal. Open Drain Output set free after SS has finished and pulled low when triggering any protection. Pull up to a voltage lower than 5V (typ), if not used it can be left floating. PGOOD - AMD Mode. Open Drain Output set free after SS has finished and pulled low when VSEN is lower than the relative threshold. Pull up to a voltage lower than 5V (typ), if not used it can be left floating. VR_HOT Voltage Regulator HOT. Over Temperature Alarm Signal. Open Drain Output, set free when TM overcomes the Alarm Threshold. Thermal Monitoring Output enabled if Vcc > UVLOVCC. See “Thermal monitor” Section for details and typical connections. VR_FAN Voltage Regulator FAN. Over Temperature Warning Signal. Open Drain Output, set free when TM overcomes the Warning Threshold. Thermal Monitoring Output enabled if Vcc > UVLOVCC. See “Thermal monitor” Section for details and typical connections. 49 TM Thermal Monitor Input. It senses the regulator temperature through apposite network and drives VR_FAN and VR_HOT accordingly.Short TM pin to SGND if not used. See “Thermal monitor” Section for details and typical connections. 50 SGND 46 47 48 e t le o r P All the internal references are referred to this pin. Connect to the PCB Signal Ground. o s b O - 51 VCCDR4 Channel 4 LS Driver Supply. It must be connected to others VCCDRx pins. LS Driver supply can range from 5Vbus up to 12Vbus, filter with 1µF MLCC cap vs. PGND4. 52 LGATE4 Channel 4 LS Driver Output. A small series resistor helps in reducing devicedissipated power. 53 PGND4 Channel 4 LS Driver return path. Connect to Power ground Plane. 54 PGND2 Channel 2 LS Driver return path. Connect to Power ground Plane. 55 LGATE2 Channel 2 LS Driver Output. A small series resistor helps in reducing devicedissipated power. VCCDR2 Channel 2 LS Driver Supply. It must be connected to others VCCDRx pins. LS Driver supply can range from 5Vbus up to 12Vbus, filter with 1µF MLCC cap vs. PGND2. 57 VCCDR3 Channel 3 LS Driver Supply. It must be connected to others VCCDRx pins. LS Driver supply can range from 5Vbus up to 12Vbus, filter with 1µF MLCC cap vs. PGND3. 58 LGATE3 Channel 3 LS Driver Output.A small series resistor helps in reducing devicedissipated power. 59 PGND3 Channel 3 LS Driver return path. Connect to Power ground Plane. t e l o 56 ) s ( ct u d o r P e s b O c u d ) s t( 11/70 Pin settings L6714 Table 1. Pin functions N° Pin 60 PGND1 Channel 1 LS Driver return path. Connect to Power ground Plane. 61 LGATE1 Channel 1 LS Driver Output.A small series resistor helps in reducing devicedissipated power. 62 VCCDR1 Channel 1 LS Driver Supply. It must be connected to others VCCDRx pins. LS Driver supply can range from 5Vbus up to 12Vbus, filter with 1µF MLCC cap vs. PGND1. 63 PHASE1 Channel 1 HS driver return path. It must be connected to the HS1 mosfet source and provides return path for the HS driver of channel 1. 64 N.C. PAD Function Not internally connected. Thermal pad connects the Silicon substrate and makes good thermal contact THERMAL with the PCB to dissipate the power necessary to drive the external mosfets. PAD Connect to the PGND plane with several VIAs to improve thermal conductivity. c u d e t le ) s ( ct u d o r P e t e l o s b O 12/70 o s b O - o r P ) s t( L6714 Electrical data 3 Electrical data 3.1 Maximum rating Table 2. Absolute maximum ratings Symbol Parameter Value Unit to PGNDx 15 V Boot voltage 15 V VUGATEx VPHASEx 15 V VCC - VBOOTx 7.5 V -0.3 to VCC + 0.3 V VCC, VCCDRx VBOOTx VPHASEx LGATEx, PHASEx, to PGNDx VPHASEx VID0 to VID7, VID_SEL -0.3 to 5 All other Pins to PGNDx -0.3 to 7 Static condition To PGNDx, VCC=14V, BOOTx=7V, PHASEx=-7.5V od r P e t le Positive peak voltage to PGNDx; T < 20ns @ 600kHz 3.2 V V V Value Unit Thermal resistance junction to ambient (Device soldered on 2s2p PC Board) 40 °C/W TMAX Maximum junction temperature 150 °C TSTG Storage temperature range -40 to 150 °C TJ Junction temperature range 0 to 125 °C 2.5 W Table 3. Thermal data ) s ( ct Symbol RthJA o r P e s b O V 26 Thermal data t e l o -7.5 uc ) s t( PTOT o s b O - Parameter du Maximum power dissipation at TA = 25°C 13/70 Electrical characteristics 4 L6714 Electrical characteristics VCC = 12V ± 15%, TJ = 0°C to 70°C, unless otherwise specified Table 4. Electrical characteristics Symbol Parameter Test condition Min. Typ. Max. Unit Supply Current VCC supply current HGATEx and LGATEx = OPEN VCCDRx = BOOTx = 12V 17 mA ICCDRx VCCDRx supply current LGATEx = OPEN; VCCDRx = 12V 1 mA IBOOTx BOOTx supply current HGATEx = OPEN; PHASEx to PGNDx; VCC = BOOTx = 12V 0.75 mA ICC Power-ON UVLOVCC UVLOVCCDR UVLOOVP VCC Rising; VCCDRx = 5V VCC turn-OFF VCC Falling; VCCDRx = 5V VCCDR turn-ON VCCDRx Rising; VCC = 12V VCCDR turn-OFF VCCDRx Falling; VCC = 12V Pre-OVP turn-ON VCC Rising; VCCDRx = 5V Pre-OVP turn-OFF VCC Falling; VCCDRx = 5V 3.05 3.3 OSC = OPEN OSC = OPEN; TJ = 0°C to 125°C 135 130 150 Main Oscillator Accuracy T1 SS Delay Time T2 SS Time T2 T3 SS Time T3 o r P e (t s) o s b O - Intel mode c u d 8.9 7.3 4.5 3.9 Rising thresholds voltage 9.3 4.8 4.3 3.6 3.85 V V V V 165 170 kHz ms µs 500 µs 50 0.80 V V 1 Intel mode; RSSOSC = 25kΩ Intel mode 7.7 d o r P e let Oscillator and Inhibit FOSC uc VCC turn-ON ) s t( 0.85 0.90 V Output enable intel mode t e l o OUTEN Hysteresis 100 Input low mV 0.80 V Output enable AMD mode bs O dMAX Maximum duty cycle PWMx ramp amplitude FAULT Voltage at Pin OSC 1.40 V 12.5 µA OSC = OPEN; IDROOP = 0µA 80 % OSC = OPEN; IDROOP = 140µA 40 % 4 V 5 V Pull-up current ∆VOSC 14/70 Input high OVP Active L6714 Electrical characteristics Table 4. Electrical characteristics Symbol Parameter Test condition Min. Typ. Max. Unit Intel mode VID = 1.000V to VID = 1.600V FBR = VOUT; FBG = GNDOUT -0.5 - 0.5 % AMD mode VID=1.000V to VID = 1.550V FBR = VOUT; FBG = GNDOUT -0.6 - 0.6 % Reference accuracy AMD mode; respect VID -10 - 10 mV Boot voltage Intel mode VID Pull-up current VID Pull-down current Reference and DAC kVID REF VBOOT IVID Output voltage accuracy 1.081 V Intel mode; VIDx to SGND 25 µA AMD mode; VIDx to 5.4V 12.5 µA Intel mode; Input Low AMD mode; Input Low VIDIL VID thresholds Intel mode; Input High AMD mode; Input High VIDIH VID_SEL VID_SEL threshold (Intel mode) 0.8 1.35 Input low Input high EA DC gain SR EA slew rate e t le CMRR COMP = 10pF to SGND Remote buffer common mode rejection ratio I –I INFOx AVG----------------------------------------I AVG Bias current od r P e Current sense mismatch t e l o b O - LS sense Inductor sense Rg = 1kΩ; IINFOx = 25µA V V 0.3 V 80 dB 20 V/µs 1 V/V 40 dB 25 0 µA -3 - 3 % Over current threshold ICSx-(OCP) - ICSx-(0) 30 35 40 µA kIDROOP Droop current deviation from nominal value OFFSET = SGND; Rg = 1kΩ IDROOP = 0 to 80µA; -2 - 2 µA KIOFFSET Offset current accuracy IOFFSET = 50µA to 250µA -8 - 8 % IOFFSET OFFSET current range 250 µA VOFFSET OFFSET pin bias IOCTH bs O (s) t c u Differential current sensing and offset ICSx+ o r P so RB DC gain c u d 0.8 Error amplifier and remote buffer A0 ) s t( 0.3 0.8 0 IOFFSET = 0 to 250µA 1.240 V 15/70 Electrical characteristics Table 4. L6714 Electrical characteristics Symbol Parameter Test condition Min. Typ. Max. Unit 30 ns Gate drivers HS rise time BOOTx - PHASEx = 10V; CUGATEx to PHASEx = 3.3nF 15 IUGATEx HS source current BOOTx - PHASEx = 10V 2 RUGATEx HS sink resistance BOOTx - PHASEx = 12V LS rise time ILGATEx RLGATEx tRISE_UGATEx tRISE_LGATEx A 2 2.5 Ω VCCDRx = 10V; CLGATEx to PGNDx = 5.6nF 30 55 ns LS source current VCCDRx = 10V 1.8 LS sink resistance VCCDRx = 12V 1.5 0.7 1.1 A 1.5 Ω Protections Intel mode; before VBOOT OVP Programmable OVP Pre-OVP Over voltage protection (VSEN Rising) Intel mode; above VID 100 150 AMD mode 1.700 1.740 IOVP current OVP = SGND 11.5 Comparator offset voltage OVP = 1.8V Preliminary over voltage protection UVLOOVP < VCC < UVLOVCC VCC > UVLOVCC & OUTEN = SGND Hysteresis UVP Pr e t le b O - so 12.5 13.5 µA 0 50 mV 1.800 V 350 mV mV -750 PGOOD PGOOD threshold AMD mode; VSEN falling; below VID -300 VSSEND/ SSEND / PGOOD Voltage low u d o Thermal Monitor VTM r P e I = -4mA 16/70 0.4 V VTM rising 3.2 V TM Alarm (VR_HOT) VTM rising 3.6 V 100 mV TM Hysteresis s b O mV TM Warning (VR_FAN) t e l o VVR_HOT; VVR_FAN mV V VSEN falling; below VID PGOOD 200 1.780 Under voltage protection ) s ( ct V uc od -50 ) s t( 1.300 VR_HOT voltage low; VR_FAN voltage low I = -4mA 0.4 0.4 V V L6714 VID Tables 5 VID Tables 5.1 Mapping for the Intel VR11 mode Table 5. 5.2 Voltage Identification (VID) Mapping for Intel VR11 Mode VID7 VID6 VID5 VID4 VID3 VID2 VID1 VID0 800mV 400mV 200mV 100mV 50mV 25mV 12.5mV 6.25mV Voltage Identification (VID) for Intel VR11 mode Table 6. Voltage Identification (VID) for Intel VR11 mode (See Note). Output voltage HEX Code HEX Code (1) HEX Code Output voltage (1) HEX Code (1) OFF 4 0 1.21250 8 0 0.81250 C 0 1 OFF 4 1 1.20625 8 1 0.80625 0 2 1.60000 4 2 1.20000 8 2 0.80000 od 0 3 1.59375 4 3 1.19375 8 3 0 4 1.58750 4 4 1.18750 8 0 5 1.58125 4 5 1.18125 0 6 1.57500 4 6 0 7 1.56875 4 7 0 8 1.56250 b O - 0 9 1.55625 0 A 1.55000 0 B uc 0 ) s ( ct Output voltage ) s t( (1) 0 0.41250 1 0.40625 C 2 0.40000 0.79375 C 3 0.39375 4 0.78750 C 4 0.38750 so 5 0.78125 C 5 0.38125 8 6 0.77500 C 6 0.37500 1.16875 8 7 0.76875 C 7 0.36875 1.16250 8 8 0.76250 C 8 0.36250 1.17500 8 e t le Pr C 0 4 8 4 9 1.15625 8 9 0.75625 C 9 0.35625 u d o 4 A 1.15000 8 A 0.75000 C A 0.35000 4 B 1.14375 8 B 0.74375 C B 0.34375 1.53750 4 C 1.13750 8 C 0.73750 C C 0.33750 r P e 1.54375 0 C 0 D 1.53125 4 D 1.13125 8 D 0.73125 C D 0.33125 0 E 1.52500 4 E 1.12500 8 E 0.72500 C E 0.32500 0 F 1.51875 4 F 1.11875 8 F 0.71875 C F 0.31875 1 0 1.51250 5 0 1.11250 9 0 0.71250 D 0 0.31250 1 1 1.50625 5 1 1.10625 9 1 0.70625 D 1 0.30625 1 2 1.50000 5 2 1.10000 9 2 0.70000 D 2 0.30000 1 3 1.49375 5 3 1.09375 9 3 0.69375 D 3 0.29375 1 4 1.48750 5 4 1.08750 9 4 0.68750 D 4 0.28750 1 5 1.48125 5 5 1.08125 9 5 0.68125 D 5 0.28125 1 6 1.47500 5 6 1.07500 9 6 0.67500 D 6 0.27500 t e l o s b O Output voltage 17/70 VID Tables L6714 Table 6. Voltage Identification (VID) for Intel VR11 mode (See Note). HEX Code Output voltage HEX Code (1) HEX Code Output voltage (1) HEX Code (1) Output voltage (1) 1 7 1.46875 5 7 1.06875 9 7 0.66875 D 7 0.26875 1 8 1.46250 5 8 1.06250 9 8 0.66250 D 8 0.26250 1 9 1.45625 5 9 1.05625 9 9 0.65625 D 9 0.25625 1 A 1.45000 5 A 1.05000 9 A 0.65000 D A 0.25000 1 B 1.44375 5 B 1.04375 9 B 0.64375 D B 0.24375 1 C 1.43750 5 C 1.03750 9 C 0.63750 D C 0.23750 1 D 1.43125 5 D 1.03125 9 D 0.63125 D D 0.23125 1 E 1.42500 5 E 1.02500 9 E 0.62500 D E 0.22500 1 F 1.41875 5 F 1.01875 9 F 0.61875 D F 0.21875 2 0 1.41250 6 0 1.01250 A 0 0.61250 E 0 2 1 1.40625 6 1 1.00625 A 1 0.60625 E 1 2 2 1.40000 6 2 1.00000 A 2 0.60000 E 2 2 3 1.39375 6 3 0.99375 A 3 0.59375 E 3 0.19375 2 4 1.38750 6 4 0.98750 A 4 0.58750 E 4 0.18750 2 5 1.38125 6 5 0.98125 A 2 6 1.37500 6 6 0.97500 A 2 7 1.36875 6 7 0.96875 2 8 1.36250 6 8 2 9 1.35625 6 9 2 A 1.35000 6 2 B 1.34375 2 C 1.33750 o r P e du 6 o r P 0.20625 0.20000 5 0.58125 E 5 0.18125 6 0.57500 E 6 0.17500 7 0.56875 E 7 0.16875 0.96250 so A 8 0.56250 E 8 0.16250 0.95625 A 9 0.55625 E 9 0.15625 A A b O 0.95000 A A 0.55000 E A 0.15000 B 0.94375 A B 0.54375 E B 0.14375 C 0.93750 A C 0.53750 E C 0.13750 (s) ct 6 e t le c u d ) s t( 0.21250 2 D 1.33125 6 D 0.93125 A D 0.53125 E D 0.13125 2 E 1.32500 6 E 0.92500 A E 0.52500 E E 0.12500 2 t e l o F 1.31875 6 F 0.91875 A F 0.51875 E F 0.11875 3 0 1.31250 7 0 0.91250 B 0 0.51250 F 0 0.11250 3 1 1.30625 7 1 0.90625 B 1 0.50625 F 1 0.10625 3 2 1.30000 7 2 0.90000 B 2 0.50000 F 2 0.10000 3 3 1.29375 7 3 0.89375 B 3 0.49375 F 3 0.09375 3 4 1.28750 7 4 0.88750 B 4 0.48750 F 4 0.08750 3 5 1.28125 7 5 0.88125 B 5 0.48125 F 5 0.08125 3 6 1.27500 7 6 0.87500 B 6 0.47500 F 6 0.07500 3 7 1.26875 7 7 0.86875 B 7 0.46875 F 7 0.06875 s b O 18/70 Output voltage L6714 VID Tables Table 6. Voltage Identification (VID) for Intel VR11 mode (See Note). Output voltage HEX Code HEX Code (1) Output voltage Output voltage HEX Code (1) Output voltage HEX Code (1) (1) 3 8 1.26250 7 8 0.86250 B 8 0.46250 F 8 0.06250 3 9 1.25625 7 9 0.85625 B 9 0.45625 F 9 0.05625 3 A 1.25000 7 A 0.85000 B A 0.45000 F A 0.05000 3 B 1.24375 7 B 0.84375 B B 0.44375 F B 0.04375 3 C 1.23750 7 C 0.83750 B C 0.43750 F C 0.03750 3 D 1.23125 7 D 0.83125 B D 0.43125 F D 0.03125 3 E 1.22500 7 E 0.82500 B E 0.42500 F E OFF 3 F 1.21875 7 F 0.81875 B F 0.41875 F F OFF 1. According to VR11 specs, the device automatically regulates output voltage 19mV lower to avoid any external offset to modify the built-in 0.5% accuracy improving TOB performances. Output regulated voltage is than what extracted from the table lowered by 19mV built-in offset. 5.3 c u d Voltage Identifications (VID) for Intel VR10 mode + 6.25mV (VID7 does not care) Table 7. 0 1 0 1 0 1 1 0 1 0 1 0 1 0 0 1 0 1 1 0 1 0 1 0 1 1 0 0 1 0 1 1 1 (1) so b O - Output voltage (1) 1 0 1 0 1 1 1.20000 1.59375 1 1 0 1 0 1 0 1.19375 1.58750 1 1 0 1 1 0 1 1.18750 0 1.58125 1 1 0 1 1 0 0 1.18125 1 1 1.57500 1 1 0 1 1 1 1 1.17500 1 1 0 1.56875 1 1 0 1 1 1 0 1.16875 0 0 0 1 1.56250 1 1 1 0 0 0 1 1.16250 ) s ( ct 1.60000 VID VID VID VID VID VID VID 4 3 2 1 0 5 6 1 0 1 1 1 1 0 0 0 0 1.55625 1 1 1 0 0 0 0 1.15625 0 1 1 0 0 1 1 1.55000 1 1 1 0 0 1 1 1.15000 0 1 1 0 0 1 0 1.54375 1 1 1 0 0 1 0 1.14375 0 1 1 0 1 0 1 1.53750 1 1 1 0 1 0 1 1.13750 0 1 1 0 1 0 0 1.53125 1 1 1 0 1 0 0 1.13125 0 1 1 0 1 1 1 1.52500 1 1 1 0 1 1 1 1.12500 0 1 1 0 1 1 0 1.51875 1 1 1 0 1 1 0 1.11875 0 1 1 1 0 0 1 1.51250 1 1 1 1 0 0 1 1.11250 0 1 1 1 0 0 0 1.50625 1 1 1 1 0 0 0 1.10625 0 t e l o 0 bs Output voltage 1 u d o r P e 0 e t le o r P Voltage identifications (VID) for Intel VR10 mode + 6.25mV (See Note). VID VID VID VID VID VID VID 4 3 2 1 0 5 6 O ) s t( 19/70 VID Tables L6714 Table 7. Voltage identifications (VID) for Intel VR10 mode + 6.25mV (See Note). VID VID VID VID VID VID VID 4 3 2 1 0 5 6 Output voltage (1) 1 1 1 0 1 1 1.50000 1 1 1 1 0 1 1 1.10000 0 1 1 1 0 1 0 1.49375 1 1 1 1 0 1 0 1.09375 0 1 1 1 1 0 1 1.48750 1 1 1 1 1 0 1 OFF 0 1 1 1 1 0 0 1.48125 1 1 1 1 1 0 0 OFF 0 1 1 1 1 1 1 1.47500 1 1 1 1 1 1 1 OFF 0 1 1 1 1 1 0 1.46875 1 1 1 1 1 1 0 OFF 1 0 0 0 0 0 1 1.46250 0 0 0 0 0 0 1 1.08750 1 0 0 0 0 0 0 1.45625 0 0 0 0 0 0 0 1.08125 1 0 0 0 0 1 1 1.45000 0 0 0 0 0 1 1 1.07500 1 0 0 0 0 1 0 1.44375 0 0 0 0 0 1 0 1 0 0 0 1 0 1 1.43750 0 0 0 0 1 0 1 1 0 0 0 1 0 0 1.43125 0 0 0 0 1 0 0 1 0 0 0 1 1 1 1.42500 0 0 0 1 1 1.05000 1 0 0 0 1 1 0 1.41875 0 0 0 1 0 1.04375 1 0 0 1 0 0 1 1.41250 0 1 0 0 1 0 0 0 1.40625 0 1 0 0 1 0 1 1 1.40000 1 0 0 1 0 1 0 1 0 0 1 1 0 1 1 0 0 1 1 0 1 0 0 1 1 1 0 0 o r P e c u d ) s t( 1.06875 1.06250 1.05625 0 0 o r P 1 0 0 1 1.03750 0 0 1 0 0 0 1.03125 0 0 1 0 1 1 1.02500 0 0 0 1 0 1 0 1.01875 1.38750 0 0 0 1 1 0 1 1.01250 so e t le 0 0 1 0 1 0 b O 1.38125 0 0 0 1 1 0 0 1.00625 1 1 1.37500 0 0 0 1 1 1 1 1.00000 du (s) ct 1.39375 1 1 1 0 1.36875 0 0 0 1 1 1 0 0.99375 0 0 0 1 1.36250 0 0 1 0 0 0 1 0.98750 0 1 0 1 0 0 0 0 1.35625 0 0 1 0 0 0 0 0.98125 0 1 0 0 1 1 1.35000 0 0 1 0 0 1 1 0.97500 0 1 0 0 1 0 1.34375 0 0 1 0 0 1 0 0.96875 1 0 1 0 1 0 1 1.33750 0 0 1 0 1 0 1 0.96250 1 0 1 0 1 0 0 1.33125 0 0 1 0 1 0 0 0.95625 1 0 1 0 1 1 1 1.32500 0 0 1 0 1 1 1 0.95000 1 0 1 0 1 1 0 1.31875 0 0 1 0 1 1 0 0.94375 1 0 1 1 0 0 1 1.31250 0 0 1 1 0 0 1 0.93750 1 0 1 1 0 0 0 1.30625 0 0 1 1 0 0 0 0.93125 1 0 1 1 0 1 1 1.30000 0 0 1 1 0 1 1 0.92500 1 1 t e l o 1 20/70 (1) VID VID VID VID VID VID VID 4 3 2 1 0 5 6 0 1 s b O Output voltage L6714 VID Tables Table 7. Voltage identifications (VID) for Intel VR10 mode + 6.25mV (See Note). VID VID VID VID VID VID VID 4 3 2 1 0 5 6 Output voltage (1) VID VID VID VID VID VID VID 4 3 2 1 0 5 6 Output voltage (1) 1 0 1 1 0 1 0 1.29375 0 0 1 1 0 1 0 0.91875 1 0 1 1 1 0 1 1.28750 0 0 1 1 1 0 1 0.91250 1 0 1 1 1 0 0 1.28125 0 0 1 1 1 0 0 0.90625 1 0 1 1 1 1 1 1.27500 0 0 1 1 1 1 1 0.90000 1 0 1 1 1 1 0 1.26875 0 0 1 1 1 1 0 0.89375 1 1 0 0 0 0 1 1.26250 0 1 0 0 0 0 1 0.88750 1 1 0 0 0 0 0 1.25625 0 1 0 0 0 0 0 0.88125 1 1 0 0 0 1 1 1.25000 0 1 0 0 0 1 1 0.87500 1 1 0 0 0 1 0 1.24375 0 1 0 0 0 1 0 0.86875 1 1 0 0 1 0 1 1.23750 0 1 0 0 1 0 1 1 1 0 0 1 0 0 1.23125 0 1 0 0 1 0 0 1 1 0 0 1 1 1 1.22500 0 1 0 0 1 1 1 1 1 0 0 1 1 0 1.21875 0 1 0 0 0.84375 1 1 0 1 0 0 1 1.21250 0 1 0 0 1 0.83750 1 1 0 1 0 0 0 1.20625 0 o r P 1 0 0 0.83125 e t le 1 0 0 1 1 0 1 0 ) s t( 0.86250 c u d 0.85625 0.85000 1. According to VR10.x specs, the device automatically regulates output voltage 19mV lower to avoid any external offset to modify the built-in 0.5% accuracy improving TOB performances. Output regulated voltage is than what extracted from the table lowered by 19mVbuilt-in offset. VID7 doesn’t care. 5.4 o s b Mapping for the AMD 6BITO mode ) s ( t c u d o r P Voltage identifications (VID) codes for AMD 6BIT mode e t e Table 8. 5.5 b O l o s Voltage identifications (VID) mapping for AMD 6BIT mode VID4 VID3 VID2 VID1 VID0 400mV 200mV 100mV 50mV 25mV Table 9. Voltage identifications (VID) codes for AMD 6BIT mode (See Note). VID 5 VID 4 VID 3 VID 2 VID 1 VID 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Output Voltage Output Voltage (1) VID 5 VID 4 VID 3 VID 2 VID 1 VID 0 0 1.5500 1 0 0 0 0 0 0.7625 0 1 1.5250 1 0 0 0 0 1 0.7500 0 1 0 1.5000 1 0 0 0 1 0 0.7375 0 1 1 1.4750 1 0 0 0 1 1 0.7250 (1) 21/70 VID Tables L6714 Table 9. VID 5 VID 4 VID 3 VID 2 VID 1 VID 0 0 0 0 1 0 0 0 0 1 0 0 0 0 0 0 Output Voltage (1) VID 4 VID 3 VID 2 VID 1 VID 0 0 1.4500 1 0 0 1 0 0 0.7125 0 1 1.4250 1 0 0 1 0 1 0.7000 1 1 0 1.4000 1 0 0 1 1 0 0.6875 0 1 1 1 1.3750 1 0 0 1 1 1 0.6750 0 1 0 0 0 1.3500 1 0 1 0 0 0 0.6625 0 0 1 0 0 1 1.3250 1 0 1 0 0 1 0.6500 0 0 1 0 1 0 1.3000 1 0 1 0 1 0 0.6375 0 0 1 0 1 1 1.2750 1 0 1 0 1 1 0.6250 0 0 1 1 0 0 1.2500 1 0 1 1 0 0 0.6125 0 0 1 1 0 1 1.2250 1 0 1 1 0 1 0 0 1 1 1 0 1.2000 1 0 1 1 1 0 0 0 1 1 1 1 1.1750 1 0 1 1 1 1 0 1 0 0 0 0 1.1500 1 1 0 0 0 0.5625 0 1 0 0 0 1 1.1250 1 1 0 0 1 0.5500 0 1 0 0 1 0 1.1000 1 0 1 0 0.5375 0 1 0 0 1 1 1.0750 1 0 1 0 1 0 0 1.0500 0 1 0 1 0 1 0 1 0 1 1 0 0 1 0 1 1 0 1 1 0 0 1 1 du 0 0 o r P e 0 e t le o r P c u d 0 0 (1) ) s t( 0.6000 0.5875 0.5750 1 0 1 0 0 1 1 0.5250 1 0 1 0 0 0.5125 1.0250 so 1 1 0 1 0 1 0.5000 1.0000 1 1 0 1 1 0 0.4875 1 1 b O 0.9750 1 1 0 1 1 1 0.4750 0 0.9500 1 1 1 0 0 0 0.4625 1 0.9250 1 1 1 0 0 1 0.4500 1 0 0.9000 1 1 1 0 1 0 0.4375 ct (s) 0 1 1 1 1 0 1 1 0.8750 1 1 1 0 1 1 0.4250 1 1 1 0 0 0.8500 1 1 1 1 0 0 0.4125 1 1 1 0 1 0.8250 1 1 1 1 0 1 0.4000 0 1 1 1 1 0 0.8000 1 1 1 1 1 0 0.3875 0 1 1 1 1 1 0.7750 1 1 1 1 1 1 0.3750 0 0 t e l o 0 22/70 Output Voltage VID 5 0 s b O Voltage identifications (VID) codes for AMD 6BIT mode (See Note). 1. VID6 Not Applicable, need to be left unconnected. L6714 6 Reference schematic Reference schematic Figure 3. Reference schematic - Intel VR10.x, VR11 inductor sense VIN LIN to BOOT2 62 56 57 51 15 19,50 33 16 32 37 18 38 39 VID bus from CPU 40 41 42 43 44 45 34 VID_SEL 17 OUTEN 23 CF t e l o 22 21 BOOT1 UGATE1 VCCDR3 PHASE1 VCCDR4 LGATE1 VCC PGND1 SGND CS1- OVP CS1+ DAC / CS_SEL OFFSET BOOT2 UGATE2 OSC/FAULT PHASE2 SSOSC / REF LGATE2 VID7 / DVID VID6 PGND2 VID5 CS2- VID4 VID3 VID2 VID1 VID0 VID_SEL (t s) OUTEN CS2+ BOOT3 47 48 +5V NTC 49 to BOOT3 CIN VIN PHASE3 LGATE3 COMP PGND3 CS3- FB CS3+ DROOP BOOT4 UGATE4 VSEN PHASE4 VR_HOT LGATE4 VR_FAN PGND4 TM CS4CS4+ SS_END / PGOOD FBR 1 HS1 63,64 L1 61 LS1 R 60 C 31 Rg 30 10 VIN 9 HS2 7,8 55 LS2 54 27 e t le Rg 26 so 6 5 c u d L2 b O UGATE3 RFB 20 2 to BOOT4 VCCDR2 uc d o r P e RF VCCDR1 L6714 GNDIN s b O to BOOT1 58 o r P R C Vcc_core VIN COUT HS3 3,4 ) s t( LOAD L3 LS3 R 59 C 29 Rg 28 14 VIN 13 HS4 11,12 L4 52 LS4 R 53 C 25 Rg 24 46 SS_END FBG L6714 REF. SCH. (INDUCTOR - Intel Mode) 35 36 23/70 Reference schematic Figure 4. L6714 Reference schematic - Intel VR10.x, VR11 LS MOSFET sense VIN LIN to BOOT1 to BOOT2 62 56 57 51 15 19,50 33 170k 15 32 37 18 38 39 VID bus from CPU 40 41 42 43 44 45 34 VID_SEL 17 OUTEN CF o r P e BOOT1 UGATE1 VCCDR3 PHASE1 VCCDR4 LGATE1 VCC PGND1 SGND CS1- OVP CS1+ DAC / CS_SEL OFFSET du 22 21 BOOT2 UGATE2 OSC/FAULT PHASE2 SSOSC / REF LGATE2 VID7 / D-VID VID6 PGND2 VID5 CS2- VID4 VID3 VID2 VID1 VID0 VID_SEL OUTEN CS2+ BOOT3 UGATE3 t e l o s b O 47 48 +5V NTC 49 COMP LGATE3 PGND3 CS3- FB DROOP CS3+ BOOT4 UGATE4 VSEN PHASE4 VR_HOT LGATE4 VR_FAN PGND4 TM CS4CS4+ SSEND / PGOOD FBR FBG L6714 REF. SCH. (MOSFET - Intel Mode) 35 24/70 to BOOT3 CIN VIN 1 HS1 63,64 L1 61 LS1 60 31 Rg 30 Rg 10 VIN 9 HS2 L2 7,8 55 54 27 Rg 26 Rg 36 e t le 6 so 58 ) s t( o r P Vcc_core VIN 5 3,4 c u d LS2 b O PHASE3 RFB 20 2 to BOOT4 VCCDR2 ) s ( ct 23 RF VCCDR1 L6714 GNDIN COUT HS3 LOAD L3 LS3 59 29 Rg 28 Rg 14 VIN 13 HS4 11,12 L4 52 LS4 53 25 Rg 24 Rg 46 PGOOD L6714 Reference schematic Figure 5. Reference schematic - AMD 6BIT inductor sense VIN LIN to BOOT1 to BOOT2 62 56 57 51 15 19,50 33 270k 16 32 37 18 38 39 40 VID bus from CPU 41 42 43 44 45 34 17 OUTEN 23 CF c u d RF o r P e 22 21 VCCDR1 BOOT1 VCCDR3 UGATE1 PHASE1 VCCDR4 LGATE1 VCC PGND1 SGND CS1- OVP CS1+ BOOT2 DAC / CS_SEL OFFSET UGATE2 OSC/FAULT PHASE2 SSOSC / REF LGATE2 VID7 / DVID VID6 PGND2 VID5 CS2- VID4 VID3 VID2 VID1 VID0 VID_SEL OUTEN CS2+ BOOT3 UGATE3 s b O t e l o 47 48 +5V NTC 49 to BOOT3 CIN VIN (t s) COMP LGATE3 PGND3 CS3- FB CS3+ DROOP BOOT4 UGATE4 VSEN PHASE4 VR_HOT LGATE4 VR_FAN PGND4 TM CS4CS4+ SS_END / PGOOD FBR 1 HS1 63,64 L1 61 LS1 R 60 C 31 Rg 30 10 VIN 9 HS2 7,8 L2 55 LS2 54 Rg e t le 26 6 so 58 ) s t( o r P Vcc_core VIN 5 3,4 c u d R C 27 b O PHASE3 RFB 20 2 to BOOT4 VCCDR2 L6714 GNDIN COUT HS3 LOAD L3 LS3 R 59 C 29 Rg 28 14 VIN 13 HS4 11,12 L4 52 LS4 R 53 C 25 Rg 24 46 SS_END FBG L6714 REF. SCH. (INDUCTOR - AMD 6BIT Mode) 35 36 25/70 Reference schematic Figure 6. L6714 Reference schematic - AMD 6BIT LS MOSFET sense VIN LIN to BOOT1 to BOOT2 62 56 57 51 15 19,50 33 15 32 37 18 38 39 40 VID bus from CPU 41 42 43 44 45 34 17 OUTEN CF o r P e BOOT1 UGATE1 VCCDR3 PHASE1 VCCDR4 LGATE1 VCC PGND1 SGND CS1- OVP CS1+ DAC / CS_SEL OFFSET du 22 21 BOOT2 UGATE2 OSC/FAULT PHASE2 SSOSC / REF LGATE2 VID7 / D-VID VID6 PGND2 VID5 CS2- VID4 VID3 VID2 VID1 VID0 VID_SEL OUTEN CS2+ BOOT3 UGATE3 t e l o s b O 47 48 +5V NTC 49 COMP LGATE3 PGND3 CS3- FB DROOP CS3+ BOOT4 UGATE4 VSEN PHASE4 VR_HOT LGATE4 VR_FAN PGND4 TM CS4CS4+ SSEND / PGOOD FBR FBG L6714 REF. SCH. (MOSFET - AMD 6BIT Mode) 35 26/70 to BOOT3 CIN VIN 1 HS1 63,64 L1 61 LS1 60 31 Rg 30 Rg 10 VIN 9 HS2 L2 7,8 55 54 27 Rg 26 Rg 36 e t le 6 so 58 ) s t( o r P Vcc_core VIN 5 3,4 c u d LS2 b O PHASE3 RFB 20 2 to BOOT4 VCCDR2 ) s ( ct 23 RF VCCDR1 L6714 GNDIN COUT HS3 LOAD L3 LS3 59 29 Rg 28 Rg 14 VIN 13 HS4 11,12 L4 52 LS4 53 25 Rg 24 Rg 46 PGOOD L6714 7 Device description Device description L6714 is four-phase PWM controller with embedded high current drivers that provides complete control logic and protections for a high performance step-down DC-DC voltage regulator optimized for advanced microprocessor power supply. Multi phase buck is the simplest and most cost-effective topology employable to satisfy the increasing current demand of newer microprocessors and modern high current VRM modules. It allows distributing equally load and power between the phases using smaller, cheaper and most common external power MOSFET and inductors. Moreover, thanks to the equal phase shift between each phase, the input and output capacitor count results in being reduced. Phase interleaving causes in fact input RMS current and output ripple voltage reduction and show an effective output switching frequency increase: the 150kHz free-running frequency per phase, externally adjustable through a resistor, results multiplied on the output by the number of phases. L6714 permits easy and flexible system design by allowing current reading across either inductor or low side MOSFET in fully differential mode simply selecting the desired way through apposite pin. In both cases, also a sense resistor in series to the related element can be considered to improve reading precision. The current information read corrects the PWM output in order to equalize the average current carried by each phase limiting the error at ±3% over static and dynamic conditions unless considering the sensing element spread. c u d ) s t( o r P The controller includes multiple DACs, selectable through an apposite pin, allowing compatibility with both Intel VR10,VR11 and AMD 6BIT processors specifications, also performing D-VID transitions accordingly. e t le Low-Side-Less start-up allows soft start over pre-biased output avoiding dangerous current return through the main inductors as well as negative spike at the load side. o s b O - L6714 provides programmable Over-Voltage protection to protect the load from dangerous over stress. It can be externally set to a fixed voltage through an apposite resistor, or it can be set internally, latching immediately by turning ON the lower driver and driving high the FAULT pin. Furthermore, preliminary OVP protection also allows the device to protect load from dangerous OVP when VCC is not above the UVLO threshold. ) s ( ct The Over-Current protection provided, with an OC threshold for each phase, causes the device to enter in constant current mode until the latched UVP. u d o L6714 provides system Thermal Monitoring: through an apposite pin the device senses the temperature of the hottest component in the application driving the Warning and the Alarm signal as a consequence. r P e t e l o A compact 10x10mm body TQFP64 package with exposed thermal pad allows dissipating the power to drive the external MOSFET through the system board. s b O 27/70 Configuring the device 8 L6714 Configuring the device Multiple DACs and different current reading methodologies need to be configured before the system starts-up by programming the apposite pin DAC/CS_SEL. The configuration of this pin identifies two main working areas (See Table 10) distinguishing between compliancy with Intel VR10,VR11 or AMD 6BIT specifications. According to the main specification considered, further customs can be done: main differences are regarding the DAC table, soft-start implementation, protection management and Dynamic VID Transitions. Of course, the Current Reading method can be still selected through DAC / CS_SEL pin. See Table 11 and See Table 12 for further details about the device configuration. 8.1 DAC selection ) s t( L6714 embeds a selectable DAC (through DAC/CS_SEL, See Table 10) that allows to regulate the output voltage with a tolerance of ±0.5% (±0.6% for AMD DAC) recovering from offsets and manufacturing variations. In case of selecting Intel Mode, the device automatically introduces a -19mV (both VRD10.x and VR11) offset to the regulated voltage in order to avoid any external offset circuitry to worsen the guaranteed accuracy and, as a consequence, the calculated system TOB. c u d Table 10. DAC / CS_SEL Resistance vs. SGND DAC 0 (Short) 170kΩ (s) 270kΩ t c u OPEN o s b O - d o r P e MOSFET RdsON Inductor DCR AMD MOSFET RdsON OVP UVP VID + 150mV (typ) or Programmable -750mV (typ) 1.800V (typ) or Programmable -750mV (typ) Filter DAC/CS_SEL pin with 100pF(max) vs. SGND. Output voltage is programmed through the VID pins: they are inputs of an internal DAC that is realized by means of a series of resistors providing a partition of the internal voltage reference. The VID code drives a multiplexer that selects a voltage on a precise point of the divider. The DAC output is delivered to an amplifier obtaining the voltage reference (i.e. the set-point of the error amplifier, VREF). t e l o s b O 28/70 Current sense method Inductor DCR Intel Note: e t le DAC / CS_SEL settings (See Note). o r P L6714 Configuring the device Table 11. Intel mode configuration (See Note). Pin Function DAC / CS_SEL It allows selecting the Intel Mode and, furthermore, between Inductor or LS MOSFET current reading. Static info, no dynamic changes allowed. SGND: Inductor Sense; 170kΩ to SGND: LS MOSFET Sense. Filter with 100pF(max). SSOSC / REF It allows programming the soft-start time TSS. See “Soft start” Section for details. Resistor RSSOSC vs. SGND. It allows selecting between VR11 DAC or VR10.x + 6.25mV extended DAC. Static info, no dynamic changes allowed. Open: VR11 (Table 6). Short to SGND: VR10.x (Table 7). They allow programming the Output Voltage according to Table 6 and Table 7. Dynamic transitions managed, See “Dynamic VID transitions” Section for details. Open: Logic “1” (25µA pull-up) Short to SGND: “0” VID_SEL VID7 to VID0 SSEND / PGOOD Note: ) s t( Soft Start end signal set free after soft-start has Pull-up to anything lower than finished. It only indicates soft-start has finished. 5V. c u d VID pull-ups / pull-downs, VID voltage thresholds and OUTEN thresholds changes according to the selected DAC: See Table 4 for details. Table 12. Function o s b O - o r P Typical connection DAC / CS_SEL It allows selecting the AMD mode and, furthermore, between Inductor or LS MOSFET current reading. Static info, no dynamic changes allowed. 270kΩ to SGND: Inductor Sense; OPEN: LS MOSFET Sense; Filter with 100pF(max). SSOSC / REF The reference used for the regulation is available on this pin. Filter with 47Ω - 4.7nF vs. SGND. Not Applicable Need to be shorted to SGND. VID_SEL o r P e VID7 / DVID VID6 c u d (t s) Pulled high when performing a D-VID transition. Not Applicable The pin is kept high with a 32 clock cycles delay. Not Applicable Needs to be shorted to SGND VID5 to VID0 They allow programming the Output Voltage according to Table 9. Dynamic transitions managed, See “Dynamic VID transitions” Section for details. Open: “0” (12.5µA pull-down) Pull-up to V > 1.4V: “1” SSEND / PGOOD Power Good signal set free after soft-start has finished whenever the output voltage is within limits. Pull-up to anything lower than 5V. t e l o s b O e t le AMD mode configuration (See Note). Pin Note: Typical connection VID pull-ups / pull-downs, VID voltage thresholds and OUTEN thresholds changes according to the selected DAC: See Table 4 for details. 29/70 Power dissipation 9 L6714 Power dissipation L6714 embeds high current MOSFET drivers for both high side and low side MOSFET: it is then important to consider the power the device is going to dissipate in driving them in order to avoid overcoming the maximum junction operative temperature. In addition, since the device has an exposed pad to better dissipate the power, the thermal resistance between junction and ambient consequent to the layout is also important: thermal pad need to be soldered to the PCB ground plane through several VIAs in order to facilitate the heat dissipation. Two main terms contribute to the device power dissipation: bias power and drivers' power. The first one (PDC) depends on the static consumption of the device through the supply pins and is simply quantifiable as follows (assuming to supply HS and LS drivers with the same VCC of the device): P DC = V CC ⋅ ( I CC + N ⋅ I CCDRx + N ⋅ I BOOTx ) where N is the number of phases. ) s t( Drivers' power is the power needed by the driver to continuously switch on and off the external MOSFET; it is a function of the switching frequency and total gate charge of the selected MOSFET. It can be quantified considering that the total power PSW dissipated to switch the MOSFET (easy calculable) is dissipated by three main factors: external gate resistance (when present), intrinsic MOSFET resistance and intrinsic driver resistance. This last term is the important one to be determined to calculate the device power dissipation. c u d e t le The total power dissipated to switch the MOSFET results: o r P P SW = N ⋅ F SW ⋅ ( Q GHS ⋅ V BOOT + Q GLS ⋅ V CCDRx ) o s b O - External gate resistors help the device to dissipate the switching power since the same power PSW will be shared between the internal driver impedance and the external resistor resulting in a general cooling of the device. When driving multiple MOSFET in parallel, it is suggested to use one gate resistor for each MOSFET. ) s ( ct u d o r P e t e l o s b O 30/70 L6714 Power dissipation Figure 7. L6714 dissipated power (Quiescent + switching). L6714; Rgate=0; Rmosfet=0 Controller Dissipated Power [mW] 5000 HS=1xSTD38NH02L; LS=1xSTD90NH02L HS=2xSTD38NH02L; LS=2xSTD90NH02L HS=1xSTD55NH22L; LS=1xSTD95NH02L HS=2xSTD55NH22L; LS=2xSTD95NH02L HS=3xSTD55NH22L; LS=3xSTD95NH02L 4500 4000 3500 3000 2500 2000 1500 1000 500 0 50 100 150 200 250 300 350 400 450 500 550 Switching frequency [kHz] per phase Controller Dissipated Power [mW] c u d L6714; Rhs=2.2; Rls=3.3; Rmosfet=1 7000 HS=1xSTD38NH02L; LS=1xSTD90NH02L HS=2xSTD38NH02L; LS=2xSTD90NH02L HS=1xSTD55NH2LL; LS=1xSTD95NH02L HS=2xSTD55NH2LL; LS=2xSTD95NH02L HS=3xSTD55NH2LL; LS=3xSTD95NH02L 6000 5000 e t le 4000 3000 2000 1000 ) s ( ct 0 50 100 u d o 150 ) s t( o r P o s b O 200 250 300 350 400 450 500 550 Switching Frequency per phase [kHz] r P e t e l o s b O 31/70 Current reading and current sharing loop 10 L6714 Current reading and current sharing loop L6714 embeds a flexible, fully-differential current sense circuitry that is able to read across both low side or inductor parasitic resistance or across a sense resistor placed in series to that element. The fully-differential current reading rejects noise and allows placing sensing element in different locations without affecting the measurement's accuracy. The kind of sense element can be simply chosen through the DAC/CS_SEL pin according to See Table 10. Current sharing control loop reported in Figure 8: it considers a current IINFOx proportional to the current delivered by each phase and the average current I AVG = ΣI INFOx ⁄ ( N ). The error between the read current IINFOx and the reference IAVG is then converted into a voltage that with a proper gain is used to adjust the duty cycle whose dominant value is set by the voltage error amplifier in order to equalize the current carried by each phase. Details about connections are shown in Figure 9. Figure 8. Current sharing loop. c u d IINFO1 o r P PWM1 Out e t le IAVG IINFO2 AVG so From EA b O - PWM2 Out IINFO3 ) s ( ct o r P e t e l o s b O 32/70 du PWM3 Out IINFO4 PWM4 Out ) s t( L6714 10.1 Current reading and current sharing loop Low side current reading When reading current across LS, the current flowing trough each phase is read using the voltage drop across the low side MOSFET RdsON or across a sense resistor in its series and it is internally converted into a current. The trans-conductance ratio is issued by the external resistor Rg placed outside the chip between CSx- and CSx+ pins toward the reading points. The current sense circuit tracks the current information for a time TTRACK centered in the middle of the LS conduction time and holds the tracked information during the rest of the period. L6714 sources a constant 25µA bias current from the CSx+ pin: the current reading circuitry uses this pin as a reference and the reaction keeps the CSx- pin to this voltage during the reading time (an internal clamp keeps CSx+ and CSx- at the same voltage sinking from the CSx- pin the necessary current during the hold time; this is needed to avoid absolute maximum rating overcome on CSx- pin). The current that flows from the CSx- pin is then given by (See Figure 9): R dsON I CSx- = 25µA + ----------------- ⋅ I PHASEx = 25µA + I INFOx Rg ) s t( where RdsON is the ON resistance of the low side MOSFET and Rg is the trans-conductance resistor used between CSx- and CSx+ pins toward the reading points; IPHASEx is the current carried by the relative phase and IINFOx is the current information signal reproduced internally. c u d o r P 25µA offset allows negative current reading, enabling the device to check for dangerous returning current between the phases assuring the complete current equalization. 10.2 e t le o s b O - Inductor current reading When reading current across the inductor DCR, the current flowing trough each phase is read using the voltage drop across the output inductor or across a sense resistor in its series and internally converted into a current. The trans-conductance ratio is issued by the external resistor Rg placed outside the chip between CSx- pin toward the reading points. ) s ( ct The current sense circuit always tracks the current information, no bias current is sourced from the CSx+ pin: this pin is used as a reference keeping the CSx- pin to this voltage. To correctly reproduce the inductor current an R-C filtering network must be introduced in parallel to the sensing element. u d o r P e The current that flows from the CSx- pin is then given by the following equation (See Figure 9): s b O t e l o RL 1 + s ⋅ L ⁄ RL I CSx- = -------- ⋅ ------------------------------------- ⋅ I Rg 1 + s ⋅ R ⋅ C PHASEx Where IPHASEx is the current carried by the relative phase. 33/70 Current reading and current sharing loop Figure 9. L6714 Current reading connections. IPHASEx IPHASEx Lx PHASEx LGATEx ICSx- CSx- RLx R C CSx+ Rg NO Bias ICSx-=IINFOx 25µA CSx+ CSx- Rg LS Mosfet RdsON Current Sense Rg Inductor DCR Current Sense Considering now to match the time constant between the inductor and the R-C filter applied (Time constant mismatches cause the introduction of poles into the current reading network causing instability. In addition, it is also important for the load transient response and to let the system show resistive equivalent output impedance), it results: L- = R ⋅ C -----RL ⇒ RL I CSx- = -------- ⋅ I PHASEx = I INFOx ⇒ Rg RL I INFOX = -------- ⋅ I PHASEx Rg Where IINFOx is the current information reproduced internally. e t le ) s ( ct u d o r P e t e l o s b O 34/70 o s b O - c u d ) s t( o r P L6714 11 Remote voltage sense Remote voltage sense The device embeds a Remote Sense Buffer to sense remotely the regulated voltage without any additional external components. In this way, the output voltage programmed is regulated between the remote buffer inputs compensating motherboard or connector losses. It senses the output voltage remotely through the pins FBR and FBG (FBR is for the regulated voltage sense while FBG is for the ground sense) and reports this voltage internally at VSEN pin with unity gain eliminating the errors. Keeping the FBR and FBG traces parallel and guarded by a power plane results in common mode coupling for any picked-up noise. If remote sense is not required, it is enough connecting the resistor RFB directly to the regulated voltage: VSEN becomes not connected and still senses the output voltage through the remote buffer. In this case the FBG and FBR pins must be connected anyway to the regulated voltage (See Figure 10). The remote buffer is included in the trimming chain in order to achieve ±0.5% accuracy (0.6% for the AMD DAC) on the output voltage when the RB is used: eliminating it from the control loop causes the regulation error to be increased by the RB offset worsening the device performances. c u d e t le Figure 10. Remote buffer connections VREF FB od RF r P e RFB t e l o t c u COMP CF VSEN FBR FBG o r P 64k VREF 64k FB COMP RF VSEN 64k 64k 64k (s) o s b O 64k 64k ) s t( 64k Warning: FBR FBG CF To Vcore (Remote Sense) Remote Buffer Used (Up to 0.5% Accuracy) RFB To Vcore Remote Buffer NOT Used (Precision Worsened) s b O 35/70 Voltage positioning 12 L6714 Voltage positioning Output voltage positioning is performed by selecting the reference DAC and by programming the Droop Function and Offset to the reference (See Figure 11). The currents sourced from DROOP and FB pins cause the output voltage to vary according to the external RFB resistor. In addition, the embedded Remote Buffer allows to precisely programming the output voltage offsets and variations by recovering the voltage drops across distribution lines. The output voltage is then driven by the following relationship: V OUT = V REF – R FB ⋅ ( I DROOP – I OFFSET ) where ⎧ V REF = ⎨ VID – 19mV VR10 - VR11 AMD 6BIT ⎩ VID ) s t( DROOP function can be disabled as well as the OFFSET: connecting DROOP pin and FB pin together implements the load regulation dependence while, if this effect is not desired, by shorting DROOP pin to SGND it is possible for the device to operate as a classic Voltage Mode Buck converter. The DROOP pin can also be connected to SGND through a resistor obtaining a voltage proportional to the delivered current usable for monitoring purposes. OFFSET can be disabled by shorting the relative pin to SGND. c u d e t le ) s ( ct u d o r P e t e l o s b O 36/70 o s b O - o r P L6714 12.1 Voltage positioning Droop function (Optional) This method "recovers" part of the drop due to the output capacitor ESR in the load transient, introducing a dependence of the output voltage on the load current: a static error proportional to the output current causes the output voltage to vary according to the sensed current. As shown in Figure 11, the ESR drop is present in any case, but using the droop function the total deviation of the output voltage is minimized. Moreover, more and more highperformance CPUs require precise load-line regulation to perform in the proper way. DROOP function is not then required only to optimize the output filter, but also beacomes a requirement of the load. Connecting DROOP pin and FB pin together, the device forces a current IDROOP, proportional to the read current, into the feedback resistor RFB implementing the load regulation dependence. Since IDROOP depends on the current information about the three phases, the output characteristic vs. load current is then given by: R SENSE V OUT = V REF – R FB ⋅ I DROOP = V REF – R FB ⋅ --------------------- ⋅ I OUT = V REF – R DROOP ⋅ I OUT Rg ) s t( Where RSENSE is the chosen sensing element resistance (Inductor DCR or LS RdsON) and IOUT is the output current of the system. c u d The whole power supply can be then represented by a "real" voltage generator with an equivalent output resistance RDROOP and a voltage value of VREF. RFB resistor can be also designed according to the RDROOP specifications as follow: e t le Rg R FB = R DROOP ⋅ --------------------R SENSE o r P o s b O - Droop function is optional, in case it is not desired, the DROOP pin can be disconnected from the FB and an information about the total delivered current becomes available for debugging, and/or current monitoring. When not used, the pin can be shorted to SGND. ) s ( ct Figure 11. Voltage positioning (left) and droop function (right) O bs ESR Drop VREF VMAX 64k FB COMP RF VSEN 64k DROOP 64k 64k t e l o IOFFSET IDROOP o r P e du FBR FBG CF To Vcore VNOM VMIN RESPONSE WITHOUT DROOP RESPONSE WITH DROOP (Remote Sense) RFB 37/70 Voltage positioning 12.2 L6714 Offset (Optional) The OFFSET pin allows programming a positive offset (VOS) for the output voltage by connecting a resistor ROFFSET vs. SGND; this offset has to be considered in addition to the one already introduced during the production stage for the Intel VR10,VR11 Mode. The OFFSET pin is internally fixed at 1.240V (See Table 4) a current is programmed by connecting the resistor ROFFSET between the pin and SGND: this current is mirrored and then properly sunk from the FB pin as shown in Figure 12. Output voltage is then programmed as follow: V OUT = V REF – R FB ⋅ ( I DROOP – I OFFSET ) Offset resistor can be designed by considering the following relationship (RFB is fixed by the Droop effect): 1.240V R OFFSET = ------------------- ⋅ R FB V OS ) s t( Offset automatically given by the DAC selection differs from the offset implemented through the OFFSET pin: the built-in feature is trimmed in production and assures ±0.5% error (±0.6% for the AMD DAC) over load and line variations. c u d (s) DROOP OFFSET t c u ROFFSET d o r P e t e l o s b O 38/70 o s b O VREF FB RF 64k 64k COMP VSEN 64k IOFFSET 1.240V e t le o r P 64k IDROOP IOFFSET Figure 12. Voltage positioning with offset FBR FBG CF To Vcore (Remote Sense) RFB L6714 13 Dynamic VID transitions Dynamic VID transitions The device is able to manage Dynamic VID Code changes that allow Output Voltage modification during normal device operation. OVP and UVP signals (and PGOOD in case of AMD Mode) are masked during every VID transition and they are re-activated after the transition finishes with a 32 clock cycles delay to prevent from false triggering due to the transition. When changing dynamically the regulated voltage (D-VID), the system needs to charge or discharge the output capacitor accordingly. This means that an extra-current ID-VID needs to be delivered, especially when increasing the output regulated voltage and it must be considered when setting the over current threshold. This current can be estimated using the following relationships: dV OUT I D – VID = C OUT ⋅ -----------------dT VID ) s t( where dVOUT is the selected DAC LSB (6.25mV for VR11 and VR10 Extended DAC or 25mV for AMD DAC) and TVID is the time interval between each LSB transition (externally driven). Overcoming the OC threshold during the dynamic VID causes the device to enter the constant current limitation slowing down the output voltage dV/dt also causing the failure in the D-VID test. c u d o r P L6714 checks for VID code modifications (See Figure 13) on the rising edge of an internal additional DVID-clock and waits for a confirmation on the following falling edge. Once the new code is stable, on the next rising edge, the reference starts stepping up or down in LSB increments every VID-clock cycle until the new VID code is reached. During the transition, VID code changes are ignored; the device re-starts monitoring VID after the transition has finished on the next rising edge available. VID-clock frequency (FDVID) depends on the operative mode selected: for Intel Mode it is in the range of 1MHz to assure compatibility with the specifications while, for AMD Mode, this frequency is lowered to about 250kHz. e t le ) s ( ct o s b O - When L6714 performs a D-VID transition in AMD Mode, DVID pin is pulled high as long as the device is performing the transition (also including the additional 32clocks delay) u d o Warning: r P e s b O t e l o If the new VID code is more than 1 LSB different from the previous, the device will execute the transition stepping the reference with the DVID-clock frequency FDVID until the new code has reached: for this reason it is recommended to carefully control the VID change rate in order to carefully control the slope of the output voltage variation especially in Intel Mode. 39/70 r P e s b O t e l o 40/70 u d o Vout Slope Controlled by internal DVID-Clock Oscillator x 4 Step VID Transition ) s ( ct o s b O - Vout TVID 4 x 1 Step VID Transition Vout Slope Controlled by external driving circuit (TVID) e t le Tsw c u d o r P VID Sampled VID Sampled VID Sampled VID Sampled VID Stable Ref Moved (1) VID Sampled VID Sampled VID Stable Ref Moved (1) VID Sampled VID Sampled VID Stable Ref Moved (1) VID Sampled VID Sampled VID Stable Ref Moved (1) VID Sampled VID Sampled VID Sampled VID Sampled Ref Moved (4) Ref Moved (3) Ref Moved (2) VID Sampled VID Stable Ref Moved (1) VID Sampled VID Sampled Dynamic VID transitions L6714 Figure 13. Dynamic VID transitions VID Clock VID [0,7] t Int. Reference t TDVID ) s t( t t L6714 14 Enable and disable Enable and disable L6714 has three different supplies: VCC pin to supply the internal control logic, VCCDRx to supply the low side drivers and BOOTx to supply the high side drivers. If the voltage at pins VCC and VCCDRx are not above the turn on thresholds specified in the Electrical characteristics, the device is shut down: all drivers keep the MOSFET off to show high impedance to the load. Once the device is correctly supplied, proper operation is assured and the device can be driven by the OUTEN pin to control the power sequencing. Setting the pin free, the device implements a soft start up to the programmed voltage. Shorting the pin to SGND, it resets the device (SS_END/PGOOD is shorted to SGND in this condition) from any latched condition and also disables the device keeping all the MOSFET turned off to show high impedance to the load. c u d e t le ) s ( ct ) s t( o r P o s b O - u d o r P e t e l o s b O 41/70 Soft start 15 L6714 Soft start L6714 implements a soft-start to smoothly charge the output filter avoiding high in-rush currents to be required to the input power supply. The device increases the reference from zero up to the programmed value in different ways according to the selected Operative Mode and the output voltage increases accordingly with closed loop regulation. The device implements Soft-Start only when all the power supplies are above their own turnon thresholds and the OUTEN pin is set free. At the end of the digital Soft-Start, SS_END/PGOOD signal is set free. Protections are active during this phase; Under Voltage is enabled when the reference voltage reaches 0.6V while Over Voltage is always enabled with a threshold dependent on the selected Operative Mode or with the fixed threshold programmed by ROVP (See “Over voltage and programmable OVP” Section). Figure 14. Soft start Intel Mode OUTEN t T1 T2 u d o r P e 42/70 T3 T4 ) s ( ct TSS s b O VOUT t OVP SS_END t e l o c u d OUTEN VOUT ) s t( AMD 6BIT Mode PGOOD t t so b O t e t le o r P TSS t L6714 15.1 Soft start Intel mode Once L6714 receives all the correct supplies and enables, and Intel Mode has been selected, it initiates the Soft-Start phase with a T1 = 1ms(min) delay. After that, the reference ramps up to VBOOT = 1.081V (1.100V - 19mV) in T2 according to the SSOSC settings and waits for T3 = 75µsec(typ) during which the device reads the VID lines. Output voltage will then ramps up to the programmed value in T4 with the same slope as before (See Figure 14). SSOSC defines the frequency of an internal additional Soft-Start-oscillator used to step the reference from zero up to the programmed value; this oscillator is independent from the main oscillator whose frequency is programmed through the OSC pin. SSOSC sets then the Output Voltage dV/dt during Soft-Start according to the resistor RSSOSC connected vs. SGND. In particular, it allows to precisely programming the start-up time up to VBOOT (T2) since it is a fixed voltage independent by the programmed VID. Total Soft-Start time dependence on the programmed VID results (See Figure 15): R SSOSC [ kΩ] = T 2 [ µs ] ⋅ 4.9783 ⋅ 10 ⎧ ⎪ ⎪ T SS [ µs ] = 1075 [ µs ] + ⎨ ⎪ ⎪ ⎩ –2 R SSOSC [ kΩ] ------------------------------------ ⋅ V SS –2 5.3816 ⋅ 10 R SSOSC [ kΩ] ------------------------------------ ⋅ [ V BOOT + ( V BOOT – V SS ) ] –2 5.3816 ⋅ 10 e t le c u d ) s t( if ( V SS > V BOOT ) o r P if ( V SS < V BOOT ) where TSS is the time spent to reach the programmed voltage VSS and RSSOSC the resistor connected between SSOSC and SGND in kΩ. o s b O - Protections are active during Soft-Start, UVP is enabled after the reference reaches 0.6V while OVP is always active with a fixed 1.24V threshold before VBOOT and with the threshold coming from the VID (or the programmed VOVP) after VBOOT (See red-dashed line in Figure 14). ) s ( ct Note: If during T3 the programmed VID selects an output voltage lower than VBOOT, the output voltage will ramp to the programmed voltage starting from VBOOT. u d o r P e t e l o s b O 43/70 Soft start L6714 Figure 15. Soft-start time for Intel mode. 8 Soft Start Time Tss [ms] 7 Time to Vboot Time to 1.6000V 6 5 4 3 2 1 0 1 10 100 1000 Rssosc [kOhms] vs. SGND 15.2 AMD mode c u d ) s t( Once L6714 receives all the correct supplies and enables, and AMD Mode has been selected, it initiates the Soft-Start by stepping the reference from zero up to the programmed VID code (See Figure 14); the clock now used to step the reference is the same as the main oscillator programmed by the OSC pin, SSOSC pin is not applicable in this case. The SoftStart time results then (See Figure 16): e t le o r P dV OUT V SS ----------------- = 3.125 ⋅ F SW [ kkHz ] ⇒ TSS = ------------------------------------------------dT 3.125 ⋅ F SW [ kHz ] o s b O - where TSS is the time spent to reach VSS and FSW is the main switching frequency programmed by OSC pin. Protections are active during Soft-Start, UVP is enabled after the reference reaches 0.6V while OVP is always active with the fixed 1.800V threshold (or the programmed VOVP). ) s ( ct u d o r P e t e l o s b O 44/70 L6714 Soft start 4 550 3.5 500 3 450 2.5 400 2 350 1.5 300 Time to 1.6000V Time to 1.1000V 1 250 Switching Frequency per phase 0.5 Switching Freqency [kHz] SoftStart Time Tss [msec] Figure 16. Soft-start time for AMD mode 200 0 150 0 200 400 600 800 1000 4 550 3.5 500 Switching Freqency [kHz] SoftStart Time Tss [msec] Rosc [kOhms] to SGND c u d 3 450 2.5 2 1.5 Time to 1.6000V e t le Time to 1.1000V 1 o r P 400 350 300 250 Switching Frequency per phase so 0.5 0 0 200 b O 400 600 ) s t( 200 150 800 1000 Rosc [kOhms] to SGND ) s ( ct u d o r P e t e l o s b O 45/70 Soft start 15.3 L6714 Low-Side-Less startup In order to avoid any kind of negative undershoot on the load side during start-up, L6714 performs a special sequence in enabling LS driver to switch: during the soft-start phase, the LS driver results disabled (LS=OFF) until the HS starts to switch. This avoid the dangerous negative spike on the output voltage that can happen if starting over a pre-biased output (See Figure 17). This particular feature of the device masks the LS turn-on only from the control loop point of view: protections are still allowed to turn-ON the LS MOSFET in case of over voltage if needed. Figure 17. Low-Side-Less start-up comparison c u d e t le ) s ( ct u d o r P e t e l o s b O 46/70 o s b O - o r P ) s t( L6714 16 Output voltage monitor and protections Output voltage monitor and protections L6714 monitors through pin VSEN the regulated voltage in order to manage the OVP, UVP and PGOOD (when applicable) conditions. The device shows different thresholds when programming different operation mode (Intel or AMD, See Table 10) but the behavior in response to a protection event is still the same as described below. Protections are active also during soft-start (See “Soft start” Section) while are masked during D-VID transitions with an additional 32 clock cycle delay after the transition has finished to avoid false triggering. 16.1 Under voltage If the output voltage monitored by VSEN drops more than -750mV below the programmed reference for more than one clock period, L6714 turns off all MOSFET and latches the condition: to recover it is required to cycle Vcc or the OUTEN pin. This is independent of the selected operative mode. 16.2 c u d Preliminary over voltage ) s t( o r P To provide a protection while VCC is below the UVLOVCC threshold is fundamental to avoid damage to the CPU in case of failed HS MOSFET. In fact, since the device is supplied from the 12V bus, it is basically “blind” for any voltage below the turn-on threshold (UVLOVCC). In order to give full protection to the load, a preliminary-OVP protection is provided while VCC is within UVLOVCC and UVLOOVP. e t le o s b O - This protection turns-on the low side MOSFET as long as the FBR pin voltage is greater than 1.800V with a 350mV hysteresis. When set, the protection drives the LS MOSFET with a gate-to-source voltage depending on the voltage applied to VCCDRx and independently by the turn-ON threshold across these pins (UVLOVCCDR). This protection depends also on the OUTEN pin status as detailed in Figure 18. ) s ( ct A simple way to provide protection to the output in all conditions when the device is OFF (then avoiding the unprotected red region in Figure 18-Left) consists in supplying the controller through the 5VSB bus as shown in Figure 18-Right: 5VSB is always present before +12V and, in case of HS short, the LS MOSFET is driven with 5V assuring a reliable protection of the load. Preliminary OVP is always active before UVLOVCC for both Intel and AMD Modes. u d o r P e t e l o Figure 18. Output voltage protections and typical principle connections O bs +5V Vcc UVLOVCC (OUTEN = 0) Preliminary OVP FBR Monitored (OUTEN = 1) Programmable OVP VSEN Monitored Preliminary OVP Enabled FBR Monitored UVLOOVP SB +12V VCC VCCDR1 VCCDR2 No Protection Provided VCCDR3 47/70 Output voltage monitor and protections 16.3 L6714 Over voltage and programmable OVP Once VCC crosses the turn-ON threshold and the device is enabled (OUTEN = 1), L6714 provides an Over Voltage Protection: when the voltage sensed by VSEN overcomes the OVP threshold, the controller permanently switches on all the low-side MOSFET and switches off all the high-side MOSFET in order to protect the load. The OSC/ FAULT pin is driven high (5V) and power supply or OUTEN pin cycling is required to restart operations.The OVP Threshold varies according to the operative mode selected (See Table 10). The OVP threshold can be also programmed through the OVP pin: leaving the pin floating, it is internally pulled-up and the OVP threshold is set according to Table 10. Connecting the OVP pin to SGND through a resistor ROVP, the OVP threshold becomes the voltage present at the pin. Since the OVP pin sources a constant IOVP = 12.5µA current(See Table 10), the programmed voltage becomes: OVP TH = R OVP ⋅ 12.5µA ⇒ OVP TH R OVP = ------------------12.5µA Filter OVP pin with 100pF(max) vs. SGND. 16.4 c u d PGOOD (Only for AMD mode) o r P ) s t( It is an open-drain signal set free after the soft-start sequence has finished. It is pulled low when the output voltage drops below -300mV of the programmed voltage. e t le ) s ( ct u d o r P e t e l o s b O 48/70 o s b O - L6714 17 Maximum Duty-cycle limitation Maximum Duty-cycle limitation The device limits the maximum duty cycle and this value is not fixed but it depends on the delivered current given by the following relationship: R SENSE D ( max ) = 0.80 – ( I DROOP × 2.857k ) = 0.80 – ⎛ --------------------- × I × 2.857k⎞ ⎝ Rg ⎠ OUT From the previous relationships the maximum duty cycle results: ⎧ 80% D ( max ) = ⎨ ⎩ 40% I DROOP = 0µA I DROOP = 140µA If the desired output characteristic crosses the limited-DMAX maximum output voltage, the output resulting voltage will start to drop after the cross-point. In this case the output voltage starts to decrease following the resulting characteristic (dotted in Figure 19) until UVP is detected or anyway until IDROOP=140µA. c u d ) s t( Figure 19. Maximum Duty-Cycle (left) and limited DMAX output voltage (right) Maximum Duty Cycle VOUT 80 % 0.80 VIN e t le 40 % o r P Limited DMAX Output Voltage DMAX o s b O - 0.40 VIN (s) IDROOP = 140µA (IOCP = N x IOCPx ) t c u Limted-DMAX Output Char. Desired output Char. Resulting Output Char. UVP Threshold IDROOP IOUT IOCP = N x IOCPx (IDROOP = 140µA) d o r P e t e l o s b O 49/70 Over current protection 18 L6714 Over current protection Depending on the current reading method selected, the device limits the peak or the bottom of the inductor current entering in constant current until setting UVP as below explained. The Over Current threshold has to be programmed, by designing the Rg resistors, to a safe value, in order to be sure that the device doesn't enter OCP during normal operation of the device. This value must take into consideration also the extra current needed during the Dynamic VID Transition ID-VID and, since the device reads across MOSFET RdsON or inductor DCR, the process spread and temperature variations of these sensing elements. Moreover, since also the internal threshold spreads, the Rg design has to consider the minimum value IOCTH(min) of the threshold as follow: I OCPx ( max ) ⋅ R SENSE ( max ) Rg = ----------------------------------------------------------------------I OCTH ( min ) where IOCPx is the current measured by the current reading circuitry when the device enters Quasi-Constant-Current. IOCPx must be calculated starting from the corresponding output current value IOUT(OCP) as follow (ID-VID must also be considered when D-VID are implemented) considering that the device performs Track & Hold only for the LS sense mode: I OCPx ⎧I OUT ( OCP ) ∆I PP I D – VID ⎪ -------------------------- – ------------ + -----------------N 2 N ⎪ = ⎨ ∆I I I ⎪ OUT ( OCP ) PP D – VID - + ----------- + ----------------⎪ -------------------------N 2 N ⎩ c u d ) s t( o r P LowSideMosfetSense o s b O - e t le InductorDCRSense where IOUT(OCP) is still the output current value at which the device enters Quasi-ConstantCurrent, IPP is the inductor current ripple in each phase ID-VID is the additional current required by D-VID (when applicable) and N the number of phases. In particular, since the device limits the peak or the valley of the inductor current (according to DAC/CS_SEL status), the ripple entity, when not negligible, impacts on the real OC threshold value and must be considered. ) s ( ct u d o r P e t e l o s b O 50/70 L6714 18.1 Over current protection Low side MOSFET sense over current The device detects an Over Current condition for each phase when the current information IINFOx overcomes the fixed threshold of IOCTH (35µA Typ,). When this happens, the device keeps the relative LS MOSFET on, also skipping clock cycles, until the threshold is crossed back and IINFOx results being lower than the IOCTH threshold. After exiting the OC condition, the LS MOSFET is turned off and the HS is turned on with a duty cycle driven by the PWM comparator. Keeping the LS on, skipping clock cycles, causes the on-time subsequent to the exit from the OC condition, driven by the control loop, to increase. Considering now that the device has a maximum on-time dependence with the delivered current given by the following relationship: ⎧ 0.80 ⋅ T SW T ON ( max ) = ⎨ ⎩ 0.40 ⋅ T SW I DROOP = 0µA I DROOP = 140µA Where IOUT is the output current ( I OUT = ΣI PHASEx ) and TSW is the switching period (TSW=1/FSW). This linear dependence has a value at zero load of 0.80·TSW and at maximum current of 0.40·TSW typical. c u d ) s t( When the current information IINFOx overcomes the fixed threshold of IOCTH (35µA Typ), the device enters in Quasi-Constant-Current operation: the low-side MOSFET stays ON until the current read becomes lower than IOCPx (IINFOx < IOCTH) skipping clock cycles. The high side MOSFET can be then turned ON with a TON imposed by the control loop after the LS turn-off and the device works in the usual way until another OCP event is detected. e t le o r P This means that the average current delivered can slightly increase in Quasi-ConstantCurrent operation since the current ripple increases. In fact, the ON time increases due to the OFF time rise because of the current has to reach the IOCPx bottom. The worst-case condition is when the ON time reaches its maximum value. o s b O - When this happens, the device works in Constant Current and the output voltage decrease as the load increase. Crossing the UVP threshold causes the device to latch (Figure 20 shows this working condition). ) s ( ct It can be observed that the peak current (IPEAK) is greater than IOCPx but it can be determined as follow: u d o V IN – V OUT ( min ) V IN – V OUT ( min ) I PEAK = I OCPx + ------------------------------------------ ⋅ T ON ( max ) = I OCPx + ------------------------------------------ ⋅ 0.40 ⋅ T SW L L r P e s b O t e l o Where VoutMIN is the UVP threshold, (inductor saturation must be considered). When that threshold is crossed, all MOSFET are turned OFF and the device stops working. Cycle the power supply or the OUTEN pin to restart operation. The maximum average current during the Constant-Current behavior results: I MAX, tot I PEAK – I OCPx⎞ = N ⋅ I MAX = N ⋅ ⎛ I OCPx + -----------------------------------⎝ ⎠ 2 51/70 Over current protection L6714 in this particular situation, the switching frequency for each phase results reduced. The ON time is the maximum allowed TON(max) while the OFF time depends on the application: I PEAK – I OCPx T OFF = L ⋅ -----------------------------------V OUT 1 f = -------------------------------------------T ON ( max ) + T OFF Figure 20. Constant current Constant Current (Exploded) IPEAK VOUT 0.40 VIN IMAX IOCPx TON(max) LS ON Skipping Clock Cycles Limted-TON Char. Resulting Out. Char. UVP Threshold TON(max) TSW IOCP = 4 x IOCPx (IDROOP = 140µA) TSW c u d Quasi-Const. Current Droop Effect ) s t( IOUT IMAX,tot The trans-conductance resistor Rg can be designed considering that the device limits the bottom of the inductor current ripple and also considering the additional current delivered during the quasi-constant-current behavior as previously described in the worst case conditions. e t le o r P Moreover, when designing D-VID compatible systems, the additional current due to the output filter charge during dynamic VID transitions must be considered. o s b O - I OCPx ( max ) ⋅ R SENSE ( max ) Rg = ----------------------------------------------------------------------I OCTH ( min ) ) s ( ct where u d o r P e t e l o s b O 52/70 I OUT ( OCP ) ∆I PP I D – VID - – ------------ + -----------------I OCPx = -------------------------N 2 N L6714 18.2 Over current protection Inductor sense over current The device detects an over current when the IINFOx overcome the fixed threshold IOCTH. Since the device always senses the current across the inductor, the IOCTH crossing will happen during the HS conduction time: as a consequence of OCP detection, the device will turn OFF the HS MOSFET and turns ON the LSMOSFET of that phase until IINFOx re-cross the threshold or until the next clock cycle. This implies that the device limits the peak of the inductor current. In any case, the inductor current won't overcome the IOCPx value and this will represent the maximum peak value to consider in the OC design. The device works in Constant-Current, and the output voltage decreases as the load increase, until the output voltage reaches the UVP threshold. When this threshold is crossed, all MOSFETs are turned off and the device stops working. Cycle the power supply or the OUTEN pin to restart operation. The transconductance resistor Rg can be designed considering that the device limits the inductor current ripple peak. Moreover, when designing D-VID systems, the additional current due to the output filter charge during dynamic VID transitions must be considered. I OCPx ( max ) ⋅ R SENSE ( max ) Rg = ----------------------------------------------------------------------I OCTH ( min ) where I OUT ( OCP ) ∆I PP I D – VID I OCPx = -------------------------- + ------------ + -----------------N 2 N e t le ) s ( ct c u d ) s t( o r P o s b O - u d o r P e t e l o s b O 53/70 Oscillator 19 L6714 Oscillator L6714 embeds four phase oscillator with optimized phase-shift (90º phase-shift) in order to reduce the input rms current and optimize the output filter definition. The internal oscillator generates the triangular waveform for the PWM charging and discharging with a constant current an internal capacitor. The switching frequency for each channel, FSW, is internally fixed at 150kHz so that the resulting switching frequency at the load side results in being multiplied by N (number of phases). The current delivered to the oscillator is typically 25µA (corresponding to the free running frequency FSW = 150kHz) and it may be varied using an external resistor (ROSC) connected between the OSC pin and SGND or VCC (or a fixed voltage greater than 1.24V). Since the OSC pin is fixed at 1.24V, the frequency is varied proportionally to the current sunk (forced) from (into) the pin considering the internal gain of 6KHz/µA. In particular connecting ROSC to SGND the frequency is increased (current is sunk from the pin), while connecting ROSC to VCC = 12V the frequency is reduced (current is forced into the pin), according the following relationships: ROSC vs. SGND c u d 3 ) s t( 1.240V kHz 7.422 ⋅ 10 · F SW = 150 ( kHz ) + --------------------------- ⋅ 6 ----------- = 150 ( kHz ) + ------------------------------- ⇒R OSC ( kΩ) = ----------R OSC ( kΩ) µA R OSC ( kΩ) F SW 3 o r P 3 Hz7.422 ⋅ 10 · 7.422 ⋅ 10 -------= 150 ( kHz ) + ------------------------------- ⇒R OSC ( kΩ) = ----------------------------------------------------------- [ kΩ] µA R OSC ( kΩ) F SW ( kHz ) – 150 ( kHz ) e t le ROSC vs. +12V o s b O - 4 12V – 1.240V kHz 6.456 ⋅ 10 ⇒R F SW = 150 ( kHz ) – ------------------------------------ ⋅ 6 ----------- = 150 ( kHz ) – ------------------------------OSC ( kΩ) = ----R OSC ( kΩ) µA R OSC ( kΩ) 15 ) s ( ct 4 4 kHz ⋅ 10 ⇒R 6.456 ⋅ 10 6 ----------- = 150 ( kHz ) – 6.456 ------------------------------( kΩ) = ----------------------------------------------------------- [ kΩ] OSC µA R OSC ( kΩ) 150 ( kHz ) – F SW ( kHz ) u d o r P e When using the Low-Side MOSFETs current sense, the maximum programmable switching frequency per phase must be limited to 500kHz to avoid current reading errors causing, as a consequence, current sharing errors. t e l o s b O 54/70 Anyway, device power dissipation must be checked prior to design high switching frequency systems. L6714 Oscillator Figure 21. ROSC vs. switching frequency 7000 Rosc [kOhms] to +12V 6000 5000 4000 3000 2000 1000 0 25 50 75 100 125 150 Fsw [kHz] Selected c u d 550 Rosc [kOhms] to SGND 500 450 400 e t le 350 300 250 200 150 100 50 ) s ( ct 0 150 u d o 250 350 ) s t( o r P o s b O 450 550 650 750 850 950 1050 Fsw [kHz] Programmed r P e t e l o s b O 55/70 Driver section 20 L6714 Driver section The integrated high-current drivers allow using different types of power MOS (also multiple MOS to reduce the equivalent RdsON), maintaining fast switching transition. The drivers for the high-side MOSFETs use BOOTx pins for supply and PHASEx pins for return. The drivers for the low-side MOSFETs use VCCDRx pin for supply and PGNDx pin for return. A minimum voltage at VCCDRx pin is required to start operations of the device. VCCDRx pins must be connected together. The controller embodies a sophisticated anti-shoot-through system to minimize low side body diode conduction time maintaining good efficiency saving the use of Schottky diodes: when the high-side MOSFET turns off, the voltage on its source begins to fall; when the voltage reaches 2V, the low-side MOSFET gate drive is suddenly applied. When the lowside MOSFET turns off, the voltage at LGATEx pin is sensed. When it drops below 1V, the high-side MOSFET gate drive is suddenly applied. If the current flowing in the inductor is negative, the source of high-side MOSFET will never drop. To allow the turning on of the low-side MOSFET even in this case, a watchdog controller is enabled: if the source of the high-side MOSFET doesn't drop, the low side MOSFET is switched on so allowing the negative current of the inductor to recirculate. This mechanism allows the system to regulate even if the current is negative. c u d ) s t( o r P The BOOTx and VCCDRx pins are separated from IC's power supply (VCC pin) as well as signal ground (SGND pin) and power ground (PGNDx pin) in order to maximize the switching noise immunity. The separated supply for the different drivers gives high flexibility in MOSFET choice, allowing the use of logic-level MOSFET. Several combination of supply can be chosen to optimize performance and efficiency of the application. e t le o s b O - Power conversion input is also flexible; 5V, 12V bus or any bus that allows the conversion (See maximum duty cycle limitations) can be chosen freely. ) s ( ct u d o r P e t e l o s b O 56/70 L6714 21 System control loop compensation System control loop compensation The control loop is composed by the Current Sharing control loop (See Figure 8) and the Average Current Mode control loop. Each loop gives, with a proper gain, the correction to the PWM in order to minimize the error in its regulation: the Current Sharing control loop equalize the currents in the inductors while the Average Current Mode control loop fixes the output voltage equal to the reference programmed by VID. Figure 22 shows the block diagram of the system control loop. The system Control Loop is reported in Figure 23. The current information IDROOP sourced by the DROOP pin flows into RFB implementing the dependence of the output voltage from the read current. Figure 22. Main control loop L4 PWM4 1/5 L3 c u d PWM3 1/5 L2 PWM2 1/5 L1 PWM1 e t le 1/5 ERROR AMPLIFIER o s b O 4/5 CURRENT SHARING DUTY CYCLE CORRECTION IINFO1 IINFO2 IINFO3 IINFO4 t c u (s) o r P ) s t( COUT ROUT VREF IDROOP COMP FB ZF(s) DROOP ZFB(s) d o r P e The system can be modeled with an equivalent single phase converter which only difference is the equivalent inductor L/N (where each phase has an L inductor).The Control Loop gain results (obtained opening the loop after the COMP pin): s b O t e l o PWM ⋅ Z F ( s ) ⋅ ( R DROOP + Z P ( s ) ) G LOOP ( s ) = – -----------------------------------------------------------------------------------------------------------------------ZF ( s ) ⎛ 1 [ Z P ( s ) + Z L ( s ) ] ⋅ -------------+ 1 + ------------⎞ ⋅ R FB A( s) ⎝ A ( s )⎠ 57/70 System control loop compensation L6714 Where: ● RSENSE is the MOSFET RdsON or the Inductor DCR depending on the sensing element selected; R SENSE R DROOP = --------------------- ⋅ R FB is the equivalent output resistance determined by the droop Rg ● function; ● ZP(s) is the impedance resulting by the parallel of the output capacitor (and its ESR) and the applied load RO; ● ZF(s) is the compensation network impedance; ● ZL(s) is the parallel of the N inductor impedance; ● A(s) is the error amplifier gain; V IN 4 PWM = --- ⋅ ------------------- is the PWM transfer function where ∆VOSC is the oscillator ramp 5 ∆V OSC ● amplitude and has a typical value of 4V. Removing the dependence from the Error Amplifier gain, so assuming this gain high enough, and with further simplifications, the control loop gain results: G LOOP ) s t( 1 + s ⋅ C O ⋅ ( R DROOP //R O + ESR ) V IN Z F ( s ) R O + R DROOP 4 ( s ) = – --- ⋅ ---------------------- ⋅ --------------- ⋅ -------------------------------------------- ⋅ ------------------------------------------------------------------------------------------------------------------------------------------------------------R 5 ∆V R R 2 L L OSC FB L L R + ------s ⋅ C O ⋅ ----- + s ⋅ ---------------------- + C O ⋅ ESR + C O ⋅ ------- + 1 O N N N N ⋅ RO c u d o r P The system Control Loop gain (See Figure 23) is designed in order to obtain a high DC gain to minimize static error and to cross the 0dB axes with a constant -20dB/dec slope with the desired crossover frequency ωT. Neglecting the effect of ZF(s), the transfer function has one zero and two poles; both the poles are fixed once the output filter is designed (LC filter resonance ωLC) and the zero (ωESR) is fixed by ESR and the Droop resistance. e t le o s b O - Figure 23. Equivalent control loop block diagram (left) and bode diagram (right). IDROOP u d o VID r P e DROOP t e l o FB RF ZF(s) s b O ZFB(s) VOUT d VOUT L / N ) s ( ct PWM VOUT dB ESR CO RO REMOTE BUFFER 64k GLOOP(s) 64k FBG 64k FBR K ZF(s) RF[dB] COMP CF VSEN ωLC = ωF ωESR ωT RFB To obtain the desired shape an RF - CF series network is considered for the ZF(s) implementation. A zero at ωF = 1/RFCF is then introduced together with an integrator. This integrator minimizes the static error while placing the zero ωF in correspondence with the LC resonance assures a simple -20dB/dec shape of the gain. In fact, considering the usual value for the output filter, the LC resonance results to be at frequency lower than the above reported zero. 58/70 ω L6714 System control loop compensation Compensation network can be simply designed placing ωF=ωLC and imposing the cross-over frequency ωT as desired obtaining (always considering that ωT might be not higher than 1/10th of the switching frequency FSW): R FB ⋅ ∆V OSC 5 L R F = ------------------------------------- ⋅ --- ⋅ ωT ⋅ ----------------------------------------------------------V IN 4 N ⋅ ( R DROOP + ESR ) CF 21.1 L C O ⋅ ---N = -----------------------RF Compensation network guidelines The Compensation Network design assures to having system response according to the cross-over frequency selected and to the output filter considered: it is anyway possible to further fine-tune the compensation network modifying the bandwidth in order to get the best response of the system as follow (See Figure 24): ) s t( ● Increase RF to increase the system bandwidth accordingly; ● Decrease RF to decrease the system bandwidth accordingly; ● Increase CF to move ωF to low frequencies increasing as a consequence the system phase margin. c u d o r P Having the fastest compensation network gives not the confidence to satisfy the requirements of the load: the inductor still limits the maximum dI/dt that the system can afford. In fact, when a load transient is applied, the best that the controller can do is to “saturate” the duty cycle to its maximum (dMAX) or minimum (0) value. The output voltage dV/dt is then limited by the inductor charge / discharge time and by the output capacitance. In particular, the most limiting transition corresponds to the load removal since the inductor results being discharged only by VOUT (while it is charged by dMAXVIN-VOUT during a load appliance). e t le ) s ( ct o s b O - Referring to Figure 24-left, further tuning the Compensation network cannot give any improvements unless the output filter changes: only modifying the main inductors ot the output capacitance improves the system response. u d o Figure 24. RF-CF impact on bandwidth. r P e CF t e l o s b O dB GLOOP(s) K ZF(s) RF[dB] RF ωLC = ωF ωESR ωT ω 59/70 Thermal monitor 22 L6714 Thermal monitor L6714 continuously senses the system temperature through TM pin: depending on the voltage sensed by this pin, the device sets free the VR_FAN pin as a warning and, after further temperature increase, also the VR_HOT pin as an alarm condition. These signals can be used to give a boost to the system fan (VR_FAN) and improve the VR cooling, or to initiate the CPU low power state (VR_HOT) in order to reduce the current demand from the processor so reducing also the VR temperature. In a different manner, VR_FAN can be used to initiate the CPU low power state so reducing the processor current requirements and VR_HOT to reset the system in case of further dangerous temperature increase. Thermal sensors is external to the PWM control IC since the controller is normally not located near the heat generating components: it is basically composed by a NTC resistor and a proper biasing resistor RTM. NTC must be connected as close as possible at the system hot-spot in order to be sure to control the hottest point of the VR. ) s t( Typical connection is reported in Figure 25 that also shows how the trip point can be easily programmed by modifying the divider values in order to cross the VR_FAN and VR_HOT thresholds at the desired temperatures. c u d Both VR_HOT and VR_FAN are active high and open drain outputs. Thermal Monitoring Output are enabled if Vcc > UVLOVCC. Figure 25. System thermal monitor typical connections. e t le o r P +5V o s b O - Sense Element (Place remotely, near Hot Spot) TM (s) t c u od t e l o bs O TM Voltage[V] r P e RTM TM Voltage - NTC=3300/4250K 4.00 3.80 3.60 3.40 3.20 3.00 2.80 2.60 Rtm = 330 2.40 Rtm = 390 2.20 Rtm = 470 2.00 80 85 90 95 100 105 Temperature [degC] 60/70 110 115 120 L6714 23 Tolerance band (TOB) definition Tolerance band (TOB) definition Output voltage load-line varies considering component process variation, system temperature extremes, and age degradation limits. Moreover, individual tolerance of the components also varies among designs: it is then possible to define a Manufacturing Tolerance Band (TOBManuf) that defines the possible output voltage spread across the nominal load line characteristic. TOBManuf can be sliced into different three main categories: Controller Tolerance, External Current Sense Circuit Tolerance and Time Constant Matching Error Tolerance. All these parameters can be composed thanks to the RSS analysis so that the manufacturing variation on TOB results to be: TOB Manuf = 2 2 2 TOB Controller + TOB CurrSense + TOB TCMatching Output voltage ripple (VP = VPP/2) and temperature measurement error (VTC) must be added to the Manufacturing TOB in order to get the system Tolerance Band as follow: TOB = TOB Manuf + V P + V TC c u d ) s t( All the component spreads and variations are usually considered at 3σ. Here follows an explanation on how to calculate these parameters for a reference L6714 application. 23.1 e t le Controller tolerance (TOB controller) It can be further sliced as follow: ● o s b O - Reference tolerance. L6714 is trimmed during the production stage to ensure the output voltage to be within kVID = ±0.5% (±0.6% for AMD DAC) over temperature and line variations. In addition, the device automatically adds a -19mV offset (Only for Intel Mode) avoiding the use of any external component. This offset is already included during the trimming process in order to avoid the use of any external circuit to generate this offsets and, moreover, avoiding the introduction of any further error to be considered in the TOB calculation. ) s ( ct ● u d o Current Reading Circuit. The device reads the current flowing across the MOSFET RdsON or the inductor DCR by using its dedicated differential inputs. The current sourced by the VRD is then reproduced and sourced from the DROOP pin scaled down by a proper designed gain as follow: r P e t e l o s b O o r P R SENSE I DROOP = --------------------- ⋅ I OUT Rg This current multiplied by the RFB resistor connected from FB pin vs. the load allows programming the droop function according to the selected RL/Rg gain and RFB resistor. Deviations in the current sourced due to errors in the current reading, impacts on the output voltage depending on the size of RFB resistor. The device is trimmed during the production stage in order to guarantee a maximum deviation of kIFB = ±1µA from the nominal value. Controller tolerance results then to be: TOB Controller = 2 [ ( VID – 19mV ) ⋅ k VID ] + ( k IDROOP ⋅ R FB ) 2 61/70 Tolerance band (TOB) definition 23.2 L6714 Ext. current sense circuit tolerance (TOB CurrSense - Inductor Sense) It can be further sliced as follow: ● Inductor DCR Tolerance (kDCR). Variations in the inductor DCR impacts on the output voltage since the device reads a current that is different from the real current flowing into the sense element. As a results, the controller will source a IDROOP current different from the nominal. The results will be an AVP different from the nominal in the same percentage as the DCR is different from the nominal. Since all the sense elements results to be in parallel, the error related to the inductor DCR has to be divided by the number of phases (N). ● Trans-conductance resistors tolerance (kRg). Variations in the Rg resistors impacts in the current reading circuit gain and so impacts on the output voltage. The results will be an AVP different from the nominal in the same percentage as the Rg is different from the nominal. Since all the sense elements results to be in parallel, and so the three current reading circuits, the error related to the Rg resistors has to be divided by the number of phases (N). ● NTC Initial Accuracy (kNTC_0). Variations in the NTC nominal value at room temperature used for the thermal compensation impacts on the AVP in the same percentage as before. In addition, the benefit of the division by the number of phases N cannot be applied in this case. c u d ● NTC Temperature Accuracy (kNTC). NTC variations from room to hot also impacts on the output voltage positioning. The impact is bigger as big is the temperature variation from room to hot (∆T). ● All these parameters impacts the AVP, so they must be weighted on the maximum voltage swing from zero load up to the maximum electrical current (VAVP). Total error from external current sense circuit results: e t le TOB CurrSense = 2 u d o r P e t e l o 62/70 o s b O - V AVP ⋅ ) s ( ct s b O o r P ) s t( 2 2 α ⋅ ∆T ⋅ k NTC 2 k DCR k Rg 2 ------------- + --------- + k NTC0 + ⎛⎝ ---------------------------------------⎞⎠ DCR N N L6714 23.3 Tolerance band (TOB) definition Time constant matching error tolerance (TOB TCMatching) ● Inductance and capacitance Tolerance (kL, kC). Variations in the inductance value and in the value of the capacitor used for the Time Constant Matching causes over/under shoots after a load transient appliance. This impacts the output voltage and then the TOB. Since all the sense elements results to be in parallel, the error related to the time constant mismatch has to be divided by the number of phases (N). ● Capacitance Temperature Variations (kCt). The capacitor used for time constant matching also vary with temperature (∆TC) impacting on the output voltage transients ad before. Since all the sense elements results to be in parallel, the error related to the time constant mismatch has to be divided by the number of phases (N). ● All these parameters impact the Dynamic AVP, so they must be weighted on the maximum dynamic voltage swing (Idyn). Total error due to time constant mismatch results: 2 TOB TCMatching = 23.4 2 k L + k C + ( k Ct ⋅ ∆TC ) 2 V AVPDyn ⋅ --------------------------------------------------------N c u d Temperature measurement error (VTC) ) s t( Error in the measured temperature (for thermal compensation) impacts on the output regulated voltage since the correction form the compensation circuit is not what required to keep the output voltage flat. e t le o r P The measurement error (ε Temp) must be multiplied by the copper temp coefficient (α) and compared with the sensing resistance (RSENSE): this percentage affects the AVP voltage as follow: o s b O - V TC ) s ( ct α ⋅ ε Temp = -------------------------- ⋅ V AVP R SENSE u d o r P e t e l o s b O 63/70 Layout guidelines 24 L6714 Layout guidelines Since the device manages control functions and high-current drivers, layout is one of the most important things to consider when designing such high current applications. A good layout solution can generate a benefit in lowering power dissipation on the power paths, reducing radiation and a proper connection between signal and power ground can optimize the performance of the control loops. Two kind of critical components and connections have to be considered when layouting a VRM based on L6714: power components and connections and small signal components connections. 24.1 Power components and connections These are the components and connections where switching and high continuous current flows from the input to the load. The first priority when placing components has to be reserved to this power section, minimizing the length of each connection and loop as much as possible. To minimize noise and voltage spikes (EMI and losses) these interconnections must be a part of a power plane and anyway realized by wide and thick copper traces: loop must be anyway minimized. The critical components, i.e. the power transistors, must be close one to the other. The use of multi-layer printed circuit board is recommended. c u d ) s t( o r P Figure 26 shows the details of the power connections involved and the current loops. The input capacitance (CIN), or at least a portion of the total capacitance needed, has to be placed close to the power section in order to eliminate the stray inductance generated by the copper traces. Low ESR and ESL capacitors are preferred, MLCC are suggested to be connected near the HS drain. e t le o s b O - Use proper VIAs number when power traces have to move between different planes on the PCB in order to reduce both parasitic resistance and inductance. Moreover, reproducing the same high-current trace on more than one PCB layer will reduce the parasitic resistance associated to that connection. ) s ( ct Connect output bulk capacitor as near as possible to the load, minimizing parasitic inductance and resistance associated to the copper trace also adding extra decoupling capacitors along the way to the load when this results in being far from the bulk capacitor bank. u d o r P e Gate traces must be sized according to the driver RMS current delivered to the power MOSFET. The device robustness allows managing applications with the power section far from the controller without losing performances. External gate resistors help the device to dissipate power resulting in a general cooling of the device. When driving multiple MOSFETs in parallel, it is suggested to use one resistor for each MOSFET. t e l o s b O 64/70 L6714 24.2 Layout guidelines Small signal components and connections These are small signal components and connections to critical nodes of the application as well as bypass capacitors for the device supply (See Figure 26). Locate the bypass capacitor (VCC, VCCDRx and Bootstrap capacitor) close to the device and refer sensible components such as frequency set-up resistor ROSC, offset resistor ROFFSET and OVP resistor ROVP to SGND. Star grounding is suggested: connect SGND to PGND plane in a single point to avoid that drops due to the high current delivered causes errors in the device behavior. VSEN pin filtered vs. SGND helps in reducing noise injection into device and OUTEN pin filtered vs. SGND helps in reducing false trip due to coupled noise: take care in routing driving net for this pin in order to minimize coupled noise. Warning: Boot Capacitor Extra Charge. Systems that do not use Schottky diodes might show big negative spikes on the phase pin. This spike can be limited as well as the positive spike but has an additional consequence: it causes the bootstrap capacitor to be over-charged. This extra-charge can cause, in the worst case condition of maximum input voltage and during particular transients, that boot-to-phase voltage overcomes the abs. max. ratings also causing device failures. It is then suggested in this cases to limit this extracharge by adding a small resistor in series to the boot diode (one resistor can be enough for all the three diodes if placed upstream the diode anode, See Figure 26) and by using standard and low-capacitive diodes. c u d e t le o s b O - ) s t( o r P Figure 26. Power connections and related connections layout (same for all phases). UGATEx r P e LGATEx PGNDx s b O t e l o uc od PHASEx CIN (t s) To limit C BOOT Extra-Charge VIN BOOTx CBOOT VIN CIN PHASEx L L VCC LOAD LOAD SGND +Vcc Remote Buffer Connection must be routed as parallel nets from the FBG/FBR pins to the load in order to avoid the pick-up of any common mode noise. Connecting these pins in points far from the load will cause a non-optimum load regulation, increasing output tolerance. Locate current reading components close to the device. The PCB traces connecting the reading point must use dedicated nets, routed as parallel traces in order to avoid the pick-up of any common mode noise. It's also important to avoid any offset in the measurement and, to get a better precision, to connect the traces as close as possible to the sensing elements. Symmetrical layout is also suggested. Small filtering capacitor can be added, near the controller, between VOUT and SGND, on the CSx- line when reading across inductor to allow higher layout flexibility. 65/70 Embedding L6714 - Based VR 25 L6714 Embedding L6714 - Based VR When embedding the VRD into the application, additional care must be taken since the whole VRD is a switching DC/DC regulator and the most common system in which it has to work is a digital system such as MB or similar. In fact, latest MB has become faster and powerful: high speed data bus are more and more common and switching-induced noise produced by the VRD can affect data integrity if not following additional layout guidelines. Few easy points must be considered mainly when routing traces in which high switching currents flow (high switching currents cause voltage spikes across the stray inductance of the trace causing noise that can affect the near traces): Keep safe guarding distance between high current switching VRD traces and data buses, especially if high-speed data bus to minimize noise coupling. Keep safe guard distance or filter properly when routing bias traces for I/O sub-systems that must walk near the VRD. Possible causes of noise can be located in the PHASE connections, MOSFET gate drive and Input voltage path (from input bulk capacitors and HS drain). Also PGND connections must be considered if not insisting on a power ground plane. These connections must be carefully kept far away from noise-sensitive data bus. c u d ) s t( Since the generated noise is mainly due to the switching activity of the VRM, noise emissions depend on how fast the current switches. To reduce noise emission levels, it is also possible, in addition to the previous guidelines, to reduce the current slope by properly tuning the HS gate resistor and the PHASE snuber network. e t le ) s ( ct u d o r P e t e l o s b O 66/70 o s b O - o r P L6714 26 Package mechanical data Package mechanical data In order to meet environmental requirements, ST offers these devices in ECOPACK® packages. These packages have a Lead-free second level interconnect. The category of second Level Interconnect is marked on the package and on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. ECOPACK is an ST trademark. ECOPACK specifications are available at: www.st.com. c u d e t le ) s ( ct ) s t( o r P o s b O - u d o r P e t e l o s b O 67/70 Package mechanical data Table 13. L6714 TQFP64 mechanical data mm. inch Dim. Min Typ Max A A1 0.05 A2 0.95 b 0.17 c 0.09 D 11.80 D1 9.80 D2 3.50 0.15 0.002 1.00 1.05 0.0374 0.0393 0.0413 0.22 0.27 0.0066 0.0086 0.0086 0.20 0.0035 12.00 12.20 0.464 0.472 0.480 10.00 10.20 0.386 0.394 0.401 6.10 0.1378 0.0078 0.2402 0.295 11.80 12.00 12.20 0.464 0.472 E1 9.80 10.00 10.20 0.386 0.394 E2 3.50 6.10 0.1378 E3 7.50 e 0.50 0.60 L1 0° 3.5° ccc ) s ( ct u d o r P e o r P 0.480 ) s t( 0.401 0.2402 0.0197 0.75 0.0177 e t le 7° so 0.080 Figure 27. Package dimensions c u d 0.295 1.00 k 68/70 0.006 E 0.45 Max 0.0472 7.50 L s b O Typ 1.20 D3 t e l o Min b O - 0° 0.0236 0.0295 0.0393 3.5° 7° 0.0031 L6714 27 Revision history Revision history Table 14. Revision history Date Revision Changes 16-Mar-2006 1 Initial release. 02-Aug-2006 2 Updated KIDROOP, KIOFFSET values in Table 4: Electrical characteristics on page 14. 07-Nov-2006 3 Updated D2 and E2 exposed tab measures in Table 13: TQFP64 mechanical data. c u d e t le ) s ( ct ) s t( o r P o s b O - u d o r P e t e l o s b O 69/70 Revision history L6714 Please Read Carefully: Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any time, without notice. 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