L6716TR

L6716 2/3/4 phase controller with embedded drivers for Intel® VR11.1 Features ■ Load transient boost LTB Technology™ to minimize the number of output capacitors ■ 2 or 3-phase operation with internal driver ■ 4-phase operation with external PWM driver signal ■ PSI input with programmable strategy ■ Imon output ■ 0.5% output voltage accuracy ■ 8-bit programmable output up to 1.60000 V Intel VR11.1 DAC - backward compatible with VR10/VR11 VFQFPN-48 - 7 x 7 mm ■ Full differential current sense across inductor ■ Differential remote voltage sensing ■ Adjustable voltage offset ■ LSLess startup to manage pre-biased output ■ Feedback disconnection protection ■ Preliminary overvoltage protection ■ Programmable overcurrent protection ■ Programmable overvoltage protection ■ Adjustable switching frequency ■ SS_END and OUTEN signal ■ VFQFPN-48 7x7 mm package with exposed pad The device implements a two-to-four phases stepdown controller with three integrated high current drivers in a compact 7x7 mm body package with exposed pad. Load transient boost LTB Technology™ reduces system cost by providing the fastest response to load transition therefore requiring less bulk and ceramic output capacitors to satisfy load transient requirements. The device embeds VR11.x DACs: the output voltage ranges up to 1.60000 V managing D-VID with ±0.5% output voltage accuracy over line and temperature variations. Applications ■ High current VRM/VRD for desktop / server / workstation CPUs ■ High density DC/DC converters Table 1. Description The controller assures fast protection against load overcurrent and under / overvoltage (in this last case also before UVLO). Feedback disconnection prevents from damaging the load in case of disconnections in the system board. In case of overcurrent, the system works in constant current mode until UVP. Device summary Order codes Package L6716 Packing Tray VFQFPN-48 L6716TR January 2010 Tape and reel Doc ID 14521 Rev 3 1/57 www.st.com 57 Contents L6716 Contents 1 2 Principle application circuit and block diagram . . . . . . . . . . . . . . . . . . . 4 1.1 Principle application circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 1.2 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Pin description and connection diagram . . . . . . . . . . . . . . . . . . . . . . . . 8 2.1 3 4 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 3.1 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 3.2 Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 4.1 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 5 Voltage identifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 6 Device description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 7 DAC and Phase number selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 8 Power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 9 Current reading and current sharing loop . . . . . . . . . . . . . . . . . . . . . . 23 10 Differential remote voltage sensing . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 11 Voltage positioning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 11.1 Offset (optional) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 11.2 Droop function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 12 Droop thermal compensation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 13 Output current monitoring (IMON) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 14 Load transient boost technology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 2/57 Doc ID 14521 Rev 3 L6716 Contents 15 Dynamic VID transitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 16 Enable and disable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 17 Soft-start . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 17.1 18 Low-side-less startup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Output voltage monitor and protections . . . . . . . . . . . . . . . . . . . . . . . . 39 18.1 Undervoltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 18.2 Preliminary overvoltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 18.3 Overvoltage and programmable OVP . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 18.4 Overcurrent protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 18.5 Feedback disconnection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 19 Low power state management and PSI# . . . . . . . . . . . . . . . . . . . . . . . . 44 20 Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 21 Driver section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 22 System control loop compensation . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 23 Tolerance band (TOB) definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 24 23.1 Controller tolerance (TOBController) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 23.2 External current sense circuit tolerance (TOBCurrSense) . . . . . . . . . . . . 50 23.3 Time constant matching error tolerance (TOBTCMatching) . . . . . . . . . . . 50 23.4 Temperature measurement error (VTC) . . . . . . . . . . . . . . . . . . . . . . . . . . 51 Layout guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 24.1 Power components and connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 24.2 Small signal components and connections . . . . . . . . . . . . . . . . . . . . . . . 53 25 Embedding L6716 - based VR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 26 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 27 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 Doc ID 14521 Rev 3 3/57 Principle application circuit and block diagram L6716 1 Principle application circuit and block diagram 1.1 Principle application circuit Principle application circuit for VR11.1 - 2 phase operation (a) Figure 1. LIN VIN to BOOT1 GNDIN 42 VCCDR BOOT1 1 to BOOT3 CIN VIN 5VSB UGATE1 Optional:Pre-OVP 3 VCC Vcc PHASE1 12 ROVP 13 ROFFSET 11 RLTBGAIN L1 LS1 R C OVPSEL CS1OCSET/PSI_A CS1+ 18 Rg 220nF 17 OFFSET 10 LTBGAIN ROSC_SGND 14 HS1 47 LGATE1 45 2 SGND ROCSET 48 BOOT2 OSC/FAULT UGATE2 39 40 ROSC_VCC To Vcc PHASE2 RSS_FLIM 15 SSOSC LGATE2 41 44 RSSOSC RFLIMT D CS2- 10k Q VTT 1k 35 SSEND VID bus from CPU SS_END 33 32 31 30 29 28 27 26 VID7 VID6 VID5 VID4 VID3 VID2 VID1 VID0 To CPU 34 PSI To Enable circuitry 16 OUTEN +3V3 L6716 Optional: See DS CS2+ 20 Rg 220nF 19 Vcc_core BOOT3 UGATE3 36 VIN 37 COUT ROUT GND_core PHASE3 LGATE3 L3 38 43 LS3 R C RIMON_OS 9 IMON CS3R1 CIMON CS3+ RIMON_TOT 22 Rg 220nF 21 R2 R3 NTC To GND CORE 8 LTB CLTB 4 COMP 25 PWM4 / PH_SEL CF RLTB CP RF 5 RFB1 FB RFB CI RFB2 RI RFB3 CS4NTC 6 7 L6716 REF.SCH: 2Phase Operation VSEN FBG 24 Rg 23 PGND CS4+ 49 a. Refer to the application note for the reference schematic. 4/57 LOAD HS3 Doc ID 14521 Rev 3 220nF L6716 Principle application circuit and block diagram Principle application circuit for VR11.1- 3 phase operation (b) Figure 2. LIN VIN to BOOT1 to BOOT2 GNDIN 42 VCCDR BOOT1 1 to BOOT3 CIN VIN 5VSB UGATE1 Optional:Pre-OVP 3 VCC Vcc PHASE1 ROVP 12 13 ROFFSET 11 RLTBGAIN L1 LS1 R C OVPSEL CS1OCSET/PSI_A CS1+ 18 Rg 220nF 17 OFFSET 10 LTBGAIN ROSC_SGND 14 HS1 47 LGATE1 45 2 SGND ROCSET 48 BOOT2 OSC/FAULT UGATE2 39 VIN 40 HS2 ROSC_VCC To Vcc PHASE2 RSS_FLIM 15 SSOSC LGATE2 41 L2 44 LS2 R RSSOSC C RFLIMT D CS2- 10k L6716 Optional: See DS Q VTT 35 SSEND VID bus from CPU SS_END 1k 33 32 31 30 29 28 27 26 VID7 VID6 VID5 VID4 VID3 VID2 VID1 VID0 Rg 220nF 19 Vcc_core BOOT3 UGATE3 36 VIN 37 COUT ROUT LOAD HS3 GND_core PHASE3 To CPU 34 PSI To Enable circuitry 16 OUTEN +3V3 CS2+ 20 LGATE3 L3 38 43 LS3 R C RIMON_OS 9 IMON CS3R1 CIMON CS3+ RIMON_TOT 22 Rg 220nF 21 R2 R3 NTC To GND CORE 8 LTB CLTB 4 COMP 25 PWM4 / PH_SEL CF RLTB CP RF 5 RFB1 FB RFB CI RFB2 RI RFB3 CS4NTC 6 7 L6716 REF.SCH: 3-Phase Operation VSEN FBG 24 Rg 23 PGND 220nF CS4+ 49 b. Refer to the application note for the reference schematic. Doc ID 14521 Rev 3 5/57 Principle application circuit and block diagram L6716 Principle application circuit for VR11.1- 4 phase operation (c) Figure 3. LIN VIN to BOOT1 to BOOT2 GNDIN 42 VCCDR BOOT1 1 to BOOT3 CIN VIN 5VSB UGATE1 Optional:Pre-OVP 3 VCC Vcc PHASE1 12 ROCSET 13 ROFFSET 11 RLTBGAIN L1 47 R LS1 C OVPSEL CS1OCSET/PSI_A CS1+ 18 Rg 220nF 17 OFFSET 10 LTBGAIN ROSC_SGND 14 HS1 LGATE1 45 2 SGND ROVP 48 BOOT2 OSC/FAULT UGATE2 39 VIN 40 HS2 ROSC_VCC To Vcc PHASE2 RSS_FLIM 15 SSOSC LGATE2 41 L2 44 R LS2 RSSOSC C RFLIMT D CS2- 10k Q VTT 35 SSEND VID bus from CPU SS_END 1k 33 32 31 30 29 28 27 26 VID7 VID6 VID5 VID4 VID3 VID2 VID1 VID0 CS2+ 20 Rg 220nF 19 Vcc_core BOOT3 UGATE3 36 VIN 37 COUT ROUT To CPU 34 PSI 16 OUTEN HS3 LGATE3 L3 38 43 R LS3 C RIMON_OS 9 IMON CS3R1 CIMON CS3+ RIMON_TOT Rg 22 220nF 21 R2 R3 VIN NTC Optional To GND CORE 7 6 3V3 8 LTB VCC CLTB 4 COMP 1 5 PHASE 8 PWM 1k HS4 L4 FB 4 RFB1 UGATE CHF 3 RF 5 2 L6741 CP VIN PVCC BOOT 1k 25 PWM4 / PH_SEL CF RLTB RFB GND LGATE EX_PAD 5 LS4 R C CI RFB2 RI RFB3 CS4NTC 6 7 L6716 REF.SCH: 4-Phase Operation c. 6/57 VSEN FBG LOAD GND_core PHASE3 To Enable circuitry +3V3 L6716 Optional: See DS 24 Rg 23 PGND CS4+ 49 Refer to the application note for the reference schematic. Doc ID 14521 Rev 3 220nF L6716 Block diagram PWM4/PH_SEL VCCDR PGND LGATE3 PHASE3 UGATE3 BOOT3 LGATE2 PHASE2 UGATE2 BOOT2 LGATE1 PHASE1 UGATE1 Block diagram BOOT1 Figure 4. 10uA SS_END HS1 LS1 LS2 HS2 HS3 LS3 +.1240V LTBGAIN LOGIC PWM ADAPTIVE ANTI CROSS CONDUCTION PWM1 LTB PWM2 PWM1 PWM2 PWM3 OCP L6716 CONTROL LOGIC AND PROTECTIONS OUTEN SSOSC IDROOP TOTAL DELIVERED CURRENT CS1CS1+ CH2 CURRENT READING CS2CS2+ IDROOP 20uA Doc ID 14521 Rev 3 LTB VSEN OFFSET CS3CS3+ VCC VCC SGND OVP IMON 50uA IOFFSET LTB COMP CS4+ +.1240V ERROR AMPLIFIER FB CH1 CURRENT READING CH3 CURRENT READING OVPSEL IOFFSET GND DROP RECOVERY FBG CS4- +175mV / 1.800V / OVP OVP COMPARATOR VREF OUTEN 10uA CH4 CURRENT READING PSI IOCSET DAC WITH DYNAMIC VID CONTROL IOCSET +.1240V PSI PWM4 PWM4 VCC VID0 VID1 VID2 VID3 VID4 VID5 VID6 VID7 LTB PWM3 DIGITAL SOFT START VCCDR CURRENT SHARING CORRECTION CURRENT SHARING CORRECTION CURRENT SHARING CORRECTION LTB OCSET /PSI_A SSOSC CURRENT SHARING CORRECTION LTB 2/4 PHASE OSCILLATOR OSC / FAULT LOGIC PWM ADAPTIVE ANTI CROSS CONDUCTION AVERAGE CURRENT LOGIC PWM ADAPTIVE ANTI CROSS CONDUCTION OUTEN 1.2 Principle application circuit and block diagram 7/57 Pin description and connection diagram Pin description and connection diagram VID7 VID6 VID5 VID4 VID3 VID2 VID1 VID0 35 34 33 32 31 30 29 28 27 26 PWM4/ PH_SEL PSI Pin connection (top view) BOOT3 UGATE3 36 37 25 24 PHASE3 38 23 CS4+ CS4- BOOT2 39 22 CS3- UGATE2 40 21 CS3+ PHASE2 41 20 CS2- VCCDR 42 19 CS2+ LGATE3 43 18 CS1- LGATE2 44 17 CS1+ LGATE1 45 16 OUTEN N.C. 46 15 SSOSC PHASE1 47 14 OSC/FAULT UGATE1 48 2.1 Pin description Table 2. Pin description 6 SGND VCC COMP FB VSEN 7 8 9 10 11 13 12 OVPSEL 5 OFFSET 4 LTBGAIN 3 IMON 2 LTB 1 BOOT1 49 PGND FBG Figure 5. SSEND 2 L6716 OCSET/PSI_A N° Name Description 1 BOOT1 Channel 1 HS driver supply. Connect through a capacitor (100 nF typ.) to PHASE1 and provide necessary bootstrap diode. A small resistor in series to the boot diode helps in reducing boot capacitor overcharge. 2 SGND All the internal references are referred to this pin. Connect it to the PCB signal ground. 3 VCC 4 COMP 5 FB 6 VSEN 7 FBG 8/57 Device supply voltage pin. The operative supply voltage is 12 V ±15%. Filter with at least 1 μF capacitor vs. SGND. Error amplifier output. Connect with an RF - CF//CP vs. FB pin. The device cannot be disabled by pulling down this pin. Error amplifier inverting input pin. Connect with a resistor RFB vs. VSEN and with an RF - CF//CP vs. COMP pin. A current proportional to the load current is sourced from this pin in order to implement the Droop effect. See “Droop function” Section for details. Output voltage monitor, manages OVP/UVP protections and FB disconnection. Connect to the positive side of the load to perform remote sense. See “Layout guidelines” Section for proper layout of this connection. Connect to the negative side of the load to perform remote sense. See “Layout guidelines” Section for proper layout of this connection. Doc ID 14521 Rev 3 L6716 Table 2. N° 8 9 Pin description and connection diagram Pin description (continued) Name Description LTB Load transient boost pin. Internally fixed at 2 V, connecting a RLTB - CLTB vs. VOUT allows to enable the load transient boost technology™: as soon as the device detects a transient load it turns on all the PHASEs at the same time. Short to SGND to disable the function. See “Load transient boost technology” Section for details. IMON Current monitor output pin. A current proportional to the load current is sourced from this pin. Connect through a resistor RMON to FBG to implement a load indicator. Connect the load indicator directly to VR11.1 CPUs.The pin voltage is clamped to 1.1 V max to preserve the CPU from excessive voltages. 10 Load transient boost technology™ gain pin. LTBGAIN Internally fixed at 1.24 V, connecting a RLTBGAIN resistor vs SGND allows setting the gain of the LTB action. See See “Load transient boost technology” Section for details. 11 Offset programming pin. Internally fixed at 1.240 V, connecting a ROFFSET resistor vs. SGND allows setting a current OFFSET that is mirrored into FB pin in order to program a positive offset according to the selected RFB. Short to SGND to disable the function. See “Offset (optional)” Section for details. 12 Overvoltage programming pin. Internally pulled up by 20 µA (typ) to 3.3 V. Leave floating to use built-in protection thresholds (OVPTH = VID + 175 mV typ). Connect to SGND through a ROVP resistor and filter with 100 pF (max) to set the OVP OVPSEL threshold to a fixed voltage according to the ROVP resistor. See “Overvoltage and programmable OVP” Section for details. Connect to SGND to select VR10/VR11 table. In this case the OVP threshold becomes 1.800 V (typ). 13 Overcurrent setting, PSI action pin. OCSET/ Connect to SGND through a ROCSET resistor to set the OCP threshold for each phase. PSI_A It also allows to select the number of phase when PSI mode is selected. See “Overcurrent protection” Section for details. 14 15 OSC/ FAULT Oscillator, FAULT pin. It allows programming the switching frequency FSW of each channel: the equivalent switching frequency at the load side results in being multiplied by the phase number N. Frequency is programmed according to the resistor connected from the pin vs. SGND or VCC with a gain of 9.1 kHz/µA (see relevant section for details). Leaving the pin floating programs a switching frequency of 200 kHz per phase. The pin is forced high (3.3 V typ) to signal an OVP/UVP fault: to recover from this condition, cycle VCC or the OUTEN pin. See “Oscillator” Section for details. SSOSC Soft-start oscillator pin. By connecting a resistor RSS to GND, it allows programming the soft-start time. Soft-Start time TSS will proportionally change with a gain of 25 [µs / kΩ]. The same slope implemented to reach VBOOT has to be considered also when the reference moves from VBOOT to the programmed VID code. The pin is kept to a fixed 1.240 V. See “Soft-start” Section for details. Doc ID 14521 Rev 3 9/57 Pin description and connection diagram Table 2. N° L6716 Pin description (continued) Name Description Output enable pin. Internally pulled up by 10 µA (typ) to 3 V. Forced low, the device stops operations with all MOSFETs OFF: all the protections are disabled except for preliminary overvoltage. Leave floating, the device starts-up implementing soft-start up to the selected VID code. Cycle this pin to recover latch from protections; filter with 1 nF (typ) vs. SGND. 16 OUTEN 17 CS1+ Channel 1 current sense positive input. Connect through an R-C filter to the phase-side of the channel 1 inductor. See “Layout guidelines” Section for proper layout of this connection. 18 CS1- Channel 1 current sense negative input. Connect through a Rg resistor to the output-side of the channel 1 inductor. See “Layout guidelines” Section for proper layout of this connection. CS2+ Channel 2 current sense positive input. Connect through an R-C filter to the phase-side of the channel 2 inductor. Short to VOUT when using 2-phase operation. See “Layout guidelines” Section for proper layout of this connection. 20 CS2- Channel 2 current sense negative input. Connect through a Rg resistor to the output-side of the channel 2 inductor. Still connect to VOUT through Rg resistor when using 2-phase operation. See “Layout guidelines” Section for proper layout of this connection. 21 CS3+ Channel 3 current sense positive input. Connect through an R-C filter to the phase-side of the channel 3 inductor. See “Layout guidelines” Section for proper layout of this connection. CS3- Channel 3 current sense negative input. Connect through a Rg resistor to the output-side of the channel 3 inductor. See “Layout guidelines” Section for proper layout of this connection. CS4+ Channel 4 current sense positive input. Connect through an R-C filter to the phase-side of the channel 4 inductor. Short to VOUT when using 2-phase or 3-phase operation. See “Layout guidelines” Section for proper layout of this connection. CS4- Channel 4 current sense negative input. Connect through a Rg resistor to the output-side of the channel 4 inductor. Still connect to VOUT through Rg resistor when using 2-phase or 3-phase operation. See “Layout guidelines” Section for proper layout of this connection. 19 22 23 24 25 26 to 33 10/57 PWM outputs, phase selection pin. Internally pulled up by 10 µA to 3.3 V (until the soft-start has not finished), connect to external PWM4/ driver PWM input when 4-phase operation is used. PH_SEL The device is able to manage HiZ status by setting the pis floating. Short to SGND to select 3-phase operation and leave floating to select 2-phase operation. VID0 to VID7 Voltage identification pins. (not internally pulled up). Connect to SGND to program a '0' or connect to the external pull-up resistor to program a '1'. They allow programming output voltage as specified in Table 7. Doc ID 14521 Rev 3 L6716 Table 2. N° Pin description and connection diagram Pin description (continued) Name Description Power saving indicator pin. Connect to the PSI pin of the CPU to manage low-power state. When asserted (pulled low), the controller will act as programmed on the OCSET/PSI_A. 34 PSI 35 SSEND Soft-start END signal. Open drain output sets free after ss has finished and pulled low when triggering any protection. Pull up to a voltage lower than 3.3 V, if not used it can be left floating. 36 BOOT3 Channel 3 HS driver supply. Connect through a capacitor (100 nF typ.) to PHASE3 and provide necessary bootstrap diode.A small resistor in series to the boot diode helps in reducing boot capacitor overcharge. 37 Channel 3HS driver output. UGATE3 It must be connected to the HS3 MOSFET gate. A small series resistors helps in reducing device-dissipated power. 38 Channel 3 HS driver return path. PHASE3 It must be connected to the HS3 MOSFET source and provides return path for the HS driver of channel 3. Channel 2 HS driver supply. Connect through a capacitor (100 nF typ.) to PHASE2 and provide necessary bootstrap diode. A small resistor in series to the boot diode helps in reducing Boot capacitor overcharge. Leave floating when using 2-Phase operation. 39 BOOT2 40 Channel 2HS driver output. UGATE2 It must be connected to the HS2 MOSFET gate. A small series resistors helps in reducing device-dissipated power. Leave floating when using 2-Phase operation. 41 Channel 2 HS driver return path. PHASE2 It must be connected to the HS2 MOSFET source and provides return path for the HS driver of channel 2. Leave floating when using 2-phase operation. 42 VCCDR LS Driver Supply. VCDDR pin voltage has to be the same of VCC pin. Filter with 2 x 1 µF MLCC capacitor vs. PGND. 43 LGATE3 Channel 3LS driver output. A small series resistor helps in reducing device-dissipated power. 44 Channel 2LS driver output. LGATE2 A small series resistor helps in reducing device-dissipated power. Leave floating when using 2-phase operation. 45 LGATE1 46 N.C. 47 Channel 1LS driver output. A small series resistor helps in reducing device-dissipated power. Not internally connected. Channel 1 HS driver return path. PHASE1 It must be connected to the HS1 MOSFET source and provides return path for the HS driver of channel 1. Doc ID 14521 Rev 3 11/57 Pin description and connection diagram Table 2. N° 48 49 12/57 L6716 Pin description (continued) Name Description Channel 1HS driver output. UGATE1 It must be connected to the HS1 MOSFET gate. A small series resistors helps in reducing device-dissipated power. PGND Power ground pin (LS drivers return path). Connect to power ground plane. Exposed pad connects also the silicon substrate. As a consequence it makes a good thermal contact with the PCB to dissipate the power necessary to drive the external MOSFETs. Connect it to the power ground plane using 5.2 x 5.2 mm square area on the PCB and with sixteen vias (uniformly distributed), to improve electrical and thermal conductivity. Doc ID 14521 Rev 3 L6716 Maximum ratings 3 Maximum ratings 3.1 Absolute maximum ratings Table 3. Absolute maximum ratings Symbol VCC, VCCDR VBOOTxVPHASEx Parameter Value Unit To PGND 15 V Boot voltage 15 V 15 V -0.3 to Vcc+0.3 V -0.3 to 3.6 V Negative peak voltage to PGND; T < 400 ns VCC = VCCDR = 12 V -8 V Positive voltage to PGND VCC = VCCDR = 12 V 26 V Positive peak voltage to PGND; T < 200 ns VCC = VCCDR = 12 V 30 V +/- 1750 V Value Unit VUGATExVPHASEx LGATEx to PGND All other pins to PGND VPHASE Maximum withstanding voltage range test condition: CDF-AEC-Q100-002- “human body model” acceptance criteria: “normal performance” 3.2 Thermal data Table 4. Symbol Thermal data Parameter RthJA Thermal resistance junction to ambient (Device soldered on 2s2p PC board) 40 °C / W TMAX Maximum junction temperature 150 °C Tstg Storage temperature range -40 to 150 °C TJ Junction temperature range -10 to 125 °C Ptot Max power dissipation at TA = 25 °C 2.5 W Doc ID 14521 Rev 3 13/57 Electrical characteristics L6716 4 Electrical characteristics 4.1 Electrical characteristics VCC = 12 V ± 15%, TJ = 0 °C to 70 °C unless otherwise specified. Table 5. Electrical characteristics Symbol Parameter Test condition Min. Typ. Max. Unit Supply current and power-on VCC supply current UGATEx and LGATEx open; VCC = VBOOTx = 12 V 22 25 mA ICCDR VCCDR supply current LGATEx = OPEN; VCCDR = 12 V 5 7 mA IBOOTx BOOTx supply current UGATEx = OPEN; PHASEx to PGND; VCC = BOOTx = 12V 1.8 2.7 mA VCC turn-ON VCC rising; VCCDR = VCC 3.7 4.0 V VCC turn-OFF VCC falling; VCCDR = VCC Pre-OVP turn-ON VCC rising; VCCDR = VCC Pre-OVP turn-OFF VCC falling; VCCDR = VCC 3.3 3.5 OSC=OPEN; TJ = 0 to 125 °C 180 200 1 1.5 ms 500 μs 150 250 μs 0.80 0.85 ICC Power-on UVLOVCC UVLOPre-OVP 3.3 3.5 3.7 V 4.0 V V Oscillator and inhibit FOSC Initial accuracy TD1 SS delay time TD2 SS TD2 time TD3 SS TD3 time RSSOSC = 20 kΩ Rising thresholds voltage 220 0.90 kHz V Output enable OUTEN Output pull-up current ΔVosc Ramp amplitude FAULT Voltage at pin OSC/FAULT Hysteresis 100 mV OUTEN to SGND 10 μA 1.5 V 3.3 V OVP and UVP Active Reference and DAC KVID VBOOT 14/57 Output voltage accuracy VID = 1.000 V to VID = 1.600 V FB = VOUT; FBG = GNDOUT -0.5 - 0.5 % VID = 0.800 V to VID = 1.000 V FB = VOUT; FBG = GNDOUT -5 - +5 mV VID = 0.500 V to VID = 0.800 V FB = VOUT; FBG = GNDOUT -8 - +8 mV Boot voltage 1.081 Doc ID 14521 Rev 3 V L6716 Table 5. Electrical characteristics Electrical characteristics (continued) Symbol IVID VIDIH Parameter VID pull-up current Test condition Min. VIDx to SGND Typ. Max. μA 0 Input low Unit 0.35 V VID thresholds Input high VIDIL 0.8 V Input low 0.4 PSI thresholds PSI V Input high PSI pull-up current 0.8 PSI to SGND 0 μA 130 dB 25 V/μs 0 μA Error amplifier A0 EA DC gain SR EA slew-rate COMP = 10 pF to SGND Differential current sensing and offset ICSx+ Bias current VOCSET OCSET pin voltage KIDROOP Rg = 1 kΩ; 1-PHASE, IDROOP = 25 μA; Droop current deviation from 2-PHASE, IDROOP = 50 μA; nominal value 3-PHASE, IDROOP = 75 μA; 4-PHASE, IDROOP = 100 μA; KIOFFSET Offset current accuracy IOFFSET OFFSET current range VOFFSET OFFSET pin bias IOFFSET = 0 to 250 μA High side rise time IUGATEx RUGATEx IOFFSET = 50 μA to 250 μA 1.105 1.245 1.385 mV -3 - +3 μA -5 - 5 % 250 μA 0 1.240 V BOOTx-PHASEx = 12 V; CUGATEx to PHASEx = 3.3 nF 20 ns High side source current BOOTx-PHASEx = 12 V 1.5 A High side sink resistance BOOTx-PHASEx = 12 V 2 Ω Low side rise time VCCDR = 12 V; CLGATEx to PGNDx = 5.6 nF 25 ns ILGATEx Low side source current VCCDR = 12 V 2 A RLGATEx Low side sink resistance VCCDR = 12 V 1 Ω Output high I = 1 mA Output low I = -1 mA PWM4 pull-up current Before SSEND = 1; PWM4 to SGND Gate drivers tRISE UGATE tRISE LGATE PWM output 3 V PWM4 IPWM4 Doc ID 14521 Rev 3 0.2 10 V μA 15/57 Electrical characteristics Table 5. Symbol L6716 Electrical characteristics (continued) Parameter Test condition Min. Typ. Max. Unit 1.24 1.300 V Protections OVP Overvoltage protection (VSEN rising) Programmab IOVP current le OVP Comparator offset voltage Pre- OVP Preliminary overvoltage protection Before VBOOT Above VID-19 mV (after TD3) 150 175 200 mV OVP = SGND 20 22 24 μA OVP = 1.800 V -20 0 20 mV 1.800 1.850 V UVLOOVP < VCC < UVLOVCC VCC> UVLOVCC and OUTEN = SGND 1.750 VSEN rising Hysteresis UVP VSSEND 16/57 Under voltage threshold VSEN falling; below VID-19 mV SS_END voltage low I = -4 mA Doc ID 14521 Rev 3 350 550 600 mV 650 mV 0.4 V L6716 5 Voltage identifications Voltage identifications Table 6. Voltage identification (VID) mapping for intel VR11.1 mode VID7 VID6 VID5 VID4 VID3 VID2 VID1 VID0 800 mV 400 mV 200 mV 100 mV 50 mV 25 mV 12.5 mV 6.25 mV Table 7. HEX code Voltage identification (VID) for Intel VR11.1 mode Output Output Output Output HEX code HEX code HEX code voltage (1) voltage (1) voltage (1) voltage (1) 0 0 OFF 4 0 1.21250 8 0 0.81250 C 0 0.41250 0 1 OFF 4 1 1.20625 8 1 0.80625 C 1 0.40625 0 2 1.60000 4 2 1.20000 8 2 0.80000 C 2 0.40000 0 3 1.59375 4 3 1.19375 8 3 0.79375 C 3 0.39375 0 4 1.58750 4 4 1.18750 8 4 0.78750 C 4 0.38750 0 5 1.58125 4 5 1.18125 8 5 0.78125 C 5 0.38125 0 6 1.57500 4 6 1.17500 8 6 0.77500 C 6 0.37500 0 7 1.56875 4 7 1.16875 8 7 0.76875 C 7 0.36875 0 8 1.56250 4 8 1.16250 8 8 0.76250 C 8 0.36250 0 9 1.55625 4 9 1.15625 8 9 0.75625 C 9 0.35625 0 A 1.55000 4 A 1.15000 8 A 0.75000 C A 0.35000 0 B 1.54375 4 B 1.14375 8 B 0.74375 C B 0.34375 0 C 1.53750 4 C 1.13750 8 C 0.73750 C C 0.33750 0 D 1.53125 4 D 1.13125 8 D 0.73125 C D 0.33125 0 E 1.52500 4 E 1.12500 8 E 0.72500 C E 0.32500 0 F 1.51875 4 F 1.11875 8 F 0.71875 C F 0.31875 1 0 1.51250 5 0 1.11250 9 0 0.71250 D 0 0.31250 1 1 1.50625 5 1 1.10625 9 1 0.70625 D 1 0.30625 1 2 1.50000 5 2 1.10000 9 2 0.70000 D 2 0.30000 1 3 1.49375 5 3 1.09375 9 3 0.69375 D 3 0.29375 1 4 1.48750 5 4 1.08750 9 4 0.68750 D 4 0.28750 1 5 1.48125 5 5 1.08125 9 5 0.68125 D 5 0.28125 1 6 1.47500 5 6 1.07500 9 6 0.67500 D 6 0.27500 1 7 1.46875 5 7 1.06875 9 7 0.66875 D 7 0.26875 1 8 1.46250 5 8 1.06250 9 8 0.66250 D 8 0.26250 1 9 1.45625 5 9 1.05625 9 9 0.65625 D 9 0.25625 Doc ID 14521 Rev 3 17/57 Voltage identifications Table 7. HEX code 18/57 L6716 Voltage identification (VID) for Intel VR11.1 mode (continued) Output Output Output Output HEX code HEX code HEX code voltage (1) voltage (1) voltage (1) voltage (1) 1 A 1.45000 5 A 1.05000 9 A 0.65000 D A 0.25000 1 B 1.44375 5 B 1.04375 9 B 0.64375 D B 0.24375 1 C 1.43750 5 C 1.03750 9 C 0.63750 D C 0.23750 1 D 1.43125 5 D 1.03125 9 D 0.63125 D D 0.23125 1 E 1.42500 5 E 1.02500 9 E 0.62500 D E 0.22500 1 F 1.41875 5 F 1.01875 9 F 0.61875 D F 0.21875 2 0 1.41250 6 0 1.01250 A 0 0.61250 E 0 0.21250 2 1 1.40625 6 1 1.00625 A 1 0.60625 E 1 0.20625 2 2 1.40000 6 2 1.00000 A 2 0.60000 E 2 0.20000 2 3 1.39375 6 3 0.99375 A 3 0.59375 E 3 0.19375 2 4 1.38750 6 4 0.98750 A 4 0.58750 E 4 0.18750 2 5 1.38125 6 5 0.98125 A 5 0.58125 E 5 0.18125 2 6 1.37500 6 6 0.97500 A 6 0.57500 E 6 0.17500 2 7 1.36875 6 7 0.96875 A 7 0.56875 E 7 0.16875 2 8 1.36250 6 8 0.96250 A 8 0.56250 E 8 0.16250 2 9 1.35625 6 9 0.95625 A 9 0.55625 E 9 0.15625 2 A 1.35000 6 A 0.95000 A A 0.55000 E A 0.15000 2 B 1.34375 6 B 0.94375 A B 0.54375 E B 0.14375 2 C 1.33750 6 C 0.93750 A C 0.53750 E C 0.13750 2 D 1.33125 6 D 0.93125 A D 0.53125 E D 0.13125 2 E 1.32500 6 E 0.92500 A E 0.52500 E E 0.12500 2 F 1.31875 6 F 0.91875 A F 0.51875 E F 0.11875 3 0 1.31250 7 0 0.91250 B 0 0.51250 F 0 0.11250 3 1 1.30625 7 1 0.90625 B 1 0.50625 F 1 0.10625 3 2 1.30000 7 2 0.90000 B 2 0.50000 F 2 0.10000 3 3 1.29375 7 3 0.89375 B 3 0.49375 F 3 0.09375 3 4 1.28750 7 4 0.88750 B 4 0.48750 F 4 0.08750 3 5 1.28125 7 5 0.88125 B 5 0.48125 F 5 0.08125 3 6 1.27500 7 6 0.87500 B 6 0.47500 F 6 0.07500 3 7 1.26875 7 7 0.86875 B 7 0.46875 F 7 0.06875 3 8 1.26250 7 8 0.86250 B 8 0.46250 F 8 0.06250 3 9 1.25625 7 9 0.85625 B 9 0.45625 F 9 0.05625 3 A 1.25000 7 A 0.85000 B A 0.45000 F A 0.05000 3 B 1.24375 7 B 0.84375 B B 0.44375 F B 0.04375 Doc ID 14521 Rev 3 L6716 Voltage identifications Table 7. HEX code Voltage identification (VID) for Intel VR11.1 mode (continued) Output Output Output Output HEX code HEX code HEX code voltage (1) voltage (1) voltage (1) voltage (1) 3 C 1.23750 7 C 0.83750 B C 0.43750 F C 0.03750 3 D 1.23125 7 D 0.83125 B D 0.43125 F D 0.03125 3 E 1.22500 7 E 0.82500 B E 0.42500 F E OFF 3 F 1.21875 7 F 0.81875 B F 0.41875 F F OFF 1. According to INTEL specs, the device automatically regulates output voltage 19 mV lower to avoid any external offset to modify the built-in 0.5% accuracy improving TOB performances. Output regulated voltage is than what extracted from the table lowered by 19 mV. Doc ID 14521 Rev 3 19/57 Device description 6 L6716 Device description L6716 is two-to-four phase PWM controller with three embedded high current drivers providing complete control logic and protections for a high performance step-down DC-DC voltage regulator optimized for advanced microprocessor power supply. Multi phase buck is the simplest and most cost-effective topology employable to satisfy the increasing current demand of newer microprocessors and modern high current VRM modules. It allows distributing equally load and power between the phases using smaller, cheaper and most common external power MOSFETs and inductors. Moreover, thanks to the equal phase shift between each phase, the input and output capacitor count results in being reduced. Phase interleaving causes in fact input rms current and output ripple voltage reduction. L6716 is a dual-edge asynchronous PWM controller featuring load transient boost LTB Technology™: the device turns on simultaneously all the phases as soon as a load transient is detected allowing to minimize system cost by providing the fastest response to load transition. Load transition is detected (through LTB pin) measuring the derivate dV/dt of the output voltage and the dV/dt can be easily programmed extending the system design flexibility. Moreover, load transient boost (LTB) Technology™ gain can be easily modified in order to keep under control the output voltage ring back. LTB Technology™ can be disabled and in this condition the device works as a dual-edge asynchronous PWM. The controller allows to implement a scalable design: a three phase design can be easily downgraded to two phase and upgraded to four phase (using an external driver).The same design can be used for more than one project saving development and debug time. L6716 permits easy system design by allowing current reading across inductor in fully differential mode. Also a sense resistor in series to the inductor can be considered to improve reading precision. The current information read corrects the PWM output in order to equalize the average current carried by each phase limiting the error in the static and dynamic conditions. The controller allows compatibility with both Intel VR11.0 and VR11.1 processors specifications, also performing D-VID transitions accordingly. The device is VR11.1 compatible implementing IMON signal and managing the PSI# signal to enhance the system performances at low current in low-power states. Low-side-less start-up allows soft-start over pre-biased output avoiding dangerous current return through the main inductors as well as negative spike at the load side. L6716 provides a programmable overvoltage protection to protect the load from dangerous over stress, latching immediately by turning ON the lower driver and driving high the OSC/FAULT pin. Furthermore, preliminary OVP protection also allows the device to protect load from dangerous OVP when VCC is not above the UVLO threshold or OUTEN is low. The overcurrent protection is for each phase and externally adjustable through a single resistor. The device keeps constant the peak of the inductor current ripple working in constant current mode until the latched UVP. A compact 7x7 mm body VFQFPN-48 package with exposed thermal pad allows dissipating the power to drive the external MOSFET through the system board. 20/57 Doc ID 14521 Rev 3 L6716 7 DAC and Phase number selection DAC and Phase number selection L6716 embeds VRD11.x DAC (see Table 7) that allows to regulate the output voltage with a tolerance of ±0.5% recovering from offsets and manufacturing variations. The device automatically introduces a -19 mV (both VRD11.x and VR10) offset to the regulated voltage in order to avoid any external offset circuitry to worsen the guaranteed accuracy and, as a consequence, the calculated system TOB. Output voltage is programmed through the VID pins: they are inputs of an internal DAC that is realized by means of a series of resistors providing a partition of the internal voltage reference. The VID code drives a multiplexer that selects a voltage on a precise point of the divider. The DAC output is delivered to an amplifier obtaining the voltage reference (i.e. the set-point of the error amplifier, VREF). L6716 implements a flexible 2 to 4 interleaved-phase converter. The device allows to select the phase number operation simply using the PWM4/PHASE_SEL pin, as shown in the following table. Table 8. Note: Number of phases setting PWM4 / PH_SEL pin Number of phases Phases used Floating 2-PHASE Phase1, Phase3 Short to SGND 3-PHASE Phase1, Phase2, Phase3 Connect to PWM driver input 4-PHASE Phase1, Phase2, Phase3, Phase4 PWM4 pin is internally pulled up by 10 µA to 3.3 V, until soft-start is not finished. For the disabled phase(s), the current reading pins need to be properly connected to avoid errors in current-sharing and voltage-positioning: CSx+ needs to be connected to the regulated output voltage while CSX- needs to be connected to VOUT trough the same RG resistor used for the other phases. Note: To select VR10/VR11 table, short to SGND the OVP pin. In this case the PSI pin becomes the VIDSEL pin (to select VR10 and VR11 table, in according to the VR11 specification). Doc ID 14521 Rev 3 21/57 Power dissipation 8 L6716 Power dissipation L6716 embeds three high current MOSFET drivers for both high side and low side MOSFETs: it is then important to consider the power the device is going to dissipate in driving them in order to avoid overcoming the maximum junction operative temperature. Exposed pad (PGND pin) needs to be soldered to the PCB power ground plane through several VIAs in order to facilitate the heat dissipation. Two main terms contribute in the device power dissipation: bias power and drivers' power. The first one (PDC) depends on the static consumption of the device through the supply pins and it is simply quantifiable as follow (assuming to supply HS and LS drivers with the same VCC of the device): P DC = V CC ⋅ ( I CC + I CCDR + N D ⋅ I BOOTx ) where ND is the number of internal drivers used. Drivers' power is the power needed by the driver to continuously switch on and off the external MOSFETs; it is a function of the switching frequency and total gate charge of the selected MOSFETs. It can be quantified considering that the total power PSW dissipated to switch the MOSFETs (easy calculable) is dissipated by three main factors: external gate resistance (when present), intrinsic MOSFET resistance and intrinsic driver resistance. This last term is the important one to be determined to calculate the device power dissipation. The total power dissipated to switch the MOSFETs results: P SW = N D ⋅ F SW ⋅ ( Q GHS ⋅ V BOOT + Q GLS ⋅ V CCDR ) External gate resistors helps the device to dissipate the switching power since the same power PSW will be shared between the internal driver impedance and the external resistor resulting in a general cooling of the device. When driving multiple MOSFETs in parallel, it is suggested to use one gate resistor for each MOSFET. Figure 6. 22/57 L6716 dissipated power (quiescent + switching) Doc ID 14521 Rev 3 L6716 9 Current reading and current sharing loop Current reading and current sharing loop L6716 embeds a flexible, fully-differential current sense circuitry that is able to read across inductor parasitic resistance or across a sense resistor placed in series to the inductor element. The fully-differential current reading rejects noise and allows placing sensing element in different locations without affecting the measurement's accuracy. Reading current across the inductor DCR, the current flowing trough each phase is read using the voltage drop across the output inductor or across a sense resistor in its series and internally converted into a current. The trans-conductance ratio is issued by the external resistor Rg placed outside the chip between CSx- pin toward the reading points. The current sense circuit always tracks the current information, no bias current is sourced from the CSx+ pin: this pin is used as a reference keeping the CSx- pin to this voltage. To correctly reproduce the inductor current an R-C filtering network must be introduced in parallel to the sensing element. The current that flows from the CSx- pin is then given by the following equation (see Figure 7): DCR 1 + s ⋅ L ⁄ ( DCR ) I CSx- = ------------- ⋅ ------------------------------------------- ⋅ I Rg 1+s⋅R⋅C PHASEx Where IPHASEx is the current carried by the relative phase. Figure 7. Current reading connections IPHASEx Lx PHASEx DCRx R C CSx+ NO Bias ICSx-=IINFOx CSx- Rg Inductor DCR Current Sense Considering now to match the time constant between the inductor and the R-C filter applied (Time constant mismatches cause the introduction of poles into the current reading network causing instability. In addition, it is also important for the load transient response and to let the system show resistive equivalent output impedance), it results: L - = R⋅C -----------DCR ⇒ DCR I CSx- = ------------- ⋅ I PHASEx = I INFOx ⇒ Rg DCR I INFOX = ------------- ⋅ I PHASEx Rg Where IINFOx is the current information reproduced internally. The Rg trans-conductance resistor has to be selected using the following formula, in order to guarantee the correct functionality of internal current reading circuitry: MAX I DCR OUT MAX Rg = ------------------------ ⋅ -------------------------N 20μA Where IOUTMAX is the maximum output current, DCRMAX the maximum inductor DCR and N number of phases. Doc ID 14521 Rev 3 23/57 Current reading and current sharing loop L6716 For the disabled phase(s), the current reading pins need to be properly connected to avoid errors in current-sharing and voltage-positioning: CSx+ needs to be connected to the regulated output voltage while CSX- needs to be connected to VOUT trough the same RG resistor used for the other phases, as shown in figure Figure 9. Figure 8. Current reading connections for the disabled phase Current Sense connection Disabled Phase CSx+ VOUT CSx- Rg Current sharing control loop reported in Figure 9: it considers a current IINFOx proportional to the current delivered by each phase and the average current I AVG = ΣI INFOx ⁄ N. The error between the read current IINFOx and the reference IAVG is then converted into a voltage that with a proper gain is used to adjust the duty cycle whose dominant value is set by the voltage error amplifier in order to equalize the current carried by each phase. Details about connections are shown in Figure 9. Figure 9. Current sharing loop IINFO1 PWM1 Out AVG IAVG IINFO2 From EA PWM2 Out IINFO3 PWM3 Out IINFO4 PWM4 Out (PHASE4 Only when using 4-PHASE Operation - PHASE2 when using 3 or 4 PHASE Operation) 24/57 Doc ID 14521 Rev 3 L6716 10 Differential remote voltage sensing Differential remote voltage sensing The output voltage is sensed in fully-differential mode between the FB and FBG pin. The FB pin has to be connected through a resistor to the regulation point while the FBG pin has to be connected directly to the remote sense ground point. In this way, the output voltage programmed is regulated between the remote sense point compensating motherboard or connector losses. Keeping the FB and FBG traces parallel and guarded by a power plane results in common mode coupling for any picked-up noise. Figure 10. Differential remote voltage sensing connections VPROG VREF ERROR AMPLIFIER GND DROP RECOVERY IOFFSET FBG IDROOP VSEN To GND_core To VCC_core (Remote Sense) (Remote Sense) Doc ID 14521 Rev 3 COMP FB RFB RF CF CP 25/57 Voltage positioning 11 L6716 Voltage positioning Output voltage positioning is performed by selecting the internal reference value through VID pins and by programming the droop function and offset to the reference (see Figure 11). The currents sourced/sunk from FB pin cause the output voltage to vary according to the external RFB. The output voltage is then driven by the following relationship: V OUT ( I OUT ) = V PROG – R FB ⋅ [ I DROOP ( I OUT ) – I OFFSET ] where: V PROG = VID – 19mV DCR I DROOP ( I OUT ) = ------------- ⋅ I OUT Rg 1.240V I OFFSET = -----------------------R OFFSET OFFSET function can be disabled shorting to SGND the OFFSET pin. Figure 11. Voltage positioning (left) and droop function (right) ERROR AMPLIFIER VREF VPROG GND DROP RECOVERY IOFFSET ESR Drop VMAX IDROOP VNOM FBG 11.1 VSEN To GND_core To VCC_core (Remote Sense) (Remote Sense) COMP FB RFB RF CF VMIN RESPONSE WITHOUT DROOP RESPONSE WITH DROOP CP Offset (optional) The OFFSET pin allows programming a positive offset (VOS) for the output voltage by connecting a resistor ROFFSET vs. SGND as shown in Figure 12; this offset has to be considered in addition to the one already introduced during the production stage (VPROG=VID-19 mV). OFFSET function can be disabled shorting to SGND the OFFSET pin. The OFFSET pin is internally fixed at 1.240 V (See Table 5) a current is programmed by connecting the resistor ROFFSET between the pin and SGND: this current is mirrored and then properly sunk from the FB pin as shown in Figure 12. Output voltage is then programmed as follow: 1.240V V OUT ( I OUT ) = V PROG – R FB ⋅ I DROOP ( I OUT ) – -----------------------R OFFSET 26/57 Doc ID 14521 Rev 3 L6716 Voltage positioning where: 1.240V V OS = R FB ⋅ -----------------------R OFFSET Offset resistor can be designed by considering the following relationship (RFB is fixed by the Droop effect): 1.240V R OFFSET = R FB ⋅ ------------------V OS Offset automatically given by the DAC selection differs from the offset implemented through the OFFSET pin: the built-in feature is trimmed in production and assures ±0.5% error over load and line variations. Figure 12. Voltage positioning with positive offset ERROR AMPLIFIER VREF VPROG GND DROP RECOVERY IOFFSET 1.240V FBG OFFSET IOFFSET IDROOP VSEN FB COMP ROFFSET 11.2 To GND_core To VCC_core (Remote Sense) (Remote Sense) RFB RF CF CP Droop function This method “recovers” part of the drop due to the output capacitor ESR in the load transient, introducing a dependence of the output voltage on the load current: a static error proportional to the output current causes the output voltage to vary according to the sensed current. As shown in Figure 11, the ESR drop is present in any case, but using the droop function the total deviation of the output voltage is minimized. Moreover, more and more highperformance CPUs require precise load-line regulation to perform in the proper way. DROOP function is not then required only to optimize the output filter, but also becomes a requirement of the load. The device forces a current IDROOP, proportional to the read current, into the feedback RFB resistor implementing the load regulation dependence. Since IDROOP depends on the current information about the N phases, the output characteristic vs. load current is then given by (neglecting the OFFSET voltage term): DCR V OUT = V PROG – R FB ⋅ I DROOP = V REF – R FB ⋅ ------------- ⋅ I OUT = V PROG – R DROOP ⋅ I OUT Rg Where DCR is the inductor parasitic resistance (or sense resistor when used) and IOUT is the output current of the system. The whole power supply can be then represented by a “real” voltage generator with an equivalent output resistance RDROOP and a voltage value of VPROG. RFB resistor can be also designed according to the RDROOP specifications as follow: Rg R FB = R DROOP ⋅ ------------DCR Doc ID 14521 Rev 3 27/57 Droop thermal compensation 12 L6716 Droop thermal compensation Current sense element (DCR inductor) has a non-negligible temperature variation. As a consequence, the sensed current is subjected to a measurement error that causes the regulated output voltage to vary accordingly (when droop function is implemented). To recover from this temperature related error, NTC resistor can be added into feedback compensation network, as shown in Figure 13. The output voltage is then driven by the following relationship (neglecting the OFFSET voltage term): V OUT = V PROG – ( R FB ⋅ I DROOP ) where RFB is the equivalent feedback resistor and it depends on the temperature through NTC resistor. Considering the relationships between IDROOP and the IOUT, the output voltage results: DCR [ T ] V OUT [ (T,I OUT) ] = V PROG – ⎛ R FB [ T ] ⋅ ---------------------- ⋅ I OUT⎞ ⎝ ⎠ Rg where T is the temperature. If the inductor temperature increases the DCR inductor increases and NTC resistor decreases. As a consequence the equivalent RFB resistor decreases keeping constant the output voltage respect to temperature variation. NTC resistor must be placed as close as possible to the sense elements (phase inductor). Figure 13. NTC connections for DC load line thermal compensation VPROG VREF ERROR AMPLIFIER GND DROP RECOVERY IOS IDROOP FBG FB COMP RFB RF RFB3 NTC RFB2 CF RFB1 CP To GND_core (Remote Sense) 28/57 To VCC_core (Remote Sense) Doc ID 14521 Rev 3 L6716 13 Output current monitoring (IMON) Output current monitoring (IMON) The device sources from IMON pin a current proportional to the load current (the sourced current is a copy of Droop current). Connect IMON pin through a RIMON resistor to remote ground (GND core) to implement a load indicator, as shown in Figure 14. As Intel VR11.1 specification required, on the IMON voltage as to be added a small positive offset to avoid under-estimation of the output load (due to elements accuracy). The voltage across IMON pin is given by the following formula: R IMON ⋅ R OS R IMON V MONITORING = ----------------------------------- ⋅ I DROOP + V REF ⋅ ----------------------------------R IMON + R OS R IMON + R OS where: DCR I DROOP = ------------- ⋅ I OUT Rg The IMON pin voltage is clamped to 1.100 V max to preserve the CPU from excessive voltages as Intel VR11.1 specification required. Figure 14. Output monitoring connection (left) and thermal compensation (right) IDROOP IDROOP IMON VREF = +3V3 IMON VREF = +3V3 RIMON_OS CIMON To CPU RIMON_OS CIMON To CPU R3 R2 RIMON NTC To GND_core To GND_core (Remote Sense) (Remote Sense) RIMON R1 Current sense element (DCR inductor) has a non-negligible temperature variation. As a consequence, the sensed current is subjected to a measurement error that causes the monitoring voltage to vary accordingly. To recover from this temperature related error, NTC resistor can be added into monitoring network, as shown in Figure 14. The monitoring voltage is then driven by the following relationship (neglecting the offset term for simplicity): R IMON ⋅ R OS DCR R IMON ⋅ R OS V MONITORING = ----------------------------------- ⋅ I DROOP = ----------------------------------- ⋅ ------------- ⋅ I OUT R IMON + R OS R IMON + R OS Rg where now the RIMON is the equivalent monitoring resistor and it depends on the temperature through NTC resistor. Considering the relationships between IDROOP and the IOUT, the voltage results: R IMON T ⋅ R OS DCR [ T ] V MONITORING [ (T,I OUT) ] = ---------------------------------------------- ⋅ ---------------------- ⋅ I OUT R IMON T + R OS Rg where T is the temperature. Doc ID 14521 Rev 3 29/57 Output current monitoring (IMON) L6716 If the inductor temperature increases the DCR inductor increases and NTC resistor decreases. As a consequence the equivalent RIMON resistor decreases keeping constant the monitoring voltage respect to temperature variation. NTC resistor must be placed as close as possible to the sense elements (phase inductor). 30/57 Doc ID 14521 Rev 3 L6716 Load transient boost technology LTB Technology™ further enhances the performances of dual-edge asynchronous systems by reducing the system latencies and immediately turning ON all the phases to provide the correct amount of energy to the load. By properly designing the LTB network, as well as the LTB gain, the undershoot and the ring-back can be minimized also optimizing the output capacitors count. LTB Technology™ monitors the output voltage through a dedicated pin (see Figure 16) detecting load-transients with selected dV/dt, it cancels the interleaved phase-shift, turningon simultaneously all phases. It then implements a parallel independent loop that (bypassing error amplifier (E/A) latencies) reacts to load-transients in very short time ( V BOOT ) R SSOSC [ kΩ ] V SS 1.24 ---------------------------------- ⋅ ---------------------------------------------- ⋅ 1 + ----------------–3 1.24 V – [ V ] V DIODE BOOT 40 ⋅ 10 if ( V SS < V BOOT ) where TSS is the time spent to reach the programmed voltage VSS and RSSOSC the resistor connected between SSOSC and SSEND (through a signal diode) in kΩ. Figure 20. Soft-start time (TSS) when using RSSOSC, diode versus SSEND Use the following relationship to select the maximum LTB switching frequency: BJT 4 1.24 – V CE [V] 2.11 ⋅ 10 R FLIMIT [ kΩ ] = --------------------------------- ⋅ ----------------------------------------------1.24 F LIMIT [ kHz ] where FLIMIT has to be higher than the FSW switching frequency. Doc ID 14521 Rev 3 37/57 Soft-start Note: L6716 Connecting SSOSC pin to SGND through only the RFLIM_SS resistor (blue one network in Figure 19), the Soft-start time depends on the FLIMIT selected. In this case use the following relationship to select FLIMIT and as a consequence the softstart time: 4 2.11 ⋅ 10 R FLIM – SS [ kΩ ] = -------------------------------F LIMIT [ kHz ] 5 5.275 ⋅ 10 T D2 [ μs ] = --------------------------------F LIMIT [ kHz ] Figure 21. Soft-start time (TSS) vs FLIMIT when using RFLIM_SS resistor versus SGND 17.1 Low-side-less startup In order to avoid any kind of negative undershoot on the load side during start-up, L6716 performs a special sequence in enabling LS driver to switch: during the soft-start phase, the LS driver results disabled (LS=OFF) until the HS starts to switch. This avoid the dangerous negative spike on the output voltage that can happen if starting over a pre-biased output (see Figure 22). This particular feature of the device masks the LS turn-on only from the control loop point of view: protections are still allowed to turn-ON the LS MOSFET in case of overvoltage if needed. Figure 22. Low-side-less start-up comparison.with LS-less start-up Without LS-Less start-up VOUT With LS-Less start-up VOUT LGATE 38/57 Doc ID 14521 Rev 3 LGATE L6716 18 Output voltage monitor and protections Output voltage monitor and protections L6716 monitors through pin VSEN the regulated voltage in order to manage the OVP and UVP conditions. Protections are active also during soft-start (Section 17: Soft-start on page 36) while they are masked during D-VID transitions with an additional 67 µs delay after the transition has finished to avoid false triggering. 18.1 Undervoltage If the output voltage monitored by VSEN drops more than 600 mV (typ) below the programmed reference for more than one clock period, the L6716: 18.2 ● Permanently turns OFF all the MOSFETs (PWM4 is forced in high impedance when external driver is used) ● Drives the OSC/ FAULT pin high (3.3 V typ). ● Power supply or OUTEN pin cycling is required to restart operations. Preliminary overvoltage To provide a protection while VCC is below the UVLOVCC threshold is fundamental to avoid damage to the CPU in case of failed HS MOSFETs. In fact, since the device is supplied from the 12 V bus, it is basically “blind” for any voltage below the turn-on threshold (UVLOVCC). In order to give full protection to the load, a preliminary-OVP protection is provided while VCC is within UVLOVCC and UVLOPre-OVP. This protection turns-on the low side MOSFETs as long as the VSEN pin voltage is greater than 1.800 V with a 350 mV hysteresis. When set, the protection drives the LS MOSFET with a gate-to-source voltage depending on the voltage applied to VCC. This protection depends also on the OUTEN pin status as detailed in Figure 23. A simple way to provide protection to the output in all conditions when the device is OFF (then avoiding the unprotected red region in Figure 23-Left) consists in supplying the controller through the 5 VSB bus as shown in Figure 23-Right: 5 VSB is always present before +12 V and, in case of HS short, the LS MOSFET is driven with 5 V assuring a reliable protection of the load. Figure 23. Output voltage protections and typical principle connections +5V Vcc UVLOVCC (OUTEN = 0) Preliminary OVP VSEN Monitored (OUTEN = 1) Programmable OVP VSEN Monitored SB +12V BAT54C 10Ω VCC Preliminary OVP Enabled VSEN Monitored 2.2Ω 1μF VCCDR UVLOOVP 2x1μF No Protection Provided Note: The device turns ON only LS MOSFETs of Phase1-Phase3 if the Pre-OVP is detected before that VCC is higher than UVLOVCC. (The device reads PWM4 information if the VCC is higher than UVLOVCC). Doc ID 14521 Rev 3 39/57 Output voltage monitor and protections 18.3 L6716 Overvoltage and programmable OVP Once VCC crosses the turn-ON threshold and the device is enabled (OUTEN = 1), L6716 provides an overvoltage protection: when the voltage sensed by VSEN overcomes the OVP threshold (OVPTH), the controller: ● Permanently turns OFF all the high-side MOSFETs. ● Permanently turns ON all the low-side MOSFETs (PWM4 is forced low when external driver is used) in order to protect the load. ● Drives the OSC/ FAULT pin high (3.3 V typ). ● Power supply or OUTEN pin cycling is required to restart operations. The OVP threshold can be also programmed through the OVP pin: leaving the pin floating, it is internally pulled-up and the OVP threshold is set to VID+150 mV (typ). Connecting the OVP pin to SGND through a resistor ROVP, the OVP threshold becomes the voltage present at the pin. Since the OVP pin sources a constant IOVP = 20 µA current (see Table 5), the programmed voltage becomes: OVP TH = R OVP ⋅ 20μA ⇒ OVP TH R OVP = ------------------20μA Filter OVP pin with 100 pF (max) vs. SGND. Table 9. Overvoltage protection threshold OVP pin Thresholds OVP threshold Floating Tracking OVPTH = VID + 175 mV (typ) ROVP to SGND Fixed OVPTH = ROVP * 20 μA (typ) Overvoltage protections is always active during the soft-start, as shown in the following picture: Figure 24. OVP threshold during soft-start for tracking (left) and fixed (right) mode OUTEN OUTEN t VOUT t VOUT t SS_END t SS_END t OVPTH VID+175mV 1.240V t Note: 40/57 t OVPTH ROVP * 20uA t When VR10/VR11 table is selected (OVP pin to SGND) the OVP threshold becomes 1.800 V (typ) fixed. Doc ID 14521 Rev 3 L6716 Overcurrent protection The device limits the peak the inductor current entering in constant current until setting UVP as below explained. The overcurrent threshold has to be programmed, by designing the ROCSET resistors as shown in the Figure 25, to a safe value, in order to be sure that the device doesn't enter OCP during normal operation of the device. This value must take into consideration also the extra current needed during the Dynamic VID Transition ID-VID (See “Dynamic VID transitions” Section for details): IOUT OCP > IOUT MAX + I D – VID The device detects an overcurrent when the IINFOx overcome the threshold IOCTH externally programmable through OCSET pin. V OCSET ( typ -) - = 1.240V -------------------------------I OCTH = --------------------R OCSET R OCSET OCP I INFOx OCP DCR ⎛ I OUT ΔIL-⎞ = ------------- ⋅ ⎜ ---------------------- + -------⎟ Rg ⎝ N 2 ⎠ where ΔIL is the inductor ripple current (peak-to-peak). Since the device always senses the current across the inductor, the IOCTH crossing will happen during the HS conduction time: as a consequence of OCP detection, the device will turn OFF the HS MOSFET and turns ON the LSMOSFET of that phase until IINFOx re-cross the threshold or until the next clock cycle. This implies that the device limits the peak of the inductor current. In any case, the inductor current won't overcome the IOCPx value and this will represent the maximum peak value to consider in the OC design. The device works in constant-current, and the output voltage decreases as the load increase, until the output voltage reaches the UVP threshold. When this threshold is crossed, all MOSFETs are turned off and the device stops working. Cycle the power supply or the OUTEN pin to restart operation. Figure 25. Overcurrent protection connection IOCTH 18.4 Output voltage monitor and protections VOCSET =1.240V (TYP) OCSET/PSI_A ROCSET Doc ID 14521 Rev 3 41/57 Output voltage monitor and protections Note: L6716 In order to avoid the OCP intervention during the DVID, the device automatically increases the OCP threshold to 150% of the selected OCP threshold during every VID transition (adding an extra 15 µs of delay). Since the device reads the current information across inductor DCR, the process spread and temperature variations of these sensing elements has to be considered. Also the programmable threshold spread (IOCTH current spread as a consequence of VOCSET spread, See “Electrical characteristics” Section) has to be considered for the ROCSET design: V OCSET ( MIN ) R OCSET = ----------------------------------------------------------------------------------------I OUT ( OCP ) ΔIL⎞ DCR ( MAX ) ⎛ -------------------------------- ⋅ ------------------------------- + --------⎝ Rg N 2 ⎠ The OCSET pin is also used to select the number of phases when PSI mode is asserted. To select the desired OCP threshold and number of phase during PSI mode, refer to the following table. Table 10. # phases when PSI is asserted # phase normal mode (N) # phase PSI mode (N_PSI) Phases enabled ROCSET 1 PHASE1 V OCSET ( MIN ) R OCSET = ----------------------------------------------------------------------------------------------------------------------DCR ( MAX ) )- ⎛ I OUT ( OCP ) ΔIL⎞ ---------------------------------⋅ ⎝ ------------------------------- + ---------⎠ + 77μA Rg N 2 2 PHASE1 PHASE3 V OCSET ( MIN ) R OCSET = ----------------------------------------------------------------------------------------DCR ( MAX )- ⎛ I OUT ( OCP ) ΔIL⎞ ------------------------------⋅ ⎝ ------------------------------- + ---------⎠ Rg N 2 1 PHASE1 V OCSET ( MIN ) R OCSET = ----------------------------------------------------------------------------------------DCR ( MAX )- ⎛ I OUT ( OCP ) ΔIL⎞ ------------------------------⋅ ⎝ ------------------------------- + ---------⎠ Rg N 2 2 PHASE1 PHASE3 V OCSET ( MIN ) R OCSET = ----------------------------------------------------------------------------------------------------------------------DCR ( MAX ) )- ⎛ I OUT ( OCP ) ΔIL⎞ ---------------------------------⋅ ------------------------------- + --------- + 77μA ⎝ Rg N 2 ⎠ 1 PHASE1 V OCSET ( MIN ) R OCSET = ----------------------------------------------------------------------------------------DCR ( MAX )- ⎛ I OUT ( OCP ) ΔIL⎞ ------------------------------⋅ ------------------------------- + --------⎝ Rg N 2 ⎠ 2 N. A. Do not use this condition (Not applicable) 4 3 2 42/57 Doc ID 14521 Rev 3 L6716 18.5 Output voltage monitor and protections Feedback disconnection L6716 allows to protect the load from dangerous overvoltage also in case of feedback disconnection. The device is able to recognize both FB pin and FBG pin disconnections, as shown in the Figure 26. When VSEN pin is more than 500 mV higher then VPROG, the device recognize a FBG disconnections. Viceversa, when CS1- is more than 700 mV higher then VSEN, the device recognize a FB disconnection. In both of the previous condition the device stops switching with all the MOSFETs permanently OFF and drives high the OSC/FAULT pin. The condition is latched until VCC or OUTEN cycled. Figure 26. Feedback disconnection 500mV FBG DISCONNECTED VREF FB DISCONNECTED 700mV IOS IDROOP ERROR AMPLIFIER VPROG GND DROP RECOVERY FBG VSEN COMP FB CS1+ CS1Rg RF C CF CP To GND_core (Remote Sense) To VCC_core RFB R PHASE1 L1 DCR1 VOUT (Remote Sense) Doc ID 14521 Rev 3 43/57 Low power state management and PSI# 19 L6716 Low power state management and PSI# The device is able to manage the low power state mode: when the PSI is driven low (PSI is active low) the device turns OFF some phase in order to increase the system efficiency. The number of phases active when low power state is active depends on the OCSET/PSI_A pin (trough ROCSET versus SGND) as shown in the following table: Table 11: # phases when PSI is asserted # phase normal mode (N) # phase PSI mode (N_PSI) Phases enabled ROCSET 1 PHASE1 V OCSET ( MIN ) R OCSET = ----------------------------------------------------------------------------------------------------------------------DCR ( MAX ) )- ⎛ I OUT ( OCP ) ΔIL⎞ ---------------------------------⋅ ⎝ ------------------------------- + ---------⎠ + 77μA Rg N 2 2 PHASE1 PHASE3 V OCSET ( MIN ) R OCSET = ----------------------------------------------------------------------------------------DCR ( MAX )- ⎛ I OUT ( OCP ) ΔIL⎞ ------------------------------⋅ ⎝ ------------------------------- + ---------⎠ Rg N 2 1 PHASE1 V OCSET ( MIN ) R OCSET = ----------------------------------------------------------------------------------------DCR ( MAX )- ⎛ I OUT ( OCP ) ΔIL⎞ ------------------------------⋅ ⎝ ------------------------------- + ---------⎠ Rg N 2 2 PHASE1 PHASE3 V OCSET ( MIN ) R OCSET = ----------------------------------------------------------------------------------------------------------------------I OUT ( OCP ) ΔIL⎞ DCR ( MAX ) ) ⎛ ----------------------------------- ⋅ ------------------------------- + --------- + 77μA ⎝ Rg N 2 ⎠ 1 PHASE1 V OCSET ( MIN ) R OCSET = ----------------------------------------------------------------------------------------I OUT ( OCP ) ΔIL⎞ DCR ( MAX ) ⎛ -------------------------------- ⋅ ------------------------------- + --------⎝ Rg N 2 ⎠ 2 N. A. Do not use this condition (Not applicable) 4 3 2 If DVID (dynamic VID change) happens during low power state (PSI low), the device turns on all the N phases in order to follow the DVID change reducing the over/under shoot of the output voltage. Note: 44/57 If the PSI is already low during the start-up, the device implements the soft-start using the N phases selected trough PWM4 pin. When the soft-start is finished the device turns OFF some phases in according to the PSI strategy. Doc ID 14521 Rev 3 L6716 20 Oscillator Oscillator L6716 embeds two-to-four phase oscillator with optimized phase-shift (180º/120º/90º phase-shift) in order to reduce the input rms current and optimize the output filter definition. The internal oscillator generates the triangular waveform for the PWM charging and discharging with a constant current an internal capacitor. The switching frequency for each channel, FSW, is internally fixed at 200 kHz so that the resulting switching frequency at the load side results in being multiplied by N (number of phases). The current delivered to the oscillator is typically 25 μA (corresponding to the free running frequency FSW = 200 kHz) and it may be varied using an external resistor (ROSC) connected between the OSC/FAULT pin and SGND or VCC (or a fixed voltage greater than 1.24 V). Since the OSC/FAULT pin is fixed at 1.240 V, the frequency is varied proportionally to the current sunk (forced) from (into) the pin considering the internal gain of 9.1 kHz/μA. In particular connecting ROSC to SGND the frequency is increased (current is sunk from the pin), while connecting ROSC to VCC = 12 V the frequency is reduced (current is forced into the pin), according the following relationships: ROSC vs. SGND 3 3 1.240V kHz 11.284 ⋅ 10 11.284 ⋅ 10 - [ kΩ ] F SW = 200 ( kHz ) + ---------------------------- ⋅ 9.1 ----------- = 200 ( kHz ) + -------------------------------- ⇒ R OSC ( kΩ ) = ----------------------------------------------------------R OSC ( kΩ ) μA R OSC ( kΩ ) F SW ( kHz ) – 200 ( kHz ) ROSC vs. +12 V 4 4 12V – 1.240V kHz 9.7916 ⋅ 10 9.7916 ⋅ 10 - ⇒ R F SW = 200 ( kHz ) – ------------------------------------ ⋅ 9.1 ----------- = 200 ( kHz ) – ------------------------------OSC ( kΩ ) = ------------------------------------------------------------ [ kΩ ] R OSC ( kΩ ) μA R OSC ( kΩ ) 200 ( kHz ) – F SW ( kHz ) Maximum programmable switching frequency per phase must be limited to 1 MHz to avoid minimum Ton limitation. Anyway, device power dissipation must be checked prior to design high switching frequency systems. Figure 27. ROSC vs. switching frequency Doc ID 14521 Rev 3 45/57 Driver section 21 L6716 Driver section The integrated high-current drivers allow using different types of power MOS (also multiple MOS to reduce the equivalent Rds(ON)), maintaining fast switching transition. The drivers for the high-side MOSFETs use BOOTx pins for supply and PHASEx pins for return. The drivers for the low-side MOSFETs use VCCDR pin for supply and PGND pin for return. A minimum voltage at VCCDR pin is required to start operations of the device. The controller embodies a sophisticated anti-shoot-through system to minimize low side body diode conduction time maintaining good efficiency saving the use of Schottky diodes: when the high-side MOSFET turns off, the voltage on its source begins to fall; when the voltage reaches 2 V, the low-side MOSFET gate drive is suddenly applied. When the lowside MOSFET turns off, the voltage at LGATEx pin is sensed. When it drops below 1 V, the high-side MOSFET gate drive is suddenly applied. If the current flowing in the inductor is negative, the source of high-side MOSFET will never drop. To allow the turning on of the low-side MOSFET even in this case, a watchdog controller is enabled: if the source of the high-side MOSFET doesn't drop, the low side MOSFET is switched on so allowing the negative current of the inductor to recirculate. This mechanism allows the system to regulate even if the current is negative. The BOOTx and VCCDR pins are separated from IC's power supply (VCC pin) as well as signal ground (SGND pin) and power ground (PGND pin) in order to maximize the switching noise immunity. 46/57 Doc ID 14521 Rev 3 L6716 22 System control loop compensation System control loop compensation The control loop is composed by the current sharing control loop (see Figure 9) and the average current mode control loop. Each loop gives, with a proper gain, the correction to the PWM in order to minimize the error in its regulation: the current sharing control loop equalize the currents in the inductors while the average current mode control loop fixes the output voltage equal to the reference programmed by VID. Figure 28 shows the block diagram of the system control loop. The system control loop is reported in Figure 29. The current information IDROOP sourced by the FB pin flows into RFB implementing the dependence of the output voltage from the read current. Figure 28. Main control loop L4 PWM4 2/5 L3 PWM3 2/5 L2 PWM2 COUT ROUT 2/5 L1 PWM1 2/5 ERROR AMPLIFIER VREF 3/5 IDROOP CURRENT SHARING DUTY CYCLE CORRECTION IINFO1 IINFO2 IINFO3 IINFO4 COMP FB ZF(s) ZFB(s) (IINFO2,IINFO4 only applied when using 3-PHASE or 4-PHASE Operation) The system can be modeled with an equivalent single phase converter which only difference is the equivalent inductor L/N (where each phase has an L inductor). The control loop gain results (obtained opening the loop after the COMP pin): PWM ⋅ Z F ( s ) ⋅ ( R DROOP + Z P ( s ) ) G LOOP ( s ) = – -----------------------------------------------------------------------------------------------------------------ZF ( s ) ⎛ 1 -⎞ ⋅ R [ Z P ( s ) + Z L ( s ) ] ⋅ -------------+ 1 + ----------FB A(s) ⎝ A ( s )⎠ Where: DCR is the inductor parasitic resistance; is the equivalent output resistance determined by the droop function; DCR R DROOP = ------------- ⋅ R FB Rg ZP(s) is the impedance resulting by the parallel of the output capacitor (and its ESR) and the applied load RO ZF(s) is the compensation network impedance ZL(s) is the parallel of the N inductor impedance A(s) is the error amplifier gain Doc ID 14521 Rev 3 47/57 System control loop compensation L6716 V IN 3 PWM = --- ⋅ ------------------5 ΔV OSC is the PWM transfer function where ΔVOSC is the oscillator ramp amplitude and has a typical value of 1.5 V. Removing the dependence from the error amplifier gain, so assuming this gain high enough, and with further simplifications, the control loop gain results: G LOOP 1 + s ⋅ C ⋅ (R //R + ESR ) 3 V IN Z F ( s ) R O + R DROOP O DROOP O ( s ) = – ---- ⋅ ---------------------- ⋅ --------------- ⋅ -------------------------------------------- ⋅ -------------------------------------------------------------------------------------------------------------------------------------------R FB RL RL 5 ΔV 2 L OSC L R + ------s ⋅ C ⋅ ----- + s ⋅ ------------------- + C ⋅ ESR + C ⋅ ------- + 1 O N O N O N N ⋅ RO O The system control loop gain (see Figure 28) is designed in order to obtain a high DC gain to minimize static error and to cross the 0 dB axes with a constant -20 dB/dec slope with the desired crossover frequency ωT. Neglecting the effect of ZF(s), the transfer function has one zero and two poles; both the poles are fixed once the output filter is designed (LC filter resonance ωLC) and the zero (ωESR) is fixed by ESR and the Droop resistance. Figure 29. Equivalent control loop block diagram (left) and bode diagram (right) PWM d VOUT L / N VOUT dB IDROOP ESR CO RO VREF GLOOP(s) K FB COMP VSEN FBRTN ZF(s) RF[dB] CF RF ZF(s) CP ZFB(s) ω ωLC = ωF ωESR RFB ωT To obtain the desired shape an RF-CF series network is considered for the ZF(s) implementation. A zero at ωF = 1/RFCF is then introduced together with an integrator. This integrator minimizes the static error while placing the zero ωF in correspondence with the LC resonance assures a simple -20 dB/dec shape of the gain. In fact, considering the usual value for the output filter, the LC resonance results to be at frequency lower than the above reported zero. Compensation network can be simply designed placing ωF = ωLC and imposing the crossover frequency ωT as desired obtaining (always considering that ωT might be not higher than 1/10th of the switching frequency FSW): RF L C O ⋅ ---R FB ⋅ ΔV OSC 5 L N = ---------------------------------- ⋅ --- ⋅ ω T ⋅ -------------------------------------------------------- C F = --------------------V IN 3 N ⋅ ( R DROOP + ESR ) RF Moreover, it is suggested to filter the high frequency ripple on the COMP pin adding also a capacitor between COMP pin and FB pin (it does not change the system bandwidth): 1 C P = ----------------------------------------------2 ⋅ π ⋅ R F ⋅ N ⋅ F SW 48/57 Doc ID 14521 Rev 3 L6716 23 Tolerance band (TOB) definition Tolerance band (TOB) definition Output voltage load-line varies considering component process variation, system temperature extremes, and age degradation limits. Moreover, individual tolerance of the components also varies among designs: it is then possible to define a manufacturing tolerance band (TOBManuf) that defines the possible output voltage spread across the nominal load line characteristic. TOBManuf can be sliced into different three main categories: controller tolerance, external current sense circuit tolerance and time constant matching error tolerance. All these parameters can be composed thanks to the RSS analysis so that the manufacturing variation on TOB results to be: TOB Manuf = 2 2 2 TOB Controller + TOB CurrSense + TOB TCMatching Output voltage ripple (VP=VPP/2) and temperature measurement error (VTC) must be added to the manufacturing TOB in order to get the system tolerance band as follow: TOB = TOB Manuf + V P + V TC All the component spreads and variations are usually considered at 3σ. Here follows an explanation on how to calculate these parameters for a reference L6716 application. 23.1 Controller tolerance (TOBController) It can be further sliced as follow: Reference tolerance. L6716 is trimmed during the production stage to ensure the output voltage to be within kVID = ±0.5% over temperature and line variations. In addition, the device automatically adds a -19 mV offset avoiding the use of any external component. This offset is already included during the trimming process in order to avoid the use of any external circuit to generate this offsets and, moreover, avoiding the introduction of any further error to be considered in the TOB calculation. Current reading circuit. The device reads the current flowing across the inductor DCR by using its dedicated differential inputs. The current sourced by the VRD is then reproduced and sourced from the FB pin scaled down by a proper designed gain as follow: DCR I DROOP = ------------- ⋅ I OUT Rg This current multiplied by the RFB resistor connected from FB pin vs. the load allows programming the droop function according to the selected DCR/Rg gain and RFB resistor. Deviations in the current sourced due to errors in the current reading, impacts on the output voltage depending on the size of RFB resistor. The device is trimmed during the production stage in order to guarantee a maximum deviation of kIFB = ± 3 μA from the nominal value. Controller tolerance results then to be: TOB Controller = 2 [ ( VID – 19mV ) ⋅ k VID ] + ( k IDROOP ⋅ R FB ) Doc ID 14521 Rev 3 2 49/57 Tolerance band (TOB) definition 23.2 L6716 External current sense circuit tolerance (TOBCurrSense) It can be further sliced as follow: Inductor DCR tolerance (kDCR). Variations in the inductor DCR impacts on the output voltage since the device reads a current that is different from the real current flowing into the sense element. As a results, the controller will source a IDROOP current different from the nominal. The results will be an AVP different from the nominal in the same percentage as the DCR is different from the nominal. Since all the sense elements results to be in parallel, the error related to the inductor DCR has to be divided by the number of phases (N). Trans-conductance resistors tolerance (kRg). Variations in the Rg resistors impacts in the current reading circuit gain and so impacts on the output voltage. The results will be an AVP different from the nominal in the same percentage as the Rg is different from the nominal. Since all the sense elements results to be in parallel, and so the three current reading circuits, the error related to the Rg resistors has to be divided by the number of phases (N). NTC Initial Accuracy (kNTC_0). Variations in the NTC nominal value at room temperature used for the thermal compensation impacts on the AVP in the same percentage as before. In addition, the benefit of the division by the number of phases N cannot be applied in this case. NTC temperature accuracy (kNTC). NTC variations from room to hot also impacts on the output voltage positioning. The impact is bigger as big is the temperature variation from room to hot (ΔT). All these parameters impacts the AVP, so they must be weighted on the maximum voltage swing from zero load up to the maximum electrical current (VAVP). Total error from external current sense circuit results: 2 TOB CurrSense = 23.3 2 α ⋅ ΔT ⋅ k NTC 2 k DCR k Rg 2 2 V AVP ⋅ ------------- + --------- + k NTC0 + ⎛⎝ ----------------------------------⎞⎠ DCR N N Time constant matching error tolerance (TOBTCMatching) Inductance and capacitance tolerance (kL, kC). Variations in the inductance value and in the value of the capacitor used for the time constant matching causes over/under shoots after a load transient appliance. This impacts the output voltage and then the TOB. Since all the sense elements results to be in parallel, the error related to the time constant mismatch has to be divided by the number of phases (N). Capacitance temperature variations (kCt). The capacitor used for time constant matching also vary with temperature (ΔTC) impacting on the output voltage transients ad before. Since all the sense elements results to be in parallel, the error related to the time constant mismatch has to be divided by the number of phases (N). All these parameters impact the dynamic AVP, so they must be weighted on the maximum dynamic voltage swing (Idyn). Total error due to time constant mismatch results: 2 TOB TCMatching = 50/57 2 2 k L + k C + ( k Ct ⋅ ΔTC ) 2 V AVPDyn ⋅ ---------------------------------------------------------N Doc ID 14521 Rev 3 L6716 23.4 Tolerance band (TOB) definition Temperature measurement error (VTC) Error in the measured temperature (for thermal compensation) impacts on the output regulated voltage since the correction form the compensation circuit is not what required to keep the output voltage flat. The measurement error (εTemp) must be multiplied by the copper temp coefficient (α) and compared with the sensing resistance (RSENSE): this percentage affects the AVP voltage as follow: α ⋅ ε Temp V TC = ------------------------ ⋅ V AVP R SENSE Doc ID 14521 Rev 3 51/57 Layout guidelines 24 L6716 Layout guidelines Since the device manages control functions and high-current drivers, layout is one of the most important things to consider when designing such high current applications. A good layout solution can generate a benefit in lowering power dissipation on the power paths, reducing radiation and a proper connection between signal and power ground can optimize the performance of the control loops. Two kind of critical components and connections have to be considered when layouting a VRM based on L6716: power components and connections and small signal components connections. 24.1 Power components and connections These are the components and connections where switching and high continuous current flows from the input to the load. The first priority when placing components has to be reserved to this power section, minimizing the length of each connection and loop as much as possible. To minimize noise and voltage spikes (EMI and losses) these interconnections must be a part of a power plane and anyway realized by wide and thick copper traces: loop must be anyway minimized. The critical components, i.e. the power transistors, must be close one to the other. The use of multi-layer printed circuit board is recommended. Figure 30 shows the details of the power connections involved and the current loops. The input capacitance (CIN), or at least a portion of the total capacitance needed, has to be placed close to the power section in order to eliminate the stray inductance generated by the copper traces. Low ESR and ESL capacitors are preferred, MLCC are suggested to be connected near the HS drain. Figure 30. Power connections and related connections layout (same for all phases) To limit C BOOT Extra-Charge VIN UGATEx PHASEx BOOTx CIN CBOOT VIN CIN PHASEx L L VCC LGATEx PGND LOAD LOAD SGND +Vcc Note: Boot capacitor extra charge. Systems that do not use Schottky diodes might show big negative spikes on the phase pin. This spike can be limited as well as the positive spike but has an additional consequence: it causes the bootstrap capacitor to be over-charged. This extra-charge can cause, in the worst case condition of maximum input voltage and during particular transients, that boot-to-phase voltage overcomes the abs. max. ratings also causing device failures. It is then suggested in this cases to limit this extra-charge by adding a small resistor in series to the boot diode (one resistor can be enough for all the three diodes if placed upstream the diode anode, see Figure 30) and by using standard and lowcapacitive diodes. Use proper VIAs number when power traces have to move between different planes on the PCB in order to reduce both parasitic resistance and inductance. Moreover, reproducing the 52/57 Doc ID 14521 Rev 3 L6716 Layout guidelines same high-current trace on more than one PCB layer will reduce the parasitic resistance associated to that connection. Connect output bulk capacitor as near as possible to the load, minimizing parasitic inductance and resistance associated to the copper trace also adding extra decoupling capacitors along the way to the load when this results in being far from the bulk capacitor bank. Gate traces must be sized according to the driver RMS current delivered to the power MOSFET. The device robustness allows managing applications with the power section far from the controller without losing performances. External gate resistors help the device to dissipate power resulting in a general cooling of the device. When driving multiple MOSFETs in parallel, it is suggested to use one resistor for each MOSFET. Device exposed pad is the power ground pin (LS drivers return path) as a consequence it has be tied to ground plane layer trough the lowest impedance connection. Connect it to the power ground plane using 5.2 x 5.2 mm square area on the PCB and with sixteen vias (uniformly distributed) to improve electrical and thermal conductivity, as shown in the Figure 31. Figure 31. Exposed pad VIAs number/location to ground plane 24.2 Small signal components and connections These are small signal components and connections to critical nodes of the application as well as bypass capacitors for the device supply (see Figure 30). Locate the bypass capacitor (VCC and Bootstrap capacitor) close to the device and refer sensible components such as frequency set-up resistor ROSC, overcurrent resistor ROCSET. Star grounding is suggested: connect SGND to PGND plane in a single point to avoid that drops due to the high current delivered causes errors in the device behavior. Remote sensing connection must be routed as parallel nets from the FBG/VSEN pins to the load in order to avoid the pick-up of any common mode noise. Connecting these pins in points far from the load will cause a non-optimum load regulation, increasing output tolerance. Locate current reading components close to the device. The PCB traces connecting the reading point must use dedicated nets, routed as parallel traces in order to avoid the pick-up of any common mode noise. It's also important to avoid any offset in the measurement and, to get a better precision, to connect the traces as close as possible to the sensing elements. Small filtering capacitor can be added, near the controller, between VOUT and SGND, on the CSx- line to allow higher layout flexibility. Doc ID 14521 Rev 3 53/57 Embedding L6716 - based VR 25 L6716 Embedding L6716 - based VR When embedding the VRD into the application, additional care must be taken since the whole VRD is a switching DC/DC regulator and the most common system in which it has to work is a digital system such as MB or similar. In fact, latest MB has become faster and powerful: high speed data bus are more and more common and switching-induced noise produced by the VRD can affect data integrity if not following additional layout guidelines. Few easy points must be considered mainly when routing traces in which high switching currents flow (high switching currents cause voltage spikes across the stray inductance of the trace causing noise that can affect the near traces): Keep safe guarding distance between high current switching VRD traces and data buses, especially if high-speed data bus to minimize noise coupling. Keep safe guard distance or filter properly when routing bias traces for I/O sub-systems that must walk near the VRD. Possible causes of noise can be located in the PHASE connections, MOSFET gate drive and Input voltage path (from input bulk capacitors and HS drain). Also PGND connections must be considered if not insisting on a power ground plane. These connections must be carefully kept far away from noise-sensitive data bus. Since the generated noise is mainly due to the switching activity of the VRM, noise emissions depend on how fast the current switches. To reduce noise emission levels, it is also possible, in addition to the previous guidelines, to reduce the current slope by properly tuning the HS gate resistor and the PHASE snubber network. 54/57 Doc ID 14521 Rev 3 L6716 26 Package mechanical data Package mechanical data In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK® packages, depending on their level of environmental compliance. ECOPACK® specifications, grade definitions and product status are available at: www.st.com. ECOPACK is an ST trademark. Figure 32. VFQFPN-48 mechanical data and package dimensions mm mils OUTLINE AND MECHANICAL DATA DIM. A MIN. TYP. MAX. MIN. TYP. MAX. 0.800 0.900 1.000 31.50 35.43 39.37 A3 0.200 7.874 b 0.180 0.250 0.300 7.087 9.843 11.81 D 6.900 7.000 7.100 271.6 275.6 279.5 D2 5.050 5.150 5.250 198.8 202.7 . 206.7 E 6.900 7.000 7.100 271.6 275.6 279.5 E2 5.050 5.150 5.250 198.8 202.7 206.7 e L ddd 0.500 0.300 0.400 19.68 0.500 0.080 11.81 15.75 19.68 VFQFPN-48 (7x7x1.0mm) Very Fine Quad Flat Package No lead 3.150 ddd Doc ID 14521 Rev 3 55/57 Revision history 27 L6716 Revision history Table 12. 56/57 Document revision history Date Revision Changes 28-May-2009 1 First release 12-Aug-2009 2 Updated Table 3 on page 13. 20-Jan-2010 3 Updated Table 2 on page 8, Table 3 on page 13, Chapter 13 on page 29, Figure 14 on page 29 and Chapter 20 on page 45 Doc ID 14521 Rev 3 L6716 Please Read Carefully: Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any time, without notice. All ST products are sold pursuant to ST’s terms and conditions of sale. Purchasers are solely responsible for the choice, selection and use of the ST products and services described herein, and ST assumes no liability whatsoever relating to the choice, selection or use of the ST products and services described herein. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted under this document. If any part of this document refers to any third party products or services it shall not be deemed a license grant by ST for the use of such third party products or services, or any intellectual property contained therein or considered as a warranty covering the use in any manner whatsoever of such third party products or services or any intellectual property contained therein. UNLESS OTHERWISE SET FORTH IN ST’S TERMS AND CONDITIONS OF SALE ST DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY WITH RESPECT TO THE USE AND/OR SALE OF ST PRODUCTS INCLUDING WITHOUT LIMITATION IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE (AND THEIR EQUIVALENTS UNDER THE LAWS OF ANY JURISDICTION), OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT. UNLESS EXPRESSLY APPROVED IN WRITING BY AN AUTHORIZED ST REPRESENTATIVE, ST PRODUCTS ARE NOT RECOMMENDED, AUTHORIZED OR WARRANTED FOR USE IN MILITARY, AIR CRAFT, SPACE, LIFE SAVING, OR LIFE SUSTAINING APPLICATIONS, NOR IN PRODUCTS OR SYSTEMS WHERE FAILURE OR MALFUNCTION MAY RESULT IN PERSONAL INJURY, DEATH, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE. ST PRODUCTS WHICH ARE NOT SPECIFIED AS "AUTOMOTIVE GRADE" MAY ONLY BE USED IN AUTOMOTIVE APPLICATIONS AT USER’S OWN RISK. Resale of ST products with provisions different from the statements and/or technical features set forth in this document shall immediately void any warranty granted by ST for the ST product or service described herein and shall not create or extend in any manner whatsoever, any liability of ST. ST and the ST logo are trademarks or registered trademarks of ST in various countries. Information in this document supersedes and replaces all information previously supplied. The ST logo is a registered trademark of STMicroelectronics. All other names are the property of their respective owners. © 2010 STMicroelectronics - All rights reserved STMicroelectronics group of companies Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan Malaysia - Malta - Morocco - Philippines - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States of America www.st.com Doc ID 14521 Rev 3 57/57