L6725
L6725A
Voltage mode PWM controller
with bootstrap anti-discharging system
Features
■
Input voltage range from 1.8V to 18V
■
Supply voltage range from 4.5V to 18V
■
Adjustable output voltage down to 0.6V with
±0.8% accuracy over line voltage and
temperature (0°C~125°C)
■
Fixed frequency voltage mode control
■
0% to 100% duty cycle
■
External input voltage reference
■
Soft-start and inhibit
■
Bootstrap anti-discharging system
■
High current embedded drivers
■
Predictive anti-cross conduction control
■
Programmable high-side and low-side RDS(on)
sense over-current-protection
SO16N (Narrow)
■
Sink current capability
■
Selectable switching frequency 250KHz/
500KHz
■
Power good and synch available with L6725A
■
Pre-bias start up capability
■
Over voltage protection
■
Thermal shut-down
■
Package: SO16N
Table 1.
June 2007
Applications
■
Low voltage distributed DC-DC
■
Graphic cards
Device summary
Order codes
Package
Packing
L6725
SO16N
Tube
L6725TR
SO16N
Tape & Reel
L6725A
SO16N
Tube
L6725ATR
SO16N
Tape & Reel
Rev 5
1/32
www.st.com
32
L6725 - L6725A
Contents
Contents
1
Summary description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
1.1
2
Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Electrical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2.1
Maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2.2
Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
3
Pin connections and functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
4
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
5
Device description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2/32
5.1
Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
5.2
Internal LDO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
5.3
Bypassing the LDO to avoid the voltage drop with low Vcc . . . . . . . . . . . . . 11
5.4
Internal and external references . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
5.5
Error amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
5.6
Soft start . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
5.7
Driver section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
5.8
Monitoring and protections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
5.9
Hiccup mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
5.10
Thermal shutdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
L6725 - L6725A
Contents
5.11
Synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
5.12
Bootstrap anti-discharging system . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
5.12.1 Fan's power supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
6
7
Application details . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
6.1
Inductor design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
6.2
Output capacitors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
6.3
Input capacitors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
6.4
Compensation network . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
L6725 demoboard . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
7.1
20A board description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
7.2
5A board description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
8
Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
9
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
3/32
L6725 - L6725A
Summary description
1
Summary description
The device is a flexible high performance PWM buck controller dedicated for low voltage
distributed DC-DC. The input voltage can range from 1.8V to 18V, while the supply voltage can
range from 4.5V to 18V. The output voltage is adjustable down to 0.6V.
High peak current gate drivers provide for fast switching to the external power section, and the
output current can be in excess of 20A. The device is capable to manage minimum on-times
(TON) shorter than 100ns making possible conversions with very low duty cycle and very high
switching frequency. In order to guarantee a real overcurrent protection, also with very narrow
TON, the current sense is realized both on the high-side and low-side MOSFETs. When
necessary, two different current limit protections can be externally set through an external
resistor. The device can sink current after the soft-start phase while, during the soft-start, the
sink mode capability is disabled in order to allow a proper start-up also in pre-biased output
voltage conditions. Other features are over-voltage-protection and thermal shutdown.
1.1
Functional description
Figure 1.
Block diagram
Vcc=4.5V-14V
Vcc = 14V - 18V
Vin = 14V - 18V
Vin=1.8V-14V
OCH
OCL
VCCDR
BOOT
LDO
SS
Monitor
HGATE
Protection and Ref
OSC
-
PHASE
V OUT
EAREF
L6725
PGOOD
+
-
LGATE
0.6V
+
PWM
+
FB
4/32
PGND
E/A
SYNCH
-
GND
COMP
L6725 - L6725A
2
Electrical data
2.1
Maximum rating
Table 2.
Electrical data
Absolute maximum ratings
Symbol
Parameter
VCC
Value
Unit
-0.3 to 20
V
0 to 6
\
0 to VBOOT - VPHASE
V
BOOT
-0.3 to 26
V
PHASE
-1 to 20
VCC to GND and PGND, OCH
VBOOT - VPHASE Boot voltage
VHGATE - VPHASE
VBOOT
VPHASE
PHASE Spike, transient < 50ns (FSW = 500KHz)
SS, FB, EAREF, OCL, LGATE, COMP, VCCDR
OCH Pin
OTHER PINS
2.2
Maximum withstanding voltage range
Test Condition: CDF-AEC-Q100-002 "Human Body Model"
Acceptance Criteria: "Normal Performance"
-3
V
+24
-0.3 to 6
V
±1500
V
±2000
Thermal data
Table 3.
Thermal data
Symbol
Value
Unit
50
°C/W
Storage temperature range
-40 to 150
°C
TJ
Junction operating temperature range
-40 to 125
°C
TA
Ambient operating temperature range
-40 to +85
°C
RthJA(1)
TSTG
Description
Max. thermal resistance junction to ambient
1. Package mounted on demoboard
5/32
L6725 - L6725A
Pin connections and functions
3
Pin connections and functions
Figure 2.
Pins connection (top view)
COMP
1
16
FB
SS/INH
2
15
SGND
EAREF
3
14
SYNCH/NC
OCL
4
13
PGOOD/NC
OCH
5
12
VCC
PHASE
6
11
VCCDR
HGATE
7
10
BOOT
8
9
LGATE
PGND
SO16N
Table 4.
Pin functions
Pin n°
Name
Function
1
COMP
This pin is connected to the error amplifier output and is used to compensate the
voltage control feedback loop.
2
SS/INH
The soft-start time is programmed connecting an external capacitor from this pin to
GND. The internal current generator forces a current of 10µA through the capacitor.
When the voltage at this pin is lower than 0.5V the device is disabled.
By setting the voltage at this pin is possible to select the internal/external reference
and the switching frequency:
VEAREF 0-80% of VCCDR -> External Reference/FSW = 250KHz
3
EAREF
VEAREF = 80% - 95% of VCCDR -> VREF = 0.6V/FSW = 500KHz
VEAREF = 95% - 100% of VCCDR ->VREF = 0.6V/FSW = 250KHz
An internal clamp limits the maximum VEAREF at 2.5V (typ.). The device captures the
analog value present at this pin at the start-up when VCC meets the UVLO threshold.
4
OCL
A resistor connected from this pin to ground sets the valley- current-limit. The valley
current is sensed through the low-side MOSFET(s). The internal current generator
sources a current of 100µA (IOCL) from this pin to ground through the external resistor
(ROCL). The over-current threshold is given by the following equation:
I
6/32
VALLEY
=
IOCL ⋅ R OCL
2 ⋅ RDSonLS
L6725 - L6725A
Table 4.
Pin n°
5
Pin connections and functions
Pin functions
Name
Function
OCH
A resistor connected from this pin and the high-side MOSFET(s) drain sets the peakcurrent-limit. The peak current is sensed through the high-side MOSFET(s). The
internal 100µA current generator (IOCH) sinks a current from the drain through the
external resistor (ROCH). The over-current threshold is given by the following
equation:
IPEAK =
IOCH ⋅ R OCH
RDSonHS
6
PHASE
This pin is connected to the source of the high-side MOSFET(s) and provides the
return path for the high-side driver. This pin monitors the drop across both the upper
and lower MOSFET(s) for the current limit together with OCH and OCL.
7
HGATE
This pin is connected to the high-side MOSFET(s) gate.
8
BOOT
Through this pin is supplied the high-side driver. Connect a capacitor from this pin to
the PHASE pin and a diode from VCCDR to this pin (cathode versus BOOT).
9
PGND
This pin has to be connected closely to the low-side MOSFET(s) source in order to
reduce the noise injection into the device.
10
LGATE
This pin is connected to the low-side MOSFET(s) gate.
11
VCCDR
5V internally regulated voltage. It is used to supply the internal drivers. Filter it to
ground with a 1uF ceramic cap.
12
VCC
13
PGOOD
(L6725A)
N.C.
(L6725)
In L6725 this pin is N.C. With L6725A this pin is an open collector output and it is
pulled low if the output voltage is not
within the specified thresholds (90%-110%). If not used it may be left floating. Pull-up
this pin to VCCDR with a 10K resistor to obtain a logical signal.
14
SYNCH
(L6725A)
N.C.
(L6725)
In L6725 this pin is N.C. With L6725A it is a Master-Slave pin. Two or more devices
can be synchronized by simply
connecting the SYNCH pins together. The device operating with the highest FSW will
be the Master. The Slave devices will operate with 180° phase shift from the Master.
The best way to synchronize devices together is to set their FSW at the same value. If
it is not used the SYNCH pin can be left floating.
15
SGND
16
FB
Supply voltage pin. The operative supply voltage range is from 4.5V to 14V.
All the internal references are referred to this pin.
This pin is connected to the error amplifier inverting input. Connect it to VOUT through
the compensation network. This pin is also used to sense the output voltage in order
to manage the over voltage protection.
7/32
L6725 - L6725A
Electrical characteristics
4
Electrical characteristics
VCC = 12V, TA = 25°C unless otherwise specified.
Table 5.
Electrical characteristics
Symbol
Parameter
Test condition
Min
Typ
Max
7
9
8.5
10
Unit
VCC supply current
ICC
VCC Stand by current
SS to GND
VCC quiescent current
HG = open, LG = open, PH=open
Turn-ON VCC threshold
VOCH = 1.7V
4.0
4.2
4.4
V
Turn-OFF VCC threshold
VOCH = 1.7V
3.6
3.8
4.0
V
Turn-ON VOCH threshold
1.1
1.25
1.47
V
Turn-OFF VOCH threshold
0.9
1.05
1.27
V
4.5
5
5.5
V
SS = 2V
7
10
13
SS = 0 to 0.5V
20
30
45
237
250
263
KHz
450
500
550
KHz
mA
Power-ON
VCC
VIN OK
VCCDR Regulation
VCCDR voltage
VCC =5.5V to 18V
IDR = 1mA to 100mA
Soft Start and Inhibit
ISS
Soft Start Current
µA
Oscillator
fOSC
∆VOSC
Accuracy
Ramp Amplitude
2.1
V
Output Voltage
VFB
8/32
Output Voltage
0.597
0.6
0.603
V
L6725 - L6725A
Table 5.
Electrical characteristics
Electrical characteristics
Symbol
Parameter
Test condition
Min.
Typ.
Max.
Unit
70
100
150
kΩ
0.290
0.5
µA
Error Amplifier
REAREF
IFB
EAREF Input Resistance
Vs. GND
I.I. bias current
VFΒ = 0V
Ext Ref
Clamp
VOFFSET
2.3
V
Error amplifier offset
Vref = 0.6V
GV
Open Loop Voltage Gain
Guaranteed by design
100
dB
GBWP
Gain-Bandwidth Product
Guaranteed by design
10
MHz
Slew-Rate
COMP = 10pF
Guaranteed by design
5
V/µs
High Side Source Resistance
VBOOT - VPHASE = 5V
1.7
Ω
RHGATE_OFF High Side Sink Resistance
VBOOT - VPHASE = 5V
1.12
Ω
RLGATE_ON
VCCDR = 5V
1.15
Ω
VCCDR = 5V
0.6
Ω
SR
-5
+5
mV
Gate drivers
RHGATE_ON
Low Side Source Resistance
RLGATE_OFF Low Side Sink Resistance
Protections
IOCH
OCH Current Source
IOCL
OCL Current Source
VOCH = 1.7V
VFB Rising
OVP
Over Voltage Trip
(VFB / VEAREF)
VEAREF = 0.6V
VFB Falling
VEAREF = 0.6V
90
100
110
µΑ
90
100
110
µΑ
120
%
117
%
9/32
L6725 - L6725A
5
Device description
Device description
The controller provides complete control logic and protection for flexible and cost-effective DCDC converters. It is designed to drive N-Channel MOSFETs in a synchronous rectified buck
topology. The output voltage of the converter can be precisely regulated down to 600mV with a
maximum tolerance of ±0.8%, when the internal reference is used. The device allows also
using an external reference (0V to 2.5V) for the regulation. The device provides voltage-mode
control. The switching frequency can be set at two different values: 250KHz or 500KHz. The
error amplifier features a 10MHz gain-bandwidth-product and 5V/µs slew-rate that permits to
realize high converter bandwidth for fast transient response. The PWM duty cycle can range
from 0% to 100%. The device protects against over current conditions providing a constantcurrent-protection during the soft-start phase and entering in HICCUP mode in all the other
conditions. The device monitors the current by using the RDS(ON) of both the high-side and lowside MOSFET(s), eliminating the need for a current sensing resistor and guaranteeing an
effective over-current-protection in all the application conditions. Other features are overvoltage-protection and thermal shutdown. The device is available in SO16N package.
5.1
Oscillator
The switching frequency can be fixed to two values: 250KHz or 500KHz by setting the proper
voltage at the EAREF pin (see Table 4. Pins function and section 4.3 Internal and external
reference).
5.2
Internal LDO
An internal LDO supplies the internal circuitry of the device. The input of this stage is the VCC
pin and the output (5V) is the VCCDR pin. The LDO can be by-passed, providing directly a 5V
voltage to VCCDR. In this case VCC and VCCDR pins must be shorted together as shown in
Figure 3. VCCDR pin must be filtered with a 1uF capacitor to sustain the internal LDO during the
recharge of the bootstrap capacitor.
10/32
L6725 - L6725A
5.3
Device description
Bypassing the LDO to avoid the voltage drop with low Vcc
If VCC≈5V the internal LDO works in dropout with an output resistance of about 1Ω. The
maximum LDO output current is about 100mA and so the output voltage drop is 100mV, to
avoid this the LDO can be bypassed.
Figure 3.
5.4
Bypassing the LDO
Internal and external references
It is possible to set the internal/external reference and the switching frequency by setting the
proper voltage at the EAREF pin. The maximum value of the external reference depends on the
VCC: with VCC = 4V the clamp operates at about 2V (typ.), while with VCC greater than 5V the
maximum external reference is 2.5V (typ.).
●
VEAREF from 0% to 80% of VCCDR -> External reference/Fsw = 250KHz
●
VEAREF from 80% to 95% of VCCDR -> VREF = 0.6V/Fsw = 500KHz
●
VEAREF from 95% to 100% of VCCDR -> VREF = 0.6V/Fsw = 250KHz
Providing an external reference from 0V to 450mV the output voltage will be regulated but
some restrictions must be considered:
●
The minimum OVP threshold is set at 300mV;
●
The under-voltage-protection doesn't work;
To set the resistor divider it must be considered that a 100K pull-down resistor is integrated into
the device (see Figure 4.). Finally it must be taken into account that the voltage at the EAREF
pin is captured by the device at the start-up when VCC is about 4V.
11/32
L6725 - L6725A
Device description
5.5
Figure 4.
5.6
Error amplifier
Error amplifier reference
Soft start
When both VCC and VIN are above their turn-ON thresholds (VIN is monitored by the OCH pin)
the start-up phase takes place. Otherwise the SS pin is internally shorted to GND. At start-up, a
ramp is generated charging the external capacitor CSS with an internal current generator. The
initial value for this current is 35µA and charges the capacitor up to 0.5V. After that it becomes
10µA until the final charge value of approximately 4V (see Figure 5.).
Figure 5.
Soft-Start phase.
Vcc
Vin
4.2V
1.25V
t
Vss
4V
0.5V
t
12/32
L6725 - L6725A
Device description
L6725:The output of the error amplifier is clamped with this voltage (VSS) until it reaches the
programmed value.
L6725A:The reference of the error amplifier is clamped with this voltage (VSS) until it reaches
the programmed value. No switching activity is observable if VSS is lower than 0.5V and both
MOSFETs are OFF. When VSS is between 0.5V and 1.1V the low-side MOSFET is turned ON.
As VSS reaches 1.1V (i.e. the oscillator triangular wave inferior limit) even the high-side
MOSFET begins to switch and the output voltage starts to increase. During the soft-start phase
the current can’t be reversed in order to allow pre-biased start-up (see Figure 6. and Figure 7.).
Figure 6.
Start-up without pre-bias
LGate
VOUT
IL
VSS
Figure 7.
Start-up with pre-bias
LGate
VOUT
IL
VSS
If an over current is detected during the soft-start phase, the device provides a constantcurrent-protection. In this way, in case of short soft-start time and/or small inductor value and/or
high output capacitors value, the converter can start in any case, limiting the current
(Chapter 5.8: Monitoring and protections on page 14). The soft-start phase ends when Vss
reaches 3.5V. After that the over-current-protection triggers the HICCUP mode.
13/32
L6725 - L6725A
Device description
5.7
Driver section
The high-side and low-side drivers allow using different types of power MOSFETs (also multiple
MOSFETs to reduce the RDSON), maintaining fast switching transitions. The low-side driver is
supplied by VCCDR while the high-side driver is supplied by the BOOT pin. A predictive dead
time control avoids MOSFETs cross-conduction maintaining very short dead time duration in
the range of 20ns. The control monitors the phase node in order to sense the low-side body
diode recirculation. If the phase node voltage is less than a certain threshold (-350mV typ.)
during the dead time, it will be reduced in the next PWM cycle. The predictive dead time control
doesn’t work when the high-side body diode is conducting because the phase node doesn’t go
negative. This situation happens when the converter is sinking current for example and, in this
case, an adaptive dead time control operates.
5.8
Monitoring and protections
The output voltage is monitored by means of pin FB. The device provides over-voltageprotection: when the voltage sensed on FB pin reaches a value 20% (typ.) greater than the
reference the low-side driver is turned on as long as the over voltage is detected (see Figure 8).
Figure 8.
OVP
LGate
FB
The device realizes the over-current-protection (OCP) sensing the current both on the high-side
MOSFET(s) and the low-side MOSFET(s) and so 2 current limit thresholds can be set (see
OCH pin and OCL pin in Table 4: Pin functions):
●
Peak Current Limit
●
Valley Current Limit
The Peak Current Protection is active when the high-side MOSFET(s) is turned on, after a
masking time of 100ns. The valley-current-protection is enabled when the low-side MOSFET(s)
is turned on after a masking time of 500ns. If, when the soft-start phase is completed, an over
current event occurs during the on time (peak-current-protection) or during the off time (valleycurrent-protection) the device enters in HICCUP mode: the high-side and low-side MOSFET(s)
are turned off, the soft-start capacitor is discharged with a constant current of 10µA and when
the voltage at the SS pin reaches 0.5V the soft-start phase restarts (see Figure 9).
14/32
L6725 - L6725A
5.9
Figure 9.
Device description
Hiccup mode
Constant current and Hiccup Mode during an OCP.
VSS
VCOMP
IL
During the soft-start phase the OCP provides a constant-current-protection. If during the TON
the OCH comparator triggers an over current the high-side MOSFET(s) is immediately turned
OFF (after the masking time and the internal delay) and returned on at the next pwm cycle. The
limit of this protection is that the TON cannot be less than masking time plus propagation delay,
because during the masking time the peak-current-protection is disabled. In case of very hard
short circuit, even with this short TON, the current could escalate. The valley-current-protection
is very helpful in this case to limit the current. If during the off-time the OCL comparator triggers
an over current, the high-side MOSFET(s) is not turned on until the current is over the valleycurrent-limit. This implies that, if it is necessary, some pulses of the high-side MOSFET(s) will
be skipped, guaranteeing a maximum current due to the following formula:
I MAX = IVALLEY +
5.10
Vin − Vout
⋅ TON , MIN
L
(1)
Thermal shutdown
When the junction temperature reaches 150°C ±10°C the device enters in thermal shutdown.
Both MOSFETs are turned OFF and the soft-start capacitor is rapidly discharged with an
internal switch. The device does not restart until the junction temperature goes down to 120°C
and, in any case, until the voltage at the soft-start pin reaches 500mV.
15/32
L6725 - L6725A
Device description
5.11
Synchronization
The presence of many converters on the same board can generate beating frequency noise. To
avoid this it is important to make them operate at the same switching frequency. Moreover, a
phase shift between different modules helps to minimize the RMS current on the common input
capacitors. Figure 10. and Figure 11. shows the results of two modules in synchronization. Two
or more devices can be synchronized simply connecting together the SYNCH pins. The device
with the higher switching frequency will be the Master while the other one will be the Slave. The
Slave controller will increase its switching frequency reducing the ramp amplitude proportionally
and then the modulator gain will be increased.
Figure 10. Synchronization: PWM Signal
Figure 11. Synchronization: Inductor Currents
To avoid a huge variation of the modulator gain, the best way to synchronize two or more
devices is to make them work at the same switching frequency and, in any case, the switching
frequencies can differ for a maximum of 50% of the lowest one. If, during synchronization
between two (or more) L6725A, it's important to know in advance which the master is, it's timely
to set its switching frequency at least 15% higher than the slave. Using an external clock signal
(fEXT) to synchronize one or more devices that are working at a different switching frequency
(fSW) it is recommended to follow the below formula:
f SW ≤ f EXT ≤ 1,3 ⋅ f SW
The phase shift between master and slaves is approximately 180°.
16/32
L6725 - L6725A
5.12
Device description
Bootstrap anti-discharging system
This built-in system avoids that the voltage across the bootstrap capacitor becomes less than
3.3V. An internal comparator senses the voltage across the external bootstrap capacitor
keeping it charged, eventually turning-on the low-side MOSFET for approximately 200ns. If the
bootstrap capacitor is not enough charged the high-side MOSFET cannot be effectively turnedon and it will present a higher RDSON. In some cases the OCP can be also triggered. The
bootstrap capacitor can be discharged during the soft-start in case of very long soft-start time
and light loads. It's also possible to mention one application condition during which the
bootstrap capacitor can be discharged:
5.12.1 Fan's power supply
In many applications the FAN is a DC MOTOR driven by a voltage-mode DC/DC converter.
Often only the speed of the MOTOR is controlled by varying the voltage applied to the input
terminal and there's no control on the torque because the current is not directly controlled. In
order to vary the MOTOR speed the output voltage of the converter must be varied. The L6725
has a dedicated pin called EAREF (see the related section) that allows providing an external
reference to the non-inverting input of the error-amplifier.
In these applications the duty cycle depends on the MOTOR's speed and sometimes 100% has
to be set in order to go at the maximum speed. Unfortunately in these conditions the bootstrap
capacitor can not be recharged and the system cannot work properly. Some PWM controller
limits the maximum duty-cycle to 80-90% in order to keep the bootstrap cap charged but this
make worse the performance during the load transient. Thanks to the "bootstrap antidischarging system" the L6732 can work at 100% without any problem. The following picture
shows the device behaviour when input voltage is 5V and 100% is set by the external
reference.
Figure 12. 100% duty cycle operation
17/32
L6725 - L6725A
Application details
6
Application details
6.1
Inductor design
The inductance value is defined by a compromise between the transient response time, the
efficiency, the cost and the size. The inductor has to be calculated to sustain the output and the
input voltage variation to maintain the ripple current (ÄIL) between 20% and 30% of the
maximum output current. The inductance value can be calculated with the following
relationship:
L≅
Vin − Vout Vout
⋅
Fsw ⋅ ∆I L Vin
(2)
Where FSW is the switching frequency, VIN is the input voltage and VOUT is the output voltage.
Figure 13 shows the ripple current vs. the output voltage for different values of the inductor, with
VIN = 5V and VIN = 12V at a switching frequency of 500KHz.
INDUCT O R CURRE NT RIP P L
Figure 13. Inductor current ripple.
8
7
Vin=12V, L=1uH
6
5
4
Vin=12V, L=2uH
3
2
Vin=5V, L=500nH
1
Vin=5V, L=1.5uH
0
0
1
2
3
4
O UT P UT V O L T AG E (V )
Increasing the value of the inductance reduces the ripple current but, at the same time,
increases the converter response time to a load transient. If the compensation network is well
designed, during a load transient the device is able to set the duty cycle to 100% or to 0%.
When one of these conditions is reached, the response time is limited by the time required to
change the inductor current. During this time the output current is supplied by the output
capacitors. Minimizing the response time can minimize the output capacitor size.
18/32
L6725 - L6725A
6.2
Application details
Output capacitors
The output capacitors are basic components for the fast transient response of the power supply.
For example, during a positive load transient, they supply the current to the load until the
converter reacts. The controller recognizes immediately the load transient and sets the duty
cycle at 100%, but the current slope is limited by the inductor value. The output voltage has a
first drop due to the current variation inside the capacitor (neglecting the effect of the ESL):
∆Vout ESR = ∆Iout ⋅ ESR
(3)
Moreover, there is an additional drop due to the effective capacitor discharge that is given by:
∆VoutCOUT
∆Iout 2 ⋅ L
=
2 ⋅ Cout ⋅ (Vin, min⋅ D max − Vout )
(4)
Where DMAX is the maximum duty cycle value that in the L6725 is 100%. Usually the voltage
drop due to the ESR is the biggest one while the drop due to the capacitor discharge is almost
negligible. Moreover the ESR value also affects the voltage static ripple, that is:
∆Vout = ESR ⋅ ∆I L
6.3
(5)
Input capacitors
The input capacitors have to sustain the RMS current flowing through them, that is:
Irms = Iout ⋅ D ⋅ (1 − D)
(6)
Where D is the duty cycle. The equation reaches its maximum value, IOUT /2 with D = 0.5. The
losses in worst case are:
P = ESR ⋅ (0.5 ⋅ Iout ) 2
(7)
19/32
Application details
6.4
L6725 - L6725A
Compensation network
The loop is based on a voltage mode control (Figure 14). The output voltage is regulated to the
internal/external reference voltage and scaled by the external resistor divider. The error
amplifier output VCOMP is then compared with the oscillator triangular waveform to provide a
pulse-width modulated (PWM) with an amplitude of VIN at the PHASE node. This waveform is
filtered by the output filter. The modulator transfer function is the small signal transfer function
of VOUT/VCOMP. This function has a double pole at frequency FLC depending on the L-COUT
resonance and a zero at FESR depending on the output capacitor’s ESR. The DC Gain of the
modulator is simply the input voltage VIN divided by the peak-to-peak oscillator voltage: VOSC.
Figure 14. Compensation Network
The compensation network consists in the internal error amplifier, the impedance networks ZIN
(R3, R4 and C20) and ZFB (R5, C18 and C19). The compensation network has to provide a
closed loop transfer function with the highest 0dB crossing frequency to have fastest transient
response (but always lower than fSW/10) and the highest gain in DC conditions to minimize the
load regulation error. A stable control loop has a gain crossing the 0dB axis with -20dB/decade
slope and a phase margin greater than 45°. To locate poles and zeroes of the compensation
networks, the following suggestions may be used:
20/32
L6725 - L6725A
●
Application details
Modulator singularity frequencies:
ω LC =
●
●
1
L ⋅ Cout
(8)
ω ESR =
1
ESR ⋅ Cout
(9)
Compensation network singularity frequencies:
ω P1 =
1
(10)
⎛ C18 ⋅ C19 ⎞
⎟⎟
R5 ⋅ ⎜⎜
⎝ C18 + C19 ⎠
ωZ 1 =
1
R5 ⋅ C19
(12)
ωP 2 =
ωZ 2 =
1
R4 ⋅ C20
1
C20 ⋅ (R3 + R4 )
(11)
(13)
Compensation network design:
–
Put the gain R5/R3 in order to obtain the desired converter bandwidth:
ϖC =
R5 Vin
⋅
⋅ϖ LC (14)
R3 ∆Vosc
–
Place ωZ1 before the output filter resonance ωLC;
–
Place ωZ2 at the output filter resonance ωLC;
–
Place ωP1 at the output capacitor ESR zero ωESR;
–
Place ωP2 at one half of the switching frequency;
–
Check the loop gain considering the error amplifier open loop gain.
Figure 15. Asymptotic Bode plot of Converter's open loop gain
21/32
L6725 - L6725A
Demoboard
7
Demoboard
7.1
20A board description
L6725 demoboard realizes in a four layer PCB a step-down DC/DC converter and shows the
operation of the device in a general purpose application. The input voltage can range from 4.5V
to 14V and the output voltage is at 3.3V. The module can deliver an output current in excess of
20A. The switching frequency is set at 250kHz (controller free-running FBSWB) but it can be
set to 500kHz acting on the EAREF pin.
Figure 16. Demoboard schematic
VIN
R9
D1
J1
C11
C12-C13
C10
R5
VCCDR
GIN
R6
C9
BOOT
8
11
EAREF
J2
OCH
R11
5
7
3
HGATE
L1
Q4-6
EXT REF
6
C5
VCC
VCC
C8
R8
C7
GND
10
12
U1
L6725
15
PHASE
LGATE
VOUT
R10
R12
D3
C15
Q1-3
9
PGND
GOUT
SS
2
C4
4
OCL
1
16
VFB
COMP
R3
R7
R4
C2
C3
R2
22/32
C16-C19
R1
C1
L6725 - L6725A
Table 6.
Demoboard
Demoboard part list
Reference
Value
Manufacturer
Package
Supplier
R1
1kΩ
Neohm
SMD 0603
IFARCAD
R2
1kΩ
Neohm
SMD 0603
IFARCAD
R3
4K7
R4
2k7
Neohm
SMD 0603
IFARCAD
R5
0Ω
Neohm
SMD 0603
IFARCAD
R6
N.C.
Neohm
SMD 0603
IFARCAD
R7
2KΩ
Neohm
SMD 0603
IFARCAD
R8
10Ω
Neohm
SMD 0603
IFARCAD
R9
1KΩ
Neohm
SMD 0603
IFARCAD
R10
2.2Ω
Neohm
SMD 0603
IFARCAD
R11
2.2Ω
Neohm
SMD 0603
IFARCAD
R12
N.C.
Neohm
SMD 0603
IFARCAD
C1
4.7nF
Kemet
SMD 0603
IFARCAD
C2
47nF
Kemet
SMD 0603
IFARCAD
C3
1nF
Kemet
SMD 0603
IFARCAD
C4
100nF
Kemet
SMD 0603
IFARCAD
C5
100nF
Kemet
SMD 0603
IFARCAD
C6
N.C.
/
/
/
C7
100nF
Kemet
SMD 0603
IFARCAD
C8
4.7uF 20V
AVX
SMA6032
IFARCAD
C9
1nF
Kemet
SMD 0603
IFARCAD
C10
1uF
Kemet
SMD 0603
IFARCAD
C11
220nF
Kemet
SMD 0603
IFARCAD
C12-13
3X 15uF
/
/
ST (TDK)
C15
N.C.
/
/
/
C16-19
2X 330uF
/
/
ST (poscap)
L1
1.8uH
Panasonic
SMD
ST
D1
STPS1L30M
ST
DO216AA
ST
D3
N.C.
/
/
/
Q1-Q2
STS12NH3LL
ST
SO8
ST
Q4-Q5
STS25NH3LL
ST
SO8
ST
U1
L6725
ST
SO16N
ST
23/32
L6725 - L6725A
Demoboard
Table 7.
Other inductor manufacturer
Manufacturer
Series
Inductor Value (µH)
Saturation Current (A)
WURTH ELEKTRONIC
744318180
1.8
20
SUMIDA
CDEP134-2R7MC-H
2.7
15
EPCOS
HPI_13 T640
1.4
22
TDK
SPM12550T-1R0M220
1
22
TOKO
FDA1254
2.2
14
HCF1305-1R0
1.15
22
HC5-1R0
1.3
27
Series
Capacitor value(µF)
Rated voltage (V)
C4532X5R1E156M
15
25
C3225X5R0J107M
100
6.3
NIPPON CHEMI-CON
25PS100MJ12
100
25
PANASONIC
ECJ4YB0J107M
100
6.3
COILTRONICS
Table 8.
Other capacitor manufacturer
Manufacturer
TDK
Figure 17. Demoboard efficiency
Fs
F
w ==4500KHz
00K H z
SW
E F F IC IE N
95.00%
90.00%
VIN = 5V
85.00%
80.00%
VIN = 12V
75.00%
1
3
5
7
9
I o u t (A )
24/32
11
13
15
L6725 - L6725A
Demoboard
Figure 18. PCB Layout: top layer
Figure 19. PCB Layout: power ground layer
Figure 20. PCB Layout: signal-ground layer
25/32
L6725 - L6725A
Demoboard
7.2
5A board description
L6725 demoboard realizes in a two layer PCB a step-down DC/DC converter and shows the
operation of the device in a general purpose application. The input voltage can range from 4.5V
to 14V and the output voltage is at 3.3V. The module can deliver an output current in excess of
5A. The switching frequency is set at 250kHz (controller free-running FBSWB) but it can be set
to 500kHz acting on the EAREF pin. Compared to the 20A version, the only difference of this
board, compared to the first one, is the presence of a dual mosfet chip, for the High-side and
Low-side MOSFETS; besides R13 has been inserted between High side MOSFET Gate and
Phase pin; R15 has been inserted between Low side mosfet Gate and Pgnd pin.
Table 9.
26/32
Demoboard part list
Reference
Value
Manufacturer
Package
Supplier
R1
1kΩ
Neohm
SMD 0603
IFARCAD
R2
1kΩ
Neohm
SMD 0603
IFARCAD
R3
4K7
R4
2k7
Neohm
SMD 0603
IFARCAD
R5
0Ω
Neohm
SMD 0603
IFARCAD
R6
N.C.
Neohm
SMD 0603
IFARCAD
R7
4K99
Neohm
SMD 0603
IFARCAD
R8
10Ω
Neohm
SMD 0603
IFARCAD
R9
2K49
Neohm
SMD 0603
IFARCAD
R10
2.2Ω
Neohm
SMD 0603
IFARCAD
R11
2.2Ω
Neohm
SMD 0603
IFARCAD
R12
N.C.
Neohm
SMD 0603
IFARCAD
R13
N.C.
Neohm
SMD 0603
IFARCAD
R15
N.C.
Neohm
SMD 0603
IFARCAD
C1
4.7nF
Kemet
SMD 0603
IFARCAD
C2
47nF
Kemet
SMD 0603
IFARCAD
C3
1nF
Kemet
SMD 0603
IFARCAD
C4
100nF
Kemet
SMD 0603
IFARCAD
C5
100nF
Kemet
SMD 0603
IFARCAD
C6
N.C.
/
/
/
C7
100nF
Kemet
SMD 0603
IFARCAD
C8
4.7uF 20V
AVX
SMA6032
IFARCAD
C9
1nF
Kemet
SMD 0603
IFARCAD
C10
1uF
Kemet
SMD 0603
IFARCAD
C11
220nF
Kemet
SMD 0603
IFARCAD
C12-13
3X 10uF
/
/
ST (TDK)
L6725 - L6725A
Table 9.
Demoboard
Demoboard part list
Reference
Value
Manufacturer
Package
Supplier
C15
N.C.
/
/
/
C16-19
2X 330uF
/
/
ST (poscap)
L1
2,7uH
DO3316P-272HC
Coilcraft
SMD
ST
D1
STPS1L30M
ST
DO216AA
ST
D3
N.C.
/
/
/
Q1
STS8DNH3LL
(Dual Mosfet)
ST
SO8
ST
U1
L6725
ST
SO16N
ST
Figure 21. Demoboard efficiency
F sw =500K H z
Efficiency (%)
95
90
85
80
75
0,5
1
1,5
2
2,5
3
3,5
4
4,5
5
I o u t (A )
27/32
Demoboard
Figure 22. Demoboard layout
Figure 23. Demoboard layout
28/32
L6725 - L6725A
L6725 - L6725A
8
Package mechanical data
Package mechanical data
In order to meet environmental requirements, ST offers these devices in ECOPACK® packages.
These packages have a Lead-free second level interconnect . The category of second Level
Interconnect is marked on the package and on the inner box label, in compliance with JEDEC
Standard JESD97. The maximum ratings related to soldering conditions are also marked on
the inner box label. ECOPACK is an ST trademark. ECOPACK specifications are available at:
www.st.com.
29/32
L6725 - L6725A
Package mechanical data
Table 10.
SO16N mechanical data
mm
inch
Dim
Min
Typ
A
a1
Max
Min
Typ
1.75
0.1
0.069
0.25
a2
0.004
0.009
1.6
b
0.35
b1
0.19
C
0.063
0.46
0.014
0.25
0.007
0.5
c1
0.018
0.010
0.020
45°
(typ.)
D(1)
9.8
10
0.386
0.394
E
5.8
6.2
0.228
0.244
e
1.27
0.050
e3
8.89
0.350
(1)
3.8
4.0
0.150
0.157
G
4.60
5.30
0.181
0.208
L
0.4
1.27
0.150
0.050
F
M
S
0.62
0.024
8 °(max.)
1. "D" and "F" do not include mold flash or protrusions -Mold flash or protrusions shall not exceed 0.15mm (.006inc.)
Figure 24. Package dimensions
30/32
Max
L6725 - L6725A
9
Revision history
Revision history
Table 11.
Revision history
Date
Revision
Changes
20-Dec-2005
1
Initial release.
30-May-2006
2
New template, thermal data updated
26-Jun-2006
3
Note page 5 deleted
5-Oct-2006
4
Added new orderable L6725A, and 5A demoboard
28-Jun-2007
5
Extended operative range
31/32
L6725 - L6725A
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