L6727_10

L6727 Single phase PWM controller Feature ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ Flexible power supply from 5 V to 12 V Power conversion input as low as 1.5 V 1 % output voltage accuracy High-current integrated drivers Adjustable output voltage 0.8 V internal reference Simple voltage mode control loop Sensorless and programmable OCP across Low-side RdsON Oscillator internally fixed at 300 kHz Internal Soft-start LS-LESS to manage pre-bias start-up Disable function OV / UV protection FB disconnection protection SO-8 package SO-8 Description L6727 is a single-phase step-down controller with integrated high-current drivers that provides complete control logic, protections and reference voltage to realize in an easy and simple way general DC-DC converters by using a compact SO-8 package. Device flexibility allows managing conversions with power input VIN as low as 1.5 V and device supply voltage in the range of 5 V to 12 V. L6727 provides simple control loop with voltagemode error-amplifier. The integrated 0.8 V reference allows regulating output voltages with ±1 % accuracy over line and temperature variations. Oscillator is internally fixed to 300 kHz. L6727 provides programmable over current protection as well as over and under voltage protection. Current information is monitored across the low-side MOSFET RdsON saving the use of expensive and space-consuming sense resistors while output voltage is monitored through FB pin. FB disconnection protection prevents excessive and dangerous output voltages in case of floating FB pin. Applications ■ ■ ■ ■ ■ Subsystem power supply (MCH, IOCH, PCI...) Memory and termination supply CPU and DSP power supply Distributed power supply General DC / DC converters Table 1. Device summary Order codes L6727 SO-8 L6727TR Tape and reel Package Packaging Tube March 2010 Doc ID 12933 Rev 4 1/34 www.st.com 34 Contents L6727 Contents 1 Typical application circuit and block diagram . . . . . . . . . . . . . . . . . . . . 4 1.1 1.2 Application circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 2 Pins description and connection diagrams . . . . . . . . . . . . . . . . . . . . . . 5 2.1 2.2 Pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 3 Electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 3.1 3.2 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 4 5 Device description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Driver section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 5.1 Power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 6 Soft-start and disable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 6.1 6.2 Low-side-less start up (LSLess) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Enable / disable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 7 Overcurrent protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 7.1 Overcurrent threshold setting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 8 Output voltage monitor and protections . . . . . . . . . . . . . . . . . . . . . . . . 14 8.1 8.2 8.3 8.4 Undervoltage protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Overvoltage protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Feedback disconnection protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Undervoltage lock out . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 9 Application details . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 9.1 9.2 Output voltage selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Compensation network . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 2/34 Doc ID 12933 Rev 4 L6727 Contents 9.3 9.4 Layout guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Embedding L6727-based VRs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 10 Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 10.1 10.2 10.3 Output inductor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Output capacitors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Input capacitors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 11 20 A demonstration board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 11.1 Board description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 11.1.1 11.1.2 11.1.3 11.1.4 11.1.5 Power input (VIN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Power output (VOUT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 IC additional supply (VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Test points . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Demonstration board efficiency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 12 5 A demonstration board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 12.1 Board description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 12.1.1 12.1.2 12.1.3 12.1.4 12.1.5 Power input (VIN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Power iutput (VOUT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 IC additional supply (VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Test points . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Demonstration board efficiency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 13 14 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Doc ID 12933 Rev 4 3/34 Typical application circuit and block diagram L6727 1 1.1 Typical application circuit and block diagram Application circuit Figure 1. Typical application circuit VIN = 1.5V to 19V (**) D RD CBOOT 2 RgHS VCC = 5V to 12V CDEC ROCSET (*) 5 VCC 7 BOOT COMP / DIS / OC 1 CHF HS L CBULK CF CP RF L6727 UGATE 6 PHASE 8 Vout FB LGATE 4 RgLS LS RSN COUT ROS RFB GND 3 CSN LOAD L6727 Reference Schematic (*) ROCSET not to be connected when VCC > 5V (**) Up to 12V with Vcc > 5V 1.2 Block diagram Figure 2. Block diagram VCC CONTROL LOGIC & PROTECTIONS CURRENT READ & OCP Vout Monitor BOOT ADAPTIVE ANTI CROSS CONDUCTION HS IOCSET UGATE PHASE DISABLE PWM VCC 300 kHz OSCILLATOR + 0.8V LS LGATE GND L6727 COMP / DIS / OC ERROR AMPLIFIER 4/34 Doc ID 12933 Rev 4 FB L6727 Pins description and connection diagrams 2 Pins description and connection diagrams Figure 3. Pins connection (top view) BOOT UGATE GND LGATE 1 2 3 4 8 7 L6727 6 5 PHASE COMP / DIS / OC FB VCC 2.1 Pin descriptions Table 2. Pin # Pins descriptions Name Function HS driver supply. Connect through a capacitor (100 nF) to the floating node (LS-drain) pin and provide necessary bootstrap diode from VCC. HS driver output. Connect to HS MOSFET gate. All internal references, logic and drivers are connected to this pin. Connect to the PCB ground plane. LS driver output. Connect to LS MOSFET gate. Device and LS driver power supply. Operative range from 4.1 V to 13.2 V. Filter with at least 1μF MLCC to GND. Error Amplifier Inverting Input. Connect with a resistor RFB to the output regulated voltage. Additional resistor ROS to GND may be used to regulate voltages higher than the reference. 1 2 3 4 5 BOOT UGATE GND LGATE VCC 6 FB 7 COMP. Error amplifier output. Connect with an RF - CF // CP to FB to compensate the control-loop. DIS. The device can be disabled by forcing this pin lower than 0.5V(typ). To disable the device, the external pull-down need to overcome 10mA of COMP / DIS COMP output current for about 15 μs. Once disabled, COMP output current / OC drops to 20 μA. OC. Over current threshold set. Connect with an ROCSET resistor to VCC (ONLY IF VCC is supplied by 5 V bus) to program OC threshold. When VCC > 5V, ROCSET need to be not-connected. HS driver return path, current-reading and adaptive-dead-time monitor. Connect to the LS drain to sense RdsON drop to measure the output current. This pin is also used by the adaptive-dead-time control circuitry to monitor when HS MOSFET is OFF. 8 PHASE Doc ID 12933 Rev 4 5/34 Electrical specifications L6727 2.2 Thermal data Table 3. Symbol RthJA TMAX TSTG TJ Thermal data Parameter Thermal resistance junction to ambient (1) Maximum junction temperature Storage temperature range Junction temperature range Value 85 150 -40 to 150 -20 to 150 Unit °C/W °C °C °C 1. Measured with the component mounted on a 2S2P board in free air (6.7cm x 6.7cm, 35μm (P) and 17.5 μm (S) copper thickness). 3 3.1 Electrical specifications Absolute maximum ratings Table 4. Symbol VCC VBOOT to GND to PHASE to GND to PHASE to PHASE; t < 50 ns to GND to GND to GND to GND; t < 50 ns COMP to GND FB to GND Absolute maximum ratings Parameter Value -0.3 to 15 15 45 -0.3 to (VBOOT - VPHASE) + 0.3 -1 VBOOT + 0.3 -8 to 30 -0.3 to VCC + 0.3 -1 -0.3 to 7 -0.3 to 3.6 Unit V V VUGATE VPHASE VLGATE V V V V V 6/34 Doc ID 12933 Rev 4 L6727 Electrical specifications 3.2 Table 5. Symbol Electrical characteristics VCC = 12 V; TA = -20 °C to +85 °C, unless otherwise specified. Electrical characteristics Parameter Test conditions Min. Typ. Max. Unit Recommended operating conditions VCC VIN Device supply voltage See Figure 1 13.2 Conversion input voltage VCC < 7.0 V 19.0 V V 4.1 13.2 V Supply current and power-ON ICC IBOOT UVLO Hysteresis Oscillator 0 °C to +70 °C FSW ΔVOSC dMAX Reference Output voltage accuracy Error amplifier A0 GBWP SR IFB DIS DC gain(1) Gain-bandwidth Slew-rate (1) VCC supply current BOOT supply current VCC turn-ON UGATE and LGATE = OPEN UGATE = OPEN; PHASE to GND VCC rising 6 0.5 4.1 0.2 mA mA V V 270 250 300 300 1.5 330 350 kHz kHz V % Main oscillator accuracy PWM ramp amplitude Maximum duty cycle 80 VOUT = 0.8 V, TA = 0 °C to 70 °C VOUT = 0.8 V -1 -1.5 - 1 1.5 % % 120 product(1) 15 8 Sourced from FB COMP falling 0.43 100 0.5 dB MHz V/μs nA V Input bias current Disable threshold Gate drivers IUGATE RUGATE ILGATE RLGATE HS source current HS sink resistance LS source current LS sink resistance BOOT - PHASE = 5 V to 12 V BOOT - PHASE = 5 V to 12 V VCC = 5 V to 12 V VCC = 5 V to 12 V 1.5 1.1 1.5 0.65 A Ω A Ω Overcurrent protection IOCSET OCSET current source Sunk from COMP pin, before SS 55 60 65 μA Doc ID 12933 Rev 4 7/34 Electrical specifications Table 5. Symbol VCC_OC VOCTH L6727 Electrical characteristics (continued) Parameter OC Switch-over threshold Fixed OC threshold Test conditions VCC rising VPHASE to GND, VCC > VCC_OC Min. Typ. 8 -400 Max. Unit V mV Over and undervoltage protections OVP UVP OVP threshold UVP threshold FB rising FB falling 1 0.6 V V 1. Guaranteed by design, not subject to test. 8/34 Doc ID 12933 Rev 4 L6727 Device description 4 Device description L6727 is a single-phase PWM controller with embedded high-current drivers that provides complete control logic and protections to realize in an easy and simple way a general DCDC step-down converter. Designed to drive N-channel MOSFETs in a synchronous buck topology, with its high level of integration this 8-pin device allows reducing cost and size of the power supply solution. L6727 is designed to operate from a 5 V or 12 V supply bus. Thanks to the high precision 0.8V internal reference, the output voltage can be precisely regulated to as low as 0.8 V with ±1 % accuracy over line and temperature variations (between 0 °C and +70 °C). The switching frequency is internally set to 300 kHz. This device provides a simple control loop with a voltage-mode error-amplifier. The erroramplifier features a 15 MHz gain-bandwidth product and 8V/µs slew rate, allowing high regulator bandwidth for fast transient response. To avoid load damages, L6727 provides over current protection as well as over voltage, under voltage and feedback disconnection protection. When the device is supplied from 5 V, over current trip threshold is programmable by a simple resistor. Output current is monitored across Low-side MOSFET RdsON, saving the use of expensive and space-consuming sense resistor. Output voltage and feedback disconnection are monitored through FB pin. L6727 implements soft-start increasing the internal reference from 0 V to 0.8 V in 5.1 ms (typ) in closed loop regulation. Low-side-less feature allows the device to perform soft-start over pre-biased output avoiding high current return through the output inductor and dangerous negative spike at the load side. Doc ID 12933 Rev 4 9/34 Driver section L6727 5 Driver section The integrated high-current drivers allow using different types of power MOSFET (also multiple MOSFETs to reduce the equivalent RdsON), maintaining fast switching transition. The driver for the high-side MOSFET uses BOOT pin for supply and PHASE pin for return. The driver for low-side MOSFET uses the VCC pin for supply and GND pin for return. The controller embodies an anti-shoot-through and adaptive dead-time control to minimize low side body diode conduction time, maintaining good efficiency while saving the use of Schottky diode: ● ● to check high-side MOSFET turn off, PHASE pin is sensed. When the voltage at PHASE pin drops down, the low-side MOSFET gate drive is suddenly applied; to check low-side MOSFET turn off, LGATE pin is sensed. When the voltage at LGATE has fallen, the high-side MOSFET gate drive is suddenly applied. If the current flowing in the inductor is negative, voltage on PHASE pin will never drop. To allow the low-side MOSFET to turn-on even in this case, a watchdog controller is enabled: if the source of the high-side MOSFET doesn't drop, the low side MOSFET is switched on so allowing the negative current of the inductor to recirculate. This mechanism allows the system to regulate even if the current is negative. Power conversion input is flexible: 5 V, 12 V bus or any bus that allows the conversion (See maximum duty cycle limitation and recommended operating conditions, in Table 5) can be chosen freely. 5.1 Power dissipation L6727 embeds high current MOSFET drivers for both high side and low side MOSFETs: it is then important to consider the power that the device is going to dissipate in driving them in order to avoid overcoming the maximum junction operative temperature. Two main terms contribute in the device power dissipation: bias power and drivers' power. ● Device bias power (PDC) depends on the static consumption of the device through the supply pins and it is simply quantifiable as follow (assuming to supply HS and LS drivers with the same VCC of the device): P DC = V CC ⋅ ( I CC + I BOOT ) ● Drivers power is the power needed by the driver to continuously switch on and off the external MOSFETs; it is a function of the switching frequency and total gate charge of the selected MOSFETs. It can be quantified considering that the total power PSW dissipated to switch the MOSFETs (easy calculable) is dissipated by three main factors: external gate resistance (when present), intrinsic MOSFET resistance and intrinsic driver resistance. This last term is the important one to be determined to calculate the device power dissipation. The total power dissipated to switch the MOSFETs results: P SW = F SW ⋅ [ Q gHS ⋅ ( V BOOT – V PHASE ) + Q gLS ⋅ V CC ] where VBOOT - VPHASE is the voltage across the bootstrap capacitor. External gate resistors helps the device to dissipate the switching power since the same power PSW will be shared between the internal driver impedance and the external resistor resulting in a general cooling of the device. 10/34 Doc ID 12933 Rev 4 L6727 Soft-start and disable 6 Soft-start and disable L6727 implements a soft-start to smoothly charge the output filter avoiding high in-rush currents to be required from the input power supply. The device progressively increases the internal reference from 0 V to 0.8 V in about 5.1 ms, in closed loop regulation, gradually charging the output capacitors to the final regulation voltage. In the event of an overcurrent triggering during soft start, the over current logic will override the soft start sequence and will shut down both the high side and low side gates for the internal soft start residual time (up to 2048 clock cycles) plus 2048 clock cycles, then it will begin a new soft start. The device begins soft start phase only when VCC power supply is above UVLO threshold and overcurrent threshold setting phase has been completed. 6.1 Low-side-less start up (LSLess) In order to manage start up over pre-biased output, L6727 performs a special sequence in enabling LS driver to switch: during the soft-start phase, LS driver results disabled (LS = OFF) until HS starts to switch. This avoids the dangerous negative spike on the output voltage that can happen if starting over a pre-biased output. If the output voltage is pre-biased to a voltage lower than the programmed one, neither HS nor LS will turn on until the soft start ramp exceeds the output pre-bias voltage; then VOUT will ramp up from there, without any drop or current return. If the output voltage is pre-biased to a voltage higher than the programmed one, HS would never start to switch. In this case, at the end of soft start time, LS is enabled and discharges the output to the final regulation value. This particular feature of the device masks the LS turn-on only from the control loop point of view: protections by-pass LSLESS, turning ON the LS MOSFET in case of need. Figure 4. LSless startup (left) vs non-lsless startup (right) Doc ID 12933 Rev 4 11/34 Soft-start and disable L6727 6.2 Enable / disable The device can be disabled by externally pushing COMP / DIS pin under 0.5 V (typ). In disable condition HS and LS MOSFETs are turned off, and a 20 μA current is sourced from COMP / DIS pin. Setting free the pin, this current pulls it over the threshold and the device enables again performing a new SS. To disable the device, the external pull-down needs to overcome 10 mA of COMP output current for about 15 μs. Once disabled, COMP output current drops to 20μA. Figure 5. Start up sequence; VCC = 5V (Left) overcurrent hiccup (Right) 12/34 Doc ID 12933 Rev 4 L6727 Overcurrent protection 7 Overcurrent protection The overcurrent feature protects the converter from a shorted output or overload, by sensing the output current information across the low side MOSFET drain-source on-resistance, RdsON. This method reduces cost and enhances converter efficiency by avoiding the use of expensive and space-consuming sense resistors. The low side RdsON current sense is implemented by comparing the voltage at the PHASE node when LS MOSFET is turned on with the programmed OCP threshold voltage, internally held. If the monitored voltage drop (GND to PHASE) exceeds this threshold, an overcurrent event is detected. If two overcurrent events are detected in two consecutive switching cycles, the protection will be triggered and the device will turn off both LS and HS MOSFETs for 2048 clock cycles (plus internal SS remaining time, if triggered during a SS phase); then it will begin a new soft-start. If the overcurrent condition is not removed, the continuous fault will cause L6727 to go into a hiccup mode with a typical period of 13.6 ms (Figure 5), guaranteeing safe load protection and very low power dissipation. 7.1 Overcurrent threshold setting When supplied with VCC = 5 V, L6727 allows to easily program an overcurrent threshold ranging from 50 mV to 500 mV, simply by adding a resistor (ROCSET) between COMP and VCC. During a short period of time (5.5 ms - 6.5 ms) following the first enable (given VCC over UVLO threshold), an internal 60µA current (IOCSET) is sunk from COMP pin, determining a voltage drop across ROCSET. This voltage drop, differentially sensed between VCC and COMP, divided by a factor 3, will be sampled and internally held by the device as Over Current Threshold until next VCC cycling. Differential sensing versus VCC allows OCSET procedure to be fully independent from VIN rail. The OC setting procedure overall time length ranges from 5.5 ms to 6.5 ms, proportionally to the threshold being set. Connecting an ROCSET resistor between COMP and VCC, the programmed threshold will be: 1 I OCSET ⋅ R OCSET I OCth = -- ⋅ ------------------------------------------3 R dsON ROCSET values range from 2.5 kΩ to 25 kΩ. If the voltage drop across ROCSET is too low, the system will be very sensitive to start-up inrush current and noise. This can result in a continuous OCP triggering and hiccup mode. In this case, consider to increase ROCSET value. In case ROCSET is not connected (and VCC = 5 V), the device will set the maximum threshold. If the device is supplied with a VCC higher than 7 V, ROCSET must be not connected. In this case, as soon as VCC rises over VCC_OC (8 V typ.), L6727 switches OC threshold to 400mV (internally fixed value). See Figure 5 for OC threshold setting and soft start oscilloscope sample waveforms. Doc ID 12933 Rev 4 13/34 Output voltage monitor and protections L6727 8 Output voltage monitor and protections L6727 monitors the voltage at FB pin and compares it to internal reference voltage in order to provide Under Voltage and Over Voltage protections. 8.1 Undervoltage protection If the voltage at FB pin drops below UV threshold (0.6 V typ), the device turns off both HS and LS MOSFETs, waits for 2048 clock cycles and then performs a new soft start. If under voltage condition is not removed, the device enters a hiccup mode with a typical period of 13.6 ms. UVP is active from the end of soft start. 8.2 Overvoltage protection If the voltage at FB pin rises over OV threshold (1 V typ), over voltage protection turns off HS MOSFET and turns on LS MOSFET overriding PWM logic as long as over voltage is detected. OVP is always active with top priority as soon as over current threshold setting phase has been completed. 8.3 Feedback disconnection protection In order to provide load protection even if FB pin is not connected, a 100 nA bias current is always sourced from this pin. If FB pin is not connected, this current will permanently pull up FB over OVP threshold: thus LS will be latched on preventing output voltage from rising out of control. 8.4 Undervoltage lock out In order to avoid anomalous behaviors of the device when the supply voltage is too low to support its internal rails, UVLO is provided: the device will start up when VCC reaches UVLO upper threshold and will shutdown when VCC drops below UVLO lower threshold. The 4.1 V maximum UVLO upper threshold allows L6727 to be supplied from 5 V and 12 V busses in or-ing diode configuration. 14/34 Doc ID 12933 Rev 4 L6727 Application details 9 9.1 Application details Output voltage selection L6727 is capable to precisely regulate an output voltage as low as 0.8 V. In fact, the device comes with a fixed 0.8 V internal reference that guarantees the output regulated voltage to be within ±1 % tolerance over line and temperature variations between 0 °C and +70 °C (excluding output resistor divider tolerance, when present). Output voltage higher than 0.8 V can be easily achieved by adding a resistor ROS between FB pin and ground. Referring to Figure 1, the steady state DC output voltage will be: R FB V OUT = V REF ⋅ ⎛ 1 + ---------- ⎞ ⎝ R OS⎠ where VREF is 0.8V. 9.2 Compensation network The control loop showed in Figure 6 is a voltage mode control loop. The error amplifier is a voltage mode type. The output voltage is regulated to the internal reference (when present, offset resistor between FB node and GND can be neglected in control loop calculation). Error Amplifier output is compared to oscillator saw-tooth waveform to provide PWM signal to the driver section. PWM signal is then transferred to the switching node with VIN amplitude. This waveform is filtered by the output filter. The converter transfer function is the small signal transfer function between the output of the EA and VOUT. This function has a double pole at frequency FLC depending on the L-COUT resonance and a zero at FESR depending on the output capacitor ESR. The DC Gain of the modulator is simply the input voltage VIN divided by the peak-to-peak oscillator voltage ΔVOSC. The compensation network closes the loop joining VOUT and EA output with transfer function ideally equal to -ZF/ZFB. Figure 6. PWM control loop VIN OSC ΔV OSC _ + PWM COMPARATOR ERROR AMPLIFIER + _ L R COUT ESR V OUT VREF RFB CF CP RF CS ZF RS ZFB Doc ID 12933 Rev 4 15/34 Application details L6727 Compensation goal is to close the control loop assuring high DC regulation accuracy, good dynamic performances and stability. To achieve this, the overall loop needs high DC gain, high bandwidth and good phase margin. High DC gain is achieved giving an integrator shape to compensation network transfer function. Loop bandwidth (F0dB) can be fixed choosing the right RF/RFB ratio, however, for stability, it should not exceed FSW/2π. To achieve a good phase margin, the control loop gain has to cross 0dB axis with -20 dB/decade slope. As an example, Figure 7 shows an asymptotic bode plot of a type III compensation. Figure 7. Example of type III compensation. Gain [dB] open loop EA gain FZ1 FZ2 closed loop gain compensation gain open loop converter gain 0dB F0dB FLC FESR 20log (RF/RFB) 20log (VIN/ΔVOSC ) Log (Freq) FP1 FP2 ● Open loop converter singularities: a) b) 1 F LC = --------------------------------2 π L ⋅ C OUT 1 F ESR = ------------------------------------------2 π ⋅ C OUT ⋅ ESR ● Compensation Network singularities frequencies: a) b) c) 1 F Z1 = -----------------------------2 π ⋅ RF ⋅ CF 1 F Z2 = ---------------------------------------------------2 π ⋅ ( R FB + R S ) ⋅ C S 1 F P1 = ------------------------------------------------CF ⋅ CP ⎛ -------------------- ⎞ 2 π ⋅ RF ⋅ ⎝ C F + C P⎠ 1 F P2 = -----------------------------2 π ⋅ RS ⋅ CS d) 16/34 Doc ID 12933 Rev 4 L6727 Application details To place the poles and zeroes of the compensation network, the following suggestions may be followed: a) Set the gain RF/RFB in order to obtain the desired closed loop regulator bandwidth according to the approximated formula (suggested values for RFB range from 2 kΩ to 5 kΩ): F 0dB Δ V OSC RF ---------- = ------------ ⋅ -----------------F LC V IN R FB b) Place FZ1 below FLC (typically 0.5*FLC): 1 C F = ----------------------------π ⋅ R F ⋅ F LC c) Place FP1 at FESR: CF C P = ---------------------------------------------------------2 π ⋅ R F ⋅ C F ⋅ F ESR – 1 d) Place FZ2 at FLC and FP2 at half of the switching frequency: R FB R S = -------------------------F SW ----------------- – 1 2 ⋅ F LC 1 C S = -----------------------------π ⋅ R S ⋅ F SW e) f) Check that compensation network gain is lower than open loop EA gain; Estimate phase margin obtained (it should be greater than 45 °) and repeat, modifying parameters, if necessary. 9.3 Layout guidelines L6727 provides control functions and high current integrated drivers to implement highcurrent step-down DC-DC converters. In this kind of application, a good layout is very important. The first priority when placing components for these applications has to be reserved to the power section, minimizing the length of each connection and loop as much as possible. To minimize noise and voltage spikes (EMI and losses) power connections (highlighted in Figure 8) must be part of a power plane and anyway realized by wide and thick copper traces: loop must be anyway minimized. The critical components, i.e. the power MOSFETs, must be close one to the other. The use of multi-layer printed circuit board is recommended. The input capacitance (CIN), or at least a portion of the total capacitance needed, has to be placed close to the power section in order to eliminate the stray inductance generated by the copper traces. Low ESR and ESL capacitors are preferred, MLCC are suggested to be connected near the HS drain. Use proper VIAs number when power traces have to move between different planes on the PCB in order to reduce both parasitic resistance and inductance. Moreover, reproducing the Doc ID 12933 Rev 4 17/34 Application details L6727 same high-current trace on more than one PCB layer will reduce the parasitic resistance associated to that connection. Connect output bulk capacitors (COUT) as near as possible to the load, minimizing parasitic inductance and resistance associated to the copper trace, also adding extra decoupling capacitors along the way to the load when this results in being far from the bulk capacitors bank. Figure 8. Power connections (heavy lines) VIN UGATE PHASE CIN L L6727 LGATE GND COUT LOAD Gate traces and phase trace must be sized according to the driver RMS current delivered to the power MOSFET. The device robustness allows managing applications with the power section far from the controller without losing performances. Anyway, when possible, it is recommended to minimize the distance between controller and power section. See Figure 9 for drivers current paths. Small signal components and connections to critical nodes of the application, as well as bypass capacitors for the device supply, are also important. Locate bypass capacitor (VCC and Bootstrap capacitor) and loop compensation components as close to the device as practical. For over current programmability, place ROCSET close to the device and avoid leakage current paths on COMP / OC pin, since the internal current source is only 60μA. Systems that do not use Schottky diode in parallel to the Low-Side MOSFET might show big negative spikes on the phase pin. This spike must be limited within the absolute maximum ratings (for example, adding a gate resistor in series to HS MOSFET gate, or a phase resistor in series to PHASE pin), as well as the positive spike, but has an additional consequence: it causes the bootstrap capacitor to be over-charged. This extra-charge can cause, in the worst case condition of maximum input voltage and during particular transients, that boot-to-phase voltage overcomes the absolute maximum ratings also causing device failures. It is then suggested in this cases to limit this extra-charge by adding a small resistor in series to the bootstrap diode (RD in Figure 1). Figure 9. LS DRIVER VCC CGD RGATE LGATE CGS CDS RINT UGATE RPHASE PHASE CGS CDS RGATE RINT Drivers turn-on and turn-off paths LS MOSFET HS DRIVER BOOT CGD HS MOSFET GND 18/34 Doc ID 12933 Rev 4 L6727 Application details 9.4 Embedding L6727-based VRs When embedding the VR into the application, additional care must be taken since the whole VR is a switching DC/DC regulator and the most common system in which it has to work is a digital system such as MB or similar. In fact, latest MBs have become faster and more powerful: high speed data busses are more and more common and switching-induced noise produced by the VR can affect data integrity if additional layout guidelines are not followed. Few easy points must be considered mainly when routing traces in which switching high currents flow (switching high currents cause voltage spikes across the stray inductance of the traces causing noise that can affect the near traces): When reproducing high current path on internal layers, keep all layers the same size in order to avoid "surrounding" effects that increase noise coupling. Keep safe guard distance between high current switching VR traces and data busses, especially if high-speed data busses, to minimize noise coupling. Keep safe guard distance or filter properly when routing bias traces for I/O sub-systems that must walk near the VR. Possible causes of noise can be located in the PHASE connections, MOSFETs gate drive and Input voltage path (from input bulk capacitors and HS drain). Also GND connection must be considered if not insisting on a power ground plane. These connections must be carefully kept far away from noise-sensitive data busses. Since the generated noise is mainly due to the switching activity of the VR, noise emissions depend on how fast the current switches. To reduce noise emission levels, it is also possible, in addition to the previous guidelines, to reduce the current slope and thus to increase the switching times: this will cause, as a consequence of the higher switching time, an increase in switching losses that must be considered in the thermal design of the system. Doc ID 12933 Rev 4 19/34 Application information L6727 10 10.1 Application information Output inductor Inductor value is defined by a compromise between dynamic response, ripple, efficiency, cost and size. Usually, inductance is calculated to maintain inductor ripple current (ΔIL) between 20 % and 30 % of maximum output current. Given the switching frequency (FSW), the input voltage (VIN), the output voltage (VOUT) and the desired ripple current (ΔIL), inductance can be calculated as follows: V IN – V OUT V OUT L = ----------------------------- ⋅ -------------F SW ⋅ Δ I L V IN Figure 1 shows the ripple current vs. the output voltage for different inductance, with VIN = 5 V and VIN = 12 V. Increasing inductance reduces inductor ripple current (and output voltage ripple accordingly) but, at the same time, increases the converter response time to load transients. Higher inductance means that the inductor needs more time to change its current from initial to final value. Until the inductor has not finished its charging, the additional output current is supplied by output capacitors. Minimizing the response time lead to minimize the output capacitance required. If the compensation network is designed with high bandwidth, during an heavy load transient the device is able to saturate duty cycle (0 % or 80 %). When this condition is reached, the response time is limited only by the time required to charge the inductor. Figure 10. Inductor current ripple vs output voltage 20/34 Doc ID 12933 Rev 4 L6727 Application information 10.2 Output capacitors Output capacitors choice depends on the application constraints in point of output voltage ripple and output voltage deviation during a load transient. During steady-state conditions, the output voltage ripple is influenced by ESR and capacitance of the output capacitors as follows: Δ V OUT_ESR = Δ I L ⋅ ESR 1 Δ V OUT_C = Δ I L ⋅ -------------------------------------8 ⋅ C OUT ⋅ F SW Where ΔIL is the inductor current ripple. These contribution are not in phase, so total ripple will be lower than the sum of their moduli. Even ESL and board parasitic inductance can contribute significantly to output ripple. During a load variation, the output capacitors supply to the load the additional current or absorb the current in excess delivered by the inductor until converter reaction is completed. In fact, even if the controller react immediately to the load transient saturating the duty cycle to 80 % or 0 %, the current slew rate is limited by the inductance. At first approximation, output voltage drop, based on ESR and capacitor charge/discharge and considering an ideal load-step, can be estimated as follows: Δ V OUT_ESR = Δ I OUT ⋅ ESR L ⋅ Δ I OUT Δ V OUT_C = ------------------------------------2 ⋅ C OUT ⋅ Δ V L 2 Where ΔVL is the voltage applied to the inductor during the transient ( D MAX ⋅ VIN – V OUT for the load appliance or VOUT for the load removal). MLCC capacitors typically have low ESR to minimize the ripple but also have low capacitance that do not minimize the capacitive voltage deviation during load transient. On the contrary, electrolytic capacitors usually have higher capacitance to minimize capacitive voltage deviation during load transient, but also higher ESR value resulting in higher ripple voltage and resistive voltage drop. For these reasons, a mix between electrolytic and MLCC capacitor is usually suggested to minimize ripple as well as reducing voltage deviation in dynamic conditions. 10.3 Input capacitors The input capacitor bank is designed mainly to stand input rms current, which depends on output current (IOUT) and duty-cycle (D) for the regulation as follows: I rms = I OUT ⋅ D ⋅ ( 1 – D ) The equation reaches its maximum value, IOUT/2, when D = 0.5. Losses depend on input capacitor ESR: P = ESR ⋅ Irms 2 Doc ID 12933 Rev 4 21/34 20 A demonstration board L6727 11 20 A demonstration board L6727 demonstration board realizes on a four-layer PCB a step-down DC/DC converter and shows the operation of the device in a general purpose application. Input voltage can range from 5 V to 12 V bus (when VCC > 5 V, R6 need to be removed). Output voltage is programmed to 1.25 V. The voltage regulator can deliver up to 20 A output current. The switching frequency is 300 kHz. Figure 11. 20 A demonstration board (left) and components placement (right) Figure 12. 20 A demonstration board top (left) and bottom (right) layers 22/34 Doc ID 12933 Rev 4 L6727 Figure 13. 20 A demonstration board inner layers 20 A demonstration board Doc ID 12933 Rev 4 23/34 5 6 7 8 5 6 7 8 5 6 7 8 1 2 3 1 2 3 VCC PHASE 3.3 1uF VIN_POWER UGATE 4.7uF Q4 STD55NH2LL C11 C12 C13 3 4.7uF 4.7uF UGATE R3 2.2 PHASE HSG 1 2 HSD C38 BOOT 100nF C10 D1 1N4148 R2 VCC GND GNDCC GND 0 0 U1 0 PHASE 0 0 BOOT PHASE COMP FB 2 VCC LGATE R5 3 3 0 1 LSG1 Q5 STD90NH2LL 1 Q6 NC 5 LGATE 2 R4 1.8 6 FB 7 COMP 2.2 L2 2 T60-18 6Ts 1 8 1 L6726A/27 R17 BOOT UGATE 2 UGATE VOUT1 VOUT OUT C15 NC C16 NC C17 NC C18 2200uF C19 NC C20 NC C21 NC C22 NC GNDOUT1 GNDOUT GND VCC_PIN VCC 3.3 1uF R1 C14 3 GND Figure 14. 20 A demonstration board schematic VCC_PIN PHASE OUT COMP R6 12k R8 0 R14 R12 NC NC NC R13 3.9k C36 2.2k R9 R7 C24 FB Doc ID 12933 Rev 4 0 NC R15 LGATE 4 LGATE R18 NC 0 LSG2 0 C23 6.8nF 0 0 0 0 0 0 0 0 0 1 2 3 24/34 L1 PHASE 1 NC 2 NC HSD PHASE R16 0 C1 1800uF C4 HSG 4 LSG1 4 C5 C6 C7 C8 C9 C2 1800uF C3 NC Q1 NC Q2 NC NC NC NC NC NC OUT PHASE Q3 NC LSG2 4 VIN1 VIN_POWER GNDIN1 20 A demonstration board GNDIN_POWER 0 VCC 0 0 0 0 0 0 0 0 0 GND GND 0 COMP FB OUT C25 R10 NC R11 0 C37 NC 2200uF C26 NC C27 NC C28 NC C29 NC C30 NC C31 NC C32 NC C33 C33 NC C34 NC 33k 10nF C35 0 0 0 0 0 0 0 0 0 0 33pF 0 0 L6727 L6727 Table 6. Qty Capacitors 2 1 3 2 2 1 1 1 C1, C2 C10 C11 to C13 C14, C38 C18, C25 C23 C24 C35 20 A demonstration board 20 A demonstration board - bill of material Reference Description Package Electrolytic Cap 1800 μF 16 V Nippon chemi-con KZJ or KZG MLCC, 100 nF, 25 V, X7R MLCC, 4.7 μF, 16 V, X5R Murata GRM31CR61C475MA01 MLCC, 1 μF, 16 V, X7R Electrolytic Cap 2200 μF 6.3 V Nippon chemi-con KZJ or KZG MLCC, 6.8 nF, X7R MLCC, 10 nF, X7R MLCC, 33 pF, X7R Radial 10 x 25 mm SMD0603 SMD1206 SMD0805 Radial 10 x 20 mm SMD0603 Resistors 2 1 2 1 1 2 1 1 1 1 Inductor 1 L1 Inductor, 1.25 μH, T60-18, 6Turns Easymagnet AP106019006P-1R1M na R1, R2 R17 R5, R16 R3 R4 R11, R8 R9 R13 R7 R6 Resistor, 3R3, 1/16 W, 1 % SMD0603 Resistor, 2R2, 1/16 W, 1 % Resistor, 0R, 1/8 W, 1 % Resistor, 2R2, 1/8 W, 1 % Resistor, 1R8, 1/8 W, 1 % Resistor, 0R, 1/16 W, 1 % Resistor, 2K2, 1/16 W, 1 % Resistor, 3K9, 1/16 W, 1 % Resistor, 33K, 1/16 W, 1 % Resistor, 12K, 1/16 W, 1 % SMD0603 SMD0805 Active components 1 1 1 1 D1 Q5 Q6 U1 Diode, 1N4148 or BAT54 STD55NH2LL DPACK STD90NH2LL Controller, L6727 SO8 SOT23 Doc ID 12933 Rev 4 25/34 20 A demonstration board L6727 11.1 11.1.1 Board description Power input (VIN) This is the input voltage for the power conversion. The high-side MOSFET drain is connected to this input. Supply must be compliant with VIN recommended operating conditions and capacitors rating. If VIN voltage is compliant also to VCC range listed in recommended operating conditions, it can supply also the device through R16 resistor. When VCC > 5 V, R6 need to be removed. 11.1.2 Power output (VOUT) This is the output voltage of the power conversion. The output voltage is programmed to 1.25 V. It can be changed by replacing R13. R6 allows to adjust OCP threshold when VCC = 5 V. 11.1.3 IC additional supply (VCC) The controller can be supplied separately from the power conversion through VCC input. In this case, to separate VCC from VIN, R16 resistor must be removed. When VCC > 5 V, R6 need to be removed. 11.1.4 Test points The following test points are provided to allow easy probing of important signals: – – – – – COMP: output of the error amplifier; FB: inverting input of the error amplifier; PH: Phase pin of the device; LG: Low-Side gate pin of the device; UG: High-Side gate pin of the device. 11.1.5 Demonstration board efficiency Figure 15. 20 A demonstration board efficiency 26/34 Doc ID 12933 Rev 4 L6727 5 A demonstration board 12 5 A demonstration board L6727 demonstration board realizes on a two-layer PCB a step-down DC/DC converter and shows the operation of the device in a general-purpose low-current application. Input voltage can range from 5 V to 12 V bus. Output voltage is programmed at 1.25 V. The application can deliver an output current in excess of 5 A. The switching frequency is 300 kHz. Figure 16. 5 A demonstration board (left) and components placement (right) Figure 17. 5 A demonstration board top (left) and bottom (right) layers Doc ID 12933 Rev 4 27/34 GND Figure 18. 5 A demonstration board schematic COMP FB FB FB OUT Doc ID 12933 Rev 4 PHASE 2 PHASE PIN 2 78 R4 1.8 R17 3.3 PHASE L2 2.2uH 3 L3 NC U1 LGATE 8 LGATE COMP FB VCC_PIN R1 3.3 VCC 1 2 LSG1 7 6 5 PHASE PIN R5 0 U5A STS9D8NH3LL C23 6.8nF BOOT 1 BOOT UGATE GND LGATE/OC L6727 VCC FB COMP PHASE 2 3 LGATE 4 UGATE L6727 28/34 VIN1 VIN_POWER GNDIN1 GNDIN_POWER 5 A demonstration board 0 R16 0 VCC BAT54 VCC VCC GND GNDCC GND HSD 56 VIN_POWER C38 1uF BOOT D1 R2 3.3 0 UGATE R3 UGATE 4 HSG1 0 U5B STS9D8NH3LL 0 C10 100nF C12 10uF C51 10uF 0 1 1 OUT 0 VOUT1 VOUT C18 NC GNDOUT1 GNDOUT 0 0 0 R18 NC 0 0 C14 1uF C29 NC OUT OUT C30 330uF 0 COMP FB R7 4.7k 0 C24 68nF R8 R9 2.2k OUT C39 22uF C40 NC C29A NC C35 220pF R10 NC R13 3.9K R14 R14 15 C36 6.8nF 0 0 0 0 0 L6727 L6727 Table 7. Qty Capacitors 2 1 2 1 1 2 1 1 Resistors 1 4 3 1 1 1 1 Inductor 1 L1 Inductor, 2.20 μH, Wurth 744324220LF R4 R3, R5, R8, R16 R1, R2, R17 R14 R9 R13 R7 Resistor, 1R8, 1/8 W, 1 % Resistor, 0R, 1/16 W, 1 % Resistor, 3R3, 1/16 W, 1 % Resistor, 15R, 1/16 W, 1 % Resistor, 2K2, 1/16 W, 1 % Resistor, 3K9, 1/16 W, 1 % Resistor, 4K7, 1/16 W, 1 % C12, C51 C10 C14, C38 C39 C30 C23, C36 C24 C35 5 A demonstration board 5 A demonstration board - bill of material Reference Description Package 10 μF, 25 V, X5R Murata GRM31CR61E106KA12 MLCC, 100 nF, 25 V, X7R MLCC, 1 μF, 16 V, X7R MLCC, 22 μF, 6.3 V, X5R Murata GRM31CR60J226ME19 330 μF, 6.3 V, 9 mΩ Sanyo 6TPF330M9L MLCC, 6.8 nF, X7R MLCC, 68 nF, X7R MLCC, 220 pF, X7R SMD1206 SMD0603 SMD0805 SMD1206 SMD7343 SMD0603 SMD0805 SMD0603 SMD0603 na Active Components 1 1 1 D1 Q5 U1 Diode, BAT54 Mosfet, STS9D8NH3LL Controller, L6727 SOT23 SO8 SO8 Doc ID 12933 Rev 4 29/34 5 A demonstration board L6727 12.1 12.1.1 Board description Power input (VIN) This is the input voltage for the power conversion. The high-side MOSFET drain is connected to this input. Supply must be compliant with VIN recommended operating conditions and capacitors rating. If VIN voltage is compliant also to VCC range listed in recommended operating conditions, it can supply also the device through R16 resistor. 12.1.2 Power iutput (VOUT) This is the output voltage of the power conversion. The output voltage is programmed to 1.25 V. It can be changed by replacing R13. 12.1.3 IC additional supply (VCC) The controller can be supplied separately from the power conversion through VCC input. In this case, to separate VCC from VIN, R16 resistor must be removed. 12.1.4 Test points The following test points are provided to allow easy probing of important signals: – – – – – COMP: output of the error amplifier; FB: inverting input of the error amplifier; PH: Phase pin of the device; LG: Low-Side gate pin of the device; UG: High-Side gate pin of the device. 12.1.5 Demonstration board efficiency Figure 19. 5 A demonstration board efficiency 30/34 Doc ID 12933 Rev 4 L6727 Package mechanical data 13 Package mechanical data In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK® packages, depending on their level of environmental compliance. ECOPACK® specifications, grade definitions and product status are available at: www.st.com. ECOPACK is an ST trademark. Table 8. Dim. Min A 1.35 Typ Max 1.75 Min 0.053 Typ Max 0.069 SO-8 mechanical data mm. inch A1 A2 B C D (1) 0.10 1.10 0.33 0.19 4.80 3.80 1.27 5.80 0.25 0.40 0.25 1.65 0.51 0.25 5.00 4.00 0.004 0.043 0.013 0.007 0.189 0.15 0.050 0.010 0.065 0.020 0.010 0.197 0.157 E e H h L k ddd 6.20 0.50 1.27 0.228 0.010 0.016 0.244 0.020 0.050 0° (min.), 8° (max.) 0.10 0.004 1. D and F does not include mold flash or protrusions. Mold flash or potrusions shall not exceed 0.15mm (.006inch) per side. Doc ID 12933 Rev 4 31/34 Package mechanical data Figure 20. Package dimensions L6727 32/34 Doc ID 12933 Rev 4 L6727 Revision history 14 Revision history Table 9. Date 04-Dec-2006 28-Feb-2007 06-Jun-2007 Revision history Revision 1 2 3 Initial release. Updated VOCTH values in Table 5 on page 7 Updated Figure 1: Typical application circuit on page 4, Table 3 and Table 4 on page 6 Added Section 10: Application information on page 20, Section 11: 20 A demonstration board on page 22, Section 12: 5 A demonstration board on page 27 Updated: Table 5 on page 7 Changes 23-Mar-2010 4 Doc ID 12933 Rev 4 33/34 L6727 Please Read Carefully: Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any time, without notice. All ST products are sold pursuant to ST’s terms and conditions of sale. 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