L6740L

L6740L Hybrid controller (4+1) for AMD SVID and PVID processors Features ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ Hybrid controller: compatible with PVI and SVI CPUs Dual controller: 2 to 4 scalable phases for CPU CORE, 1 Phase for NB Dual-Edge asynchronous architecture with LTB technologyTM PSI management to increase efficiency in Light-Load conditions Dual Over-Current protection: Average and per-Phase Load indicator (CORE section) Voltage positioning Dual remote sense Adjustable independent reference offset Feedback disconnection protection Programmable OV protection Oscillator internally fixed at 150kHz externally adjustable LSLess startup to manage Pre-biased output Flexible driver support HTQFP48 package HTQFP48 Description L6740L is a hybrid CPU Power Supply Controller compatible with both Parallel (PVI) and Serial (SVI) protocols for AMD Processors. The device embeds two independent control loops for the CPU core and the integrated NB, each one with its own set of protections. L6740L is able to work in Single-Plane mode, addressing only the CORE Section, according to the parallel DAC codification. When in Dual-Plane mode, it is compatible with the AMD SVI specification addressing the CPU and NB voltages according to the SVI bus commands. The Dual-Edge Asynchronous Architecture is optimized by LTB technologyTM allowing fast loadtransient response minimizing the output capacitor and reducing the total BOM cost. PSI management allows the device to selectively turn-off phases when the CPU is in low-power states increasing the over-all efficiency. Fast protection against load over current is provided for both the Sections. Furthermore, feedback disconnection protection prevents from damaging the load in case of misconnections in the system board.. Applications ■ Hybrid High-Current VRM / VRD for Desktop / Server / Workstation / IPC CPUs supporting PVI and SVI interface High-density DC / DC converters ■ Table 1. Device summary Order codes Package HTQFP48 HTQFP48 Packaging Tube Tape and reel L6740L L6740LTR August 2007 Rev 2 1/44 www.st.com 1 Contents L6740L Contents 1 Typical application circuit and block diagram . . . . . . . . . . . . . . . . . . . . 4 1.1 1.2 Application circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2 Pins description and connection diagrams . . . . . . . . . . . . . . . . . . . . . . 8 2.1 2.2 Pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 3 Electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 3.1 3.2 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 4 5 Device description and operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Hybrid CPU support and CPU_TYPE detection . . . . . . . . . . . . . . . . . . 16 5.1 5.2 5.3 5.4 PVI - parallel interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 PVI start-up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 SVI - serial interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 SVI start-up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 5.4.1 5.4.2 5.4.3 5.4.4 5.4.5 Set VID command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 PWROK de-assertion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 PSI_L and efficiency optimization at light-load. . . . . . . . . . . . . . . . . . . . 21 HiZ management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Hardware jumper override - V_FIX . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 6 Output voltage positioning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 6.1 6.2 6.3 6.4 6.5 6.6 6.7 CORE section - Phase # programming . . . . . . . . . . . . . . . . . . . . . . . . . . 24 CORE section - Current reading and current sharing loop . . . . . . . . . . . 24 CORE section - Load-line and load-indicator (Optional) . . . . . . . . . . . . . 25 CORE section - Offset (Optional) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 NB section - Current reading . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 NB section - Load-line and load-indicator (Optional) . . . . . . . . . . . . . . . . 27 NB section - Offset (Optional) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 2/44 L6740L Contents 6.8 6.9 6.10 NB section - Maximum Duty-Cycle limitation . . . . . . . . . . . . . . . . . . . . . . 28 On-The-Fly VID transitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Soft-start . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 6.10.1 LS-Less Start-up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 7 Output voltage monitoring and protections . . . . . . . . . . . . . . . . . . . . . 31 7.1 7.2 7.3 7.4 Programmable over voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Feedback disconnection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 PWRGOOD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Over-current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 7.4.1 7.4.2 CORE section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 NB section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 8 9 Main oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 System control loop compensation . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 9.1 Compensation network guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 10 11 LTB technology™ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Layout guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 11.1 11.2 Power components and connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 Small signal components and connections . . . . . . . . . . . . . . . . . . . . . . . 41 12 13 TQFP48 mechanical data & package dimensions . . . . . . . . . . . . . . . . 42 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 3/44 Typical application circuit and block diagram L6740L 1 1.1 Figure 1. Typical application circuit and block diagram Application circuit Typical 4+1 application circuit LIN CDEC CBULK_IN 2 1 VCC PVCC* BOOT CHF VIN 41 PWRGOOD 37 PWROK 38 EN 35 VID0 36 VID1 40 VID2/SVD 39 VID3/SVC 25 VID4 ROVP 26 VID5 10 OVP / V_FIX ROSC 27 OSC / FLT 8 OS 29 NB_OS 11 LTB_GAIN 12 PSI_L 3 CF COMP L6741/3 ST L6740L Hybrid PVID / SVID Controller (**) GND VCC PWM1 PWM2 PWM3 PWM4 NB_PWM OC_PHASE 48 47 46 45 44 21 ROC_TH PWM UGATE HS1 L1 EN* PHASE R PVI / SVID Bus GND LGATE LS1 28 ROC_AVG OC_AVG / LI 13 CS1+ CS1- 14 CS2+ 15 CDEC RG VCC PVCC* BOOT RG CHF RG C CS2- 16 CS3+ 17 CS3- 18 CS4+ 19 L6741/3 RLTBG PWM RG UGATE HS2 L2 CS4- 20 NB_ISEN 23 EN* PHASE R RISEN FBG VSEN NB_VSEN 7 6 31 GND LGATE LS2 RF 5 4 9 RFB CLTB DROOP C NB_FBG 30 NB_COMP NB_DROOP FB LTB NB_FB ENDRV 43 NB_ENDRV 42 CDEC VCC PVCC* BOOT CHF RLTB 34 32 33 L6741/3 CF_NB RF_NB RFB_NB PWM UGATE HS3 L3 EN* PHASE R GND LGATE LS3 C CDEC_NB CBULK_NB VCC PVCC* BOOT CDEC VCC PVCC* BOOT CHF CHF_NB L6741/3 HSNB LNB UGATE L6741/3 PWM PWM UGATE HS4 L4 PHASE EN* EN* PHASE R LSNB LGATE GND GND LGATE LS4 C PVI / SVID AM2 CPU CORE COUT_NB CMLCC_NB NB CMLCC COUT SVID / PVID Interface (*) PVCC Only applies to L6741; EN Only applies to L6743. See related DS for further details (**) Pin not listed to be considered as Not Connected ST L6740L (4+1) Reference Schematic 4/44 L6740L Typical application circuit and block diagram Figure 2. Typical 3+1 application circuit LIN CDEC CBULK_IN 2 1 VCC PVCC* BOOT CHF VIN 41 PWRGOOD 37 PWROK 38 EN 35 VID0 36 VID1 40 VID2/SVD 39 VID3/SVC 25 VID4 ROVP 26 VID5 10 OVP / V_FIX ROSC 27 OSC / FLT 8 RLTBG OS L6741/3 ST L6740L Hybrid PVID / SVID Controller (**) GND VCC PWM1 PWM2 PWM3 PWM4 NB_PWM 48 47 46 45 44 21 ROC_TH PWM UGATE HS1 L1 EN* PHASE R PVI / SVID Bus GND LGATE LS1 OC_PHASE 28 ROC_AVG OC_AVG / LI 13 CS1+ CS1- 14 CS2+ 15 CDEC RG VCC PVCC* BOOT RG CHF RG C CS2- 16 CS3+ 17 29 NB_OS 11 LTB_GAIN 12 PSI_L 3 COMP CF CS3- 18 CS4+ 19 L6741/3 PWM RG UGATE HS2 L2 CS4- 20 NB_ISEN 23 EN* PHASE R RISEN FBG VSEN NB_VSEN 7 6 31 GND LGATE LS2 RF 5 4 9 RFB CLTB DROOP C NB_FBG 30 NB_COMP NB_DROOP FB LTB NB_FB ENDRV 43 NB_ENDRV 42 CDEC VCC PVCC* BOOT CHF RLTB 34 32 33 L6741/3 CF_NB RF_NB RFB_NB PWM UGATE HS3 L3 EN* PHASE R GND LGATE LS3 C CDEC_NB CBULK_NB VCC PVCC* BOOT CHF_NB HSNB LNB UGATE L6741/3 PWM PHASE EN* LSNB LGATE GND PVI / SVID AM2 CPU CORE COUT_NB CMLCC_NB NB CMLCC COUT SVID / PVID Interface (*) PVCC Only applies to L6741; EN Only applies to L6743. See related DS for further details (**) Pin not listed to be considered as Not Connected ST L6740L (3+1) Reference Schematic 5/44 Typical application circuit and block diagram L6740L Figure 3. Typical 2+1 application circuit LIN CDEC CBULK_IN 2 1 VCC PVCC* BOOT CHF VIN 41 PWRGOOD 37 PWROK 38 EN 35 VID0 36 VID1 40 VID2/SVD 39 VID3/SVC 25 VID4 ROVP 26 VID5 10 OVP / V_FIX ROSC 27 OSC / FLT 8 RLTBG OS L6741/3 ST L6740L Hybrid PVID / SVID Controller (**) GND VCC PWM1 PWM2 PWM3 PWM4 NB_PWM 48 47 46 45 44 21 ROC_TH PWM UGATE HS1 L1 EN* PHASE R PVI / SVID Bus GND LGATE LS1 OC_PHASE 28 ROC_AVG OC_AVG / LI 13 CS1+ CS1- 14 CS2+ 15 CDEC RG VCC PVCC* BOOT RG CHF RG C CS2- 16 CS3+ 17 29 NB_OS 11 LTB_GAIN 12 PSI_L 3 CF COMP CS3- 18 CS4+ 19 L6741/3 PWM RG UGATE HS2 L2 CS4- 20 NB_ISEN 23 EN* PHASE R RISEN FBG VSEN NB_VSEN 7 6 31 GND LGATE LS2 RF 5 4 9 RFB CLTB DROOP C NB_FBG 30 NB_COMP NB_DROOP 32 FB LTB RLTB 34 CF_NB RF_NB NB_FB ENDRV 43 NB_ENDRV 42 33 RFB_NB CDEC_NB CBULK_NB VCC PVCC* BOOT CHF_NB HSNB LNB UGATE L6741/3 PWM PHASE EN* LSNB LGATE GND PVI / SVID AM2 CPU CORE COUT_NB CMLCC_NB NB CMLCC COUT SVID / PVID Interface (*) PVCC Only applies to L6741; EN Only applies to L6743. See related DS for further details (**) Pin not listed to be considered as Not Connected ST L6740L (2+1) Reference Schematic 6/44 L6740L Typical application circuit and block diagram 1.2 Figure 4. OC_PHASE Block diagram Block diagram OC_AVG / LI V_FIX / OVP VID0 VID1 VID2 / SVD VID3 / SVC VID4 VID5 EN PWROK PWRGOOD LTB LTB_GAIN NB_PWM NB_PWM NB - TOT CURRENT ENDRV NB_ENDRV OSC INB_OS CS1+ CS1CS2+ CS2CS3+ CS3CS4+ CS4- IDROOP 11 µA NB_ISEN PSI_L DIFFERENTIAL CURRENT SENSE AMD SVI / PVI FLEXIBLE INTERFACE NB CURR SENSE 1.24V OFFSET CURRENT BALANCE CORE_REF & NB_REF NB_OS NB_COMP ERROR AMPLIFIER PWM1 PWM1 DUAL CHANNEL OSCILLATOR (4+1) Σ INB_OS L6740L CONTROL LOGIC PWM2 PWM2 INB_DROOP 64k PWM3 PWM3 Σ CS1CORE - TOT CURRENT 30µA IDROOP IOS IOS 64k 50µA +INB_OS 64k 64k REMOTE BUFFER Σ NB_FB NB_DROOP OUTPUT VOLTAGE MONITOR AND PROTECTION MANAGEMENT NB_FBG NB_VSEN PWM4 PWM4 OSC Σ 64k OSC VCC 1.24V REMOTE BUFFER 64k ENDRV 64k 64k VCORE_REF NB_REF (from SVI/PVI decoding) NB_ENDRV ENDRV NB_ENDRV VCC SGND OFFSET ERROR AMPLIFIER SGND FB DROOP COMP FBG VSEN OS 7/44 Pins description and connection diagrams L6740L 2 Pins description and connection diagrams Figure 5. Pins connection (Top View) OC_AVG / LI NB_DROOP NB_COMP OSC / FLT NB_VSEN NB_FBG NB_OS NB_FB VID1 VID0 VID5 PWROK EN SVC SVD PWRGOOD NB_ENDRV ENDRV NB_PWM PWM4 PWM3 PWM2 PWM1 36 35 34 33 32 31 30 29 28 27 26 25 37 24 38 39 40 41 42 43 44 45 46 47 48 1 VCC VID4 N.C. NB_ISEN N.C. OC_PHASE CS4CS4+ CS3CS3+ CS2CS2+ CS1CS1+ 23 22 21 20 L6740L 19 18 17 16 15 14 13 2 GND 3 COMP 4 FB 5 DROOP 6 VSEN 7 FBG 8 OS 9 10 11 12 LTB OVP/V_FIX LTB_GAIN PSI_L 2.1 Pin descriptions Table 2. Pin# 1 2 Pin description Name VCC SGND Function Device power supply. Operative voltage is 12V ±15%. Filter with 1µF MLCC to SGND. All the internal references are referred to this pin. Connect to the PCB Signal Ground. Error amplifier output. Connect with an RF - CF to FB. The CORE section or the device cannot be disabled by grounding this pin. Error amplifier inverting input. Connect with a resistor RFB to VSEN and with an RF - CF to COMP. Offset current programmed by OS is sunk through this pin. A current proportional to the total current read is sourced from this pin according to the Current Reading Gain. Short to FB to implement Droop Function, if not used, short to SGND. Output voltage monitor. It manages OVP and UVP protections and PWRGOOD. Connect to the positive side of the load for remote sensing. See Section 7 for details. 3 COMP 4 CORE SECTION FB 5 DROOP 6 VSEN 8/44 L6740L Table 2. Pin# Pins description and connection diagrams Pin description (continued) Name Function Remote ground sense. Connect to the negative side of the load for remote sensing. See Section 9 for proper layout of this connection. Offset programming pin. Internally set to 1.24V. Connecting a ROS resistor to SGND allows to set a current that is mirrored into FB pin in order to program a positive offset according to the selected RFB. Short to SGND to disable the function. See Section 6.4 for details. LTB TechnologyTM Input pin. Connect through an RLTB - CLTB network to the regulated voltage (CORE Section) to detect load transient. See Section 10 for details. 7 CORE SECTION FBG 8 OS 9 LTB 10 OVP. Over Voltage Programming Pin. Internally pulled-up to 3.3V by 11µA. Connect to SGND through a ROVP resistor and filter with 10nF (typ) to set a fixed voltage according to the ROVP resistor. If floating it will program 3.3V threshold. See Section 7 for details. OVP / V_FIX V_FIX - Hardware override. Short to SGND to enter VFIX mode (WARNING: this condition overrides any code programmed on the VIDx lines). In this case, the device will use SVI inputs as static VIDs and OVP threshold will be set to 1.8V. See Section 5.4.5 for details. LTB TechnologyTM gain pin. Connect to SGND through a resistor RLTBGAIN to program the LTB Gain. See Section 10 for details. Power Saving Indicator (SVI Mode). Open-drain Input/Output pin. See Section 5.4.3 for details. Channel 1 Current Sense Positive Input. Connect through an R-C filter to the phase-side of the channel 1 inductor. See Section 9 for proper layout of this connection. Channel 1 Current Sense Negative Input. Connect through a RG resistor to the output-side of the channel inductor. See Section 9 for proper layout of this connection. Channel 2 Current Sense Positive Input. Connect through an R-C filter to the phase-side of the channel 2 inductor. See Section 9 for proper layout of this connection. Channel 2 Current Sense Negative Input. Connect through a RG resistor to the output-side of the channel inductor. See Section 9 for proper layout of this connection. Channel 3 Current Sense Positive Input. Connect through an R-C filter to the phase-side of the channel 3 inductor. When working at 2 phase, directly connect to Vout_CORE. See Section 9 for proper layout of this connection. Channel 3 Current Sense Negative Input. Connect through a RG resistor to the output-side of the channel inductor. When working at 2 phase, connect through RG to CS3+. See Section 9 for proper layout of this connection. CORE SECTION 12 CORE SECTION 11 LTB_GAIN PSI_L 13 CS1+ 14 CS1- 15 CS2+ 16 CS2- 17 CS3+ 18 CS3- 9/44 Pins description and connection diagrams Table 2. Pin# L6740L Pin description (continued) Name Function Channel 4 Current Sense Positive Input. Connect through an R-C filter to the phase-side of the channel 4 inductor. When working at 2 or 3 phase, directly connect to Vout_CORE. See Section 9 for proper layout of this connection. Channel 4 Current Sense Negative Input. Connect through a RG resistor to the output-side of the channel inductor. When working at 2 or 3 phase, connect through RG to CS4+. See Section 9 for proper layout of this connection. 19 CORE SECTION CS4+ 20 CS4- 21 22 NB SECTION Per-Phase Over Current (CORE Section). OC_PHASE Internally set to 1.24V, connecting to SGND with a resistor ROC_TH it programs the OC threshold per-phase. See Section 7.4.1 for details. NC Not internally connected. NB Current Sense Pin. Used for NB voltage positioning and NB_OCP. Connect through a resistor RISEN to the relative LS Drain. See Section 7.4 for details. Not internally connected. 23 NB_ISEN 24 PVI INTERFACE NC 25, 26 Voltage IDentification Pins. VID4, VID5 Internally pulled-low by 10µA, they are used to program the output voltage. Used only in PVI-Mode, ignored when in SVI-Mode.See Section 5 for details. OSC: It allows programming the switching frequency FSW of both Sections. Switching frequency can be increased according to the resistor ROSC connected from the pin to. SGND with a gain of 6.8kHz/µA (see Section 8 for details). If floating, the switching frequency is 150kHz per phase. FLT: The pin is forced high (3.3V) in case of an OV / UV fault. To recover from this condition, cycle VCC or the EN pin. See Section 7 for details. Average Over Current and Load Indicator Pin. A current proportional to the current delivered by the CORE Section (a copy of the DROOP current) is sourced through this pin. The Average-OC threshold is programmed by connecting a resistor ROC_AVG to SGND. When the generated voltage crosses the OC_AVG threshold (VOC_AVGTH = 2.5V Typ) the device latches with all mosfets OFF (to recover, cycle VCC or the EN pin). A load indicator with 2.5V end-of-scale is then implemented. See Section 7.4.1 for details. Offset Programming Pin. Internally set to 1.24V, connecting a ROS_NB resistor to SGND allows setting a current that is mirrored into NB_FB pin in order to program a positive offset according to the selected RFB_NB. Short to SGND to disable the function. See Section 6.7 for details. Remote Ground Sense. Connect to the negative side of the load to perform remote sense. See Section 9 for proper layout of this connection. 27 OSC / FLT CORE SECTION NB SECTION 28 OC_AVG / LI 29 NB_OS 30 NB_FBG 10/44 L6740L Table 2. Pin# Pins description and connection diagrams Pin description (continued) Name Function NB output voltage monitor. It manages OVP and UVP protections and PWRGOOD. Connect to the positive side of the NB load to perform remote sensing. See Section 9 for proper layout of this connection. 31 NB_VSEN 32 NB SECTION A current proportional to the total current read by the NB section is sourced through this pin according to the Current Reading Gain NB_DROOP (RISEN). Short to NB_FB to implement Droop Function or connect to SGND through a resistor and filter with 1nF capacitor to implement NB LOAD Indicator. If not used, short to SGND. NB error amplifier inverting input. Connect with a resistor RFB_NB to NB_VSEN and with an RF_NB - CF_NB to NB_COMP. Offset current programmed by NB_OS is sunk through this pin. Error amplifier output. Connect with an RF_NB - CF_NB to NB_FB. The NB Section or the device cannot be disabled by grounding this pin. 33 NB_FB 34 NB_COMP SVI / PVI INTERFACE 35, 36 Voltage IDentification Pins. Internally pulled-low by 10µA, they are used to program the output VID0, VID1 voltage. VID1 is monitored on the EN pin rising-edge to define the operative mode of the controller (SVI or PVI). When in SVI Mode, VID0 is ignored. See Section 5 for details. System-wide Power Good Input (SVI Mode). Internally pulled-low by 10µA. When low, the device will decode the two SVI bits (SVC, SVD) to determine the Pre-PWROK Metal VID (default condition when pin is floating). When high, the device will actively run the SVI protocol. Pre-PWROK Metal VID are latched after EN is asserted and re-used in case of PWROK de-assertion. Latch is reset by VCC or EN cycle. VR Enable. Internally pulled-up to 3.3V by 10µA. Pull-low to disable the device. When set free, the device immediately checks for the VID1 status to determine the SVI / PVI protocol to be adopted and configures itself accordingly. See Section 5 for details. 37 PWROK 38 EN 39 SVI / PVI INTERFACE 41 Voltage IDentification Pin - SVI Clock Pin. SVC / VID3 Internally pulled-low by 10µA, it is used to program the output voltage. When in SVI-Mode, it is considered as Serial-VID-Data (Input / Open Drain Output). See Section 5 for details. Voltage IDentification Pins - SVI Data Pin. SVD / VID2 Internally pulled-low by 10µA, it is used to program the output voltage. When in SVI-Mode, it is considered as Serial-VID-Data (Input / Open Drain Output). See Section 5 for details. VCORE and NB Power Good. It is an open-drain output set free after SS as long as both the voltage PWRGOOD planes are within specifications. Pull-up to 3.3V (typ) or lower, if not used it can be left floating. When in PVI Mode, it monitors the CORE Section only. 40 11/44 Pins description and connection diagrams Table 2. Pin# NB SECTION L6740L Pin description (continued) Name Function 42 External driver enable. Open Drain output used to control NB Section external driver status: NB_ENDRV pulled-low to manage HiZ conditions or pulled-high to enable the driver. Pull up to 3.3V (typ) or lower. When in PVI Mode, NB Section is always kept in HiZ. External Driver enable. Open Drain output used to control CORE Section external driver status: pulled-low to manage HiZ conditions or pulled-high to enable the driver. Pull up to 3.3V (typ) or lower. PWM output. Connect to external driver PWM input. The device is able to manage HiZ status by setting the pin floating. When in PVI Mode, NB Section is kept in HiZ. See Section 5.4.4 for details about HiZ management. PWM outputs. Connect to external drivers PWM inputs. The device is able to manage HiZ status by setting the pins floating. By shorting to SGND PWM4 or PWM3 and PWM4, it is possible to program the CORE section to work at 3 or 2 phase respectively. See Section 5.4.4 for details about HiZ management. Thermal pad connects the Silicon substrate and makes good thermal contact with the PCB. Connect to the PGND plane. 43 CORE SECTION NB SECTION CORE SECTION ENDRV 44 NB_PWM 45 to 48 PWM1 to PWM4 Thermal pad 2.2 Thermal data Table 3. Symbol RthJA RthJC TMAX TSTG TJ Thermal data Parameter Thermal resistance junction to ambient (Device soldered on 2s2p PC Board) Thermal resistance junction to case Maximum junction temperature Storage temperature range Junction temperature range Value 40 1 150 -40 to 150 0 to 125 Unit °C/W °C/W °C °C °C 12/44 L6740L Electrical specifications 3 3.1 Electrical specifications Absolute maximum ratings Table 4. Symbol VCC to PGND All other Pins to PGNDx Absolute maximum ratings Parameter Value 15 -0.3 to 3.6 Unit V V 3.2 Table 5. Symbol Electrical characteristics Electrical characteristics (VCC=12V±15%, TJ = 0°C to 70°C unless otherwise specified). Parameter Test conditions Min. Typ. Max. Unit Supply current and power-ON ICC UVLOVCC Oscillator Main oscillator accuracy FSW ∆VOSC FAULT dMAX_NB Oscillator adjustability PWM ramp amplitude Voltage at Pin OSC NB duty-cycle limit ROSC = 27kΩ CORE and NB section OVP, UVP latch active INB_DROOP = 0µA INB_DROOP = 35µA 3 80 40 135 380 150 465 2 3.6 165 550 kHz kHz V V % % VCC supply current VCC Turn-ON VCC Turn-OFF VCC rising VCC falling 7 20 9 mA V V PVI / SVI interface Input high EN, PWROK Input low Pull-up current Pull-down current VID2,/SVD VID3/SVC SVD VID0 to VID5 V_FIX Input high Input low Voltage low (ACK) Input high Input low Pull-down current Entering V_FIX mode EN Pin PWORK Pin (SVI Mode) (SVI Mode) ISINK = -5mA (PVI mode) (PVI mode) 10 0.90 1.3 0.80 0.95 0.65 250 10 10 2 0.80 V V µA µA V V mV V V µA V 13/44 Electrical specifications Table 5. Symbol PSI_L L6740L Electrical characteristics (continued) (VCC=12V±15%, TJ = 0°C to 70°C unless otherwise specified). Parameter Voltage Low Test conditions ISINK = -5mA Min. Typ. Max. 250 Unit mV Voltage positioning (CORE and NB Section) CORE Output voltage accuracy NB OFFSET bias voltage OS, NB_OS OFFSET current range OFFSET - IFB accuracy DROOP DROOP accuracy NB_DROOP A0 SR EA DC gain Slew rate COMP, NB_COMP to SGND = 10pF IOS = 0 to 250µA IDROOP = 0 to 140µA; OS = OFF INB_DROOP = 0 to 35µA; OS = OFF VSEN to VCORE; FBG to GNDCORE NBVSEN to VNB; NBFBG to GNDFB IOS = 0 to 250µA -8 -10 1.190 0 -15 -9 -4 100 20 1.24 8 10 1.290 250 15 9 4 mV mV V µA % µA µA dB V/µs PWM outputs (CORE and NB Section) PWMx, NB_PWM IPWMx Output high Output low Test current I = -5mA I = 1mA I = -1mA 10 0.4 3 3.6 0.2 V V µA V ENDRV, Output low NB_ENDRV Protections Over voltage protection OVP Bias current OV programmability UVP PWRGOOD Voltage low IVSEN-DISC VFB-DISC FBG DISC VSEN disconnection Under voltage protection PGOOD threshold V_FIX Mode (V_FIX = SGND); VSEN, NB_VSEN Rising 1.720 7 1.800 11 1.800 -400 -250 1.880 15 1.870 -330 -200 0.4 V µA V mV mV V µA µA ROVP = 180kΩ VSEN, NB_VSEN Falling; wrt Ref. VSEN, NB_VSEN Falling; wrt Ref IPWRGOOD = -4mA Sourced from NB_VSEN; OS = OFF Sunk from VSEN; OS = OFF 1.730 -470 -300 50 30 500 350 1.200 2.430 -11 32 37.5 600 450 1.240 2.500 700 550 1.280 2.570 11 43 FB disconnection FBG disconnection CORE - VCS- Rising, above VSEN EA NI input wrt VID CORE section; bias voltage CORE section mV mV V V µA µA OC_PHASE Per-phase OC kVOC_AVGTH kIOC_AVGTH IOCTH_NB OC threshold Average OC IDROOP = 0 to 140µA; OS = OFF NB section 14/44 L6740L Device description and operation 4 Device description and operation L6740L is a hybrid CPU Power Supply Controller compatible with both Parallel (PVI) and Serial (SVI) protocols for AMD K8 - Second Generation Processors. The device provides complete control logic and protections for a high-performance step-down DC-DC voltage regulator, optimized for advanced microprocessor power supply supporting both PVI and SVI communication. It embeds two independent controllers for CPU CORE and the integrated NB, each one with its own set of protections. L6740L is able to detect which kind of CPU is connected in order to configure itself to work as a Single-Plane PVI controller or Dual-Plane SVI controller. The Controller performs a single-phase control for the NB Section and a programmable 2-to4 phase control for the CORE Section featuring Dual-Edge non-Latched architecture: this allows fast load-transient response optimizing the output filter consequently reducing the total BOM cost. Further reduction can be achieved by enabling LTB Technology(TM). NB phase (when enabled) will be automatically phase-shifted with respect to the CORE phases in order to reduce the total input rms current amount. PSI_L Flag is sent to the VR through the SVI bus. The controller monitors this flag and selctively modifies the phase number in order to optimize the system efficiency when the CPU enters low-power states. This causes the over-all efficiency to be maximized at light loads so reducing losses and system power consumption. Both sections feature programmable Over-Voltage protection and adjustable constant OverCurrent protection. Voltage positioning (LL) is possible thanks to an accurate fully-differential current-sense across the main inductors for the CORE Section and thanks to the loss-less current sense across Low-Side MOSFET RdsON for the NB section. In both cases, LL may be disabled and the generated current information may be used to implement a Load Indicator function. L6740L features dual remote sensing for the regulated outputs (CORE and NB) in order to recover from PCB voltage drops also protecting the load from possible feedback network disconnections. LSLess start-up function allows the controller to manage pre-biased start-up avoiding dangerous current return through the main inductors as well as negative undershoot on the output voltage if the output filter is still charged before start-up. L6740L also supports V_FIX mode for system debugging: in this particular configuration the SVI bus is used as a static bus configuring 4 operative voltages for both the sections and ignoring any serial-VID command. When working in PVI mode, the device features On-the-Fly VID management: VID code is continuously sampled and the reference update according to the variation detected, L6740L is available in TQFP48 Package. 15/44 Hybrid CPU support and CPU_TYPE detection L6740L 5 Hybrid CPU support and CPU_TYPE detection L6740L is able to detect the type of the CPU-core connected and to configure itself accordingly. At system Start-up, on the rising-edge of the EN signal, the device monitors the status of VID1 and configures the PVI mode (VID1 = 1) or SVI mode (VID1 = 0). When in PVI mode, L6740L uses the information available on the VID[0: 5] bus to address the CORE Section output voltage according to Table 6. NB Section is kept in HiZ mode. When in SVI mode, L6740L ignores the information available on VID0, VID4 and VID5 and uses VID2 and VID3 as a SVI bus addressing the CORE and NB Sections according to the SVI protocol. Caution: To avoid any risk of errors in CPU type detection (i.e. detecting SVI CPU when PVI CPU is installed on the socket and viceversa), it is reccomended to carefully control the start-up sequencing of the system hosting L6740L in order to ensure than on the EN rising-edge, VID1 is in valid and correct state. 5.1 PVI - parallel interface PVI is a 6-bit-wide parallel interface used to address the CORE Section reference. According to the selected code, the device sets the CORE Section reference and regulates its output voltage as reported into Table 6. NB Section is always kept in HiZ; no activity is performed on this section. Furthermore, PWROK information is ignored as well since the signal only applies to the SVI protocol. 5.2 PVI start-up Once the PVI mode has been detected, the device uses the whole code available on the VID[0:5] lines to define the reference for the CORE section. NB Section is kept in HiZ. SoftStart to the programmed reference is performed regardless of the state of PWROK. See Section 6.10 for details about Soft-Start. Figure 6. System start-up: SVI (to Metal-VID; left) and PVI (right) 16/44 L6740L Table 6. Hybrid CPU support and CPU_TYPE detection Voltage identifications (VID) codes for PVI mode Output Output VID5 VID4 VID3 VID2 VID1 VID0 voltage voltage 1.5500 1.5250 1.5000 1.4750 1.4500 1.4250 1.4000 1.3750 1.3500 1.3250 1.3000 1.2750 1.2500 1.2250 1.2000 1.1750 1.1500 1.1250 1.1000 1.0750 1.0500 1.0250 1.0000 0.9750 0.9500 0.9250 0.9000 0.8750 0.8500 0.8250 0.8000 0.7750 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0.7625 0.7500 0.7375 0.7250 0.7125 0.7000 0.6875 0.6750 0.6625 0.6500 0.6375 0.6250 0.6125 0.6000 0.5875 0.5750 0.5625 0.5500 0.5375 0.5250 0.5125 0.5000 0.4875 0.4750 0.4625 0.4500 0.4375 0.4250 0.4125 0.4000 0.3875 0.3750 VID5 VID4 VID3 VID2 VID1 VID0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 17/44 Hybrid CPU support and CPU_TYPE detection L6740L 5.3 SVI - serial interface SVI is a two wire, Clock and Data, bus that connects a single master (CPU) to one slave (L6740L). The master initiates and terminates SVI transactions and drives the clock, SVC, and the data, SVD, during a transaction. The slave receives the SVI transactions and acts accordingly. SVI wire protocol is based on fast-mode I2C. SVI interface also considers two additional signal needed to manage the system start-up. These signals are EN and PWROK. The device return a PWRGOOD signal if the output voltages are in regulation. 5.4 SVI start-up Once the SVI mode has been detected on the EN rising-edge, L6740L checks for the status of the two serial VID pins, SVC and SVD, and stores this value as the Pre-PWROK Metal VID. The controller initiate a soft-start phase regulating both CORE and NB voltage planes to the voltage level prescribed by the Pre-PWROK Metal VID. See Table 7 for details about Pre-PWROK Metal VID codifications. The stored Pre-PWROK Metal VID value are re-used in any case of PWROK de-assertion. After bringing the output rails into regulation, the controller asserts the PWRGOOD signal and waits for PWROK to be asserted. Until PWROK is asserted, the Controller regulates to the Pre-PWROK Metal VID ignoring any commands coming from the SVI interface. After PWROK is asserted, the processor has initialized the serial VID interface and L6740L waits for commands from the CPU to move the voltage planes from the Pre-PWROK Metal VID values to the operative VID values. As long as PWROK remains asserted, the controller will react to any command issued through the SVI interface according to SVI Protocol. See Section 6.10 for details about Soft-Start. Table 7. SVC 0 0 1 1 V_FIX mode and MetalVID Output voltage [V] SVD Pre-PWROK Metal VID 0 1 0 1 1.1V 1.0V 0.9V 0.8V V_FIX Mode 1.4V 1.2V 1.0V 0.8V 5.4.1 Set VID command The Set VID Command is defined as the command sequence that the CPU issues on the SVI bus to modify the voltage level of the CORE Section and/or the NB Section. During a Set VID Command, the processor sends the start (START) sequence followed by the address of the Section which the Set VID Command applies. The processor then sends the write (WRITE) bit. After the write bit, the Voltage Regulator (VR) sends the acknowledge (ACK) bit. The processor then sends the VID bits code during the data phase. The VR sends the acknowledge (ACK) bit after the data phase. Finally, the processor sends the stop (STOP) sequence. After the VR has detected the stop, it performs an On-the-Fly VID 18/44 L6740L Hybrid CPU support and CPU_TYPE detection transition for the addressed section(s) or, more in general, react to the sent command accordingly. Refer to Figure 7, Table 8 and Table 9 for details about the Set VID Command. L6740L is able to manage individual power OFF for both the Sections. The CPU may issue a serial VID command to power OFF or power ON one Section while the other one remains powered. In this case, the PWRGOOD signal remains asserted. Figure 7. SVI communications - Send byte START SLAVE ADDRESSING + W ACK DATA PHASE ACK STOP SVC 6 5 4 3 0 7 6 0 SVD 110b START ACK ACK Slave Addressing (7 Clocks) WRITE ACK (1Ck) (1Ck) Data Phase (8 Clocks) ACK (1Ck) STOP BUS DRIVEN BY L6740L BUS DRIVEN BY MASTER (CPU) Table 8. bits SVI send byte - Address and data phase description Description Address phase 6:4 3 2 1 0 Data phase 7 6:0 PSI_L Flag (Active low).When asserted, the VR is allowed to enter Power-Saving mode. See Section 5.4.3. VID Code. See Table 9. Always 110b. Not Applicable, ignored. Not Applicable, ignored. CORE Section(1). If set then the following data byte contains the VID code for CORE Section. NB Section(1). If set then the following data byte contains the VID code for NB Section. 1. Assertion in both bit 1 and 0 will address the VID code to both CORE and NB simultaneously. 19/44 Hybrid CPU support and CPU_TYPE detection L6740L Table 9. SVI [6:0] 000_0000 000_0001 000_0010 000_0011 000_0100 000_0101 000_0110 000_0111 000_1000 000_1001 000_1010 000_1011 000_1100 000_1101 000_1110 000_1111 001_0000 001_0001 001_0010 001_0011 001_0100 001_0101 001_0110 001_0111 001_1000 001_1001 001_1010 001_1011 001_1100 001_1101 001_1110 001_1111 Data phase - Serial VID codes. Output voltage 1.5500 1.5375 1.5250 1.5125 1.5000 1.4875 1.4750 1.4625 1.4500 1.4375 1.4250 1.4125 1.4000 1.3875 1.3750 1.3625 1.3500 1.3375 1.3250 1.3125 1.3000 1.2875 1.2750 1.2625 1.2500 1.2375 1.2250 1.2125 1.2000 1.1875 1.1750 1.1625 SVI [6:0] 010_0000 010_0001 010_0010 010_0011 010_0100 010_0101 010_0110 010_0111 010_1000 010_1001 010_1010 010_1011 010_1100 010_1101 010_1110 010_1111 011_0000 011_0001 011_0010 011_0011 011_0100 011_0101 011_0110 011_0111 011_1000 011_1001 011_1010 011_1011 011_1100 011_1101 011_1110 011_1111 Output voltage 1.1500 1.1375 1.1250 1.1125 1.1000 1.0875 1.0750 1.0625 1.0500 1.0375 1.0250 1.0125 1.0000 0.9875 0.9750 0.9625 0.9500 0.9375 0.9250 0.9125 0.9000 0.8875 0.8750 0.8625 0.8500 0.8375 0.8250 0.8125 0.8000 0.7875 0.7750 0.7625 SVI [6:0] 100_0000 100_0001 100_0010 100_0011 100_0100 100_0101 100_0110 100_0111 100_1000 100_1001 100_1010 100_1011 100_1100 100_1101 100_1110 100_1111 101_0000 101_0001 101_0010 101_0011 101_0100 101_0101 101_0110 101_0111 101_1000 101_1001 101_1010 101_1011 101_1100 101_1101 101_1110 101_1111 Output voltage 0.7500 0.7375 0.7250 0.7125 0.7000 0.6875 0.6750 0.6625 0.6500 0.6375 0.6250 0.6125 0.6000 0.5875 0.5750 0.5625 0.5500 0.5375 0.5250 0.5125 0.5000 0.4875 0.4750 0.4625 0.4500 0.4375 0.4250 0.4125 0.4000 0.3875 0.3750 0.3625 SVI [6:0] 110_0000 110_0001 110_0010 110_0011 110_0100 110_0101 110_0110 110_0111 110_1000 110_1001 110_1010 110_1011 110_1100 110_1101 110_1110 110_1111 111_0000 111_0001 111_0010 111_0011 111_0100 111_0101 111_0110 111_0111 111_1000 111_1001 111_1010 111_1011 111_1100 111_1101 111_1110 111_1111 Output voltage 0.3500 0.3375 0.3250 0.3125 0.3000 0.2875 0.2750 0.2625 0.2500 0.2375 0.2250 0.2125 0.2000 0.1875 0.1750 0.1625 0.1500 0.1375 0.1250 0.1125 0.1000 0.0875 0.0750 0.0625 0.0500 0.0375 0.0250 0.0125 OFF OFF OFF OFF 20/44 L6740L Hybrid CPU support and CPU_TYPE detection 5.4.2 PWROK de-assertion Anytime PWROK de-asserts while EN is asserted, the controller uses the previously stored Pre-PWROK Metal VID and regulates all the planes to that level performing an On-the-Fly transition to that level. PWRGOOD is treated appropriately being de-asserted in case the Pre-PWROK Metal VID voltage is out of the initial voltage specifications. 5.4.3 PSI_L and efficiency optimization at light-load. PSI_L is an active-low flag (i.e. low logic level when asserted) that can be set by the CPU to allow the VR to enter Power-Saving mode to maximize the system efficiency when in lightload conditions. The status of the flag is communicated to the controller through the SVI bus and it is reported on the PSI_L pin (open-drain). The controller monitors the PSI_L pin also to define the PSI Strategy, that is the action performed by the controller when PSI_L is asserted. According to Table 10, by programming different voltage divider on PSI_L, it is possible to configure the device to disable one or two phases while PSI_L is asserted. The device can also be configured to take no action so phase number will not change after PSI_L assertion. In case the phase number is changed, the device will disable one or two phases starting from the highest one (i.e. if working at 3 phases, phase 3 will be disabled in case of 1 phase reduction; phase 2 and 3 in case of 2phase reduction). To disable Phases, the controller will set HiZ on the related PWM and re-configure internal phase-shift to maintain the interleaving. Furthermore, the internal current-sharing will be adjusted to consider the phase number reduction. ENDRV will remain asserted. When PSI_L is de-asserted, the device will return to the original configuration. Start-up is performed with all the configured phases enabled. In case of On-the-Fly VID transitions, the device will maintain the phase configuration set before. PSI Strategy (i.e. the voltage across PSI_L) is read and stored when PWRGOOD is asserted at the end of the Soft-Start phase. The phase number management is affected by the external driver selected. ● If the external driver features the EN function, PSI_L can be tied directly to the EN of the drivers of the phases that will be disabled. Furthermore, in case the desired strategy is to work in single phase when 4phases are configured, PSI_L can be tied also to the EN of the driver connected to Phase2 (apparently, from 4phases the max reduction would be to 2phase min.) in order to disable also this phase during low-power mode. ● If the external driver manages HiZ through the PWM input, PSI_L will be connected only to the external divider used to set the strategy. The system can be down-graded to single-phase only if configured for three phases. Since PSI_L can be used to enable some of the external drivers connected, the status of the pin is the logic AND between the PSI_L Flag and the status of the ENDRV pin: if the controller wants to disable the external drivers pulling low ENDRV (because of protections or simply for start-up synchronization) also PSI_L will be tied low. NB Section is not impacted by PSI_L status change. Figure 8 shows an example of the efficiency improvement that can be achieved by enabling the PSI management. 21/44 Hybrid CPU support and CPU_TYPE detection Table 10. PSI_L GND Pull-Up to IOC_TH), the device will turn-on the LS mosfet until the threshold is re-crossed (i.e. until IINFOx < IOC_TH). OC_AVG pin allows to define a maximum total output current for the system (IOC_AVG). A copy of the DROOP current is sourced from the OC_AVG/LI pin. By connecting a resistor ROC_AVG to SGND, a load indicator with 2.5V (VOC_AVGTH) end-of-scale can be implemented. This means that when the voltage present at the LI pin crosses VOC_AVGTH, the device detects an average OC (OC_AVG) and immediately latches with all the mosfets of all the sections OFF (HiZ). – 33/44 Output voltage monitoring and protections L6740L Typical design considers the intervention of the Average OC before the per-phase OC, leaving this last one as an extreme-protection in case of hardware failures in the external components. Typical design flow is the following: – – – Define the maximum total output current (IOC_AVGmax) according to system requirements Set IOC_TH to 35µA. This implies ROC_TH = 33kΩ (OC_PHASE pin is fixed to 1.24V and IOC_TH is the current programmed through ROC_TH). Design RG resistor in order to have IINFOx = IOC_TH when IOUT is about 10% higher than the IOC_AVGmax current. It results: ( 1.1 ⋅ I OC_AVGmax ) ⋅ DCR R G = ----------------------------------------------------------------N ⋅ I OCTH where N is the number of phases and DCR the DC resistance of the inductors. RG should be designed in worst-case conditions. – Design ROC_AVG in order to have the OC_AVG/LI pin voltage to VOC_AVGTH at the desired maximum current IOC_AVGmax. It results: V OC_AVGTH ⋅ R G R OC_AVG = ----------------------------------------------I OC_AVGmax ⋅ DCR where VOC_AVGTH is typically 2.5V and IOC_AVGmax is the AVG_OC threshold desired. – – Note: Adjust the defined values according to bench-test of the application. An additional capacitor in parallel to ROC_AVG can be considered to add a delay in the protection intervention. What previoulsy listed is the typical design flow. In any case, custom design may require different settings and ratios between the per-phase OC threshold and the AVG OC threshold. Applications with huge ripple across inductors may required to set IOC_TH to values higher than 35µA: in this case the threshold may be increased still keeping IOC_TH < 50µA. 7.4.2 NB section Since the NB Section reads the current across Low-Side MOSFET, it limits the bottom of the NB inductor current entering in Constant Current until UV. In particular, since the device limits the valley of the inductor current, the ripple entity, when not negligible, impacts on the real OC threshold value and must be considered. The device detects an Over Current condition when the current information IISEN overcomes the fixed threshold of IOCTH_NB (35µA typ). When this happens, the device keeps the LowSide MOSFET on, also skipping clock cycles, until the threshold is crossed back and IISEN results being lower than the IOCTH_NB threshold. After exiting the OC condition, the LowSide MOSFET is turned off and the High-Side is turned on with a duty cycle driven by the PWM comparator. The Section enters the Quasi-Constant-Current operation: the Low-Side MOSFET stays ON until the current read becomes lower than IOCP_NB skipping clock cycles. The High-Side MOSFET can be then turned ON with a TON imposed by the control loop after the Low-Side MOSFET turn-off and the Section works in the usual way until another OC event is detected. This means that the average current delivered can slightly increase in Quasi-Constant-Cur- 34/44 L6740L Output voltage monitoring and protections rent operation since the current ripple increases. In fact, the ON time increases due to the OFF time rise because of the current has to reach the IOCP_NB bottom. The worst-case condition is when the ON time reaches its maximum value (see Section 6.8). When this happens, the Section works in Real Constant Current and the output voltage decrease as the load increase. Crossing the UV threshold causes the device to latch accordingly. It can be observed that the peak current (IPEAK_NB) is greater than IOCP_NB but it can be determined as follow: V IN – V OUT(min) V IN – V OUT(min) I PEAK_NB = I OCP_NB + --------------------------------------- ⋅ T ON(max) = I OCP_NB + --------------------------------------- ⋅ 0.40 ⋅ T SW L NB L NB Where VOUT(min) is the UV threshold, (inductor saturation must be considered). When that threshold is crossed, UV is detected. Cycle the power supply or the EN pin to restart operation. The maximum average current during the Constant-Current behavior results (see Figure 14): I PEAK – I OCP_NB I MAX_NB = I OCP_NB + ----------------------------------------2 in this particular situation, the switching frequency for the NB Section results reduced. The ON time is the maximum allowed TON(max) while the OFF time depends on the application: I PEAK – I OCP_NB T OFF = L NB ⋅ ----------------------------------------V OUT 1 f = -----------------------------------------T ON(max) + T OFF The transconductance resistor RISEN can be designed considering that the Section limits the inductor current ripple valley. Moreover the additional current due to the output filter charge during on-the-Fly VID transitions must be considered. I OCP_NB(max) ⋅ R dsON(max) R ISEN = ----------------------------------------------------------------I OCTH_NB(min) where IOCP_NB is defined above. Figure 14. NB Section - Constant current operation. Constant Current (Exploded) IPEAK_NB IMAX_NB Droop Effect Quasi-Const. Current VOUT 0.40 VIN Voltage Positioning IOCP_NB TON(max) LS ON Skipping Clock Cycles TON(max) UVP Threshold TSW TSW IOCP_NB (IDROOP_NB = 35µA) IOUT IMAX_NB 35/44 Main oscillator L6740L 8 Main oscillator The controller embeds a dual-Oscillator: one section is used for the CORE and it is a multiphase programmable oscillator managing equal phase-shift among all phases and the other section is used for the NB section. Phase-Shift between the CORE and NB ramps is automatically adjusted according to the CORE phase # programmed. The internal oscillator generates the triangular waveform for the PWM charging and discharging with a constant current an internal capacitor. The switching frequency for each channel, FSW, is internally fixed at 150kHz: the resulting switching frequency for the CORE section at the load side results in being multiplied by N (number of configured phases). The current delivered to the oscillator is typically 22µA (corresponding to the free running frequency FSW=150kHz) and it may be varied using an external resistor (ROSC) typically connected between the OSC pin and SGND. Since the OSC pin is fixed at 1.240V, the frequency is varied proportionally to the current sunk from the pin considering the internal gain of 6.8KHz/µA (See Figure 15). Connecting ROSC to SGND the frequency is increased (current is sunk from the pin), according to the following relationships: 6 1.240V kHz 8.432 ⋅ 10 F SW = 150kHz + --------------------------- ⋅ 6.8 ---------- = 150kHz + ---------------------------R OSC ( k Ω ) µA R OSC ( k Ω ) Figure 15. ROSC vs. switching frequency 1000 900 800 Switching Frequency [kHz] 700 600 500 400 300 200 100 10 100 1000 Rosc Resistor [kOhms] 36/44 L6740L System control loop compensation 9 System control loop compensation The device embeds two separate and independent control loops for CORE and NB section. The control loop for NB section is a simple Voltage-Mode control loop with (optional) voltage positioning featured when DROOP pin is shorted with FB. The control loop for the CORE section also features a Current-Sharing loop to equalize the current carried by each of the configured phases. The CORE control system can be modeled with an equivalent Single-Phase converter whose only difference is the equivalent inductor L/N (where each phase has an L inductor and N is the number of the configured phases). See Figure 16. Figure 16. Equivalent control loop for NB and CORE sections. PWM d VNB_COMP LNB ESR_NB CO_NB IDROOP_NB VOUT_NB RO_NB PWM d VCOMP LCORE/N ESR VOUT RO CO VNB_COMP Ref VID_NB IDROOP Ref VID_CORE NB_VSEN DROOP NB_DROOP NB_FBG NB_FB NB_COMP RF_NB CF-NB COMP RF CF ZF(s) ZFB(s) RFB_NB ZF(s) ZFB(s) RFB This means that the same analysis can be used for both the sections with the only exception of the different equivalent inductor value (L=LNB for NB Section and L=LCORE/N for the CORE section) and the current reading gain (RdsON/RISEN for NB Section and DCR/RG for the CORE Section). The Control Loop gain results (obtained opening the loop after the COMP pin): PWM ⋅ Z F ( s ) ⋅ ( R LL + Z P ( s ) ) G LOOP ( s ) = – ------------------------------------------------------------------------------------------------------------------ZF ( s ) 1[ Z P ( s ) + Z L ( s ) ] ⋅ -------------- + ⎛ 1 + -----------⎞ ⋅ R FB A(s) ⎝ A ( s )⎠ Where: ● ● ● ● ● ● RLL is the equivalent output resistance determined by the droop function; ZP(s) is the impedance resulting by the parallel of the output capacitor (and its ESR) and the applied load RO; ZF(s) is the compensation network impedance; ZL(s) is the equivalent inductor impedance; A(s) is the error amplifier gain; V IN 9PWM = ----- ⋅ ------------------ is the PWM transfer function. 10 ∆ V OSC The Control Loop gain for each section is designed in order to obtain a high DC gain to minimize static error and to cross the 0dB axes with a constant -20dB/Dec. slope with the desired crossover frequency ωT. Neglecting the effect of ZF(s), the transfer function has one zero and two poles; both the poles are fixed once the output filter is designed (LC filter resonance ωLC) and the zero (ωESR) is fixed by ESR and the Droop resistance. VSEN FBG VCOMP FB 37/44 System control loop compensation Figure 17. Control loop bode diagram and fine tuning (not in scale). dB dB CF GLOOP(s) K RF[dB] ZF(s) K RF[dB] RF ZF(s) GLOOP(s) L6740L ωLC = ωF ωESR ωT ω ωLC = ωF ωESR ωT ω To obtain the desired shape an RF-CF series network is considered for the ZF(s) implementation. A zero at ωF=1/RFCF is then introduced together with an integrator. This integrator minimizes the static error while placing the zero ωF in correspondence with the LC resonance assures a simple -20dB/Dec. shape of the gain. In fact, considering the usual value for the output filter, the LC resonance results to be at frequency lower than the above reported zero. Compensation network can be simply designed placing ωF=ωLC and imposing the crossover frequency ωT as desired obtaining (always considering that ωT might be not higher than 1/10th of the switching frequency FSW): R FB ⋅ ∆ V OSC 9 L R F = --------------------------------- ⋅ ----- ⋅ ω T ⋅ -----------------------------------------V IN 10 N ⋅ ( R LL + ESR ) CO ⋅ L C F = ------------------RF 9.1 Compensation network guidelines The Compensation Network design assures to having system response according to the cross-over frequency selected and to the output filter considered: it is anyway possible to further fine-tune the compensation network modifying the bandwidth in order to get the best response of the system as follow (See Figure 17): – – – Increase RF to increase the system bandwidth accordingly; Decrease RF to decrease the system bandwidth accordingly; Increase CF to move ωF to low frequencies increasing as a consequence the system phase margin. Having the fastest compensation network gives not the confidence to satisfy the requirements of the load: the inductor still limits the maximum dI/dt that the system can afford. In fact, when a load transient is applied, the best that the controller can do is to “saturate” the duty cycle to its maximum (dMAX) or minimum (0) value. The output voltage dV/dt is then limited by the inductor charge / discharge time and by the output capacitance. In particular, the most limiting transition corresponds to the load removal since the inductor results being discharged only by VOUT (while it is charged by dMAXVIN-VOUT during a load appliance). 38/44 L6740L LTB technology™ 10 LTB technology™ LTB Technology™ further enhances the performances of Dual-Edge Asynchronous Systems by reducing the system latencies and immediately turning ON all the phases to provide the correct amount of energy to the load. By properly designing the LTB network as well as the LTB Gain, the undershoot and the ring-back can be minimized also optimizing the output capacitors count. LTB Technology™ applies only to the CORE Section. LTB Technology™ monitors the output voltage through a dedicated pin detecting LoadTransients with selected dV/dt, it cancels the interleaved phase-shift, turning-on simultaneously all phases. it then implements a parallel, independent loop that reacts to Load-Transients bypassing E/A latencies. LTB Technology™ Control Loop is reported in Figure 18. Figure 18. LTB technology™ control loop (CORE section). LTB Ramp LTB LT Detect PWM_BOOST L/N d VCOMP ESR RO VOUT PWM CO VCOMP IDROOP Ref Monitor VID LT Detect FBG COMP CF FB DROOP VSEN RF RFB CH CFB LTB ZF(s) ZFB(s) RLTB CLTB The LTB detector is able to detect output load transients by coupling the output voltage through an RLTB - CLTB network. After detecting a load transient, the LTB Ramp is reset and then compared with the COMP pin level. The resulting duty-cycle programmed is then ORed with the PWMx signal of each phase by-passing the main control loop. All the phases will then be turned-on together and the EA latencies results bypassed as well. Sensitivity of the Load Transient Detector and the Gain of the LTB Ramp can be programmed in order to control precisely both the undershoot and the ring-back. ● Detector Design. RLTB - CLTB is design according to the output voltage deviation dVOUT which is desired the controller to be sensitive as follow: dV O UT R LTB = ----------------25 µ A 1 C LTB = ------------------------------------------------2 π ⋅ N ⋅ R LTB ⋅ F SW 39/44 LTB technology™ L6740L ● Gain Design. Through the LTBGAIN pin it is possible to modify the slope of the LTB Ramp in order to modulate the entity of the LTB response once the LT has been detected. In fact, the response depends on the board design and its parasitics requiring different actions from the controller. Leaving the LTBGAIN pin floating, the maximum pulse-width is programmed. The slope of the LTB ramp will be equal to 1/2 of the OSC ramp slope. Connecting RLTBGAIN to GND, the LTB Ramp slope can be modified as follow: I LTBGAIN LTBRamp Slope = OSC Slope ⋅ ⎛ 1 + -----------------------⎞ ⎝ I OSC ⎠ Where ILTBGAIN is the current sunk from LTBGAIN pin and IOSC is the OSC current (20µA plus the current sunk from the OSC pin). LTB TechnologyTM Design Tips. – – – Decrease RLTB to increase the system sensitivity making the system sensitive to smaller dVOUT. Increase CLTB to increase the system sensitivity making the system sensitive to higher dV/dt. Increase RLTBGAIN to increase the width of the LTB pulse reducing the system ring-back. 40/44 L6740L Layout guidelines 11 Layout guidelines Layout is one of the most important things to consider when designing high current applications. A good layout solution can generate a benefit in lowering power dissipation on the power paths, reducing radiation and a proper connection between signal and power ground can optimize the performance of the control loops. Two kind of critical components and connections have to be considered when laying-out a VRM based on L6740L: power components and connections and small signal components connections. 11.1 Power components and connections These are the components and connections where switching and high continuous current flows from the input to the load. The first priority when placing components has to be reserved to this power section, minimizing the length of each connection and loop as much as possible. To minimize noise and voltage spikes (EMI and losses) these interconnections must be a part of a power plane and anyway realized by wide and thick copper traces: loop must be anyway minimized. The critical components, i.e. the power transistors, must be close one to the other. The use of multi-layer printed circuit board is recommended. Since L6740L uses external drivers to switch the power MOSFETs, check the selected driver documentation for informations related to proper layout for this part. 11.2 Small signal components and connections These are small signal components and connections to critical nodes of the application as well as bypass capacitors for the device supply. Locate the bypass capacitor close to the device and refer sensible components such as frequency set-up resistor ROSC, offset resistor (both Sections) and OVP resistor ROVP to SGND. Star grounding is suggested: connect SGND to PGND plane in a single point to avoid that drops due to the high current delivered causes errors in the device behavior. VSEN pin filtered vs. SGND helps in reducing noise injection into device and EN pin filtered vs. SGND helps in reducing false trip due to coupled noise: take care in routing driving net for this pin in order to minimize coupled noise. Remote Buffer Connection must be routed as parallel nets from the FBG/FBR pins to the load in order to avoid the pick-up of any common mode noise. Connecting these pins in points far from the load will cause a non-optimum load regulation, increasing output tolerance. Locate current reading components close to the device. The PCB traces connecting the reading point must use dedicated nets, routed as parallel traces in order to avoid the pick-up of any common mode noise. It's also important to avoid any offset in the measurement and, to get a better precision, to connect the traces as close as possible to the sensing elements. Symmetrical layout is also suggested. Small filtering capacitor can be added, near the controller, between VOUT and SGND, on the CSx- line when reading across inductor to allow higher layout flexibility. 41/44 TQFP48 mechanical data & package dimensions L6740L 12 TQFP48 mechanical data & package dimensions Figure 19. TQFP48 mechanical data & package dimensions mm DIM. MIN. A A1 A2 b c D D1 D2 D3 e E E1 E2 E3 e L L1 k ccc 0.45 8.80 6.80 2.00 5.50 0.50 0.60 1.00 0.75 0.018 0.05 0.95 0.17 0.09 8.80 6.80 2.00 5.50 0.50 9.00 7.00 9.20 7.20 4.25 0.346 0.268 0.079 0.217 0.019 0.024 0.039 0.030 9.00 7.00 1.00 0.22 TYP. MAX. 1.20 0.15 1.05 0.27 0.20 9.20 7.20 4.25 0.002 0.037 0.006 0.004 0.346 0.268 0.079 0.217 0.020 0.354 0.276 0.362 0.283 0.167 0.354 0.276 0.039 0.008 MIN. TYP. MAX. 0.047 0.006 0.041 0.010 0.008 0.362 0.283 0.167 inch OUTLINE AND MECHANICAL DATA Body: 7 x 7 x 1.0mm 0˚(min.), 3.5˚(typ.), 7˚(max.) 0.08 0.0031 TQFP48 - EXPOSED PAD 7222746 B 42/44 L6740L Revision history 13 Revision history Table 13. Date 07-Jun-2007 01-Aug-2007 Document revision history Revision 1 2 First release Databrief updated to datasheet Changes 43/44 L6740L Please Read Carefully: Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any time, without notice. All ST products are sold pursuant to ST’s terms and conditions of sale. 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