L6751TR

L6751 Digitally controlled dual PWM for Intel VR12 and AMD SVI Datasheet − production data Features ■ VR12 compliant with 25 MHz SVID bus rev. 1.5 – SerialVID with programmable IMAX, TMAX, VBOOT, ADDRESS ■ AMD SVI compliant ■ Second generation LTB Technology® ■ Flexible driver/DrMOS support ■ JMode support ■ Fully configurable through PMBus™ ■ Dual controller: – up to 6 phases for CORE and memory – 1 phase for graphics (GFX), system agent (VSA) or Northbridge (VDDNB) ■ Single NTC design for TM, LL and Imon thermal compensation (for each section) ■ VFDE and GDC - gate drive control for efficiency optimization ■ DPM - dynamic phase management ■ Dual remote sense; 0.5% Vout accuracy ■ Full-differential current sense across DCR ■ AVP - adaptive voltage positioning ■ Dual independent adjustable oscillator ■ Dual current monitor ■ Pre-biased output management ■ Average and per-phase OC protection ■ OV, UV and FB disconnection protection ■ Dual VR_RDY ■ WLPGA72 6x6 mm package WPLGA72 6x6 mm Description The device is available in WLPGA72 6x6 mm package. Applications ■ High-current VRM / VRD for desktop / server / workstation Intel® / AMD CPUs ■ DDR3 memory supply November 2012 This is information on a product in full production. The L6751 is a universal digitally controlled dual PWM DC-DC designed to power Intel’s VR12 and AMD SVI processors and memories: all required parameters are programmable through dedicated pinstrapping and PMBus interface. The device features up to 6-phase programmable operation for multi-phase sections and a single-phase with independent control loops. When configured for memory supply, single-phase (VTT) reference is always tracking multi-phase (VDDQ) scaled by a factor of 2. The L6751 supports power state transitions featuring VFDE, programmable DPM and GDC maintaining the best efficiency over all loading conditions without compromising transient response. The device assures fast and independent protection against load overcurrent, under/overvoltage and feedback disconnections. Table 1. Device summary Order code Package Packaging L6751 WPLGA72 6x6 mm Tray L6751TR WPLGA72 6x 6mm Tape and reel Doc ID 023992 Rev 1 1/59 www.st.com 59 Contents L6751 Contents 1 2 3 4 Typical application circuit and block diagram . . . . . . . . . . . . . . . . . . . . 5 1.1 Application circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 1.2 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Pin description and connection diagrams . . . . . . . . . . . . . . . . . . . . . . . 7 2.1 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2.2 Thermal Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 3.1 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 3.2 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Device configuration and pinstrapping tables . . . . . . . . . . . . . . . . . . . 21 4.1 JMode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 4.2 Programming HiZ level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 5 Device description and operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 6 Output voltage positioning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 6.1 Multi-phase section - phase # programming . . . . . . . . . . . . . . . . . . . . . . 30 6.2 Multi-phase section - current reading and current sharing loop . . . . . . . . 30 6.3 Multi-phase section - defining load-line . . . . . . . . . . . . . . . . . . . . . . . . . . 31 6.4 Single-phase section - disable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 6.5 Single-phase section - current reading . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 6.6 Single-phase section - defining load-line . . . . . . . . . . . . . . . . . . . . . . . . . 32 6.7 Dynamic VID transition support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 6.7.1 6.8 7 DVID optimization: REF/SREF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Output voltage monitoring and protection . . . . . . . . . . . . . . . . . . . . . . 36 7.1 Overvoltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 7.2 Overcurrent and current monitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 7.2.1 2/59 LSLESS startup and pre-bias output . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Multi-phase section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Doc ID 023992 Rev 1 L6751 8 9 Contents 7.2.2 Overcurrent and power states . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 7.2.3 Single-phase section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Single NTC thermal monitor and compensation . . . . . . . . . . . . . . . . . 41 8.1 Thermal monitor and VR_HOT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 8.2 Thermal compensation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 8.3 TM/STM and TCOMP/STCOMP design . . . . . . . . . . . . . . . . . . . . . . . . . . 42 Efficiency optimization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 9.1 Dynamic phase management (DPM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 9.2 Variable frequency diode emulation (VFDE) . . . . . . . . . . . . . . . . . . . . . . 44 9.2.1 9.3 VFDE and DrMOS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 Gate drive control (GDC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 10 Main oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 11 System control loop compensation . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 12 11.1 Compensation network guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 11.2 LTB Technology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 PMBus support (preliminary) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 12.1 Enabling the device through PMBus . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 12.2 Controlling Vout through PMBus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 12.3 Input voltage monitoring (READ_VIN) . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 12.4 Duty cycle monitoring (READ_DUTY) . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 12.5 Output voltage monitoring (READ_VOUT) . . . . . . . . . . . . . . . . . . . . . . . . 55 12.6 Output current monitoring (READ_IOUT) . . . . . . . . . . . . . . . . . . . . . . . . 55 12.7 Temperature monitoring (READ_TEMPERATURE) . . . . . . . . . . . . . . . . . 55 12.8 Overvoltage threshold setting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 13 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 14 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 Doc ID 023992 Rev 1 3/59 List of tables L6751 List of tables Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 11. Table 12. Table 13. Table 14. Table 15. Table 16. Table 17. Table 18. Table 19. 4/59 Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Thermal data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Device configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Phase number programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 IMAX, SIMAX pinstrapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 ADDR pinstrapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 BOOT / TMAX pinstrapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 DPM pinstrapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 GDC threshold definition. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 L6751 protection at a glance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Multi-phase section OC scaling and power states . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Efficiency optimization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 Supported commands. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 OV threshold setting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 L6751 WPLGA72 6x6 mm mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 Doc ID 023992 Rev 1 L6751 List of figures List of figures Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Figure 10. Figure 11. Figure 12. Figure 13. Figure 14. Figure 15. Figure 16. Figure 17. Figure 18. Typical 6-phase application circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 L6751 pin connections (left: top view - right: bottom view) . . . . . . . . . . . . . . . . . . . . . . . . . . 8 JMode: voltage positioning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Device initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Voltage positioning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Current reading. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 LSLESS startup: enabled (left) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 LSLESS startup: disabled (right) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 DVID optimization circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Thermal monitor connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 Output current vs. switching frequency in PSK mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 Efficiency performance with and without enhancements (DPM, GDC). . . . . . . . . . . . . . . . 45 ROSC vs. FSW per phase (ROSC to GND - left; ROSC to 3.3 V - right) . . . . . . . . . . . . . . . . 46 Equivalent control loop. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 Control loop bode diagram and fine tuning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 Device initialization: PMBus controlling Vout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 L6751 WPLGA72 6x6 mm package dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 Doc ID 023992 Rev 1 5/59 Typical application circuit and block diagram L6751 1 Typical application circuit and block diagram 1.1 Application circuit Figure 1. Typical 6-phase application circuit +12V +5V +12V CDEC EN EN RSOSC GND x2 (+PAD) OSC +12V VCC BOOT GDC IMAX /SIMAX BOOT / TMAX ADDR DPM1-3 DPM4-6 TCOMP STCOMP SOSC ROSC PMBus(tm) VCC5 SMCLK SMAL# SMDATA VIN CHF L6747 VDRV EN UGATE LGATE R C +12V VRRDY SVRRDY VR_HOT VR_HOT CDEC VCC BOOT CHF EN PWM1 CS1P CS1N NTC (NTHS0805N02N6801) (Close to the hotspot) UGATE L6747 VR_RDY SVR_RDY ENDRV TM HS2 L2 PHASE LGATE PWM LS2 R C GND STM VCC5 LS1 GND L6751 VCC5 L1 PHASE PWM RG PHASE PHASE1 HS1 PWM2 CS2P CS2N NTC (NTHS0805N02N6801) (Close to the hotspot) RG +12V PWM3 CS3P CS3N SIMON RSIMON CDEC VCC BOOT PWM4 CS4P CS4N L6747 CHF ILIM RILIM EN UGATE HS3 L3 PHASE IMON RIMON PWM PWM4 CS4P CS4N SREF CSREF RS REF LGATE LS3 R C GND RG SCOMP PWM4 CS4P CS4N CSF CSP RSF +12V CDEC SFB VCC CS I UGATE SVSEN SFBR SRGND L6747 RS I BOOT CHF RSFB EN REF L4 PHASE LGATE PWM HS4 LS4 R C GND CREF RREF RG COMP CF CP +12V FB CDEC VCC BOOT RFB CHF UGATE VSEN FBR RGND LTB EN VR12 SVID Bus C +12V CDEC BOOT VCC VCC LGATE EN EN PWM PWM L6747 PHASE UGATE L6747 UGATE BOOT CHF CHF SLS R RG CDEC SL L4 LS4 GND +12V SHS HS4 PHASE LGATE PWM SCSN SCSP SPWM SENDRV SVCLK ALERT# SVDATA RI L6747 RF CI HS4 L4 PHASE LGATE LS4 R C GND GND RG CSMLCC VR12 mP LOAD CORE CSOUT UNCORE RG COUT AM14809v1 ST L6751 (6+1) Reference Schematic 6/59 CMLCC VR12 SVID s Bu Doc ID 023992 Rev 1 Block diagram VR12 Bus Manager & PinStrapping Manager To SinglePhase FLT Manager FLT SImon Imon TempZone DPM BOOT / TMAX IMAX / SIMAX DPM1-3 DPM4-6 ADDR SVCLK ALERT# SVDATA EN Figure 2. OSC Block diagram VR_RDY 1.2 GDC Typical application circuit and block diagram GND (PAD) L6751 S_EN VCC5 VDRV Start-up Logic & GDC Control EN VR12 Registers VSEN MultiPhase Fault Manager LTB Technology Modulator & Frequency Limiter Ramp & Clock Generator with VFDE DPM Control DPM FLT LTB ENDRV Dual DAC & Ref Generator PWM1 OV Σ PWM1 SREF PWM2 REF Σ FBR RGND PWM2 PWM3 I REF +175mV Σ PWM3 PWM4 REF REMOTE BUFFER Σ PWM4 PWM5 REF Σ PWM5 PWM6 VSEN Σ PWM6 ERROR AMPLIFIER OC Chan # REF Current Balance & Peak Curr Limit Voc_tot FB ILIM IMON I DROOP I LIM N I MON DPM SMCLK SMAL# SMDATA CS1P CS1N CS2P CS2N CS3P CS3N CS4P CS4N CS5P CS5N CS6P CS6N Differential Current Sense I REF COMP Chan # VSEN, SVSEN VID, SVID PMBus(TM) Decodification Engine & Control Logic PHASE Thermal Compensation and Gain adjust VIN TempZone SFBR SRGND I SREF TM VR_HOT STM Thermal Sensor and Monitor SOV SREF TCOMP +175mV SPWM / SEN SPWM SENDRV SREF SVSEN SCOMP S_EN I SREF SFLT ERROR AMPLIFIER Ramp & Clock Generator withVFDE LTB Technology Modulator & Frequency Limiter L6751 SREF SOSC SFB Voc_tot SOC SIMON SinglePhase Fault Manager To MultiPhase FLT Manage SFLT SVR_RDY STCOMP SCSP SCSN Doc ID 023992 Rev 1 AM14810v1 7/59 Pin description and connection diagrams L6751 TM SENDRV VR_HOT SIMON SOSC SREF SPWM ILIM TCOMP SCSN DPM4-6 DPM1-3 A19 D3 A18 B16 A17 B15 A16 B14 A15 B13 A14 B12 A13 B11 A12 B10 A11 B9 A10 SVSEN SCSP L6751 pin connections (left: top view - right: bottom view) SRGND Figure 3. SFB Pin description and connection diagrams SFBR 2 SCOMP IMAX/SIMAX SMDATA SMCLK ADDR STCOMP VIN EN ALERT# BOOT / TMAX GND SMAL# NC STM OSC NC SVCLK SVDATA D2 A19 B17 A20 B18 A21 B19 A22 B20 A23 B21 A24 B22 A25 B23 A26 B24 A27 A9 B8 A8 B7 A7 B6 A6 B5 A5 B4 A4 B3 A3 B2 A2 B1 A1 VCC5 D4 CS1N CS2P CS3N Table 2. Pin description Name CS4P CS5N CS6P GND NC PWM1 D1 PWM3 D(1) A1 PWM2 D B1 PWM1 D A2 PHASE A B2 NC - A3 VR_RDY D 8/59 A18 CS2N CS3P B25 B16 CS4N CS5P CS6N VR_RDY PHASE B32 B9 PWM2 PWM3 A36 PWM5 A10 B8 D2 B1 D1 A1 PWM4 A9 AM14811v1 Type Function MULTI-PHASE SECTION Pin# PWM6 ENDRV IMON REF SVR_RDY RGND LTB FB FBR VSEN COMP NC NC GDC VDRV Pin description D4 CS1P A28 B25 A29 B26 A30 B27 A31 B28 A32 B29 A33 B30 A34 B31 A35 B32 A36 D1 2.1 B24 A28 D3 L6751 L6751 A27 B17 PWM output. Connect to multi-phase channel 3 external driver PWM input. During normal operation the device is able to manage HiZ status by setting and holding the PWMx pin to a fixed predefined voltage. See Table 7 for phase number programming. PWM output. Connect to multi-phase external drivers PWM input. These pins are also used to configure HiZ levels for compatibility with drivers and DrMOS. During normal operation the device is able to manage HiZ status by setting and holding the PWMx pin to the predefined fixed voltage. Connect through resistor divider to multi-phase channel1 switching node. Not internally bonded. VR Ready. Open drain output set free after SS has finished in multi-phase section and pulled low when triggering any protection on multi-phase section. Pull up to a voltage lower than 3.3 V (typ.), if not used it can be left floating. Doc ID 023992 Rev 1 L6751 Table 2. Pin description and connection diagrams Pin description (continued) Pin# Name Type Function B3 GND A GND connection. All internal references and logic are referenced to this pin. Filter to VCC5 with proper MLCC capacitor and connect to the PCB GND plane. CS6N A B4 CS6P A Channel 6 current sense positive input. Connect through an R-C filter to the phase-side of the channel 6 inductor. When working at < 6 phases, short to the regulated voltage. A5 CS5P A B5 CS5N A MULTI-PHASE SECTION A4 Channel 6 current sense negative input. Connect through an Rg resistor to the output-side of the channel inductor. When working at < 6 phases, still connect through Rg to CS6P and then to the regulated voltage. Filter the output-side of Rg with 100 nF (typ) to GND. Channel 5 current sense positive input. Connect through an R-C filter to the phase-side of the channel 5 inductor. When working at < 5 phases, short to the regulated voltage. Channel 5 current sense negative input. Connect through an Rg resistor to the output-side of the channel inductor. When working at < 5 phases, still connect through Rg to CS5P and then to the regulated voltage. Filter the output-side of Rg with 100 nF (typ.) to GND. CS4N A B6 CS4P A Channel 4 current sense positive input. Connect through an R-C filter to the phase-side of the channel 4 inductor. When working at < 4 phases, short to the regulated voltage. A7 CS3P A Channel 3 current sense positive input. Connect through an R-C filter to the phase-side of the channel 3 inductor. When working at < 3 phases, short to the regulated voltage. MULTI-PHASE SECTION A6 Channel 4 current sense negative input. Connect through an Rg resistor to the output-side of the channel inductor. When working at < 4 phases, still connect through Rg to CS4P and then to the regulated voltage. Filter the output-side of Rg with 100 nF (typ.) to GND. Channel 3 current sense negative input. Connect through an Rg resistor to the output-side of the channel inductor. When working at < 3 phases, still connect through Rg to CS3P and then to the regulated voltage. Filter the output-side of Rg with 100 nF (typ.) to GND. B7 CS3N A A8 CS2N A B8 CS2P A A9 CS1P A Channel 1 current sense positive input. Connect through an R-C filter to the phase-side of the channel 1 inductor. D2 CS1N A Channel 1 current sense negative input. Connect through an Rg resistor to the output-side of the channel inductor. Filter the output-side of Rg with 100 nF (typ.) to GND. Channel 2 current sense negative input. Connect through an Rg resistor to the output-side of the channel inductor. Filter the output-side of Rg with 100 nF (typ.) to GND. Channel 2 current sense positive input. Connect through an R-C filter to the phase-side of the channel 2 inductor. Doc ID 023992 Rev 1 9/59 Pin description and connection diagrams A11 B10 A12 B11 A13 B12 10/59 SREF TM SPWM / SEN SENDRV ILIM VR_HOT TCOMP Function A Oscillator pin. It allows the switching frequency FSSW to be programmed for the single-phase section. The pin is internally set to 1.02 V, frequency for single-phase is programmed according to the resistor connected to GND or VCC with a gain of 11.5 kHz/µA. Leaving the pin floating programs a switching frequency of 230 kHz. See Section 10 for details. A A D D SINGLE-PHASE SECTION B9 SOSC Type MULTI-PHASE SECTION A10 Name SINGLE-PHASE SINGLE-PHASE SECTION SECTION Pin# Pin description (continued) A D A MULTI-PHASE SECTION Table 2. L6751 The reference used for the single-phase section regulation is available on this pin with -125 mV offset. Connect through an RSREF-CSREF to GND to optimize DVID transitions. Connect through RSOS resistor to the SFB pin to implement small positive offset to the regulation. Thermal monitor sensor. Connect with proper network embedding NTC to the multi-phase power section. The IC senses the power section temperature and uses the information to define the VR_HOT signal and temperature monitoring. By programming proper TCOMP gain, the IC also implements load-line and IMON/ILIM thermal compensation for the multi-phase section. In JMode, the pin disables the single-phase section if shorted to GND. Pull up to VCC5 with 1 kΩ to disable thermal sensor. See Section 8 for details. PWM output. Connect to single-phase external driver PWM input. During normal operation the device is able to manage HiZ status by setting and holding the pin to a fixed voltage defined by PWMx strapping. Connect to VCC5 with 1 kΩ to disable the single-phase section. Enable driver. CMOS output driven high when the IC commands the driver. Used in conjunction with the HiZ window on the SPWM pin to optimize the singlephase section overall efficiency. Connect directly to external driver enable pin. Multi-phase section current limit. A current proportional to the multi-phase load current is sourced from this pin. Connect through a resistor RLIM to GND. When the pin voltage reaches 2.5 V, the overcurrent protection is set and the IC latches. Filter through CLIM to GND to delay OC intervention. Voltage regulator HOT. Open drain output, this is an alarm signal asserted by the controller when the temperature sensed through the ST or TM pins exceed TMAX (active low). See Section 8 for details. Thermal monitor sensor gain. Connect proper resistor divider between VCC5 and GND to define the gain to apply to the signal sensed by the TM to implement thermal compensation for the multi-phase section. Short to GND to disable temperature compensation (but not thermal sensor). See Section 8 for details. Doc ID 023992 Rev 1 L6751 Pin description (continued) SCSP A B13 SCSN A A15 SIMON A B14 DPM4-6 A A16 SRGND A B15 DPM1-3 A A17 SFBR A B16 SVSEN A A18 SFB A D3 SCOMP A A19 IMAX / SIMAX A SINGLE-PHASE SECTION A14 Function SINGLE-PHASE PINSTRAPPING SECTION Type PINSTRAPPING Name SINGLE-PHASE SECTION Pin# PINSTRAPPING Table 2. Pin description and connection diagrams Single-phase section current senses positive input. Connect through an R-C filter to the phase-side of the channel 1 inductor. Single-phase section current senses negative input. Connect through an Rg resistor to the output-side of the channel inductor. Filter the output-side of Rg with 100 nF (typ.) to GND. Current monitor output. A current proportional to the single-phase current is sourced from this pin. Connect through a resistor RSIMON to GND. When the pin voltage reaches 1.55 V, overcurrent protection is set and the IC latches. Filtering through CSIMON to GND allows the delay for OC intervention to be controlled. Connect a resistor divider to GND/VCC5 in order to define the DPM and GDC strategies. See Table 11 and Table 12 for details. Remote buffer ground sense. Connect to the negative side of the single-phase load to perform remote sense. Connect a resistor divider to GND/VCC5 in order to define the DPM and GDC strategies. See Table 11 and Table 12 for details. Remote buffer positive sense. Connect to the positive side of the single-phase load to perform remote sense. Remote buffer output. Output voltage monitor, manages OV and UV protection. Connect with a resistor RSFB // (RSI - CSI) to SFB. Error amplifier inverting input. Connect with a resistor RSFB // (RSI - CSI) to SVSEN and with an (RSF - CSF)// CSH to SCOMP. Error amplifier output. Connect with an (RSF - CSF)// CSH to SFB. The device cannot be disabled by pulling low this pin. Connect a resistor divider to GND/VCC5 in order to define the IMAX and SIMAX registers. See Table 8 and Table 6 for details. Doc ID 023992 Rev 1 11/59 Pin description and connection diagrams Table 2. L6751 Pin description (continued) Name Type B17 GND A GND connection. All internal references and logic are referenced to this pin. Filter to VCC5 with proper MLCC capacitor and connect to the PCB GND plane. A20 SMDATA D PMBus data. B18 SMAL# D A21 SMCLK D B19 NC - A22 ADDR A A23 STCOMP A PINSTRAPPING SINGLE-PHASE SECTION STM PMBus alert. PMBus clock. Not internally bonded. Connect a resistor divider to GND/VCC5 in order to configure the IC operating mode. See Table 9 and Table 6 for details. Thermal monitor sensor. Connect with proper network embedding NTC to the single-phase power section. The IC senses the power section temperature and uses the information to define the VR_HOT signal and temperature monitoring. By programming proper STCOMP gain, the IC also implements load-line and SIMON thermal compensation for the single-phase section when applicable. Short to GND if not used. See Section 8 for details. A Thermal monitor sensor gain. Connect proper resistor divider between VCC5 and GND to define the gain to apply to the signal sensed by ST to implement thermal compensation for the single-phase section. Short to GND to disable temperature compensation. See Section 8 for details. Oscillator pin. It allows the programming of the switching frequency FSW for the multi-phase section. The pin is internally set to 1.02 V, frequency for multi-phase is programmed according to the resistor connected to GND or VCC with a gain of 10 Hz/µA. Leaving the pin floating programs a switching frequency of 200 Hz per phase. Effective frequency observable on the load results as being multiplied by the number of active phases N. See Section 10 for details. MULTI-PHASE SECTION B20 Function PMBus Pin# B21 OSC A A24 VIN A B22 NC - Not internally bonded. A25 EN D Level sensitive enable pin (3.3 V compatible). Pull low to disable the device, pull up above the turn-on threshold to enable the controller. 12/59 Input voltage monitor. Connect to input voltage monitor point through a divider RVUP / RVDWN to perform VIN sense through PMBus (RUP = 118.5 Ω; RDOWN = 10 kΩ typ.). Doc ID 023992 Rev 1 L6751 Table 2. Pin description and connection diagrams Pin description (continued) Pin# Name Type Function B23 SVCLK SVC D A26 ALERT# V_FIX D B24 SVDATA SVD D A27 BOOT / TMAX A D4 VCC5 A Main IC power supply. Operative voltage is 5 V ± 5%. Filter with 1 μF MLCC to GND (typ.). A28 GDC A Gate drive control pin. Used for efficiency optimization, see Section 9 for details. If not used, it can be left floating. Always filter with 1 μF MLCC to GND. B25 NC - Not internally bonded. SVI BUS Serial clock. Alert (Intel mode). V_FIX (AMD mode). Pull to 3.3 V to enter V_FIX mode. PINSTRAPPING Serial data. Connect a resistor divider to GND/VCC5 in order to define BOOT and TMAX registers. See Table 10 for details. A29 VDRV A Driving voltage for external drivers. Connect to the selected voltage rail to drive external MOSFET when in maximum power conditions. IC switches GDC voltage between VDRV and VCC5 to implement efficiency optimization according to selected strategies. B26 NC - Not internally bonded. Doc ID 023992 Rev 1 13/59 Pin description and connection diagrams Table 2. Pin# L6751 Pin description (continued) Name Type Function COMP / ADDR A B27 FB A Error amplifier inverting input. Connect with a resistor RFB // (RI - CI) to VSEN and with an (RF - CF)// CP to COMP. A31 VSEN A Output voltage monitor, manages OV and UV protection. Connect to the positive side of the load to perform remote sense. B28 FBR A A32 LTB A B29 RGND A B30 A34 REF IMON SVR_RDY (PWROK) Remote buffer positive sense. Connect to the positive side of the multi-phase load to perform remote sense. LTB Technology input pin. See Section 11.2 for details. Remote ground sense. Connect to the negative side of the multi-phase load to perform remote sense. A The reference used for the multi-phase section regulation is available on this pin with -125 mV offset. Connect through an RREF-CREF to GND to optimize DVID transitions. Connect through ROS resistor to FB pin to implement small positive offset to the regulation. A Current monitor output. A current proportional to the multi-phase load current is sourced from this pin. Connect through a resistor RMON to GND. The information available on this pin is used for the current reporting and DPM. The pin can be filtered through CIMON to GND. D B31 ENDRV D A35 PWM6 D B32 PWM5 D A36 PWM4 D PAD GND A MULTI-PHASE MULTI-PHASE SINGLE-PHASE SECTION SECTION SECTION A33 MULTI-PHASE SECTION A30 Error amplifier output. Connect with an (RF - CF)// CP to FB. The device cannot be disabled by pulling low this pin. Connect RCOMP = 12.5 kΩ to GND to extend PMBus addressing range (see Table 9). VR Ready (Intel mode). Open drain output set free after SS has finished and pulled low when triggering any protection for the single-phase section. Pull up to a voltage lower than 3.3 V (typ.), if not used it can be left floating. PowerOK (AMD mode). System-wide Power Good input. When low, the device decodes SVC and SVD to determine the boot voltage. Enable driver. CMOS output driven high when the IC commands the drivers. Used in conjunction with the HiZ window on the PWMx pins to optimize the multiphase section overall efficiency. Connect directly to external driver enable pin. PWM output. Connect to related multi-phase channel external driver PWM input. During normal operation the device is able to manage HiZ status by setting and holding the PWMx pin to fixed voltage defined before. See Table 7 for phase number programming. GND connection. All internal references and logic are referenced to this pin. Filter to VCC with proper MLCC capacitor and connect to the PCB GND plane. 1. D = Digital, A = Analog. 14/59 Doc ID 023992 Rev 1 L6751 2.2 Pin description and connection diagrams Thermal Data Table 3. Symbol Thermal data Parameter Value Unit RTHJA Thermal resistance junction-to-ambient (device soldered on 2s2p PC board) 40 °C/W RTHJC Thermal resistance junction-to-case 1 °C/W TMAX Maximum junction temperature 150 °C TSTG Storage temperature range -40 to 150 °C TJ Junction temperature range 0 to 125 °C Doc ID 023992 Rev 1 15/59 Electrical specifications L6751 3 Electrical specifications 3.1 Absolute maximum ratings Table 4. Absolute maximum ratings Symbol Parameter Value Unit to GND -0.3 to 14 V VCC5, TM, STM, SPWM, PWMx, SENDRV, ENDRV, SCOMP, to GND COMP, SMDATA, SMAL#, SMCLK -0.3 to 7 V -0.3 to 3.6 V VDRV, GDC All other pins 3.2 to GND Electrical characteristics (VCC5 = 5 V ± 5%, TJ = 0 °C to 70 °C unless otherwise specified.) Table 5. Symbol Electrical characteristics Parameter Test conditions Min. Typ. Max. Unit Supply current and power-on IVCC5 UVLOVCC5 UVLOVDRV EN = High 28 mA EN = Low 22 mA VCC5 supply current VCC5 turn-ON VCC5 rising VCC5 turn-OFF VCC5 falling VDRV turn-ON VDRV rising VDRV turn-OFF VDRV falling VIN turn-ON VIN rising, RUP = 118.5 kΩ; RDOWN = 10 kΩ VIN turn-OFF VIN falling, RUP = 118.5 kΩ; RDOWN = 10 kΩ UVLOVIN 4.1 3 V V 3 3 6.0 V 4.1 V 6.0 V 4.1 V Oscillator, soft-start and enable FSW FSSW Main oscillator accuracy OSC = Open 170 200 230 kHz Oscillator adjustability ROSC / RSOSC = 47 kΩ to GND 378 420 462 kHz Main oscillator accuracy SOSC = Open 212 250 287 kHz Oscillator adjustability ROSC / RSOSC = 47 kΩ to GND 450 500 550 kHz ΔVOSC PWM ramp amplitude(1) FAULT Voltage at pin OSC, SSOSC 16/59 1.5 Latch active for related section Doc ID 023992 Rev 1 3 V V L6751 Table 5. Electrical specifications Electrical characteristics (continued) Symbol Parameter SS time - Intel CPU mode Test conditions Min. Typ. Max. Unit Vboot > 0, from pinstrapping; multiphase section 5 mV/μS Vboot > 0, from pinstrapping; singlephase section 2.5 mV/μS Vboot > 0, from pinstrapping; singlephase section, JMode ON 2.5 mV/μS Vboot > 0, from pinstrapping; multiphase section 2.5 mV/μS Vboot > 0, from pinstrapping; singlephase section 1.25 mV/μS Soft-start SS time - Intel DDR mode EN SS time - AMD mode Vboot > 0, from pinstrapping; both sections Turn-ON VEN rising Turn-OFF VEN falling 6.25 mV/μS 0.6 0.4 Leakage current V V μA 1 SVI serial bus SVCLCK, SVDATA SVDATA, ALERT# Input high 0.65 Input low Voltage low (ACK) ISINK = -5 mA V 0.45 V 50 mV PMBus SMDATA, SMCLK Input high SMAL# Voltage low 1.75 Input low ISINK = -4 mA V 1.45 V 13 Ω Reference and DAC kVID kSVID VOUT accuracy (MPhase) VOUT accuracy (SPhase) kVID, kSVID VOUT accuracy kVOUT VOUT accuracy - AMD mode ΔDROOP LL accuracy (MPhase) 0 to full load IOUT = 0 A; N = 6; RG = 540 Ω; RFB = 1.108 kΩ; VID > 1.000 V -0.5 0.5 % IOUT = 0 A; RG= 1.3 kΩ; VID > 1.000 V -0.5 0.5 % IOUT = 0 A; RG = 1.3 kΩ; VID > 1.000 V; JMODE = ON -5 5 mV VID = 0.8 V to 1 V -5 5 mV VID < 0.8 V -8 8 mV -20 20 mV -3 2 μA -4.5 4.5 μA IINFOx = 0; N = 6; RG = 540 Ω; RFB = 1.108k Ω Same as above, IINFOx = 20 μA Doc ID 023992 Rev 1 17/59 Electrical specifications Table 5. L6751 Electrical characteristics (continued) Symbol Parameter SS time - Intel CPU mode Test conditions Min. Typ. Max. Unit Vboot > 0, from pinstrapping; multiphase section 5 mV/μS Vboot > 0, from pinstrapping; singlephase section 2.5 mV/μS Vboot > 0, from pinstrapping; singlephase section, JMode ON 2.5 mV/μS Vboot > 0, from pinstrapping; multiphase section 2.5 mV/μS Vboot > 0, from pinstrapping; singlephase section 1.25 mV/μS Soft-start SS time - Intel DDR mode EN SS time - AMD mode Vboot > 0, from pinstrapping; both sections Turn-ON VEN rising Turn-OFF VEN falling 6.25 mV/μS 0.6 0.4 Leakage current V V μA 1 SVI serial bus SVCLCK, SVDATA SVDATA, ALERT# Input high 0.65 Input low Voltage low (ACK) ISINK = -5 mA V 0.45 V 50 mV PMBus SMDATA, SMCLK Input high SMAL# Voltage low 1.75 Input low ISINK = -4 mA V 1.45 V 13 Ω Reference and DAC kVID kSVID VOUT accuracy (MPhase) VOUT accuracy (SPhase) kVID, kSVID VOUT accuracy kVOUT VOUT accuracy - AMD mode ΔDROOP LL accuracy (MPhase) 0 to full load 18/59 IOUT = 0 A; N = 6; RG = 540 Ω; RFB = 1.108 kΩ; VID > 1.000 V -0.5 0.5 % IOUT = 0 A; RG= 1.3 kΩ; VID > 1.000 V -0.5 0.5 % IOUT = 0 A; RG = 1.3 kΩ; VID > 1.000 V; JMODE = ON -5 5 mV VID = 0.8 V to 1 V -5 5 mV VID < 0.8 V -8 8 mV -20 20 mV -3 2 μA -4.5 4.5 μA IINFOx = 0; N = 6; RG = 540 Ω; RFB = 1.108k Ω Same as above, IINFOx = 20 μA Doc ID 023992 Rev 1 L6751 Table 5. Electrical specifications Electrical characteristics (continued) Symbol Parameter Test conditions Max. Unit -1.75 1 μA -1 1 μA 0 0.75 μA -4.5 4.5 μA ISCSN = 0 μA; RG = 1.3 kΩ 0 0.5 μA ISCSN = 20 μA; RG = 1.3 kΩ -1 1 μA ISCSN = 0; RG = 1.3 kΩ ΔSDROOP LL accuracy (SPhase) 0 to full load kIMON IINFOx = 0 μA; N = 6; RG = 540 Ω; RFB IMON accuracy (MPhase) = 1.108 kΩ ISCSN = 20 μA; RG = 1.3 kΩ Same as above, IINFOx = 20 μA kSIMON SIMON accuracy (SPhase) A0 EA DC Gain(1) SR Slew rate(1) Min. COMP to SGND = 10 pF Slew rate fast Typ. 100 dB 20 V/μs 20 mV/μs 5 mV/μs Multi-phase section DVID - Intel CPU mode Slew rate slow Slew rate fast 10 Single-phase section Slew rate slow DVID - Intel DDR mode 2.5 Slew rate fast 10 mV/μs 2.5 mV/μs Multi-phase section Slew rate slow DVID - AMD Slew rate mode Both sections GetReg(15h) IMON ADC 5 mV/μs CC Hex V(IMON) = 0.992 V Accuracy C0 CF Hex PWM outputs and ENDRV PWMx, SPWM Output high I = 1 mA Output low I = -1 mA IPWM1 Test current Sourced from pin, EN = 0. IPWM2 Test current IPWMx, SPWM Test current Sourced from pin, EN = 0. ENDRV IENDRV = -4 mA; both sections Voltage low 5 V 0.2 V 10 μA 0 μA -10 μA 0.4 V Protection (both sections) OVP Overvoltage protection VSEN rising; wrt VID 100 200 mV UVP Undervoltage protection VSEN falling; wrt VID; VID > 500 mV -525 -375 mV FBR DISC FB disconnection VCS- rising, above VSEN/SVSEN 650 700 750 mV FBG DISC FBG disconnection FBR input wrt VID 950 1000 1050 mV VR_RDY, SVR_RDY Voltage low ISINK = -4 mA 0.4 V VOC_TOT OC threshold, MPhase VILIM rising, to GND 2.5 V VSOC_TOT OC threshold, SPhase VSIMON rising, to GND 1.55 V Doc ID 023992 Rev 1 19/59 Electrical specifications Table 5. L6751 Electrical characteristics (continued) Symbol Parameter IOC_TH Constant current VR_HOT Voltage low (1) Test conditions MPhase only Min. Typ. Max. μA 35 ISINK = -4 mA Unit 13 Ω Gate drive control Max. current GDC Any PS. 200 mA PS00h (GDC=VCC12) 6 Ω > PS00h; (GDC=VCC5) 6 Ω Impedance 1. Guaranteed by design, not subject to test. 20/59 Doc ID 023992 Rev 1 L6751 4 Device configuration and pinstrapping tables Device configuration and pinstrapping tables The L6751 features a universal serial data bus fully compliant with Intel VR12/IMVP7 Protocol rev 1.5, document #456098 and AMD SVI specifications, document #40182. To guarantee proper device and CPU operation, refer to these documents for bus design, layout guidelines and any additional information required for the bus architecture. Different platforms may require different pull-up impedance on the SVI bus. Impedance matching and spacing among SVI bus lines must be followed. The controller configures itself automatically upon detection of different pinstrappings which are monitored at the IC power-up. See Table 6, 8, 9, 10, and 11 for details. JMode When enabled, multi-phase acts as if in DDR mode, while single-phase is an independent regulator with 0.75 V fixed reference (load-line disabled - TM can be used as enable for the single-phase). Output voltage higher than the internal reference may be achieved by adding a proper resistor divider (RA, RB - see Figure 4). To maintain precision in output voltage regulation, it is recommended to provide both SFBR and SRGND with the same divider. Equation 1 RA + RB V OUT = 0.750V ⋅ ----------------------RB Figure 4. JMode: voltage positioning 0.750V Protection Monitor 4.1 SFB SCOMP RF SVSEN SFBR SRGND RA CF To Vout (Remote Sense) RFB RA RB RB AM14812v1 Doc ID 023992 Rev 1 21/59 Device configuration and pinstrapping tables 4.2 L6751 Programming HiZ level The L6751 is able to manage different levels for HiZ on PWMx guaranteeing flexibility in driving different external drivers as well as DrMOS ICs. After EN assertion and before soft-start, the device uses PWM1 and PWM2 to detect the driver/DrMOS connected in order to program the suitable Hiz level of PWMx signals. During regulation, the Hiz level is used to force the external MOSFETs in high impedance state. – PWM1 sources a constant 10 μA current, if its voltage results higher than 2.8 V, HiZ level used during the regulation is 1.4 V, if lower, PWM2 information is used. – PWM2 is kept in HiZ, if its voltage results higher than 2 V, HiZ level used during the regulation is 2 V, if lower, 1.6 V. An external resistor divider can be placed on PWM1 and PWM2 to force the detection of the correct HiZ level. They must be designed considering the external driver/DrMOS selected and the HiZ level requested. Table 6. Device configuration SVI address DROOP (see Table 8) VR12 0000b Enabled. VR12(1) () 0010b 0100b MPhase: as per Table 9. SPhase: disabled AMD n/a IMAX / SIMAX BOOT / TMAX Table 8 DPM Table 10 Supported TMAX(2) supported MPhase: enabled. SPhase: Ignored as per Table 9. 1. In DDR mode, single-phase reference is multi-phase Vout/2 (JMode disabled). 2. Refer to Table 10 and choose any of the resistor combinations leading to the desired TNMAX. Other settings are ignored. Table 7. Phase number programming PHASE # PWM1 to PWM3 3 to driver 4 5 PWM4 PWM6 1 kΩ to VCC5 to driver 1 kΩ to VCC5 to driver 6 22/59 PWM5 1 kΩ to VCC5 to driver Doc ID 023992 Rev 1 L6751 Device configuration and pinstrapping tables Table 8. IMAX, SIMAX pinstrapping(1) IMAX / SIMAX Rdown Rup [kΩ] [kΩ] SIMAX [A] IMAX [A] (2) GFX VSA/DDR 40 29 35 21 30 13 10 1.5 10 2.7 22 6.8 10 3.6 25 5 27 11 40 29 12 5.6 35 21 82 43 30 13 13 7.5 25 5 56 36 40 29 18 13 35 21 15 12 30 13 18 16 25 5 15 14.7 40 29 10 11 35 21 18 22 30 13 56 75 25 5 10 15 40 29 12 20 35 21 12 22.6 30 13 39 82 25 5 47 110 40 29 10 27 35 21 22 68 30 13 10 36 25 5 18 75 40 29 15 75 35 21 10 59 30 13 10 75 25 5 10 100 40 29 10 150 35 21 10 220 30 13 10 Open 25 5 N ⋅ 25 + 56 N ⋅ 25 + 48 N ⋅ 25 + 40 N ⋅ 25 + 32 N ⋅ 25 + 24 N ⋅ 25 + 16 N ⋅ 25 + 8 N ⋅ 25 Doc ID 023992 Rev 1 23/59 Device configuration and pinstrapping tables L6751 1. Recommended values, divider needs to be connected between VCC5 pin and GND. 2. N is the number of phase programmed for the multi-phase section. Table 9. ADDR pinstrapping(1) (2) ADDR Rdown Rup [kΩ] [kΩ] 10 1.5 ADDR (3) PMBADDR (4) JMode DROOP multi-phase DROOP single-phase ON CCh 10 2.7 22 6.8 OFF ON C8h 10 3.6 OFF AMD mode 27 n/a ON 11 ON C4h 12 5.6 82 43 OFF ON C0h 13 7.5 56 36 OFF ON EEh 18 13 15 12 OFF ON EAh 18 16 15 14.7 10 11 18 22 OFF 0100b (VR12) n/a OFF ON E6h OFF ON E2h 56 75 10 15 OFF ON ECh 12 20 12 22.6 OFF ON E8h 39 82 47 110 10 27 22 68 OFF 0010b (VR12) n/a OFF ON E4h OFF ON E0h 10 24/59 36 OFF Doc ID 023992 Rev 1 L6751 Device configuration and pinstrapping tables ADDR pinstrapping(1) (2) (continued) Table 9. ADDR Rdown Rup [kΩ] [kΩ] 18 75 ADDR (3) PMBADDR JMode (4) DROOP multi-phase DROOP single-phase ON 15 75 10 59 OFF ON C8h / 88h 10 75 10 100 10 150 10 220 OFF 0000b (VR12) ON ON C4h / 84h OFF ON According to VBOOT settings (GFX / VSA) CCh / 8Ch C0h / 80h 10 Open OFF 1. Recommended values, divider needs to be connected between VCC5 pin and GND. 2. In DDR mode, when enabled, droop has 1/4th scaling factor. 3. SVI address for multi-phase. Single-phase is further offset by 0001b. In AMD mode, SVI address defaults according to AMD specifications. 4. PMBus address for multi-phase (read/write). Single-phase is further offset by 02h. When in VR12 CPU mode, RCOMP = 12.5 kΩ to GND, select between Cxh (Open) and 8xh (if installed) PMBus address. Table 10. . BOOT / TMAX pinstrapping(1) (2) BOOT - Intel address 0000b(3) Rdown Rup [kΩ] [kΩ] 10 1.5 10 2.7 Multiphase 6.8 10 3.6 TMAX [C] Link rest JMode 0.000 V VSA 11 12 5.6 43 13 7.5 120 110 100 1.500 V 130 1.000 V 82 Link rest 32 μsec (debug) 32 μsec (debug) ON 27 VBOOT 130 1.000 V 22 Singlephase Intel address 0010b, 0100b (3) 1.000 V VSA 32 μsec (debug) 10 μsec (functional) 120 110 100 Doc ID 023992 Rev 1 25/59 Device configuration and pinstrapping tables Table 10. L6751 BOOT / TMAX pinstrapping(1) (2) (continued) BOOT - Intel address 0000b(3) Rdown Rup [kΩ] [kΩ] 56 36 18 13 Multiphase 12 18 16 TMAX [C] Link rest JMode 1.100 V VSA 10 μsec (functional) 14.7 10 11 Link rest 32 μsec (debug) 120 110 100 ON 15 VBOOT 130 0.000 V 15 Singlephase Intel address 0010b, 0100b (3) 1.350 V 130 0.000 V 1.000 V VSA 10 μsec (functional) 10 μsec (functional) 120 18 22 56 75 100 10 15 130 12 20 0.000 V 12 22.6 39 82 0.900 V VSA 32 μsec (debug) 10 μsec (functional) 110 10 27 120 110 100 OFF 47 110 1.500 V 130 0.000 V 1.000 V GFX 32 μsec (debug) 10 μsec (functional) 120 22 68 10 36 100 18 75 130 15 75 1.000 V 10 59 10 75 1.000 V GFX 32 μsec (debug) 32 μsec (debug) 100 10 150 220 10 Open 1.350 V 0.000 V GFX 10 μsec (functional) 10 μsec (functional) 120 110 100 1. Recommended values, divider needs to be connected between VCC5 pin and GND. 2. BOOT is ignored in AMD mode, only TMAX is operative. 3. Operative mode defined by ADDR pin. See Table 9 for details. 26/59 110 130 0.000 V 10 120 100 OFF 10 110 Doc ID 023992 Rev 1 L6751 Device configuration and pinstrapping tables Table 11. DPM pinstrapping(1) Rdown Rup [kΩ] [kΩ] 10 1.5 DPM1-3(2)(3) DPM12 DPM23 DPM4-6(2)(3) GDC0 DPM34 DPM46 1 1 +22A +20A 10 2.7 22 6.8 0 0 1 1 +16A 10 3.6 +14A 0 0 +30A 16A 27 11 1 1 +10A 12 5.6 82 43 +8A 0 0 1 1 +6A 13 7.5 56 36 DPM OFF 0 0 1 1 +20A 18 13 15 12 +22A 0 0 1 1 +16A 18 16 +14A 0 12A 15 0 +22A 14.7 1 1 +10A 10 11 18 22 +8A 0 0 1 1 +6A 56 75 10 15 DPM OFF 0 0 1 1 +22A +20A 12 20 12 22.6 0 0 1 1 +16A 39 82 +14A 0 0 +14A 8A 47 110 1 1 +10A 10 27 22 68 +8A 0 0 1 1 +6A 10 36 18 75 DPM OFF 0 0 1 1 +22A +20A 15 75 10 59 0 0 1 1 +16A 10 10 75 100 +14A 0 OFF (12A)(4) 0 +8A 1 +10A 10 150 10 220 Open 1 +8A 0 1 +6A 10 GDC1 0 0 DPM OFF(5) 1 0 1. Suggested values, divider needs to be connected between VCC5 pin and GND. Doc ID 023992 Rev 1 27/59 Device configuration and pinstrapping tables L6751 2. Transition threshold specified as delta with respect to previous step (DPM23 is wrt DPM12). 3. GDC threshold is defined by combining GDC0 and GDC1 bits defined between the two different pinstrappings DPM1-3 and DPM4-6. See Table 12 for details. 4. Transition between 1Phase and 2Phase operation is set to 12 A but disabled in PS00h. 5. Dynamic phase management disabled, IC always working at maximum possible number of phases except from when in >PS00h when transitioning between 1Phase and 2Phase at 12 A. Table 12. GDC threshold definition(1) GDC1 GDC0 Threshold [A](2) 1 N ⋅ 17A 0 N ⋅ 13A 1 N ⋅ 9A 0 GDC OFF 1 0 1. GDC threshold is defined by combining GDC0 and GDC1 bits defined between the two different pinstrappings DPM1-3 and DPM4-6. See Table 11 for details. 2. N is the number of phase programmed for the multi-phase section. 28/59 Doc ID 023992 Rev 1 L6751 5 Device description and operation Device description and operation The L6751 is a programmable 4/5/6-phase PWM controller that provides complete control logic and protection to realize a high performance step-down DC-DC voltage regulator optimized for advanced microprocessor and memory power supply. The device features 2nd generation LTB Technology: through a load transient detector, it is able to turn on simultaneously all the phases. This allows the output voltage deviation to be minimized and, in turn, the system cost to be minimized by providing the fastest response to a load transition. The L6751 implements current reading across the inductor in fully differential mode. A sense resistor in series to the inductor can also be considered to improve reading precision. The current information read corrects the PWM output in order to equalize the average current carried by each phase. The controller supports Intel and AMD SVI bus and all the required registers. The platform may configure and program the defaults for the device through dedicated pinstrapping. A complete set of protections is available: overvoltage, undervoltage, overcurrent (perphase and total), and feedback disconnection guarantees the load to be safe in all circumstances. Special power management features like DPM, VFDE(a) and GDC modify phase number, gate driving voltage and switching frequency to optimize efficiency over the load range. The L6751 is available in WLPGA72 6x6 mm package. Figure 5. VCC5 VDRV Device initialization UVLO 2mSec POR UVLO UVLO VIN 50μSec EN ENVTT SVI BUS Command ACK but not executed PMBus Command Rejected SVI Packet SVI Packet V_SinglePhase 64μSec SVRRDY V_MultiPhase 64μSec VRRDY AM14813v1 a. VFDE feature can be enabled using dedicated PMBus command. See Section 12 for details. Doc ID 023992 Rev 1 29/59 Output voltage positioning 6 L6751 Output voltage positioning Output voltage positioning is performed by selecting the controller operative-mode, as per Table 6, for the two sections and by programming the droop function effect (see Figure 6). The controller reads the current delivered by each section by monitoring the voltage drop across the DCR inductors. The current (IDROOP / ISDROOP) sourced from the FB / SFB pins, directly proportional to the read current, causes the related section output voltage to vary according to the external RFB / RSFB resistor, therefore implementing the desired load-line effect. The L6751 embeds a dual remote-sense buffer to sense remotely the regulated voltage of each section without any additional external components. In this way, the output voltage programmed is regulated compensating for board and socket losses. Keeping the sense traces parallel and guarded by a power plane results in common mode coupling for any picked-up noise. Figure 6. Voltage positioning Protection Monitor IDROOP Ref. from DAC FB COMP RF VSEN RGND To VddCORE CF (Remote Sense) RFB 6.1 FBR AM14814v1 Multi-phase section - phase # programming The multi-phase section implements a flexible 3 to 6 interleaved-phase converter. To program the desired number of phases, simply short to VCC5 the PWMx signal that is not required, according to Table 7. Caution: For the disabled phase(s), the current reading pins need to be properly connected to avoid errors in current-sharing and voltage-positioning: CSxP needs to be connected to the regulated output voltage while CSxN needs to be connected to CSxP through the same RG resistor used for the active phases. 6.2 Multi-phase section - current reading and current sharing loop The L6751 embeds a flexible, fully-differential current sense circuitry that is able to read across inductor parasitic resistance or across a sense resistor placed in series to the inductor element. The fully-differential current reading rejects noise and allows the sensing element to be placed in different locations without affecting measurement accuracy. The trans- 30/59 Doc ID 023992 Rev 1 L6751 Output voltage positioning conductance ratio is issued by the external resistor RG placed outside the chip between the CSxN pin toward the reading points. The current sense circuit always tracks the current information; the CSxP pin is used as a reference keeping the CSxN pin to this voltage. To correctly reproduce the inductor current, an R-C filtering network must be introduced in parallel to the sensing element. The current that flows from the CSxN pin is then given by the following equation (see Figure 7): Equation 2 DCR 1 + s ⋅ L ⁄ DCR I CSxN = ------------- ⋅ -------------------------------------------- ⋅ I 1+s⋅ R⋅ C RG PHASEx Considering now the matching of the time constant between the inductor and the R-C filter applied (time constant mismatches cause the introduction of poles into the current reading network causing instability. In addition, it is also important for the load transient response and to let the system show resistive equivalent output impedance), it results: Equation 3 L ------------- = R ⋅ C DCR Figure 7. ⇒ RL I CSxN = -------- ⋅ I PHASEx = IINFOx RG Current reading IPHASEx Lx ICSxN=IINFOx DCRx VOUT R C CSxP CSxN RG Inductor DCR Current Sense AM14815v1 The current read through the CSxP / CSxN pairs is converted into a current IINFOx proportional to the current delivered by each phase and the information about the average current IAVG = ΣIINFOx / N is internally built into the device (N is the number of working phases). The error between the read current IINFOx and the reference IAVG is then converted into a voltage that, with a proper gain, is used to adjust the duty cycle whose dominant value is set by the voltage error amplifier in order to equalize the current carried by each phase. 6.3 Multi-phase section - defining load-line The L6751 introduces a dependence of the output voltage on the load current recovering part of the drop due to the output capacitor ESR in the load transient. Introducing a dependence of the output voltage on the load current, a static error, proportional to the output current, causes the output voltage to vary according to the sensed current. Figure 7 shows the current sense circuit used to implement the load-line. The current flowing across the inductor(s) is read through the R-C filter across the CSxP and CSxN pins. RG Doc ID 023992 Rev 1 31/59 Output voltage positioning L6751 programs a trans-conductance gain and generates a current ICSx proportional to the current of the phase. The sum of the ICSx current, with proper gain eventually adjusted by the PMBus commands, is then sourced by the FB pin (IDROOP). RFB gives the final gain to program the desired load-line slope (Figure 6). Time constant matching between the inductor (L / DCR) and the current reading filter (RC) is required to implement a real equivalent output impedance of the system, therefore avoiding over and/or undershoot of the output voltage as a consequence of a load transient. The output voltage characteristic vs. load current is then given by: Equation 4 DCR V OUT = VID – R FB ⋅ I DROOP = VID – RFB ⋅ ------------- ⋅ IOUT = VID – RLL ⋅ I OUT RG where RLL is the resulting load-line resistance implemented by the multi-phase section. The RFB resistor can be then designed according to the RLL specifications as follows: Equation 5 RG R FB = R LL ⋅ ------------DCR Caution: When in DDR mode, and enabled, droop current has a scaling factor equal to 1/4. All the above equations must be scaled accordingly. 6.4 Single-phase section - disable The single-phase section can be disabled by pulling high the SPWM pin. The related command is rejected. 6.5 Single-phase section - current reading The single-phase section performs the same differential current reading across DCR as the multi-phase section. According to Section 6.2, the current that flows from the SCSN pin is then given by the following equation (see Figure 7): Equation 6 DCR I SCSN = ------------- ⋅ I SOUT = I SDROOP R SG 6.6 Single-phase section - defining load-line This method introduces a dependence of the output voltage on the load current recovering part of the drop due to the output capacitor ESR in the load transient. Introducing a dependence of the output voltage on the load current, a static error, proportional to the output current, causes the output voltage to vary according to the sensed current. 32/59 Doc ID 023992 Rev 1 L6751 Output voltage positioning Figure 7 shows the current sense circuit used to implement the load-line. The current flowing across the inductor DCR is read through RSG. RSG programs a trans-conductance gain and generates a current ISDROOP proportional to the current delivered by the single-phase section that is then sourced from the SFB pin with proper gain eventually adjusted by the PMBus commands. RSFB gives the final gain to program the desired load-line slope (Figure 6). The output characteristic vs. load current is then given by: Equation 7 V SOUT = VID – R SFB ⋅ I SDROOP DCR VID – R SFB ⋅ ------------- ⋅ ISOUT = VID – RSLL ⋅ ISOUT R SG where RSLL is the resulting load-line resistance implemented by the single-phase section. The RSFB resistor can then be designed according to the RSLL as follows: Equation 8 R SG R SFB = R SLL ⋅ ------------DCR 6.7 Dynamic VID transition support The L6751 manages dynamic VID transitions that allow the output voltage of both sections to be modified during normal device operation for power management purposes. OV, UV and OC signals are masked during every DVID transition and they are re-activated with proper delay to prevent from false triggering. When changing dynamically the regulated voltage (DVID), the system needs to charge or discharge the output capacitor accordingly. This means that an extra-current IDVID needs to be delivered (especially when increasing the output regulated voltage) and it must be considered when setting the overcurrent threshold of both sections. This current results: Equation 9 dV OUT I DVID = C OUT ⋅ -----------------dT VID where dVOUT / dTVID depends on the specific command issued (20 mV/μsec for SetVID_Fast and 5 mV/μsec for SetVID_Slow). Overcoming the total OC threshold during the dynamic VID causes the device to latch and disable. Set proper filtering on ILIM to prevent from false total-OC tripping. As soon as the controller receives a new valid command to set the VID level for one (or both) of the two sections, the reference of the involved section steps up or down according to the target-VID with the programmed slope until the new code is reached. If a new valid command is issued during the transition, the device updates the target-VID level and performs the dynamic transition up to the new code. OV, UV are masked during the transition and re-activated with proper delay after the end of the transition to prevent from false triggering. Doc ID 023992 Rev 1 33/59 Output voltage positioning 6.7.1 L6751 LSLESS startup and pre-bias output Any time the device resumes from an “OFF” code and at the first power-up, in order to avoid any kind of negative undershoot on the load side, the L6751 performs a special sequence in enabling the drivers: during the soft-start phase, the LS driver results as being disabled (LS=OFF - PWMx set to HiZ and ENDRV = 0) until the first PWM pulse. After the first PWM pulse, PWMx outputs switch between logic “0” and logic “1” and ENDRV is set to logic “1”. This particular sequence avoids the dangerous negative spike on the output voltage that can occur if starting over a pre-biased output. Low-side MOSFET turn-on is masked only from the control loop point of view: protection is still allowed to turn on the low-side MOSFET if overvoltage is needed. Figure 8. LSLESS startup: enabled (left) Figure 9. 6.8 DVID optimization: REF/SREF LSLESS startup: disabled (right) High slew rate for dynamic VID transitions causes undershoot on the regulated voltage, causing violation in the microprocessor requirement. To compensate this behavior and to remove any undershoot in the transition, each section features a DVID optimization circuit. The reference used for the regulation is available on the REF/SREF pin (see Figure 10). Connect an RREF/CREF to GND (RSREF/CSREF for the single-phase) to optimize the DVID behavior. Components may be designed as follows (multi-phase, the same equations apply to single-phase): Equation 10 ΔV OSC ⎞ C REF = C F ⋅ ⎛ 1 – ---------------------⎝ k ⋅ V ⎠ V IN RF ⋅ CF R REF = --------------------C REF where ΔVosc is the PWM ramp and kV the gain for the voltage loop (see Section 11). During a falling DVID transition, the REF pin moves according to the DVID command issued; the current requested to charge/discharge the RREF/CREF network is mirrored and added to the droop current compensating for undershoot on the regulated voltage. 34/59 Doc ID 023992 Rev 1 L6751 Output voltage positioning IDROOP Figure 10. DVID optimization circuit Ref. from DAC Ref COMP FB REF RREF RF CREF CF VSEN V COMP Ref FBR RGND To VddCORE (Remote Sense) ZF(s) ZFB(s) RFB Doc ID 023992 Rev 1 AM14817v1 35/59 Output voltage monitoring and protection 7 L6751 Output voltage monitoring and protection The L6751 monitors the regulated voltage of both sections through pin VSEN and SVSEN in order to manage OV and UV. The device shows different thresholds when in different operative conditions but the behavior in response to a protection event is still the same as described below. Protection is active also during soft-start while it is properly masked during DVID transitions with an additional delay to avoid false triggering. OV protection is active during DVID with threshold modified to 1.8 V unless offset has been commanded by SVI or PMBus: in this case the fixed threshold is 2.4 V. Table 13. L6751 protection at a glance Section Multi-phase Overvoltage (OV) Undervoltage (UV) Overcurrent (OC) Dynamic VID 7.1 Single-phase VSEN, SVSEN = +175 mV above reference. Action: IC latch; LS = ON & PWMx = 0 (if applicable); other section: HiZ.VR_READY of the latched section resets (only). VSEN, SVSEN = 400 mV below reference. Active after Ref > 500 mV. Action: IC latch; both sections HiZ. VR_READY of the latched section resets (only). Current monitor across inductor DCR. Dual protection, per-phase and total. Action: UV-Like. VR_READY of the latched section resets (only). Protection masked with additional delay to prevent from false triggering. Overvoltage When the voltage sensed by VSEN and/or SVSEN surpasses the OV threshold, the controller acts in order to protect the load from excessive voltage levels avoiding any possible undershoot. To reach this target, a special sequence is performed as per the following list: – The reference performs a DVID transition down to 250 mV on the section which triggered the OV protection. – The PWMs of the section which triggered the protection are switched between HiZ and zero (ENDRV is kept high) in order to follow the voltage imposed by the DVID on-going. This limits the output voltage excursion, protects the load and assures no undershoot is generated (if Vout < 250 mV, the section is HiZ). – The PWMs of the non-involved section are set permanently to HiZ (ENDRV is kept low) in order to realize a HiZ condition. – OSC/ FLT pin is driven high. – Power supply or EN pin cycling is required to restart operation. If the cause of the failure is removed, the converter ends the transition with all PWMs in HiZ state and the output voltage of the section which triggered the protection lower than 250 mV. 36/59 Doc ID 023992 Rev 1 L6751 7.2 Output voltage monitoring and protection Overcurrent and current monitor The overcurrent threshold must be programmed to a safe value, in order to be sure that each section does not enter OC during normal operation of the device. This value must take into consideration also the process spread and temperature variations of the sensing elements (inductor DCR). Furthermore, since also the internal threshold spreads, the design must consider the minimum/maximum values of the threshold. 7.2.1 Multi-phase section The L6751 features two independent load indicator signals, IMON and ILIM, to properly manage OC protection, current monitoring and DPM. Both IMON and ILIM source a current proportional to the current delivered by the regulator, as follows: Equation 11 DCR I MON = I LIM = ------------- ⋅ IOUT RG The IMON and ILIM pins are connected to GND through a resistor (RIMON and RILIM respectively), implementing a load indicator with different targets. ● IMON is used for current reporting purposes and for the DPM phase shedding. RIMON must be designed considering that IMAX must correspond to 1.24 V (for correct IMAX detection). ● ILIM is used for the overcurrent protection only. RILIM must be designed considering that the OC protection is triggered when V(ILIM)=2.5 V. In addition, the L6751 also performs per-phase OC protection. – Per-phase OC. Maximum information current per-phase (IINFOx) is internally limited to 35 μA. This end-of-scale current (IOC_TH) is compared with the information current generated for each phase (IINFOx). If the current information for the single-phase exceeds the end-of-scale current (i.e. if IINFOx > IOC_TH), the device turns on the LS MOSFET until the threshold is re-crossed (i.e. until IINFOx < IOC_TH). – Total current OC. the ILIM pin allows a maximum total output current for the system (IOC_TOT) to be defined. ILIM current is sourced from the ILIM pin. By connecting a resistor RILIM to GND, a load indicator with 2.5 V (VOC_TOT) end-ofscale can be implemented. When the voltage present at the ILIM pin crosses VOC_TOT, the device detects an OC and immediately latches with all the MOSFETs of all the sections OFF (HiZ). Typical design considers the intervention of the total current OC before the per-phase OC, leaving this last one as an extreme-protection in case of hardware failures in the external components. Per-phase OC depends on the RG design while total OC is dependant on the ILIM design and on the application TDC and max. current supported. Typical design flow is the following: – Define the maximum total output current (IOC_TOT) according to system requirements (IMAX, ITDC). Considering IMON design, IMAX must correspond to 1.24 V (for correct IMAX detection) while considering ILIM design IOC_TOT must correspond to 2.5 V. – Design per-phase OC and RG resistor in order to have IINFOx = IOC_TH (35 μA) when IOUT is about 10% higher than the IOC_TOT current. It results: Doc ID 023992 Rev 1 37/59 Output voltage monitoring and protection L6751 Equation 12 ( 1.1 ⋅ IOC_TOT ) ⋅ DCR RG = ------------------------------------------------------------N ⋅ IOCTH where N is the number of phases and DCR the DC resistance of the inductors. RG should be designed in worst-case conditions. – Design the RIMON in order to have the IMON pin voltage to 1.24 V at the IMAX current specified by the design. It results: Equation 13 1.24V ⋅ R G R IMON = -------------------------------I MAX ⋅ DCR where IMAX is max. current requested by the processor (see Intel docs for details). – Design the RILIM in order to have the ILIM pin voltage to 2.5 V at the IOC_TOT current specified above. It results: Equation 14 2.5V ⋅ RG R ILIM = ----------------------------------------I OC_TOT ⋅ DCR where IOC_TOT is the overcurrent switch-over threshold previously defined. Note: – Adjust the defined values according to application bench testing. – CILIM in parallel to RILIM can be added with proper time constant to prevent false OC tripping and/or delay. – CIMON in parallel to RIMON can be added to adjust the averaging interval for the current reporting and/or adjust the DPM latencies. Additionally, it can be increased to prevent false total-OC tripping during DVID. This is the typical design flow. Custom design and specifications may require different settings and ratios between the per-phase OC threshold and the total current OC threshold. Applications with big ripple across inductors may be required to set per-phase OC to values different than 110%: design flow should be modified accordingly. Current reporting precision on IMON may be affected by external layout. The internal ADC is referenced to the device GND pin: in order to perform the highest accuracy in the current monitor, RIMON must be routed to the GND pin with dedicated net to avoid GND plane drops affecting the precision of the measurement. 7.2.2 Overcurrent and power states When the controller receives an SetPS command through the SVI interface, it automatically changes the number of working phases. In particular, the maximum number of phases which L6751 may work in >PS00h is limited to 2 phases regardless of the number N configured in PS00h. OC level is then scaled as the controller enters >PS00h, as per Table 14. 38/59 Doc ID 023992 Rev 1 L6751 Output voltage monitoring and protection Table 14. Multi-phase section OC scaling and power states Power state [Hex] N OC level (VOC_TOT) 00h 3 to 6 2.500 V 3 1.650 V 4 1.250 V 5 1.000 V 6 0.830 V 01h, 02h 7.2.3 Single-phase section The L6751 performs two different kinds of OC protection for the single-phase section: it monitors both the total current and the per-phase current and allows an OC threshold to be set for both. – Per-phase OC. Maximum information current per-phase (ISINFOx) is internally limited to 35 μA. This end-of-scale current (ISOC_TH) is compared with the information current generated for each phase (ISINFOx). If the current information for the single-phase exceeds the end-of-scale current (i.e. if ISINFOx > ISOC_TH), the device turns on the LS MOSFET until the threshold is re-crossed (i.e. until ISINFOx < ISOC_TH). – Total current OC. The SIMON pin allows a maximum total output current for the system (ISOC_TOT) to be defined. ISMON current is sourced from the SIMON pin. By connecting a resistor RSIMON to GND, a load indicator with 1.55 V (VSOC_TOT) endof-scale can be implemented. When the voltage present at the SIMON pin crosses VSOC_TOT, the device detects an OC and immediately latches with all the MOSFETs of all the sections OFF (HiZ). Typical design considers the intervention of the total current OC before the per-phase OC, leaving this last one as an extreme protection in case of hardware failures in the external components. Total current OC is, moreover, dependant on the SIMON design and on the application TDC and MAX current supported. Typical design flow is the following: – Define the maximum total output current (ISOC_TOT) according to system requirements (ISMAX, ISTDC). Considering ISMON design, ISMAX must correspond to 1.24 V (for correct SIMAX detection) so ISOC_TOT results defined, as a consequence, as I SOC_TOT = I SMAX ⋅ 1.55 ⁄ 1.24 – Design per-phase OC and RSG resistor in order to have ISINFOx = ISOC_TH (35 μA) when ISOUT is about 10% higher than the ISOC_TOT current. It results: Equation 15 ( 1.1 ⋅ ISOC_TOT ) ⋅ DCR R SG = ----------------------------------------------------------------I SOCTH where DCR is the DC resistance of the inductors. RSG should be designed in worst-case conditions. – Design the total current OC and RSIMON in order to have the SIMON pin voltage to 1.24 V at the ISMAX current specified by the design. It results: Doc ID 023992 Rev 1 39/59 Output voltage monitoring and protection L6751 Equation 16 1.24V ⋅ R SG R SIMON = -----------------------------------I SMAX ⋅ DCR DCR ⎛I = ------------- ⋅ I SOUT⎞ ⎝ SIMON R SG ⎠ where ISMAX is max. current requested by the processor (see Intel docs for details). Note: 40/59 – Adjust the defined values according to application bench tests. – CSIMON in parallel to RSIMON can be added with proper time constant to prevent false OC tripping. This is the typical design flow. Custom design and specifications may require different settings and ratios between the per-phase OC threshold and the total current OC threshold. Applications with big ripple across inductors may be required to set per-phase OC to values different than 110%: design flow should be modified accordingly. Doc ID 023992 Rev 1 L6751 8 Single NTC thermal monitor and compensation Single NTC thermal monitor and compensation The L6751 features single NTC for thermal sensing for both thermal monitoring and compensation. Thermal monitor consists in monitoring the converter temperature eventually reporting alarm by asserting the VR_HOT signal. This is the base for the temperature reporting. Thermal compensation consists in compensating the inductor DCR derating with temperature, so preventing drifts in any variable correlated to the DCR: voltage positioning, overcurrent (ILIM), IMON, current reporting. Both the functions share the same thermal sensor (NTC) to optimize the overall application costs without compromising performance. The thermal monitor is featured for both single-phase and multi-phase sections. 8.1 Thermal monitor and VR_HOT The diagram for the thermal monitor is reported in Figure 11. NTC should be placed close to the power stage hot-spot in order to sense the regulator temperature. As the temperature of the power stage increases, the NTC resistive value decreases, therefore reducing the voltage observable at the TM/STM pin. Recommended NTC is NTHS0805N02N6801HE for accurate temperature sensing and thermal compensation. Different NTC may be used: to reach the requested accuracy in temperature reporting, the proper resistive network must be used in order to match the resulting characteristic with the one coming from the recommended NTC. The voltage observed at the TM/STM pin is internally converted and then used for the temperature reporting. When the temperature observed on one of the two thermal sensors exceeds TMAX (programmed via pinstrapping), the L6751 asserts VR_HOT (active low - as long as the overtemperature event lasts). Figure 11. Thermal monitor connections 2k NTC TM TEMPERATURE DECODING VCC5 VR_HOT Temp. Zone AM14818v1 8.2 Thermal compensation The L6751 supports DCR sensing for output voltage positioning: the same current information used for voltage positioning is used to define the overcurrent protection and the current reporting. Having imprecise and temperature-dependant information leads to violation of the specification and misleading information: positive thermal coefficient specific from DCR needs to be compensated to get stable behavior of the converter as temperature Doc ID 023992 Rev 1 41/59 Single NTC thermal monitor and compensation L6751 increases. Un-compensated systems show temperature dependencies on the regulated voltage, overcurrent protection and current reporting. The temperature information available on the TM/STM pin and used for thermal monitoring may be used also for this purpose. By comparing the voltage on the TM/STM pin with the voltage present on the TCOMP/STCOMP pin, the L6751 corrects the IDROOP/ISDROOP current used for voltage positioning (see Section 6.3), so recovering the DCR temperature deviation. Depending on NTC location and distance from the inductors and the available airflow, the correlation between NTC temperature and DCR temperature may be different: TCOMP/STCOMP adjustments allow the gain between the sensed temperature and the correction made on the IDROOP/ISDROOP current to be modified. Short TCOMP/STCOMP to GND to disable thermal compensation (no correction of IDROOP/ISDROOP is made). 8.3 TM/STM and TCOMP/STCOMP design This procedure applies to both single-phase and multi-phase sections. 1. 42/59 Properly choose the resistive network to be connected to the TM pin. Recommended values/network is reported in Figure 11. 2. Connect voltage generator to the TCOMP pin (default value 3.3 V). 3. Power on the converter and load the thermal design current (TDC) with the desired cooling conditions. Record the output voltage regulated as soon as the load is applied. 4. Wait for thermal steady-state. Adjust down the voltage generator on the TCOMP pin in order to get the same output voltage recorded at point #3. 5. Design the voltage divider connected to TCOMP (between VCC5 and GND) in order to get the same voltage set to TCOMP at point #4. 6. Repeat the test with the TCOMP divider designed at point #5 and verify the thermal drift is acceptable. In the case of positive drift (i.e. output voltage at thermal steadystate is bigger than output voltage immediately after loading TDC current), change the divider at the TCOMP pin in order to reduce the TCOMP voltage. In the case of negative drift (i.e. output voltage at thermal steady-state is smaller than output voltage immediately after loading TDC current), change the divider at the TCOMP pin in order to increase the TCOMP voltage. 7. The same procedure can be implemented with a variable resistor in place of one of the resistors of the divider. In this case, once the compensated configuration is found, simply replace the variable resistor with a resistor with the same value. Doc ID 023992 Rev 1 L6751 9 Efficiency optimization Efficiency optimization As per VR12 specifications, the SVI master may define different power states for the VR controller. This is performed by SetPS commands. The L6751 re-configures itself to improve overall system efficiency, according to Table 15. Table 15. Efficiency optimization Feature 9.1 PS00h PS01h DPM According to pinstrapping Active. 1Phase/2Phase according to Iout VFDE Active when in single-phase and DPM enabled Active when in single-phase GDC 12 V driving GDC set to 5 V Dynamic phase management (DPM) Dynamic phase management allows the number of working phases to be adjusted according to the delivered current still maintaining the benefits of the multi-phase regulation. Phase number is reduced by monitoring the voltage level across the IMON pin: the L6751 reduces the number of working phases according to the strategy defined by the DPM pinstrapping and/or PMBus (TM) commands received (see Table 11). DPM12 refers to the current at which the controller changes from 1 to 2 phases. In the same way, DPM23 defines the current at which the controller changes from 2 to 3 phases and so on. When DPM is enabled, the L6751 starts monitoring the IMON voltage for phase number modification after VR_RDY has transition high: the soft-start is then implemented in interleaving mode with all the available phases enabled. DPM is reset in the case of an SetVID command that affects the CORE section and when LTB Technology detects a load transient. After being reset, if the voltage across IMON is compatible, DPM is re-enabled after proper delay. Delay in the intervention of DPM can be adjusted by properly sizing the filter across the IMON pin. Increasing the capacitance results in increased delay in the DPM intervention. See Section 7.2.1 for guidelines in designing the IMON load indicator. Note: During load transients with light slope, the filtering of IMON may result too slow for the IC to set the correct number of phases required for the current effectively loading the system (LTB does not trigger in the case of light slopes). The L6751 features a safety mechanism which re-enables phases that were switched off by comparing ILIM and IMON pin voltage. In fact, the ILIM pin is lightly filtered in order to perform fast reaction of OC protection while IMON is heavily filtered to perform correct averaging of the information. While working continuously in DPM, the device compares the information of IMON and ILIM: ILIM voltage is divided in N steps whose width is VOCP/(2*N) (where VOCP = 2.5 V and N the number of stuffed phases). If the DPM phase number resulting from IMON is not coherent with the step in which ILIM stays, the phase number is increased accordingly. The mechanism is active only to increase the phase number which is reduced again by DPM. Doc ID 023992 Rev 1 43/59 Efficiency optimization 9.2 L6751 Variable frequency diode emulation (VFDE) As the current required by the load is reduced, the L6751 progressively reduces the number of switching phases according to DPM settings on the multi-phase section. If single-phase operation is configured, when the delivered current approaches the CCM/DCM boundary, the controller enters VFDE operation. The single-phase section, being a single-phase, enters VFDE operation always when the delivered current approaches the CCM/DCM boundary. In a common single-phase DC-DC converter, the boundary between CCM and DCM is when the delivered current is perfectly equal to 1/2 of the peak-to-peak ripple into the inductor (Iout = Ipp/2). Further decreasing the load in this condition maintaining CCM operation would cause the current into the inductor to reverse, therefore sinking current from the output for a part of the off-time. This results in a poorly efficient system. The L6751 is able (via the CSPx/CSNx pins) to detect the sign of the current across the inductor (zero cross detection, ZCD), so it is able to recognize when the delivered current approaches the CCM/DCM boundary. In VFDE operation, the controller fires the high-side MOSFET for a TON and the low-side MOSFET for a TOFF (the same as when the controller works in CCM mode) and waits the necessary time until next firing in high impedance (HiZ). The consequence of this behavior is a linear reduction of the “apparent” switching frequency that, in turn, results in an improvement of the efficiency of the converter when in very light load conditions. The “apparent” switching frequency reduction is limited to 30 kHz so as not to enter the audible range. Figure 12. Output current vs. switching frequency in PSK mode Iout = Ipp/2 Iout < Ipp/2 t t Tsw Tsw Tvfde AM14819v1 9.2.1 VFDE and DrMOS To guarantee correct behavior for the DrMOS power stage compliant with Intel specification rev3, it is recommended to control the DrMOS’ SMOD input through the ENDRV/SENDRV pins of the L6751. DrMOS enable must be controlled with the same signal used for the L6751 EN pin. 44/59 Doc ID 023992 Rev 1 L6751 Efficiency optimization Proper HiZ level can be programmed by adding proper external resistor divider across PWM1 and PWM2. See Section 4.2 for details about HiZ level recognition. See reference schematic in Figure 1. 9.3 Gate drive control (GDC) Gate drive control (GDC) is a proprietary function which allows the L6751 to dynamically control the Power MOSFET driving voltage in order to further optimize the overall system efficiency. According to the SVI power state commanded and the configuration received through the PMBus, the device switches this pin (GDC) between the VCC5 or VDRV (inputs). By connecting the power supply of external drivers directly to this pin, it is then possible to carefully control the external MOSFET driving voltage. In fact, high driving voltages are required to obtain good efficiency in high loading conditions. On the contrary, in lower loading conditions, such high driving voltage penalizes efficiency because of high losses in Qgs. GDC allows to tune the MOSFET driving voltage according to the delivered current. The default configuration considers GDC always switched to VDRV except when entering power states higher than PS01h (included): in this case, to further increase efficiency, simply supply the Phase1 and Phase2 driver through the GDC pin. Their driving voltage is automatically updated as lower power states are commanded through the SVI interface. Further optimization may be possible by properly setting the automatic GDC threshold through the dedicated PMBus command and/or pinstrapping. It is then possible to enable the gate driving voltage switchover even in PS00h. According to the positioning of the threshold compared with DPM thresholds, it is possible to achieve different performances. Simulations and/or bench tests may be of help in defining the best performing configuration achievable with the active and passive components available. Figure 13 allows the efficiency improvements with DPM/GDC enabled to be compared with respect to the standard solution. Note: Systems supporting S3 power state may have the VDRV supplied by an OR-ing connection between 5 Vsby and 12 V or different supply voltage for S0. It is recommended to connect closely, between the VDRV and VCC5 pins, the OR-ing diode connecting VDRV to the 5 Vsby. Figure 13. Efficiency performance with and without enhancements (DPM, GDC) Doc ID 023992 Rev 1 45/59 Main oscillator 10 L6751 Main oscillator The internal oscillator generates the triangular waveform for the PWM charging and discharging, with a constant current, on the internal capacitor. The switching frequency for each channel is internally fixed at 200 kHz (FSW) and at 230 kHz (FSSW): the resulting switching frequency at the load side for the multi-phase section results in being multiplied by N (number of configured phases). The current delivered to the oscillator is typically 20 μA and may be varied using an external resistor (ROSC, RSOSC) typically connected between the OSC/SOSC pins and GND. Since the OSC/SOSC pins are fixed at 1.02 V, the frequency is varied proportionally to the current sunk from the pin considering the internal gain of 10 KHz/μA for the multi-phase section and of 11.5 kHz/μA for the single-phase section, see Figure 14. Connecting ROSC/RSOSC to SGND, the frequency is increased (current is sunk from the pin), according to the following relationships: Equation 17 1.02V kHz FSW = 200kHz + --------------------------- ⋅ 10 ----------R OSC ( kΩ) μA Equation 18 1.02V kHz FSSW = 250kHz + ------------------------------- ⋅ 11.5 ----------R SOSC ( kΩ) μA Connecting ROSC/RSOSC to a positive voltage Vbias, the frequency is reduced (current is injected into the pin), according to the following relationships: Equation 19 Vbias – 1.02V kHz FSW = 200kHz – -------------------------------------- ⋅ 10 ----------R OSC ( kΩ) μA Equation 20 Vbias – 1.02V kHz FSSW = 250kHz – -------------------------------------- ⋅ 11.5 ----------R SOSC ( kΩ) μA Figure 14. ROSC vs. FSW per phase (ROSC to GND - left; ROSC to 3.3 V - right) 1000 1000 100 Multi Phase section SinglePhase section Multi Phase section SinglePhase section 100 10 200 300 400 500 600 700 800 900 1000 75 100 125 150 175 200 225 AM14820v1 46/59 Doc ID 023992 Rev 1 L6751 System control loop compensation The control system can be modeled with an equivalent single-phase converter with the only difference being the equivalent inductor L/N (where each phase has an L inductor and N is the number of the configured phases), see Figure 15. Figure 15. Equivalent control loop. PWM d VCOMP L/N VOUT RO ESR CO IDROOP COMP RF VSEN V COMP Ref FB 11 System control loop compensation FBR RGND CF ZF(s) ZFB(s) RFB AM14821v1 The control loop gain results (obtained opening the loop after the COMP pin): Equation 21 PWM ⋅ ZF ( s ) ⋅ ( R LL + ZP ( s ) ) G LOOP ( s ) = – -----------------------------------------------------------------------------------------------------------------------ZF ( s ) ⎛ 1 ⎞ [ Z P ( s ) + Z L ( s ) ] ⋅ -------------- + 1 + ------------ ⋅ R FB A(s ) ⎝ A ( s )⎠ where: ● RLL is the equivalent output resistance determined by the droop function (voltage positioning) ● ZP(s) is the impedance resulting from the parallel of the output capacitor (and its ESR) and the applied load RO ● ZF(s) is the compensation network impedance ● ZL(s) is the equivalent inductor impedance ● A(s) is the error amplifier gain ● V IN 9 PWM = ------ ⋅ ------------------10 ΔVOSC is the PWM transfer function. The control loop gain is designed in order to obtain a high DC gain to minimize static error and to cross the 0 dB axes with a constant -20 dB/dec slope with the desired crossover frequency ωT. Neglecting the effect of ZF(s), the transfer function has one zero and two poles; both poles are fixed once the output filter is designed (LC filter resonance ωLC) and the zero (ωESR) is fixed by ESR and the droop resistance. Doc ID 023992 Rev 1 47/59 System control loop compensation L6751 Figure 16. Control loop bode diagram and fine tuning dB dB CF GLOOP(s) GLOOP(s) K K ZF(s) RF[dB] ZF(s) RF[dB] RF ω LC = ω F ω ESR ωT ω ω LC = ω F ω ESR ωT ω AM14822v1 To obtain the desired shape, an RF-CF series network is considered for the ZF(s) implementation. A zero at ωF=1/RFCF is then introduced together with an integrator. This integrator minimizes the static error while placing the zero ωF in correspondence with the LC resonance and assures a simple -20 dB/dec shape of the gain. In fact, considering the usual value for the output filter, the LC resonance results as being at a frequency lower than the above reported zero. The compensation network can be designed as follows: Equation 22 R FB ⋅ ΔV OSC 10 F SW ⋅ L R F = ------------------------------------- ⋅ ------ ⋅ ---------------------------------V IN ( RLL + ESR ) 9 Equation 23 CO ⋅ L C F = ---------------------RF 11.1 Compensation network guidelines The compensation network design assures a system response according to the crossover frequency selected and to the output filter considered: it is however possible to further fine tune the compensation network by modifying the bandwidth in order to get the best response of the system as follows (see Figure 16): – Increase RF to increase the system bandwidth accordingly. – Decrease RF to decrease the system bandwidth accordingly. – Increase CF to move ωF to low frequencies, increasing as a consequence the system phase margin. Having the fastest compensation network does not guarantee that the load requirements are satisfied: the inductor still limits the maximum dI/dt that the system can afford. In fact, when a load transient is applied, the best that the controller can do is to “saturate” the duty cycle to its maximum (dMAX) or minimum (0) value. The output voltage dV/dt is then limited by the inductor charge/discharge time and by the output capacitance. In particular, the most limiting transition corresponds to the load-removal since the inductor results as being discharged only by Vout (while it is charged by VIN-VOUT during a load appliance). 48/59 Doc ID 023992 Rev 1 L6751 System control loop compensation Note: The introduction of a capacitor (CI) in parallel to RFB significantly speeds up the transient response by coupling the output voltage dV/dt on the FB pin, so using the error amplifier as a comparator. The COMP pin suddenly reacts and, also thanks to the LTB Technology control scheme, all the phases can be turned on together to immediately give the required energy to the output. Typical design considers starting from values in the range of 100 pF, and validating the effect by bench testing. Additional series resistor (RI) can also be used. 11.2 LTB Technology LTB Technology further enhances the performance of the controller by reducing the system latencies and immediately turning on all the phases to provide the correct amount of energy to the load optimizing the output capacitor count. LTB Technology monitors the output voltage through a dedicated pin detecting loadtransients with selected dV/dt, it cancels the interleaved phase-shift, turning on simultaneously all phases. The LTB detector is able to detect output load transients by coupling the output voltage through an RLTB - CLTB network. After detecting a load transient, all the phases are turned on together and the EA latencies also result as bypassed. Sensitivity of the load transient detector can be programmed in order to control precisely both the undershoot and the ring-back. LTB Technology design tips. – Decrease RLTB to increase the system sensitivity making the system sensitive to smaller dVOUT – Increase CLTB to increase the system sensitivity making the system sensitive to higher dV/dt – Increase Ri to increase the width of the LTB pulse – Increase Ci to increase the LTB sensitivity over frequency. Doc ID 023992 Rev 1 49/59 PMBus support (preliminary) 12 L6751 PMBus support (preliminary) The L6751 is compatible with PMBus™ standard revision 1.1, refer to PMBus standard documentation for further information (www.pmbus.org). Table 16. Supported commands Per Rail Code [Hex] Mode Comments Y 01 RW Byte Used to turn the controller on/off in conjunction with the input from the control pin. Also used to set margin voltages. Soft off not supported ON_OFF_CONFIG N1 02 RW Byte Configures how the controller responds when power is applied WRITE_PROTECT Y 10 RW Byte Controls writing to the PMBus device to prevent accidental changes VOUT_COMMAND Y 21 RW Word Causes the converter to set its output voltage to the commanded value - VID mode VOUT_MAX Y 24 RW Word Sets the upper limit on the output voltage regardless of any other command VOUT_MARGIN_HIGH Y 25 RW Word Sets the voltage to which the output is to be changed when the OPERATION command is set to “margin high” VOUT_MARGIN_LOW Y 26 RW Word Sets the voltage to which the output is to be changed when the OPERATION command is set to “margin low” IOUT_CAL_OFFSET Y 39 RW Word Calibration for IOUT reading OT_FAULT_LIMIT Y 4F RW Word Overtemperature fault threshold OT_WARN_LIMIT Y 51 RW Word Overtemperature warning threshold VIN_OV_FAULT_LIMIT N 55 RW Word Input voltage monitor overvoltage limit VIN_UV_FAULT_LIMIT N 59 RW Word Input voltage monitor undervoltage limit MFR_SPECIFIC_01 N D1 RW Byte AVERAGE_TIME_SCALE. Sets the time between two measurements MFR_SPECIFIC_02 Y D2 RW Byte DEBUG_MODE. [01/10] Switches [ON/OFF] the Vout control on PMBus domain MFR_SPECIFIC_05 Y D5 RW Byte VOUT_TRIM. Used to apply a fixed offset voltage to the output voltage command value MFR_SPECIFIC_08 Y D8 RW Byte VOUT_DROOP. Used to change the Vout droop MFR_SPECIFIC_35 N1 F3 RW Byte MANUAL_PHASE_SHEDDING. Used to manage the phase shedding manually MFR_SPECIFIC_38 Y F6 RW Byte VOUT_OV_FAULT_LIMIT. Allows the OV protection threshold to be programmed for each rail MFR_SPECIFIC_39 Y F7 RW Byte VFDE_ENABLE MFR_SPECIFIC_40 Y F8 RW Byte ULTRASONIC_ENABLE Command OPERATION 50/59 Doc ID 023992 Rev 1 L6751 Table 16. PMBus support (preliminary) Supported commands Per Rail Code [Hex] Mode MFR_SPECIFIC_41 N1 F9 RW Byte GDC_THRESHOLD. To access the internal register to set GDC threshold [A] MFR_SPECIFIC_42 N1 FA RW Byte DPM12_THRESHOLD. To access the internal register to set the DPM12 threshold [A] MFR_SPECIFIC_43 N1 FB RW Byte DPM23_THRESHOLD. To access the internal register to set the DPM23 threshold [A] MFR_SPECIFIC_44 N1 FC RW Byte DPM34_THRESHOLD. To access the internal register to set the DPM34 threshold [A] MFR_SPECIFIC_45 N1 FD RW Byte DPM46_THRESHOLD. To access the internal register to set the DPM46 threshold [A] CAPABILITY N 19 R Byte Provides a way for a host system to determine key capabilities of a PMBus device, such as maximum bus speed and PMBus alert. VOUT_MODE N 20 R Byte The device operates in VID mode PMBUS_REVISION N 98 R Byte Revision of the PMBus which the device is compliant to MFR_ID N 99 R Block Returns the manufacturers ID MFR_MODEL N 9A R Block Returns manufacturers model number MFR_REVISION N 9B R Block Returns the device revision number MFR_SPECIFIC_EXT ENDED_COMMAND_ 00 Y 00 R Byte VR12_STATUS1 MFR_SPECIFIC_EXT ENDED_COMMAND_ 01 Y 01 R Byte VR12_STATUS2 MFR_SPECIFIC_EXT ENDED_COMMAND_ 02 Y 02 R Byte VR12_TEMPZONE MFR_SPECIFIC_EXT ENDED_COMMAND_ 03 Y 03 R Byte VR12_IOUT MFR_SPECIFIC_EXT ENDED_COMMAND_ 05 Y 05 R Byte VR12_VRTEMP MFR_SPECIFIC_EXT ENDED_COMMAND_ 07 Y 07 R Byte VR12_STATUS2_LASTREAD MFR_SPECIFIC_EXT ENDED_COMMAND_ 08 Y 08 R Byte VR12_ICCMAX MFR_SPECIFIC_EXT ENDED_COMMAND_ 09 Y 09 R Byte VR12_TEMPMAX Command Comments Doc ID 023992 Rev 1 51/59 PMBus support (preliminary) Table 16. L6751 Supported commands Command Per Rail Code [Hex] Mode MFR_SPECIFIC_EXT ENDED_COMMAND_ 10 Y 0A R Byte VR12_SRFAST MFR_SPECIFIC_EXT ENDED_COMMAND_ 11 Y 0B R Byte VR12_SRSLOW MFR_SPECIFIC_EXT ENDED_COMMAND_ 12 Y 0C R Byte VR12_VBOOT MFR_SPECIFIC_EXT ENDED_COMMAND_ 13 Y 0D R Byte VR12_VOUTMAX MFR_SPECIFIC_EXT ENDED_COMMAND_ 14 Y 0E R Byte VR12_VIDSETTING MFR_SPECIFIC_EXT ENDED_COMMAND_ 15 Y 0F R Byte VR12_PWRSTATE MFR_SPECIFIC_EXT ENDED_COMMAND_ 16 Y 10 R Byte VR12_OFFSET CLEAR_FAULTS N 03 READ_VIN N 88 R Word Returns the input voltage in volts (VIN pin) READ_VOUT Y 8B R Word Returns the actual reference used for the regulation in VID format READ_IOUT Y 8C R Word Returns the output current in amps N1 94 R Word Returns the duty cycle of the devices main power converter in percentage MFR_SPECIFIC_04 Y D4 R Word READ_VOUT. Returns the actual reference used for the regulation in volts for LINEAR format READ_TEMPERATUR E_1 Y 8D R Word READ_TEMPERATURE. [DegC] STATUS_BYTE Y 78 R Byte One byte with information on the most critical faults STATUS_WORD Y 79 R Word Two bytes with information on the units fault condition STATUS_VOUT Y 7A R Byte Status information on the output voltage warnings and faults STATUS_IOUT Y 7B R Byte Status information on the output current warnings and faults STATUS_TEMPERATU RE Y 7D R Byte Status information on the temperature warnings and faults STATUS_CML Y 7E R Byte Status information on the units communication, logic and memory READ_DUTY_CYCLE 52/59 Comments Send Byte Used to clear any fault bits that have been set Doc ID 023992 Rev 1 L6751 PMBus support (preliminary) Table 16. Supported commands Command STATUS_INPUT STATUS_MFR_SPECI FIC Note: 12.1 Per Rail Code [Hex] Mode N1 7C R Byte Status information on the input warning and fault Y 80 R Byte Manufacturer specific status 1 Applies to multi-phase only. 2 Applies to single-phase only. Comments Enabling the device through PMBus The default condition for the L6751 is to power up through the EN pin ignoring PMBus commands. By properly setting the ON_OFF_CONFIG command, it is also possible to let the device ignore the EN pin acting only as a consequence of the OPERATION command issued. 12.2 Controlling Vout through PMBus Vout can be set independently from SetVID commands issued through the SVI interface by using PMBus. Two main modes can be identified as: – Offset above SVI commanded voltage. By enabling the MARGIN mode through the OPERATION command and by commanding the MARGIN_HIGH and MARGIN_LOW registers, it is possible to dynamically control an offset above the output voltage commanded through the SVI bus. – Fixed Vout regardless of SVI. It is necessary to enter DEBUG_MODE. In this condition, commands from SVI are acknowledged but not executed and VOUT_COMMAND controls the voltage regulated on the output. The L6751 can enter and exit DEBUG_MODE anytime. Upon any transition, Vout remains unchanged and only the next-coming command affects the output voltage positioning (i.e. when exiting DEBUG_MODE, returning to SVI domain, output voltage remains unchanged until the next SetVID command). Doc ID 023992 Rev 1 53/59 PMBus support (preliminary) L6751 Figure 17. Device initialization: PMBus controlling Vout VCC5 VDRV UVLO 2mSec POR UVLO UVLO VIN 50μSec EN ENVTT (Ignored by ON_OFF_Config setting) SVI BUS Command ACK but not executed PMBus Command Rejected SVI Packet ON-OFF_Config Operation V_SinglePhase 64μSec SVRRDY V_MultiPhase 64μSec VRRDY AM14823v1 12.3 Input voltage monitoring (READ_VIN) The dedicated PMBus command allows the user to monitor input voltage. By connecting the VIN pin to the input voltage with the recommended resistor values, the L6751 returns the value of the input voltage measured as a voltage (linear format, N=-4). The divider needs to be programmed to have 1.24 V on the pin when VIN=15.9375 V. According to this, RUP=118.5 kΩ and RDOWN=10 kΩ. Errors in defining the divider lead to monitoring errors accordingly. Filter VIN pin locally to GND to increase stability of the voltage being measured. 12.4 Duty cycle monitoring (READ_DUTY) The dedicated PMBus command allows the user to monitor duty cycle for multi-phase with the aim of calculating input current inexpensively (no need for input current-sense resistors). By connecting the PHASE pin to the phase1 PHASE pin, the L6751 returns the value of the duty cycle as a percentage (linear format, N=-2). The divider needs to be programmed to respect absolute maximum ratings for the pin (7 Vmax). According to this, RUP=5.6 kΩ and RDOWN=470 Ω. 54/59 Doc ID 023992 Rev 1 L6751 12.5 PMBus support (preliminary) Output voltage monitoring (READ_VOUT) The dedicated PMBus command allows the user to monitor output voltage for both sections. The L6751 returns the value of the programmed VID in VID LSBs (i.e. number of LSBs. C8h = 200 dec x 5 mV = 1.000 V). 12.6 Output current monitoring (READ_IOUT) The dedicated PMBus command allows the user to monitor output current for both sections. The L6751 returns the value of the delivered current by reading IMON voltage (same as VR12 register 15h) in amperes (linear format, N=0). 12.7 Temperature monitoring (READ_TEMPERATURE) The dedicated PMBus command allows the user to monitor the temperature of the power section for multi-phase. The L6751 returns the value of the temperature sensed by NTC connected on the TM/STM pin (the same as VR12 temperature zone) in degrees Celsius (linear format, N=0). 12.8 Overvoltage threshold setting The dedicated MFR_SPECIFIC command allows the user to program specific thresholds for multi-phase and single-phase sections. The threshold can be programmed according to Table 17. Different thresholds can be configured for multi-phase and single-phase sections. Table 17. OV threshold setting Data byte [Hex] OC threshold [mV] (above programmed VID) 00h +175 mV (default) 01h +225 mV 02h +275 mV 03h +325 mV This product is subject to a limited license from Power-One®. related to digital power technology patents owned by Power-One. This license does not extend to standalone power supply products. Doc ID 023992 Rev 1 55/59 Package mechanical data 13 L6751 Package mechanical data In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK® packages, depending on their level of environmental compliance. ECOPACK specifications, grade definitions and product status are available at: www.st.com. ECOPACK is an ST trademark. Table 18. L6751 WPLGA72 6x6 mm mechanical data mm Dim. Min. Typ. Max. A 0.60 0.70 0.80 A1 0.005 0.025 0.045 D D2 6.00 3.55 E 56/59 3.60 3.65 6.00 E2 3.55 3.60 3.65 b 0.25 0.30 0.35 b1 0.20 0.25 0.30 e1 0.5 e2 0.55 k 0.20 L1 0.05 0.25 0.15 aaa 0.15 bbb 0.10 ddd 0.05 eee 0.08 fff 0.10 ccc 0.10 Doc ID 023992 Rev 1 0.30 L6751 Package mechanical data Figure 18. L6751 WPLGA72 6x6 mm package dimensions B A C a1 D Doc ID 023992 Rev 1 57/59 Revision history 14 L6751 Revision history Table 19. 58/59 Document revision history Date Revision 29-Nov-2012 1 Changes Initial release. Doc ID 023992 Rev 1 L6751 Please Read Carefully: Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any time, without notice. All ST products are sold pursuant to ST’s terms and conditions of sale. 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