L6911C
5 BIT PROGRAMMABLE STEP DOWN CONTROLLER
WITH SYNCHRONOUS RECTIFICATION
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OPERATING SUPPLY IC VOLTAGE FROM 5V
TO 12V BUSES
UP TO 1.3A GATE CURRENT CAPABILITY
TTL-COMPATIBLE 5 BIT PROGRAMMABLE
OUTPUT COMPLIANT WITH VRM 8.4 :
1.3V TO 2.05V WITH 0.05V BINARY STEPS
2.1V TO 3.5V WITH 0.1V BINARY STEPS
VOLTAGE MODE PWM CONTROL
EXCELLENT OUTPUT ACCURACY: ±1%
OVER LINE AND TEMPERATURE
VARIATIONS
VERY FAST LOAD TRANSIENT RESPONSE:
FROM 0% TO 100% DUTY CYCLE
POWER GOOD OUTPUT VOLTAGE
OVERVOLTAGE PROTECTION AND
MONITOR
OVERCURRENT PROTECTION REALIZED
USING THE UPPER MOSFET'S RdsON
200KHz INTERNAL OSCILLATOR
OSCILLATOR EXTERNALLY ADJUSTABLE
FROM 50KHz TO 1MHz
SOFT START AND INHIBIT FUNCTIONS
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APPLICATIONS
■ POWER SUPPLY FOR ADVANCED
MICROPROCESSOR CORE
■ DISTRIBUTED POWER SUPPLY
■ HIGH POWER DC-DC REGULATORS
SO-20
ORDERING NUMBERS: L6911C
L6911CTR (Tape and Reel)
DESCRIPTION
The device is a power supply controller specifically designed to provide a high performance DC/DC conversion for high current microprocessors. A precise 5-bit
digital to analog converter (DAC) allows adjusting the
output voltage from 1.30V to 2.05V with 50mV binary
steps and from 2.10V to 3.50V with 100mV binary steps.
The high precision internal reference assures the selected output voltage to be within ±1%. The high peak
current gate drive affords to have fast switching to the
external power mos providing low switching losses.
The device assures a fast protection against load
overcurrent and load overvoltage. An external SCR is
triggered to crowbar the input supply in case of hard
over-voltage. An internal crowbar is also provided
turning on the low side mosfet as long as the overvoltage is detected. In case of over-current detection,
the soft start capacitor is discharged and the system
works in HICCUP mode.
BLOCK DIAGRAM
Vcc 5 to 12V
Vin 5V to12V
VCC
PGOOD
OCSET
BOOT
SS
MONITOR and
PROTECTION
UGATE
OVP
RT
PHASE
OSC
LGATE
VD0
VD1
VD2
VD3
VD4
PGND
-
D/A
+
+
-
D01IN1260
November 2001
Vo
1.300V to 3.500V
E/A
GND
PWM
VSEN
VFB
COMP
1/20
L6911C
ABSOLUTE MAXIMUM RATINGS
Symbol
Value
Unit
VCC to GND, PGND
15
V
Boot Voltage
15
V
15
V
-0.3 to Vcc+0.3
V
7
V
6.5
V
Value
Unit
Thermal Resistance Junction to Ambient
110
°C/W
Maximum junction temperature
150
°C
VCC
VBOOT-VPHASE
Parameter
VHGATE-VPHASE
OCSET, LGATE, PHASE
RT, SS, FB, PGOOD, VSEN, VID0-4
OVP, COMP
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THERMAL DATA
Symbol
Rth j-amb
Tj
Parameter
Tstg
Storage temperature range
-40 to 150
°C
TJ
Junction temperature range
0 to 125
°C
PIN CONNECTION (Top view)
VSEN
1
20
RT
OCSET
2
19
OVP
SS/INH
3
18
VCC
VID0
4
17
LGATE
VID1
5
16
PGND
VID2
6
15
BOOT
VID3
7
14
UGATE
VID4
8
13
PHASE
COMP
9
12
PGOOD
10
11
GND
FB
D98IN958
2/20
L6911C
PIN FUNCTION
Pin
Num.
Name
1
VSEN
2
OCSET
A resistor connected from this pin and the upper Mos Drain sets the current limit protection.
The internal 200µA current generator sinks a current from the drain through the external resistor.
The Over-Current threshold is due to the following equation:
I OCSE T ⋅ R O CS ET
IP = ---------------------------------------------R DS on
3
SS/INH
The soft start time is programmed connecting an external capacitor from this pin and GND. The
internal current generator forces through the capacitor 10µA.
This pin can be used to disable the device forcing a voltage lower than 0.4V
4-8
VID0 - 4
Voltage Identification Code pins. These input are internally pulled-up and TTL compatible. They
are used to program the output voltage as specified in Table 1 and to set the overvoltage and
power good thresholds.
Connect to GND to program a ‘0’ while leave floating to program a ‘1’.
9
COMP
This pin is connected to the error amplifier output and is used to compensate the voltage control
feedback loop.
10
FB
This pin is connected to the error amplifier inverting input and is used to compensate the voltage
control feedback loop.
11
GND
12
PGOOD
This pin is an open collector output and is pulled low if the output voltage is not within the above
specified thresholds.
If not used may be left floating.
13
PHASE
This pin is connected to the source of the upper mosfet and provides the return path for the high
side driver. This pin monitors the drop across the upper mosfet for the current limit
14
UGATE
High side gate driver output.
15
BOOT
Bootstrap capacitor pin. Through this pin is supplied the high side driver and the upper mosfet.
Connect through a capacitor to the PHASE pin and through a diode to Vcc (cathode vs. boot).
16
PGND
Power ground pin. This pin has to be connected closely to the low side mosfet source in order to
reduce the noise injection into the device
17
LGATE
This pin is the lower mosfet gate driver output
18
VCC
Device supply voltage. The operative nominal supply voltage ranges from 5 to 12V.
DO NOT CONNECT VIN TO A VOLTAGE GREATER THAN VCC.
19
OVP
Over voltage protection. If the output voltage reaches the 17% above the programmed voltage
this pin is driven high and can be used to drive an external SCR that crowbar the supply voltage.
If not used, it may be left floating.
20
RT
Description
Connected to the output voltage is able to manage over-voltage conditions and the PGOOD
signal.
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All the internal references are referred to this pin. Connect it to the PCB signal ground.
Oscillator switching frequency pin. Connecting an external resistor from this pin to GND, the
external frequency is increased according to the equation:
6
4.94 ⋅ 10
f S = 200kHz + ------------------------R T ( kΩ )
Connecting a resistor from this pin to Vcc (12V), the switching frequency is reduced according to
the equation:
7
4.306 ⋅ 10
f S = 200kHz – ----------------------------RT ( kΩ )
If the pin is not connected, the switching frequency is 200KHz.
The voltage at this pin is fixed at 1.23V (typ). Forcing a 50µA current into this pin, the built in
oscillator stops to switch.
3/20
L6911C
ELECTRICAL CHARACTERISTCS (VCC = 12V, Tamb = 25°C unless otherwise specified)
Symbol
Parameter
Test Condition
Min.
Typ.
Max.
Unit
VCC SUPPLY CURRENT
Icc
Vcc Supply current
UGATE and LGATE open
5
mA
POWER-ON
Turn-On Vcc threshold
VOCSET=4.5V
Turn-Off Vcc threshold
VOCSET=4.5V
4.6
3.6
V
Rising VOCSET threshold
Soft start Current
ISS
1.24
V
10
µA
OSCILLATOR
∆Vosc
Free running frequency
RT = OPEN
180
Total Variation
6 KΩ < RT to GND < 200 KΩ
-15
Ramp amplitude
RT = OPEN
DACOUT Voltage
Accuracy
VID0, VID1, VID2, VID3, VID4
see Table1; Tamb = 0 to 70°C
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VID Pull-Up voltage
ERROR AMPLIFIER
so
DC Gain
GBWP
Gain-Bandwidth Product
SR
Slew-Rate
IUGATE
High Side Source
Current
RUGATE
High Side Sink
Resistance
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Low Side Source
Current
RLGATE
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88
%
V
dB
10
MHz
10
V/µS
1.3
A
2
0.9
%
Vp-p
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1
KHz
4
1.1
Ω
A
PHASE connected to GND
120
Over Voltage Trip
(VSEN/DACOUT)
VSEN Rising
117
120
%
OCSET Current Source
VOCSET = 4.5V
170
200
230
µA
OVP Sourcing Current
VSEN > OVP Trip, VOVP=0V
60
Upper Threshold
(VSEN/DACOUT)
VSEN Rising
110
112
114
%
Lower Threshold
(VSEN/DACOUT)
VSEN Falling
86
88
90
%
Hysteresis
(VSEN/DACOUT)
Upper and Lower threshold
PGOOD Voltage Low
IPGOOD = -5mA
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Output Driver Dead Time
3
Ω
1.5
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IOVP
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-1
VBOOT-VPHASE=12V,
IUGATE = 300mA
Vcc=12V, VLGATE = 6V
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VBOOT - VPHASE=12V,
VUGATE - VPHASE= 6V
(t s)
220
Vcc=12V, ILGATE = 300mA
Low Side Sink
Resistance
PROTECTIONS
IOCSET
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ILGATE
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COMP=10pF
GATE DRIVERS
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200
1.9
REFERENCE AND DAC
V
ns
mA
POWER GOOD
O
VPGOOD
4/20
2
%
0.5
V
L6911C
Table 1. VID Settings
VID4
VID3
VID2
VID1
VID0
Output
Voltage (V)
VID4
VID3
VID2
VID1
VID0
Output
Voltage (V)
0
1
1
1
1
1.30
1
1
1
1
1
Output Off
0
1
1
1
0
1.35
1
1
1
1
0
2.1
0
1
1
0
1
1.40
1
1
1
0
1
2.2
0
1
1
0
0
1.45
1
1
1
0
0
2.3
0
1
0
1
1
1.50
1
1
0
1
1
2.4
0
1
0
1
0
1.55
1
1
0
1
0
2.5
0
1
0
0
1
1.60
1
1
0
0
1
2.6
0
1
0
0
0
1.65
1
1
0
0
0
2.7
0
0
1
1
1
1.70
1
0
1
1
1
0
0
1
1
0
1.75
1
0
1
1
0
1
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1
0
0
0
1
0
1
1.80
1
0
1
0
0
0
1
0
0
1.85
1
0
1
0
0
0
0
1
1
1.90
1
0
0
0
0
0
1
0
1.95
1
0
0
0
0
0
0
1
2.00
1
0
0
0
0
0
0
2.05
1
Device Description
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2.8
2.9
3.0
3.1
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3.2
3.3
3.4
3.5
The device is an integrated circuit realized in BCD technology. It provides complete control logic and protections
for a high performance step-down DC-DC converter optimized for microprocessor power supply. It is designed
to drive N-Channel Mosfets in a synchronous-rectified buck topology. The device works properly with Vcc ranging from 5V to 12V and regulates the output voltage starting from a 1.26V power stage supply voltage (Vin). The
output voltage of the converter can be precisely regulated, programming the VID pins, from 1.3V to 2.05V with
50mV binary steps and from 2.1V to 3.5V with 100mV binary steps, with a maximum tolerance of ±1% over temperature and line voltage variations. The device provides voltage-mode control with fast transient response. It
includes a 200kHz free-running oscillator that is adjustable from 50kHz to 1MHz. The error amplifier features a
15MHz gain-bandwidth product and 10V/µsec slew rate which permits high converter bandwidth for fast transient performance. The resulting PWM duty cycle ranges from 0% to 100%. The device protects against overcurrent conditions entering in HICCUP mode. The device monitors the current by using the rDS(ON) of the upper
MOSFET which eliminates the need for a current sensing resistor.
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The device is available in SO20 package.
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Oscillator
The switching frequency is internally fixed to 200kHz. The internal oscillator generates the triangular waveform
for the PWM charging and discharging with a constant current an internal capacitor. The current delivered to the
oscillator is typically 50µA (Fsw=200KHz) and may be varied using an external resistor (R T) connected between
RT pin and GND or VCC. Since the RT pin is maintained at fixed voltage (typ. 1.235V), the frequency is varied
proportionally to the current sunk (forced) from (into) the pin.
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In particular connecting it to GND the frequency is increased (current is sunk from the pin), according to the
following relationship:
6
4.94 ⋅ 10
f S = 200kH z + ------------------------R T ( kΩ )
Connecting RT to VCC=12V or to VCC=5V the frequency is reduced (current is forced into the pin), according
to the following relationships:
5/20
L6911C
7
4.306 ⋅ 10
f S = 200kH z + ----------------------------R T ( kΩ )
VCC = 12V
7
15 ⋅ 10
f S = 200kH z + -------------------R T ( kΩ )
VCC = 5V
Switching frequency variations vs. RT are reported in Fig.1.
Note that forcing a 50µA current into this pin, the device stops switching because no current is delivered to the
oscillator.
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Figure 1.
1 0 00 0
R e s is ta n ce [kO h m ]
1 00 0
10 0
10
R T to G N D
R T to V C C =1 2 V
R T to V C C =5 V
10
100
1000
F re q u e n cy [kH z]
Digital to Analog Converter
The built-in digital to analog converter allows the adjustment of the output voltage from 1.30V to 2.05V with
50mV binary steps and from 2.10V to 3.50V with 100mV binary steps as shown in the previous table 1. The
internal reference is trimmed to ensure the precision of 1%.
The internal reference voltage for the regulation is programmed by the voltage identification (VID) pins. These
are TTL compatible inputs of an internal DAC that is realized by means of a series of resistors providing a partition of the internal voltage reference. The VID code drives a multiplexer that selects a voltage on a precise
point of the divider. The DAC output is delivered to an amplifier obtaining the VPROG voltage reference (i.e. the
set-point of the error amplifier). Internal pull-ups are provided (realized with a 5µA current generator); in this
way, to program a logic "1" it is enough to leave the pin floating, while to program a logic "0" it is enough to short
the pin to GND.
The voltage identification (VID) pin configuration also sets the power-good thresholds (PGOOD) and the overvoltage protection (OVP) thresholds.
The VID code "11111" disable the device (as a short on the SS pin) and no output voltage is regulated.
Soft Start and Inhibit
At start-up a ramp is generated charging the external capacitor CSS by means of a 10µA constant current, as
shown in figure 1.
When the voltage across the soft start capacitor (VSS) reaches 0.5V the lower power MOS is turned on to dis-
6/20
L6911C
charge the output capacitor. As V SS reaches 1V (i.e. the oscillator triangular wave inferior limit) also the upper
MOS begins to switch and the output voltage starts to increase.
The VSS growing voltage initially clamps the output of the error amplifier, and consequently VOUT linearly increases, as shown in figure 2. In this phase the system works in open loop. When V SS is equal to VCOMP the
clamp on the output of the error amplifier is released. In any case another clamp on the input of the error amplifier remains active, allowing to VOUT to grow with a lower slope (i.e. the slope of the VSS voltage, see figure 2).
In this second phase the system works in closed loop with a growing reference. As the output voltage reaches
the desired value VPROG, also the clamp on the error amplifier input is removed, and the soft start finishes. Vss
increases until a maximum value of about 4V.
The Soft-Start will not take place, and the relative pin is internally shorted to GND, if both VCC and OCSET pins
are not above their own turn-on thresholds. During normal operation, if any under-voltage is detected on one of
the two supplies, the SS pin is internally shorted to GND and so the SS capacitor is rapidly discharged.
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The device goes in INHIBIT state forcing SS pin below 0.4V. In this condition both external MOSFETS are kept
off.
Figure 2. Soft Start
V cc Turn-on threshold
V cc
Vin
V in Turn-on threshold
1V
V ss
to G ND
0.5V
LGATE
Vout
Timing Diagram
Aquisition: CH1 = PHASE; CH2 = V OUT;
CH3 = PGOOD; CH4 = VSS
Driver Section
The driver capability on the high and low side drivers allows using different types of power MOS (also multiple
MOS to reduce the RDSON), maintaining fast switching transition.
The low-side mos driver is supplied directly by Vcc while the high-side driver is supplied by the BOOT pin.
Adaptative dead time control is implemented to prevent cross-conduction and allow to use several kinds of mosfets. The upper mos turn-on is avoided if the lower gate is over about 200mV while the lower mos turn-on is
avoided if the PHASE pin is over about 500mV. The upper mos is in any case turned-on after 200nS from the
low side turn-off.
The peak current is shown for both the upper (fig. 3) and the lower (fig. 4) driver at 5V and 12V. A 4nF capacitive
load has been used in these measurements.
For the lower driver, the source peak current is 1.1A @ Vcc=12V and 500mA @ Vcc=5V, and the sink peak
current is 1.3A @ Vcc=12V and 500mA @ Vcc=5V.
Similarly, for the upper driver, the source peak current is 1.3A @ Vboot-Vphase=12V and 600mA @ VbootVphase =5V, and the sink peak current is 1.3A @ Vboot-Vphase =12V and 550mA @ Vboot-Vphase = 5V.
7/20
L6911C
Figure 3. High Side driver peak current. Vboot-Vphase=12V (left) Vboot-Vphase=5V (right)
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CH1 = High Side Gate
CH4 = Gate Current
Figure 4. Low Side driver peak current. Vcc=12V (left) Vcc=5V (right)
CH1 = Low Side Gate
CH4 = Gate Current
Monitoring and Protections
The output voltage is monitored by means of pin 1 (VSEN). If it is not within ±12% (typ.) of the programmed
value, the powergood output is forced low.
The device provides overvoltage protection, when the output voltage reaches a value 17% (typ.) grater than the
nominal one. If the output voltage exceeds this threshold, the OVP pin is forced high, triggering an external SCR
to shuts the supply (VIN) down, and also the lower driver is turned on as long as the over-voltage is detected.
To perform the overcurrent protection the device compares the drop across the high side MOS, due to the
RDSON, with the voltage across the external resistor (ROCS) connected between the OCSET pin and drain of
the upper MOS. Thus the overcurrent threshold (I P) can be calculated with the following relationship:
I OCS ⋅ R OCS
I P = --------------------------------R DSON
Where the typical value of IOCS is 200µA. To calculate the ROCS value it must be considered the maximum
RDSON (also the variation with temperature) and the minimum value of IOCS. To avoid undesirable trigger of
8/20
L6911C
overcurrent protection this relationship must be satisfied:
∆l
I P ≥ I OUT MAX + ----- = I PEA K
2
Where ∆I is the inductance ripple current and IOUTMAX is the maximum output current.
In case of output short circuit the soft start capacitor is discharged with constant current (10µA typ.) and when
the SS pin reaches 0.5V the soft start phase is restarted. During the soft start the over-current protection is always active and if such kind of event occurs, the device turns off both mosfets, and the SS capacitor is discharged again (after reaching the upper threshold of about 4V). The system is now working in HICCUP mode,
as shown in figure 5a. After removing the cause of the over-current, the device restart working normally without
power supplies turn off and on.
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Figure 5.
9
L=1.5µH, Vin=12V
Inductor Ripple [A]
8
7
L=2µH,
Vin=12V
6
L=3µH,
Vin=12V
5
4
L=1.5µH,
Vin=5V
3
L=2µH,
Vin=5V
2
L=3µH, Vin=5V
1
0
0.5
1.5
2.5
3.5
Output Voltage [V ]
a: Hiccup Mode
b: Inductor Ripple Current vs. Vout
Inductor design
The inductance value is defined by a compromise between the transient response time, the efficiency, the cost
and the size. The inductor has to be calculated to sustain the output and the input voltage variation to maintain
the ripple current ∆IL between 20% and 30% of the maximum output current. The inductance value can be calculated with this relationship:
V IN – V OUT V OUT
L = ------------------------------ ⋅ --------------V IN
f S ⋅ ∆I L
Where fSW is the switching frequency, VIN is the input voltage and VOUT is the output voltage. Figure 5b shows
the ripple current vs. the output voltage for different values of the inductor, with VIN = 5V and VIN = 12V.
Increasing the value of the inductance reduces the ripple current but, at the same time, reduces the converter
response time to a load transient. If the compensation network is well designed, the device is able to open or
close the duty cycle up to 100% or down to 0%. The response time is now the time required by the inductor to
change its current from initial to final value. Since the inductor has not finished its charging time, the output current is supplied by the output capacitors. Minimizing the response time can minimize the output capacitance
required.
The response time to a load transient is different for the application or the removal of the load: if during the application of the load the inductor is charged by a voltage equal to the difference between the input and the output
voltage, during the removal it is discharged only by the output voltage. The following expressions give approximate response time for ∆I load transient in case of enough fast compensation network response:
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L6911C
L ⋅ ∆I
t a pplic atio n = -----------------------------V IN – V OUT
L ⋅ ∆I
t rem ov al = --------------V OUT
The worst condition depends on the input voltage available and the output voltage selected. Anyway the worst
case is the response time after removal of the load with the minimum output voltage programmed and the maximum input voltage available.
Output Capacitor
Since the microprocessors require a current variation beyond 10A doing load transients, with a slope in the
range of tenth A/µsec, the output capacitor is a basic component for the fast response of the power supply. In
fact for first few microseconds they supply the current to the load. The controller recognizes immediately the
load transient and sets the duty cycle at 100%, but the current slope is limited by the inductor value.
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The output voltage has a first drop due to the current variation inside the capacitor (neglecting the effect of the
ESL):
∆VOUT = ∆IOUT · ESR
A minimum capacitor value is required to sustain the current during the load transient without discharge it. The
voltage drop due to the output capacitor discharge is given by the following equation:
2
∆I OUT L
∆V OUT = --------------------------------------------------------------------------------------------2 ⋅ C OUT ⋅ ( V INM IN ⋅ D M AX – V OUT )
Where DMAX is the maximum duty cycle value that is 100%. The lower is the ESR, the lower is the output drop
during load transient and the lower is the output voltage static ripple.
Input Capacitor
The input capacitor has to sustain the ripple current produced during the on time of the upper MOS, so it must
have a low ESR to minimize the losses. The rms value of this ripple is:
I rm s = I OUT D ⋅ ( 1 – D )
Where D is the duty cycle. The equation reaches its maximum value with D=0.5. The losses in worst case are:
2
P = ESR ⋅ I rm s
Compensation network design
The control loop is a voltage mode (figure 7) that uses a droop function to satisfy the requirements for a VRM
module, reducing the size and the cost of the output capacitor.
This method "recovers" part of the drop due to the output capacitor ESR in the load transient, introducing a dependence of the output voltage on the load current: at light load the output voltage will be higher than the nominal level, while at high load the output voltage will be lower than the nominal value.
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L6911C
Figure 6. Output transient response without (a) and with (b) the droop function
ESR DROP
ESR DROP
VMAX
VDROOP
VNOM
VMIN
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(a)
(b)
As shown in figure 6, the ESR drop is present in any case, but using the droop function the total deviation of the
output voltage is minimized. In practice the droop function introduces a static error (Vdroop in figure 6) proportional to the output current. Since a sense resistor is not present, the output DC current is measured by using
the intrinsic resistance of the inductance (a few mΩ). So the low-pass filtered inductor voltage (that is the inductor current) is added to the feedback signal, implementing the droop function in a simple way. Referring to the
schematic in figure 7, the static characteristic of the closed loop system is:
R3 + R 8 // R9 R L ⋅ R8 // R9
V OUT = V PRO G + V PRO G ⋅ ------------------------------------- – ----------------------------------- ⋅ I OUT
R8
R2
Where VPROG is the output voltage of the digital to analog converter (i.e. the set point) and R L is the inductance
resistance. The second term of the equation allows a positive offset at zero load (∆V+); the third term introduces
the droop effect (∆VDROOP). Note that the droop effect is equal the ESR drop if:
R L ⋅ R 8 // R9
----------------------------------- = ESR
R8
Figure 7. Compensation network
V
V
IN
V
COM P
R
L2
PHASE
L
V
O UT
PW M
ESR
R8
C18
Z
C 6-15
F
C 20
R4
R9
C 25
R3
V
ZI
PROG
R2
Considering the previous relationships R2, R3, R8 and R9 may be determined in order to obtain the desired
droop effect as follow:
■ Choose a value for R2 in the range of hundreds of KΩ to obtain realistic values for the other
components.
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L6911C
■
From the above equations, it results:
+
∆V ⋅ R 2 R L ⋅ I M AX
R8 = ----------------------- ⋅ --------------------------- ;
V PRO G ∆V DROOP
∆V DROOP
1
R9 = R8 ⋅ --------------------------- ⋅ ------------------------------------- ;
∆V DROOP
R L ⋅ I M AX
1 + --------------------------R L ⋅ I M AX
Where IMAX is the maximum output current.
The component R3 must be chosen in order to obtain R3
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