L6986F
38 V, 1.5 A synchronous step-down switching regulator with 30 µA
quiescent current
Datasheet - production data
Description
HTSSOP16 (RTH = 40 °C/W)
Features
1.5 A DC output current
4 V to 38 V operating input voltage
Low consumption mode or low noise mode
30 µA IQ at light-load (LCM VOUT = 3.3 V)
8 µA IQ-SHTDWN
Adjustable fSW (250 kHz - 2 MHz)
Output voltage adjustable from 0.85 V to VIN
Embedded output voltage supervisor
Synchronization
Adjustable soft-start time
Internal current limiting
Overvoltage protection
The L6986F is a step-down monolithic switching
regulator able to deliver up to 1.5 A DC. The
output voltage adjustability ranges from 0.85 V to
VIN. Thanks to the P-channel MOSFET high-side
power element, the device features 100% duty
cycle operation. The wide input voltage range
meet the 5 V, 12 V and 24 V power supplies. The
“Low Consumption Mode” (LCM) is designed for
applications active during idle mode, so it
maximizes the efficiency at light-load with
controlled output voltage ripple. The “Low Noise
Mode” (LNM) makes the switching frequency
constant and minimizes the output voltage ripple
overload current range, meeting the low noise
application specification. The output voltage
supervisor manages the reset phase for any
digital load (µC, FPGA). The RST open collector
output can also implement output voltage
sequencing during the power-up phase. The
synchronous rectification, designed for high
efficiency at medium - heavy load, and the high
switching frequency capability make the size of
the application compact. Pulse by pulse current
sensing on both power elements implements an
effective constant current protection.
Output voltage sequencing
Peak current mode architecture
RDSON HS = 180 m, RDSON LS = 150 m
Thermal shutdown
Applications
Designed for 12 V and 24 V buses
Programmable logic controllers (PLCs)
Decentralized intelligent nodes
Sensors and low noise applications (LNM)
February 2016
This is information on a product in full production.
DocID027843 Rev 2
1/64
www.st.com
Contents
L6986F
Contents
1
Application schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2
Pin settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2.1
Pin connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2.2
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2.3
Maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2.4
Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2.5
ESD protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
3
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
4
Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
4.1
Power supply and voltage reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Switchover feature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
4.2
Voltages monitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
4.3
Soft-start and inhibit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
4.3.1
Ratiometric startup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
4.3.2
Output voltage sequencing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
4.4
Error amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
4.5
Light-load operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
4.6
4.7
4.5.1
Low noise mode (LNM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
4.5.2
Low consumption mode (LCM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Switchover feature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
4.6.1
LCM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
4.6.2
LNM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Overcurrent protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
OCP and switchover feature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
2/64
4.8
Overvoltage protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
4.9
Thermal shutdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
DocID027843 Rev 2
L6986F
5
6
Contents
Closing the loop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
5.1
GCO(s) control to output transfer function . . . . . . . . . . . . . . . . . . . . . . . . 35
5.2
Error amplifier compensation network . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
5.3
Voltage divider . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
5.4
Total loop gain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
5.5
Compensation network design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Application notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
6.1
Output voltage adjustment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
6.2
Switching frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
6.3
MLF pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
6.4
Voltage supervisor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
6.5
Synchronization (LNM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
6.6
Design of the power components . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
6.6.1
Input capacitor selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
6.6.2
Inductor selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
6.6.3
Output capacitor selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
7
Application board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
8
Efficiency curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
9
Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
9.1
HTSSOP16 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
10
Order codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
11
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
DocID027843 Rev 2
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64
Application schematic
1
L6986F
Application schematic
Figure 1. Application schematic
4/64
DocID027843 Rev 2
L6986F
Pin settings
2
Pin settings
2.1
Pin connection
Figure 2. Pin connection (top view)
2.2
Pin description
Table 1. Pin description
No.
Pin
Description
1
RST
The RST open collector output is driven low when the output voltage is out of regulation. The RST
is released after an adjustable time DELAY once the output voltage is over the active delay
threshold.
2
VCC
Connect a ceramic capacitor (≥ 470 nF) to filter internal voltage reference. This pin supplies the
embedded analog circuitry.
3
SS/INH
An open collector stage can disable the device clamping this pin to GND (INH mode). An internal
current generator (4 A typ.) charges the external capacitor to implement the soft-start.
4
SYNCH/
ISKP
The pin features Master / Slave synchronization in LNM (see Section 4.5.1 on page 23) and skip
current level selection in LCM (see Section 4.5.2 on page 23).
5
FSW
A pull up resistor (E24 series only) to VCC or pull down to GND selects the switching frequency.
Pinstrapping is active only before the soft-start phase to minimize the IC consumption.
6
MLF
A pull up resistor (E24 series only) to VCC or pull down to GND selects the low noise mode/low
consumption mode and the active RST threshold. Pinstrapping is active only before the soft-start
phase to minimize the IC consumption.
7
COMP
Output of the error amplifier. The designed compensation network is connected at this pin.
8
DELAY
An external capacitor connected at this pin sets the time DELAY to assert the rising edge of the
RST o.c. after the output voltage is over the reset threshold. If this pin is left floating, RST is like
a Power Good.
9
FB
10
SGND
Signal GND
11
PGND
Power GND
Inverting input of the error amplifier
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64
Pin settings
L6986F
Table 1. Pin description (continued)
No.
Pin
12
PGND
13
LX
Switching node
14
LX
Switching node
15
VIN
DC input voltage
16
VBIAS
Typically connected to the regulated output voltage. An external voltage reference can be used to
supply part of the analog circuitry to increase the efficiency at light-load. Connect to GND if not
used.
-
E. p.
Exposed pad must be connected to SGND, PGND
2.3
Description
Power GND
Maximum ratings
Stressing the device above the rating listed in Table 2: Absolute maximum ratings may
cause permanent damage to the device. These are stress ratings only and operation of the
device at these or any other conditions above those indicated in the operating sections of
this specification is not implied. Exposure to absolute maximum rating conditions may affect
device reliability.
Table 2. Absolute maximum ratings
Symbol
Description
Min.
Max.
Unit
VIN
-0.3
40
V
DELAY
-0.3
VCC + 0.3
V
PGND
SGND - 0.3
SGND + 0.3
V
SGND
V
VCC
-0.3
(VIN + 0.3) or (max. 4)
V
SS / INH
-0.3
VIN + 0.3
V
-0.3
VCC + 0.3
V
-0.3
VCC + 0.3
V
VOUT
-0.3
10
V
FSW
-0.3
VCC + 0.3
V
SYNCH
-0.3
VIN + 0.3
V
VBIAS
-0.3
(VIN + 0.3) or (max. 6)
V
RST
-0.3
VIN + 0.3
V
LX
-0.3
VIN + 0.3
V
-40
150
°C
MLF
COMP
See Table 1
TJ
Operating temperature range
TSTG
Storage temperature range
-65 to 150
°C
TLEAD
Lead temperature (soldering 10 sec.)
260
°C
IHS, ILS
High-side / low-side switch current
2
A
6/64
DocID027843 Rev 2
L6986F
2.4
Pin settings
Thermal data
Table 3. Thermal data
Symbol
2.5
Parameter
Value
Unit
Rth JA
Thermal resistance junction ambient (device soldered on the
STMicroelectronics® demonstration board)
40
°C/W
Rth JC
Thermal resistance junction to exposed pad for board design
(not suggested to estimate TJ from power losses).
5
°C/W
Value
Unit
HBM
2
kV
MM
200
V
CDM
500
V
ESD protection
Table 4. ESD protection
Symbol
ESD
Test condition
DocID027843 Rev 2
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64
Electrical characteristics
3
L6986F
Electrical characteristics
TJ = 25 °C, VIN = 12 V unless otherwise specified.
Table 5. Electrical characteristics
Symbol
Parameter
VIN
Operating input voltage range
VINH
VINL
IPK
IVY
ISKIPH
ISKIPL
IVY_SNK
Test condition
Note
Min.
Typ.
Max. Unit
4
38
VCC UVLO rising threshold
2.7
3.5
VCC UVLO falling threshold
2.4
3.5
Peak current limit
Duty cycle < 20%
2.3
Duty cycle = 100%
closed loop operation
1.8
Valley current limit
A
2.4
Programmable skip current
limit
LCM, VSYNCH = GND
(1)
LCM, VSYNCH = VCC
(2)
Reverse current limit
LNM or VOUT overvoltage
0.2
0.4
0.6
0.2
0.5
1
2
RDSON HS High-side RDSON
ISW = 1 A
0.18
0.360
RDSON LS Low-side RDSON
ISW = 1 A
0.15
0.300
fSW
Selected switching frequency FSW pinstrapping before SS
IFSW
FSW biasing current
Low noise mode /
LCM/LNM Low consumption mode
selection
IMLF
D
TON MIN
MLF biasing current
V
See Table 6: fSW selection
SS ended
0
MLF pinstrapping before SS
500
nA
See Table 7 on page 11
SS ended
0
(2)
Duty cycle
0
Minimum On time
500
nA
100
%
80
ns
VCC regulator
VCC
LDO output voltage
SWO
VBIAS threshold
(3 V< VBIAS < 5.5 V)
8/64
VBIAS = GND (no switchover)
2.9
3.3
3.6
VBIAS = 5 V (switchover)
2.9
3.3
3.6
Switch internal supply from VIN to
VBIAS
2.85
3.2
Switch internal supply from VBIAS
to VIN
2.78
3.15
DocID027843 Rev 2
V
L6986F
Electrical characteristics
Table 5. Electrical characteristics (continued)
Symbol
Parameter
Test condition
Note
Min.
Typ.
Max. Unit
4
8
15
4
10
15
Power consumption
ISHTDWN
Shutdown current from VIN
VSS/INH = GND
LCM - SWO
VREF < VFB < VOVP (SLEEP)
VBIAS = 3.3 V
IQ OPVIN
Quiescent current from VIN
IQ OPVBIAS Quiescent current from VBIAS
LCM - NO SWO
VREF < VFB < VOVP (SLEEP)
VBIAS = GND
(3)
A
A
(3)
35
70
120
LNM - SWO
VFB = GND (NO SLEEP)
VBIAS = 3.3 V
0.5
1.5
5
LNM - NO SWO
VFB = GND (NO SLEEP)
VBIAS = GND
2
2.8
6
25
50
115
A
LNM - SWO
VFB = GND (NO SLEEP)
VBIAS = 3.3 V
0.5
1.2
5
mA
SS rising
200
460
700
100
140
LCM - SWO
VREF < VFB < VOVP (SLEEP)
VBIAS = 3.3 V
mA
(3)
Soft-start
VINH
VSS threshold
VINH HYST VSS hysteresis
ISS CH
CSS charging current
VSS < VINH OR
t < TSS SETUP OR
VEA+ > VFB
t > TSS SETUP AND
VEA+ < VFB
VSS START
SSGAIN
(2)
mV
1
A
(2)
Start of internal error amplifier
ramp
4
0.995
SS/INH to internal error
amplifier gain
1.1
1.150
V
0.85
0.859
V
50
500
nA
3
Error amplifier
VOUT
Voltage feedback
IVOUT
VOUT biasing current
AV
ICOMP
0.841
(2)
Error amplifier gain
100
±6
EA output current capability
DocID027843 Rev 2
±12
dB
±25
A
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64
Electrical characteristics
L6986F
Table 5. Electrical characteristics (continued)
Symbol
Parameter
Test condition
Note
Min.
Typ.
Max. Unit
2.5
A/V
Inner current loop
gCS
Current sense
transconductance (VCOMP to
inductor current gain)
Ipk = 1 A
(2)
(4)
V PP g CS Slope compensation
0.45
0.75
1
1.15
1.2
1.25
0.5
2
5
A
Overvoltage protection
VOVP
Overvoltage trip (VOVP/VREF)
VOVP HYST Overvoltage hysteresis
%
Synchronization (fan out: 6 slave devices typ.)
fSYN MIN
Synchronization frequency
LNM; fSW = VCC
266.5
VSYN TH
SYNCH input threshold
LNM, SYNCH rising
0.70
SYNCH pull-down current
LNM, VSYN = 1.2 V
High level output
LNM, 5 mA sinking load
Low level output
LNM, 0.7 mA sourcing load
Selected RST threshold
MLF pinstrapping before SS
ISYN
VSYN OUT
kHz
1.2
0.7
V
mA
1.40
0.6
V
Reset
VTHR
VTHR HYST RST hysteresis
VRST
RST open collector output
see Table 7
(2)
2
%
VIN > VINH AND
VFB < VTH
4 mA sinking load
0.4
2 < VIN < VINH
4 mA sinking load
0.8
V
Delay
VTHD
RST open collector released
as soon as VDELAY > VTHD
VFB > VTHR
1.19
ID CH
CDELAY charging current
VFB > VTHR
1
1.234 1.258
2
3
V
A
Thermal shutdown
TSHDWN
Thermal shutdown
temperature
(2)
165
THYS
Thermal shutdown hysteresis
(2)
30
°C
1. Parameter tested in static condition during testing phase. Parameter value may change over dynamic application condition.
2. Not tested in production.
3. LCM enables SLEEP mode at light-load.
4. Measured at fsw = 250 kHz.
10/64
DocID027843 Rev 2
L6986F
Electrical characteristics
TJ = 25 °C, VIN = 12 V unless otherwise specified.
Table 6. fSW selection
Symbol
fSW
RVCC (E24 series)
RGND (E24 series)
Tj
fSW min.
fSW typ.
fSW max.
0
NC
225
250
275
1.8 k
NC
3.3 k
NC
5.6 k
NC
380
10 k
NC
435
NC
0
18 k
NC
33 k
NC
56 k
NC
755
NC
1.8 k
870
NC
3.3 k
NC
5.6 k
NC
10 k
NC
18 k
NC
33 k
285
330
(1)
450
500
550
575
660
(1)
900
kHz
1000
1100
1150
(1)
1310
1500(2)
56 k
NC
Unit
1575
1750(2)
1925
1800
2000(2)
2200
1. Not tested in production.
2. No synchronization as slave in LNM.
TJ = 25 °C, VIN = 12 V unless otherwise specified.
Table 7. LNM / LCM selection
Symbol
VRST
RVCC
RGND
(E24 1%)
(E24 1%)
0
NC
8.2 k
NC
18 k
NC
39 k
Operating VRST/VOUT
mode
(tgt. value)
VRST
VRST
VRST
min.
typ.
max.
93%
0.779
0.791
0.802
80%
0.670
0.680
0.690
87%
0.728
0.740
0.751
NC
96%
0.804
0.816
0.828
NC
0
93%
0.779
0.791
0.802
NC
8.2 k
80%
0.670
0.680
0.690
NC
18 k
87%
0.728
0.740
0.751
NC
39 k
96%
0.804
0.816
0.828
LCM
LNM
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Unit
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64
Functional description
4
L6986F
Functional description
The L6986F device is based on a “peak current mode”, constant frequency control. As
a consequence, the intersection between the error amplifier output and the sensed inductor
current generates the PWM control signal to drive the power switch.
The device features LNM (low noise mode) that is forced PWM control, or LCM (low
consumption mode) to increase the efficiency at light-load.
The main internal blocks shown in the block diagram in Figure 3 are:
12/64
Embedded power elements. Thanks to the P-channel MOSFET as high-side switch the
device features low dropout operation
A fully integrated sawtooth oscillator with adjustable frequency
A transconductance error amplifier
The high-side current sense amplifier to sense the inductor current
A “Pulse Width Modulator” (PWM) comparator and the driving circuitry of the
embedded power elements
The soft-start blocks to ramp the error amplifier reference voltage and so decreases the
inrush current at power-up. The SS/INH pin inhibits the device when driven low.
The switchover capability of the internal regulator to supply a portion of the quiescent
current when the VBIAS pin is connected to an external output voltage
The synchronization circuitry to manage master / slave operation and the
synchronization to an external clock
The current limitation circuit to implement the constant current protection, sensing
pulse by pulse high-side / low-side switch current. In case of heavy short-circuit the
current protection is fold back to decrease the stress of the external components
A circuit to implement the thermal protection function
The OVP circuitry to discharge the output capacitor in case of overvoltage event
MLF pin strapping sets the LNM/LCM mode and the thresholds of the RST comparator
FSW pinstrapping sets the switching frequency
The RST open collector output.
DocID027843 Rev 2
L6986F
Functional description
Figure 3. Internal block diagram
4.1
Power supply and voltage reference
The internal regulator block consists of a start-up circuit, the voltage pre-regulator that
provides current to all the blocks and the bandgap voltage reference. The starter supplies
the startup current when the input voltage goes high and the device is enabled (SS/INH pin
over the inhibits threshold).
The pre-regulator block supplies the bandgap cell and the rest of the circuitry with
a regulated voltage that has a very low supply voltage noise sensitivity.
Switchover feature
The switchover scheme of the pre-regulator block features to derive the main contribution of
the supply current for the internal circuitry from an external voltage (3 V < VBIAS < 5.5 V is
typically connected to the regulated output voltage). This helps to decrease the equivalent
quiescent current seen at VIN. (Please refer to Section 4.6: Switchover feature on page 29).
4.2
Voltages monitor
An internal block continuously senses the VCC, VBIAS and VBG. If the monitored voltages are
good, the regulator starts operating. There is also a hysteresis on the VCC (UVLO).
DocID027843 Rev 2
13/64
64
Functional description
L6986F
Figure 4. Internal circuit
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4.3
Soft-start and inhibit
The soft-start and inhibit features are multiplexed on the same pin. An internal current
source charges the external soft-start capacitor to implement a voltage ramp on the SS/INH
pin. The device is inhibited as long as the SS/INH pin voltage is lower than the VINH
threshold and the soft-start takes place when SS/INH pin crosses VSS START. (See Figure 5:
Soft-start phase).
The internal current generator sources a 1 A typ. current when the voltage of the VCC pin
crosses the UVLO threshold. The current increases to 4 A typ. as soon as the SS/INH
voltage is higher than the VINH threshold. This feature helps to decrease the current
consumption in inhibit mode. An external open collector can be used to set the inhibit
operation clamping the SS/INH voltage below VINH threshold.
The startup feature minimizes the inrush current and decreases the stress of the power
components during the power-up phase. The ramp implemented on the reference of the
error amplifier has a gain three times higher (SSGAIN) than the external ramp present at
SS/INH pin.
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Functional description
Figure 5. Soft-start phase
The CSS is dimensioned accordingly with Equation 1:
Equation 1
I SSCH T SS
4A T SS
C SS = SS GAIN -------------------------------- = 3 --------------------------V FB
0.85V
where TSS is the soft-start time, ISS CH the charging current and VFB the reference of the
error amplifier.
The soft-start block supports the precharged output capacitor.
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L6986F
Figure 6. Soft-start phase with precharged COUT
During normal operation a new soft-start cycle takes place in case of:
Thermal shutdown event
UVLO event
The device is driven in INH mode
The soft-start capacitor is discharged with a 0.6 mA typ. current capability for 1 msec time
max. For complete and proper capacitor discharge in case of fault condition, a maximum
CSS = 67 nF value is suggested.
The application example in Figure 7 shows how to enable the L6986F and perform the softstart phase driven by an external voltage step.
Figure 7. Enable the device with external voltage step
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Functional description
The maximum capacitor value has to be limited to guarantee the device can discharge it in
case of thermal shutdown and UVLO events (see Figure 9), so restart the switching activity
ramping the error amplifier reference voltage.
Equation 2
– 1 msec
C SS ------------------------------------------------------------------------------------------V SS_FINAL – 0.9 V
R SS_EQ ln 1 – ----------------------------------------------
600 A – R SS_EQ
where:
Equation 3
R UP R DWN
R SS_EQ = --------------------------------R UP + R DWN
R DWN
V SS_FINAL = V STEP – V DIODE ---------------------------------R UP + R DWN
The optional diode prevents to disable the device if the external source drops to ground.
RUP value is selected in order to make the capacitor charge at first approximation
independent from the internal current generator (4 A typ. current capability, see Table 5 on
page 8), so:
Equation 4
V STEP – V DIODE – V SS END
----------------------------------------------------------------------- » I SS CHARGE 4 A
R UP
where:
Equation 5
V FB
V SS END = V SS START + --------------------SS GAIN
represents the SS/INH voltage correspondent to the end of the ramp on the error amplifier
(see Figure 5); refer to Table 5 for VSS START, VFB and SSGAIN parameters.
As a consequence the voltage across the soft-start capacitor can be written as:
Equation 6
1
v SS t = V SS_FINAL ----------------------------------------t
1–e
– --------------------------------C SS R SS_EQ
RSS_DOWN is selected to guarantee the device stays in inhibit mode when the internal
generator sources 1 A typ. out of the SS/INH pin and VSTEP is not present:
Equation 7
R DWN I SS INHIBIT R DWN 1 A « V INH 200 mV
so:
Equation 8
R DWN 100 k
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RUP and RDWN are selected to guarantee:
Equation 9
V SS_FINAL 2 V V SS_END
The time to ramp the internal voltage reference can be calculated from Equation 10:
Equation 10
V SS_FINAL – V SS START
T SS = C SS R SS_EQ ln -----------------------------------------------------------
V SS_FINAL – V SS END
that is the equivalent soft-start time to ramp the output voltage.
Figure 8 shows the soft-start phase with the following component selection: RUP = 180 k,
RDWN = 33 k, CSS = 200 nF, the 1N4148 is a small signal diode and VSTEP = 13 V.
Figure 8. External soft-start network VSTEP driven
The circuit in Figure 7 introduces a time delay between VSTEP and the switching activity that
can be calculated as:
Equation 11
V SS_FINAL
T SS DELAY = C SS R SS_EQ ln -----------------------------------------------------------
V SS_FINAL – V SS START
Figure 9 shows how the device discharges the soft-start capacitor after an UVLO or thermal
shutdown event in order to restart the switching activity ramping the error amplifier reference
voltage.
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Functional description
Figure 9. External soft-start after UVLO or thermal shutdown
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4.3.1
L6986F
Ratiometric startup
The ratiometric startup is implemented sharing the same soft-start capacitor for a set of the
L6986F devices.
Figure 10. Ratiometric startup
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As a consequence all the internal current generators charge in parallel the external
capacitor. The capacitor value is dimensioned accordingly with Equation 12:
Equation 12
I SSCH T SS
4A T SS
C SS = n L6986F SS GAIN -------------------------------- = n L6986F 3 --------------------------0.85V
V FB
where nL6986F represents the number of devices connected in parallel.
For better tracking of the different output voltages the synchronization of the set of
regulators is suggested.
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Functional description
Figure 11. Ratiometric startup operation
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4.3.2
L6986F
Output voltage sequencing
The L6986F device implements sequencing connecting the RST pin of the master device to
the SS/INH of the slave. The slave is inhibited as long as the master output voltage is
outside regulation so implementing the sequencing (see Figure 12).
Figure 12. Output voltage sequencing
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