L6995STR

L6995S STEP DOWN CONTROLLER FOR HIGH DIFFERENTIAL INPUT-OUTPUT CONVERSION 1 Figure 1. Package ■ FEATURES CONSTANT ON TIME TOPOLOGY ALLOWS OPERATION WITH LOWER DUTY THAN PWM TOPOLOGY VERY FAST LOAD TRANSIENTS 5V Vcc SUPPLY 1.5V TO 35V INPUT VOLTAGE RANGE 0.9V ±1% VREF MINIMUM OUTPUT VOLTAGE AS LOW AS 0.9V SELECTABLE SINKING MODE LOSSLESS CURRENT LIMIT REMOTE SENSING OVP,UVP LATCHED PROTECTIONS 600µA TYP QUIESCENT CURRENT POWER GOOD AND OVP SIGNALS PULSE SKIPPING AT LIGHT LOADS ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ 2 ■ APPLICATIONS I/O BUS FOR CPU CORE SUPPLY NOTEBOOK COMPUTERS NETWORKING DC-DC DISTRIBUTED POWER ■ ■ ) s ( ct ■ u d o TSSOP20 Table 1. Order Codes Part Number Package L6995S TSSOP20 L6995STR Tape & Reel c u d ) s t( 3 DESCRIPTION The device is a step-down controller specifically designed to provide extremely high efficiency conversion, with losses current sensing tecnique. The "constant on-time" topology assures fast load transient response. The embedded "voltage feed-forward" provides nearly constant switching frequency operation. An integrator can be introduced in the control loop to reduce the static output voltage error. The available remote sensing improve the static and dynamic regulation recovering the wires voltage drop. Pulse skipping technique reduces power consumption at light load. Drivers current capability allows output current in excess of 20A. e t le o r P o s b O - Figure 2. Minimum Component Count Application Rin1 5V t e l o VDR CIN SHDN VCC r P e 35V Rin2 OSC bs 5V BOOT HGATE C HS PHASE O LGATE D BOOT BOOT Vo L LS RILIM DS 0.9V COUT PGND ILIM L6995S GND NOSKIP VSENSE SS CSS INT VFB VREF CVREF April 2004 REV. 1 1/26 L6995S Table 2. Absolute Maximum Ratings Symbol Value Unit VCC VCC to GND Parameter -0.3 to 6 V VDR VDR to GND -0.3 to 6 V HGATE and BOOT, to PHASE -0.3 to 6 V VPHASE BOOT, HGATE and PHASE PINS HGATE and BOOT, to PGND -0.3 to 42 V PHASE -0.3-to 36 V LGATE to PGND -0.3 to VDR+0.3 V ILIM, VFB, VSENSE, NOSKIP, SHDN, PGOOD, OVP, VREF, INT, GNDSENSE to GND -0.3 to VCC+0.3 V ±750 V Maximum Withstanding Voltage Range Test Condition:CDF-AEC-Q100-002 “Human Body Model” Accepatance Criteria: “Normal Performance” OTHER PINS Ptot Power dissipation at Tamb = 25°C Tstg Storage temperature range ±2000 V 1 W -40 to 150 c u d Table 3. Thermal Data Symbol Rth j-amb Parameter Thermal Resistance Junction to Ambient e t le Junction operating temperature range Tj Figure 3. Pin Connection (Top View) NOSKIP 1 GNDSENSE 2 (s) INT o r P e BOOT 19 HGATE 18 PHASE 17 VDR VCC 5 16 LGATE GND 6 15 PGND VREF 7 14 PGOOD VFB 8 13 OVP OSC 9 12 SHDN 10 11 ILIM t e l o s b O 20 4 SS Value Unit 125 °C/W 0 to 125 °C o r P o s b O - VSENSE ct du 3 ) s t( °C TSSOP20 Table 4. Pin Function N° 2/26 Name Description 1 NOSKIP Connect to VCC to force continuous conduction mode and sink mode. 2 GNDSE NSE 3 INT 4 VSENS E Remote ground sensing pin Integrator output. Short this pin to VFB pin and connect it via a capacitor to VOUT to insert the integrator in the control loop. If the integrator is not used, short this pin to VREF. This pin must be connected to the remote output voltage to detect overvoltage and undervoltage conditions and to provide integrator feedback input. L6995S Table 4. Pin Function (continued) N° Name 5 VCC Description IC Supply Voltage. 6 GND Signal ground 7 VREF 0.9 V voltage reference. Connect max. a 10nF ceramic capacitor between this pin and ground. This pin is capable to source or sink up to 250uA 8 VFB PWM comparator feedback input. Short this pin to INT pin when using the integrator function, or to VSENSE pin without integrator. 9 OSC Connect this pin to the input voltage through a voltage divider in order to provide the feedforward function. It cannot be left floating. 10 SS Soft start pin. A 5µA constant current charges an external capacitor which value sets the softstart time. 11 ILIM 12 SHDN An external resistor connected between this pin and GND sets the current limit threshold. Shutdown. When connected to GND the device and the drivers are OFF. It cannot be left floating. 13 OVP 14 PGOOD Open drain output. During the over voltage condition it is pulled up by an external resistor. 15 PGND Low Side driver ground. 16 LGATE Low Side driver output. 17 VDR Low Side driver supply. 18 PHASE Return path of the High Side driver. 19 HGATE High side MOSFETS driver output. 20 BOOT Bootstrap capacitor pin. High Side driver is supplied through this pin. Open drain output. During the soft start and in case of output voltage fault it is low. It is pulled up by external resistor. c u d e t le o s b O - ) s t( o r P Table 5. Electrical Characteristics (VCC = VDR = 5V; Tamb = 0°C to 85°C unless otherwise specified) Symbol Parameter ) s ( ct SUPPLY SECTION Vin Input voltage range VCC, VDR VCC Turn-onvoltage Vout=Vref Fsw=110Khz Iout=1A u d o r P e Turn-off voltage Test Condition Min. t e l o IqVcc s b O Max. 1.5 35 V 5.5 V 4.2 4.4 V 4.1 4.3 V 100 Quiescent Current Drivers VFB > VREF Device Quiescent current VFB > VREF Unit 4.5 Hysteresis IqVDR Typ. 400 mV 20 µA 600 µA SHUTDOWN SECTION SHDN Device On 1.2 V Device Off ISHVDR Drivers shutdown current SHDN to GND ISHVCC Devices shutdown current SHDN to GND 10 0.6 V 5 µA 15 µA 6 µA 500 mV SOFT START SECTION ISS Soft Start current VSS = 0.8V 4 SS Clamp Voltage Soft start active range 4 400 450 V 3/26 L6995S Table 5. Electrical Characteristics (continued) (VCC = VDR = 5V; Tamb = 0°C to 85°C unless otherwise specified) Symbol Parameter Test Condition Min. Typ. Max. Unit 4.9 5 5.1 µA 2 mV CURRENT LIMIT AND ZERO CURRENT COMPARATOR ILIM input bias current RILIM = 2KΩ to 400KΩ Zero Crossing Comparator Offset Phase-gnd -2 ON TIME Ton On time duration VREF=VSENSE OSC=250mV 850 950 1050 ns VREF=VSENSE OSC=500mV 470 520 570 ns VREF=VSENSE OSC=1V 250 285 320 ns VREF=VSENSE OSC=2V 130 160 190 ns 580 ns OFF TIME TOFFMIN Minimum off time KOSC/TOFFMIN OSC=250mV 0.30 0µA < IREF < 100µA 0.891 0.60 VOLTAGE REFERENCE VREF Voltage Accuracy 0.9 Input voltage offset IFB -2 Input Bias Current INT Over Voltage Clamp VSENSE = VCC Under Voltage Clamp VSENSE = GND Integrator Input Offset Voltage VSENSE-VREF IVSENSE Input Bias Current GATE DRIVERS High side rise time High side fall time Low side rise time Low side fall time o r P e +2 mV o r P 0.1 INTEGRATOR INT V c u d PWM COMPARATOR ) s t( 0.909 c u d (t s) o s b O - e t le µA 1.04 1.07 1.1 0.82 0.84 0.86 V 5 mV -5 V µA 0.1 VDR=3.3V; C=7nF HGATE - PHASE from 1 to 3V 50 70 ns 50 70 ns VDR=3.3V; C=14nF LGATE from 1 to 3V 50 70 ns 50 70 ns 112 115 118 % 66 69 72 % PGOOD UVP/OVP PROTECTIONS OVP Over voltage threshold t e l o UVP PGOOD s b O PGOOD VPGOOD 4/26 with respect to VREF Under voltage threshold Upper threshold (VSENSE-VREF) VSENSE rising 107 110 113 % Lower threshold (VSENSE-VREF) VSENSE falling 86 89 92 % 0.14 0.2 V ISink=2mA V IN 5 uA VREF 0.9V power management 1.416 VREF 1.236V bandgap HS control pwm comparator Reference chain + + - - + + IC enable soft-start control S R NOSKIP 1.15 VREF - VSENSE 0.69 VREF - + - + 0.89 VREF VSENSE VSENSE 1.10 VREF pgood comparators + - undervoltage comparator VSENSE + overvoltage comparator one-shot Ton Ton min one-shot Toff min delay LS control Q GND zero-cross comparator - + no-skip mode Ton= Kosc V(VSENSE)/V(OSC) PHASE S R VCC no-skip mode R S Q V(PHASE)