L6996

L6996 DINAMICALLY PROGRAMMABLE SYNCHRONOUS STEP DOWN CONTROLLER FOR MOBILE CPUs s s s s s s s s s s s s s s 5 BIT DAC WITH AVAILABLE EXTERNAL OUTPUT VOLTAGE. 0.6 TO 1.750V, DYNAMICALLY ADJUSTABLE OUTPUT VOLTAGE RANGE. ±1% OUTPUT ACCURACY OVER LINE AND LOAD. ACTIVE DROOP. CONSTANT ON TIME TOPOLOGY ALLOWS LOW DUTY CYCLE AND FAST LOAD TRANSIENT. 90% EFFICIENCY FROM 12V TO 1.35V/8A. 1.750V TO 28V BATTERY INPUT RANGE. OPERATING FREQUENCY UP TO 1MHZ. INTEGRATED HIGH CURRENT DRIVERS. LATCHED OVP AND UVP PROTECTIONS. OCP PROTECTION. 350µA TYP. QUIESCENT CURRENT. 7µA TYP. SHUTDOWN SUPPLY CURRENT. PGOOD AND OVP SIGNALS. ZERO-CURRENT DETECTION AND PULSEFREQUENCY MODE. TSSOP24 ORDERING NUMBERS: L6996D (TSSOP24) L6996DTR (Tape & Reel) APPLICATIONS s ADVANCED MOBILE CPUs SUPPLY WITH DYNAMIC TRANSITIONS. s NOTEBOOK/LAPTOP, CONCEPT PC CPUs SUPPLY. s DC/DC FROM BATTERY SUPPLY EQUIPMENTS. APPLICATION DIAGRAM 5V DESCRIPTION The device is dc-dc controller specifically designed to provide extremely high efficiency conversion for mobile advanced microprocessors. The "constant on-time" topology assures fast load transient response. The embedded "voltage feedforward" provides nearly constant switching frequency operation. A precise 5-bit DAC allows select output voltage from 0.6V to 1V with 25mV steps and from 1V to 1.75V with 50mV steps. L6996 is capable of supporting CPUs VID combination changing during normal operation. The active droop allows adjust both the output loadline slope and the zero-load output voltage. 25V VCC VDR OSC BOOT HGATE HS 5V L PHASE PGOOD OVP RSENSE V OUT 1.25V L6996 LGATE LS DS ILIM PGND GND CS+ CS- SS CSS VFBVFB+ SHDN VID4:0 VPROG CVPROG July 2002 1/26 L6996 ABSOLUTE MAXIMUM RATINGS Symbol VCC VDR VCC to GND VDR to GND HGATE and BOOT, to PHASE HGATE and BOOT, to PGND VPHASE PHASE LGATE to PGND ILIM, VFB+, VFB-, CS-, CS+, SHDN, VID0-4, PGOOD, OVP, VPROG to GND Ptot Tj Tstg Maximum Power dissipation at Tamb = 25°C Junction operating temperature range Storage temperature range Parameter Value -0.3 to 6 -0.3 to 6 -0.3 to 6 -0.3 to 36 -0.3 to 30 -0.3 to VDR+0.3 -0.3 to VCC+0.3 1 0 to 125 -55 to 125 Unit V V V V V V V W °C °C THERMAL DATA Symbol Rth j-amb Parameter Thermal Resistance Junction to Ambient Value 125 Unit °C/ W PIN CONNECTION VID2 VID1 VID0 CSCS+ VCC GND VPROG VFB+ VFBOSC SS 1 2 3 4 5 6 7 8 9 10 11 12 TSSOP24 24 23 22 21 20 19 18 17 16 15 14 13 VID3 VID4 BOOT HGATE PHASE VDR LGATE PGND PGOOD OVP SHDN ILIM 2/26 L6996 PIN FUNCTIONS N 1,2,3, 23,24 4 5 6 7 8 9 Name VID4-0 CSCS+ VCC GND VPROG VFB+ Description Voltage Identification inputs. VID0 is the LSB and VID4 is the MSB for the DAC (see VID table) This pin is used for both current sensing and to detect overvoltage and undervoltage conditions. Current sense pin. Overcurrent condition is detected by sensing CS+ to CS- voltage. Supply voltage for analogy blocks. Connect it to 5V bus. Signal ground DAC output voltage. This pin provides the voltage programmed by the DAC. Connect a 10nF capacitor between this pin and GND. PWM comparator reference input. Connect this pin to VPROG. An additional external voltage divider between output and VPROG may be used to realize the active droop function. PWM comparator feedback input, to be connected to the regulated output. By inserting a resistor between this pin and the regulated output, a positive offset can be added to the output voltage. Connect this pin to the battery through a voltage divider in order to provide the voltage feedforward feature. Soft start pin. 5µA constant current charges an external capacitor whose value sets the softstart time. An external resistor connected between this pin and GND sets the current limit threshold. ShutDown input. When connected to GND the device stops working. When high, it enables the IC operation. Open drain output. The pull-down transistor is off either in OV condition or during a VID transition. Open drain output. The pull-down transistor is on during soft-start, dynamic transitions and when an output voltage fault occurs. Power Ground. This pin has to be connected close to the low side MOSFET source in order to minimize switching noise. Lower MOSFET gate driver output. Voltage supply for the low side internal driver. This pin provides the return path of the high side driver. High side MOSFET driver output. Bootstrap capacitor pin. The high side driver is supplied through this pin. 10 VFB- 11 12 13 14 15 16 17 18 19 20 21 22 OSC SS ILIM SHDN OVP PGOOD PGND LGATE VDR PHASE HGATE BOOT 3/26 L6996 ELECTRICAL CHARACTERISTICS (VCC = VDR = 5V; Tamb = 0°C to 70°C unless otherwise specified) Symbol SUPPLY SECTION Vin Vcc, VDR Vccoff VHYST Iqcc (VDR) Iqcc (Vcc) SHDN ISH (VDR) Turn-off voltage UVLO Hysteresys Quiescent current driver Quiescent current VFB- > VFB+ VFB- > VFB+ Input voltage range Vout=1V Fsw=110Khz Iout=1A 1 4.5 4.1 60 90 28 5.5 4.3 100 20 600 V V V mV µA µA Parameter Test Condition Min. Typ. Max. Unit SHUTDOWN SECTION SHDN Threshold Driver quiescent current in shutdown. SHDN to GND SHDN to GND 4 0.9 Vprog=CS- =1.15 Osc=250mV Vprog=CS-=1.15 Osc=500mV Vprog=CS-=1.15 Osc=1V Vprog=CS-=1.15 Osc=2V OFF TIME Minimum Off Time KOSC/TOFFMIN DAC Vprog Voltage Accuracy Input voltage offset IVFBILIM KC PHASEGND Input bias current (VP) ILIM input bias current Positive and negative Current Limit factor. Zero Crossing Comparator offset VID0-4 see table 1 V PROG=1.6V=VFBVVFB- =1.6V CS-=VPROG=1.6V ILIM to GND = 120KΩ RILIM = 120 KΩ 0.18 -2 -1 -2 4 5 4.95 0.3 0.24 2 +1 +2 6 % mV µA µA µA mV PWM COMPARATOR OSC=250mV VPROG=CS-=1.15V 0.28 580 ns 720 355 210 120 800 420 250 150 880 485 290 180 0.6 1.2 5 15 6 V µA µA µA V ns ns ns ns ISH (Vcc) Shut down current SOFT START SECTION ISS ON TIME Ton On time duration SS charge current Soft-start active range CURRENT LIMIT AND ZERO CURRENT COMPARATOR GATE DRIVERS High side rise time High side fall time Low side rise time Low side fall time PROTECTIONS OVP Over voltage trip CS- rising 117 120 123 % VDR=5V; C=7nF HGATE - PHASE from 2 to 4.5V 50 50 50 50 70 70 70 70 ns ns ns ns 4/26 L6996 ELECTRICAL CHARACTERISTICS (continued) (VCC = VDR = 5V; Tamb = 0°C to 70°C unless otherwise specified) Symbol UVP PGOOD PGOOD Ron PGOOD Parameter Under voltage trip Upper threshold (CS-/VPROG) Lower threshold (CS-/VPROG) Test Condition CS- falling CS- rising; PGOOD active CS- falling; PGOOD active ISOURCE=2mA Min. 66 109 84 40 Typ. 69 112 87 60 Max. 72 115 90 100 Unit % % % Ω Table 1. DAC Output Voltage VID4 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VID3 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 VID2 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 VID1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 VID0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 Output Voltage (V) 0.600 0.625 0.650 0.675 0.700 0.725 0.750 0.775 0.800 0.825 0.850 0.875 0.900 0.925 0.950 0.975 1.000 1.050 1.100 1.150 1.200 1.250 1.300 1.350 1.400 1.450 1.500 1.550 1.600 1.650 1.700 1.750 5/26 VCC FB- - Ton= Kosc V(CS-)/V(OSC) S Q pwm comparator CS- OSC Ton= Kosc V(CS-)/V(OSC) VID4:0 dynamic transition control PHASE + zero-cross comparator dynamic transition detection 80 us one-shot dynamic transition mode dynamic transition mode 5 bit DAC bandgap 1.236V + + CS+ CS0.05 negative current limit comparator VPROG 1.416 ILIM VID4:0 DAC configuration LS control Reference chain CS- OSC 6/26 5V PGOOD VCC GND + CS1.12 VPROG undervoltage comparator CS0.6 VPROG IC enable pgood comparators + 1.075 VPROG CSCS0.925 VPROG HGATE BOOT V(LGATE) VPHASE CH2 -> VOUT CH4 -> IL CH1 -> VOUT CH2 -> SS CH3 -> IL Figure 6. Startup with 10A Figure 3. Dynamic Output Voltage Transition 1.35V -> 1.55V CH1 -> VOUT CH2 -> SS CH3 -> IL CH1 -> VPHASE CH2 -> VOUT CH4 -> IL Figure 4. Load Transient 0-15A CH1 -> VOUT CH2 -> VOUT CH4 -> IL 7/26 L6996 Figure 7. Test Condition: Vin = 20V, V5v=5V, Fsw = 300kHz, Tamb = +25°C Efficency [%] 0.88 0.86 0.84 0.82 0.8 Vout=1.25 Vout=1.35 Vout=1.7 0.78 0.76 0.10 1.00 Current [A] 10.00 100.00 Figure 8. Test Condition: Vout = 1.75V, Fsw = 300kHz, V5v = 5V, Tamb = +25°C Efficency [%] 0.92 0.91 0.9 0.89 0.88 0.87 0.86 0.85 0.84 0.83 0.82 0.81 0.1 1.0 Vin=7 Vin=12 Vin=20 10.0 100.0 Current [A] Figure 9. Test Condition: Vout = 1.75V, V5v = 5V, Tamb = +25°C Frequency [KHz] 410 390 370 350 330 310 290 270 250 4 5 6 7 8 9 10 11 12 13 14 15 Vin=20 Vin=12 Vin=7 Current [A] 8/26 L6996 Figure 10. Typical Application with Active Voltage Droop 5V CV51 RV5 RVIN1 RVIN2 CVIN1 CVIN2 V IN VCC CV52 OSC VDR BOOT HGATE C HS D BOOT BOOT RPU2 RPU1 PHASE PGOOD OVP LGATE LS L RSENSE V OUT RIL1 ILIM L6996 DS CPU COUT COUT1 PGND GND RIL2 MIL SS CS+ CSVFBVFB+ CVP3 RVP1 RVP3 RVP2 CVP1 CSS SHDN VID4:0 VPROG CVPROG Figure 11. Typical Application without Active Voltage Droop 5V CV51 RV5 RVIN1 RVIN2 CVIN1 CVIN2 V IN VCC CV52 OSC VDR BOOT HGATE C HS D BOOT BOOT RPU2 RPU1 PHASE PGOOD OVP LGATE LS L RSENSE V OUT RIL1 ILIM L6996 DS CPU COUT COUT1 PGND GND RIL2 MIL SS CS+ CSVFBVFB+ CSS SHDN VID4:0 VPROG CVPROG 9/26 L6996 1 DEVICE DESCRIPTION 1.1 Constant On Time PWM Topology Figure 12. Loop block schematic diagram Vin R1 One-shot generator OSC CSFFSR RQ HGATE S Q LS LGATE VID0-4 DS R2 HS Rsense Vout DAC Vprog VFB+ VFB- + -PWM comparator This device implements a Constant On Time control, where the Ton is the on time duration forced by a one-shot circuit. The controller calculates the one-shot time directly proportional to the V CS- pin voltage and inversely to the OSC pin voltage as in Eq 1: Eq 1 V CST O N = K O SC -------------- + τ V OS C where KOSC=180ns and τ is the internal propagation delay time (Typ. 40ns). The system imposes in steady state a minimum on time corresponding to V OSC = 2V. In fact if the VOSC voltage increases above 2V the corresponding Ton will not decrease. Connecting OSC pin to a voltage partition from VIN to GND, it allows steadystate switching frequency FSW independent of V IN. It results: Eq 2 where Eq 3 R2 V OS C α O SC = -------------- = -------------------V IN R2 + R 1 V OUT 1 F SW = -------------- ⋅ ---------- → α O SC = F SW ⋅ K O SC V IN T O N The above equations allow setting the frequency divider ratio aOSC once output voltage has been set; note that such equations hold only if VOSC