L6997S
STEP DOWN CONTROLLER
FOR LOW VOLTAGE OPERATIONS
1
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Figure 1. Package
Features
FROM 3V TO 5.5V VCC RANGE
MINIMUM OUTPUT VOLTAGE AS LOW AS
0.6V
1V TO 35V INPUT VOLTAGE RANGE
CONSTANT ON TIME TOPOLOGY
VERY FAST LOAD TRANSIENTS
0.6V, ±1% VREF
SELECTABLE SINKING MODE
LOSSLESS CURRENT LIMIT, AVAILABLE
ALSO IN SINKING MODE
REMOTE SENSING
OVP,UVP LATCHED PROTECTIONS
600µA TYP QUIESCENT CURRENT
POWER GOOD AND OVP SIGNALS
PULSE SKIPPING AT LIGTH LOADS
94% EFFICIENCY FROM 3.3V TO 2.5V
TSSOP20
Table 1. Order Codes
3
Applications
NETWORKING
■ DC/DC MODULES
■ DISTRIBUTED POWER
■ MOBILE APPLICATIONS
■ CHIP SET, CPU, DSP AND MEMORIES
SUPPLY
Figure 2. Minimum Component Count Application
■
Part Number
Package
L6997S
TSSOP20
L6997STR
Tape & Reel
Description
The device is a high efficient solution for networking
dc/dc modules and mobile applications compatible
with 3.3V bus and 5V bus.
It's able to regulate an output voltage as low as 0.6V.
The constant on time topology assures fast load transient response. The embedded voltage feed-forward
provides nearly constant switching frequency operation in spite of a wide input voltage range.
An integrator can be introduced in the control loop to
reduce the static output voltage error.
The remote sensing improves the static and dynamic
regulation, recovering the wires voltage drop.
Pulse skipping technique reduces power consumption at light loads. Drivers current capability allows
output currents in excess of 20A.
3.3V
Rin2
Rin1
VCC
VDR
Cin
OSC
Dboot
BOOT
HGATE
HS
Cboot
L
0.6V
PHASE
PGOOD
Ro1
OVP
LGATE
ILIM
L6997SPGND
LS
DS
Cout
Ro2
GND
GNDSENSE
Rilim
SS
Css
VSENSE
INT
VFB
SHDN
Vref
Cvref
June 2004
REV. 1
1/30
L6997S
Table 2. Absolute Maximum Ratings
Symbol
Parameter
VCC
VDR
VPHASE
BOOT, HGATE
and PHASE
PINS
Value
Unit
VCC to GND
-0.3 to 6
V
VDR to GND
-0.3 to 6
V
HGATE and BOOT, to PHASE
-0.3 to 6
V
HGATE and BOOT, to PGND
-0.3 to 42
V
PHASE
-0.3-to 36
V
LGATE to PGND
-0.3 to VDR+0.3
V
ILIM, VFB, VSENSE, NOSKIP, SHDN, PGOOD, OVP, VREF,
INT, GNDSENSE to GND
-0.3 to VCC+0.3
V
±750
V
Maximum Withstanding Voltage Range
Test Condition:CDF-AEC-Q100-002 “Human Body Model”
Accepatance Criteria: “Normal Performance”
OTHER PINS
Ptot
Power dissipation at Tamb = 25°C
Tstg
Storage temperature range
±2000
V
1
W
-40 to 150
°C
Value
Unit
125
°C/W
-40 to 125
°C
Table 3. Thermal Data
Symbol
Rth j-amb
Tj
Parameter
Thermal Resistance Junction to Ambient
Junction operating temperature range
Figure 3. Pin Connection (Top View)
NOSKIP
1
20
BOOT
GNDSENSE
2
19
HGATE
INT
3
18
PHASE
VSENSE
4
17
VDR
VCC
5
16
LGATE
GND
6
15
PGND
VREF
7
14
PGOOD
VFB
8
13
OVP
OSC
9
12
SHDN
11
ILIM
SS
10
TSSOP20
Table 4. Pin Function
N°
Name
1
NOSKIP
2
GNDSENSE
3
INT
4
VSENSE
2/30
Description
Connect to VCC to force continuous conduction mode and sink mode.
Remote ground sensing pin
Integrator output. Short this pin to VFB pin and connect it via a capacitor to VOUT to insert the
integrator in the control loop. If the integrator is not used, short this pin to VREF.
This pin must be connected to the remote output voltage to detect overvoltage and
undervoltage conditions and to provide integrator feedback input.
L6997S
Table 4. Pin Function (continued)
N°
Name
5
VCC
IC Supply Voltage.
Description
6
GND
Signal ground
7
VREF
0.6V voltage reference. Connect a ceramic capacitor (max. 10nF) between this pin and
ground. This pin is capable to source or sink up to 250uA
8
VFB
PWM comparator feedback input. Short this pin to INT pin to enable the integrator function, or
to VSENSE to disable the integrator function.
9
OSC
Connect this pin to the input voltage through a voltage divider in order to provide the feedforward function don’t leave floating.
10
SS
Soft Start pin. A 5µA constant current charges an external capacitor. Itsvalue sets the softstart time don’t leave floating.
11
ILIM
12
SHDN
Shutdown. When connected to GND the device and the drivers are OFF. It cannot be left
floating.
13
OVP
Open drain output. During the over voltage condition it is pulled up by an external resistor.
14
PGOOD
An external resistor connected between this pin and GND sets the current limit threshold don’t
leave floating..
Open drain output. It is pulled down when the output voltage is not within the specified
thresholds. Otherwise is pulled up by external resistor. If not used it can be left floating.
15
PGND
Low Side driver ground.
16
LGATE
Low Side driver output.
17
VDR
Low Side driver supply.
18
PHASE
19
HGATE
High side driver output.
20
BOOT
Bootstrap capacitor pin. High Side driver is supplied through this pin.
Return path of the High Side driver.
Table 5. Electrical Characteristics
(VCC = VDR = 3.3V; Tamb = 0°C to 85°C unless otherwise specified)
Symbol
Parameter
Test Condition
Min.
Typ.
Max.
Unit
SUPPLY SECTION
Vin
Input voltage range
Vout=Vref Fsw=110Khz Iout=1A
1
35
V
3
5.5
V
Turn-onvoltage
2.86
2.97
V
Turn-off voltage
2.75
2.9
V
VCC,
VDR
VCC
Hysteresis
90
mV
IqVDR
Drivers Quiescent Current
VFB > VREF
7
20
µA
IqVcc
Device Quiescent current
VFB > VREF
400
600
µA
SHUTDOWN SECTION
SHDN
Device On
1.2
V
Device Off
ISHVDR
Drivers shutdown current
SHDN to GND
ISHVCC
Devices shutdown current
SHDN to GND
0.6
V
5
µA
1
15
µA
6
µA
400
500
mV
SOFT START SECTION
ISS
∆VSS
Soft Start current
Active Soft start and voltage
VSS = 0.4V
4
300
3/30
L6997S
Table 5. Electrical Characteristics (continued)
(VCC = VDR = 3.3V; Tamb = 0°C to 85°C unless otherwise specified)
Symbol
Parameter
Test Condition
Min.
Typ.
Max.
Unit
4.6
5
5.4
µA
2
mV
CURRENT LIMIT AND ZERO CURRENT COMPARATOR
ILIM
KILIM
Input bias current
RILIM = 2KΩ to 200KΩ
Zero Crossing Comparator offset
Phase-gnd
-2
Current limit factor
1.6
1.8
2
µA
VREF=VSENSE OSC=125mV
720
800
880
ns
VREF=VSENSE OSC=250mV
370
420
470
ns
VREF=VSENSE OSC=500mV
200
230
260
ns
VREF=VSENSE OSC=1000mV
90
115
140
ns
600
ns
ON TIME
Ton
On time duration
OFF TIME
TOFFMIN
Minimum off time
KOSC/TOFFMIN
OSC=250mV
0.20
0µA < IREF < 100µA
0.594
0.40
VOLTAGE REFERENCE
VREF
Voltage Accuracy
0.6
0.606
V
+2
mV
PWM COMPARATOR
Input voltage offset
IFB
-2
Input Bias Current
20
nA
INTEGRATOR
Over Voltage Clamp
VSENSE = VCC
0.62
0.75
0.88
V
Under Voltage Clamp
VSENSE = GND
0.45
0.55
0.65
V
-4
mV
-4
Integrator Input Offset Voltage
VSENSE-VREF
IVSENSE
Input Bias Current
20
nA
GATE DRIVERS
High side rise time
High side fall time
Low side rise time
Low side fall time
VDR=3.3V; C=7nF
HGATE - PHASE from 1 to 3V
50
90
ns
50
100
ns
VDR=3.3V; C=14nF
LGATE from 1 to 3V
50
90
ns
50
90
ns
121
124
%
PGOOD UVP/OVP PROTECTIONS
OVP
UVP
VPGOOD
4/30
with respect to VREF
118
67
70
73
%
Upper threshold
(VSENSE-VREF)
VSENSE rising
110
112
116
%
Lower threshold
(VSENSE-VREF)
VSENSE falling
85
88
91
%
0.2
0.4
V
Over voltage threshold
Under voltage threshold
ISink=2mA
V IN
5 uA
0.6V
VREF
OSC
SENSEGND
Gm
+
+
-
VREF
soft-start
control
IC enable
power management
1.236V
bandgap
HS control
pwm comparator
1.416
-
+
+
Reference chain
VREF
0.05
+
positive current limit
comparator
PHASE
VREF
VSENSE
INT
FB
ILIM
SS
NOSKIP
OVP
R
one-shot
Ton
Ton min
one-shot
Toff min
delay
S
1.12 VREF
-
VSENSE
0.6 VREF
0.925 VREF
VSENSE
VSENSE
1.075 VREF
LS control
PHASE
S
R
VCC
Q
GND
zero-cross comparator
-
+
no-skip
mode
Ton= Kosc V(VSENSE)/V(OSC)
-
+
-
+
pgood comparators
+
-
undervoltage comparator
VSENSE
+
overvoltage comparator
OSC
PGOOD
VSENSE
no-skip
mode
R
S
-
+
-
+
Q
S
R
one-shot
Ton
Q
level shifter
OSC
LS driver
HS driver
0.05
ILIM
negative current limit
comparator
Ton= Kosc V(VSENSE)/V(OSC)
PHASE
V(PHASE) Output voltage
Figure 29. Eff. vs Output Current sink mode
Figure 31. Normal functionality in SINK mode..
100
Efficiency (%)
95
90
85
Vin = 1.8V
80
Vout=0.9V
Vcc=5V
Fsw=200KHz
75
70
65
Vin=12V
Vin = 12V
60
0
1
2
3
4
5
6
7
Output current (A)
Ch1-> Inductor current
Ch2-> Phase Node
Ch3-> Output voltage
26/30
L6997S
Figure 32. Normal functionality in PWM mode.
Ch1-> Inductor current
Ch2-> Phase Node
Ch3-> Output voltage
Figure 33. Normal functionality in PFM mode.
Ch1-> Inductor current
Ch2-> Phase Node
Ch3-> Output voltage
Figure 34. Start up waveform with 0A load.
Ch1-> Inductor current
Ch2-> Soft start Voltage
Ch3-> Output voltage
Figure 35. Start up waveform with 5A load..
Ch1-> Inductor current
Ch2-> Soft start Voltage
Ch3-> Output voltage
27/30
L6997S
Figure 36. TSSOP20 Mechanical Data & Package Dimensions
mm
inch
DIM.
MIN.
TYP.
A
MAX.
MIN.
TYP.
1.20
A1
0.050
A2
0.800
b
MAX.
0.047
0.150
0.002
1.050
0.031
0.190
0.300
0.007
0.012
c
0.090
0.200
0.004
0.008
D (1)
6.400
6.500
6.600
0.252
0.256
0.260
E
6.200
6.400
6.600
0.244
0.252
0.260
E1 (1) 4.300
4.400
4.500
0.170
0.173
0.177
e
L
L1
k
aaa
1.000
0.650
0.450
0.600
OUTLINE AND
MECHANICAL DATA
0.006
0.039
0.041
0.026
0.750
0.018
1.000
0.024
0.030
0.039
0˚ (min.) 8˚ (max.)
0.100
0.004
Note: 1. D and E1 does not include mold flash or protrusions.
Mold flash or potrusions shall not exceed 0.15mm
(.006inch) per side.
TSSOP20
Thin Shrink Small Outline Package
0087225 (Jedec MO-153-AC)
28/30
L6997S
Table 15. Revision History
Date
Revision
June 2004
1
Description of Changes
First Issue.
29/30
L6997S
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences
of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted
by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject
to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not
authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics.
The ST logo is a registered trademark of STMicroelectronics.
All other names are the property of their respective owners
© 2004 STMicroelectronics - All rights reserved
STMicroelectronics GROUP OF COMPANIES
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30/30
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