L7983
Datasheet
60 V, 300 mA synchronous step-down switching regulator with 10 µA quiescent
current
Features
•
•
3.5 V to 60 V operating input voltage
Fixed output voltage (3.3 V and 5 V) or adjustable from 0.85 V to VIN
•
•
•
300 mA DC output current
Dynamic low consumption mode to low noise mode selection
10 µA operating quiescent current (L7983PU33R, VIN > 24 V, LCM)
•
•
•
•
•
•
•
•
•
•
•
2.3 µA shutdown current
200 kHz to 2.2 MHz programmable switching frequency
Optional spread spectrum (dithering)
Internal soft-start
Enable / adjustable UVLO threshold
Synchronization to external clock
Internal compensation network
Internal current limiting
Overvoltage protection
Output voltage sequencing
Thermal shutdown
Applications
Maturity status link
L7983
•
•
•
•
•
Designed for 12 V, 24 V and 48 V buses
Battery powered applications
Decentralized intelligent nodes
Fail safe system
Sensors and low noise applications (LNM)
Description
The L7983 device is a step-down monolithic switching regulator able to deliver up to
300 mA DC based on peak current mode architecture.
The output voltage adjustability ranges from 0.85 V to VIN. The wide input voltage
range and adjustable UVLO threshold meet the specification for the 12 V, 24 V and
48 V industrial bus standards.
The “Low Consumption Mode” (LCM) is designed for applications active during idle
mode, so it maximizes the efficiency at light load with controlled output voltage ripple.
The “Low Noise Mode” (LNM) makes the switching frequency constant overload
current range, meeting the low noise application specification. The L7983 supports
dynamic LCM to LNM transition.
The soft-start time is internally fixed and the output voltage supervisor manages the
reset phase for any digital load (microcontroller, FPGA, etc.).
The internal compensation network features high noise immunity, simple design and
saves on the component cost.
The RST open collector output can also implement output voltage sequencing during
the power-up phase.
DS13354 - Rev 1 - October 2020
For further information contact your local STMicroelectronics sales office.
www.st.com
L7983
The synchronous rectification, designed for high efficiency at medium - heavy load,
and the high switching frequency capability make the size of the application compact.
Pulse-by-pulse current sensing on both power elements implements an effective
constant current protection.
DS13354 - Rev 1
page 2/43
L7983
Application schematic and block diagram
1
Application schematic and block diagram
1.1
Application circuit
Figure 1. Typical application circuit
RESET
L7983
VIN
RST
VIN
EN/UVLO
GND
VOUT
LX
VCC
VOUT(FB)
FSW
VBIAS
LNM/LCM
EP
GND
GND
Figure 2. Block diagram
VBIAS
EN/UVLO
+
-
VCC
VCC
VIN MONITOR
UVLO
LDO
OTP
MONITOR
BIAS
and
REFERENCE
+
ENABLE
-
CLOCK
VIN
SLOPE
VIN
+ +
ENABLE
HS MOS
CLOCK
+
IPK
PWM
END SS
LOGIC
and
CONTROL
-
END SS
VMAX
VREF
VOUT(FB)
+
+
SOFT-START
CONTROL
-
SENSE
SENSE
LX
DRIVER
and
ANTI XC
COMP
gm
LX
LX
VMIN
LX
+
ZCD
-
+
FSW SET
FSW
DS13354 - Rev 1
GND
IVY
+
+
OVP
-
LS MOS
CLOCK
-
RST
SYNCH
LX
VCC
LNM/LCM
page 3/43
L7983
Pin settings
2
Pin settings
Figure 3. Pin connection (top view)
VOUT/FB
1
10
VBIAS
2
9
LX
VCC
3
8
VIN
FSW
4
7
EN/UVLO
LNM/LCM
5
6
RST
EXPOSED
PAD TO
GND
GND
Table 1. Pin description
N°
1
DS13354 - Rev 1
Pin
VOUT/FB
Description
Output voltage sensing. This pin operates as VOUT or FB accordingly with
selected part number:
•
VOUT is output voltage sensing with selected internal voltage divider.
•
FB is output voltage sensing with external resistor divider.
Input supply of the integrated LDO. Typically connected to the regulated output
voltage or an auxiliary rail to increase the efficiency at light load. Connect to GND
if not used or bypass with a 100 nF ceramic capacitor if supplied by the output
voltage or by an auxiliary rail.
2
VBIAS
3
VCC
4
FSW
Switching frequency programming pin. Connect an external resistor to VCC or
GND.
5
LNM/LCM
Dynamic pin selection between Low Consumption Mode (LCM, active low) and
Low Noise Mode operation (LNM, active high). This pin can also be used for
synchronization with an external clock (clock-in function).
6
RST
Active low open collector output for output monitoring and power-up reset
sequencing. RST is driven in low impedance when the output voltage is out of
regulation and released once the output voltage becomes valid.
7
EN/UVLO
8
VIN
DC input voltage
9
LX
Switching node
10
GND
Ground
--
E.P.
Exposed pad must be connected to GND
Output of the integrated LDO that supplies the embedded analog circuitry.
Connect a ceramic capacitor (470 nF typ.) to filter internal voltage reference.
Active high enable pin, VIN compatible. It can be exploited with an external
resistor divider to adjust the input undervoltage lockout (UVLO).
page 4/43
L7983
Absolute maximum ratings
3
Absolute maximum ratings
Stressing the device above the ratings listed in Table 2 may cause permanent damage to the device. These are
stress ratings only and operation of the device at these or any other conditions above those indicated in the
operating sections of this specification is not implied. Exposure to absolute maximum rating conditions may affect
device reliability.
Table 2. Absolute maximum ratings
Symbol
Min.
Max.
Unit
-0.3
63
V
-0.3
VIN + 0.3 or
max. 3.6
V
-0.3
VIN + 0.3
LX
-0.3
VIN + 0.3
V
VBIAS
-0.3
VIN + 0.3 or
max. 14
V
-0.3
5.5
-0.3
VCC + 0.3
V
0.3
A
VIN
Description
See Table 1
VCC
EN/UVLO
RST
VOUT/FB
LNM/LCM
FSW
IHS, ILS
TJ
3.1
High-side / low-side RMS switch current
Operating temperature range
-40
150
TSTG
Storage temperature range
-65
150
TLEAD
Lead temperature (soldering 10 sec.)
V
V
V
V
°C
260
Thermal characteristics
Table 3. Thermal data
3.2
Symbol
Parameter
Value
Unit
RthJA
Thermal resistance junction to ambient (device soldered on a
standard demonstration board)
50
°C/W
ESD protection
Table 4. ESD performance
Symbol
ESD
DS13354 - Rev 1
Test conditions
Value
Unit
HBM
2
kV
CDM
500
V
page 5/43
L7983
Operating conditions
3.3
Operating conditions
Table 5. Recommended operating conditions
Symbol
VIN
VBIAS
DS13354 - Rev 1
Parameter
Power supply voltage
Value
Min.
Typ.
Max.
Unit
3.5
60
V
0
14
V
page 6/43
L7983
Electrical characteristics
4
Electrical characteristics
TJ = 25 °C, VIN = 24 V, VEN/UVLO = VIN, LNM selected, fSW = 1 MHz unless otherwise specified.
Table 6. Electrical characteristics
Symbol
Parameter
Test Condition
Min.
Typ.
Max.
VIN rising
2.6
2.8
3.0
VIN falling
2.5
2.7
2.9
Unit
Turn on and power section characteristics
VINH
VIN turn-on
VINL
VIN turn-off
Hysteresis
0.1
VWAKEUPH
Wake-up ON threshold
VEN rising
VWAKEUPL
Wake-up OFF threshold
VEN falling
0.2
VENH
Enable ON threshold
VEN rising
1.1
1.2
1.3
VENL
Enable OFF threshold
VEN falling
0.9
1.0
1.1
0.7
Hysteresis
0.42
0.47
0.52
Duty cycle = 100%, closed loop operation (1)
0.35
0.39
0.43
Valley current limit
(1)
0.43
0.52
0.61
ISKIP
Skip current limit
(1)
INEG
Reverse current limit
LNM selected, VFB = 0.9 V (1)
HS RDSON
HS MOS ON resistance
ILX = 0.2 A
1.9
2.5
LS RDSON
LS MOS ON resistance
ILX = 0.2 A
0.85
1.2
IVY
fSW
D
tON MIN
tSS
Peak current limit
Selected switching frequency
- 0.15
450
500
550
RFSW = 0 Ω
900
1000
1100
RFSW = 56 kΩ
1980
2200
2420
0
Minimum HS MOS on-time
100
60
Internal soft-start time
A
0.08
RFSW = 5.6 kΩ
Duty cycle
V
0.2
Duty cycle < 20% (1)
IPK
V
Ω
kHz
%
ns
1.3
2
2.7
VBIAS = GND
2.9
3.3
3.6
VBIAS = 5 V
2.9
3.3
3.6
ms
VCC and VBIAS
VCC
LDO output voltage
SWO
Switchover threshold
VBIAS increasing
Hysteresis
V
3.2
V
0.075
V
Power consumption
ISHTDWN
IQVIN
Shutdown current from VIN
VEN/UVLO = GND
Quiescent current from VIN, LCM
(refer to Section 5.5 VCC and
switchover)
Quiescent current from VIN, LNM
DS13354 - Rev 1
2.3
3.2
VBIAS = 5 V, VOUT = 1.05 * VREF(2)
3
6
VBIAS = GND, VOUT = 1.05 * VREF(2)
35
50
VBIAS = 5 V, VOUT = 1.05 * VREF
170
205
VBIAS = GND, VOUT = 1.05 * VREF
1300
1500
µA
page 7/43
L7983
Electrical characteristics
Symbol
IQVBIAS
Parameter
Quiescent current from VBIAS
Test Condition
Min.
LCM, VBIAS = 5 V, VOUT = 1.05 * VREF(2)
LNM, VBIAS = 5 V, VOUT = 1.05 * VREF
Typ.
Max.
37
50
1200
1400
Unit
µA
Voltage reference and OVP
Voltage feedback, L7983PUR
VREF
Voltage feedback, L7983PU33R
Voltage feedback, L7983PU50R
VOVP
VOVP,HYST
TJ = 25 °C
0.844
0.850
0.856
-40 °C ≤ TJ ≤ 125 °C (3)
0.840
0.850
0.860
TJ = 25 °C
3.267
3.300
3.333
3.250
3.300
3.350
4.950
5.000
5.050
4.925
5.000
5.075
115
120
125
-40 °C ≤ TJ ≤ 125 °C
(3)
TJ = 25 °C
-40 °C ≤ TJ ≤ 125 °C
(3)
Overvoltage trip (VOUT/VREF)
Overvoltage hysteresis
2
V
%
%
Synchronization (clock-in) and LNM/LCM
fCLKIN
Synchronization range
180
2400
kHz
VCLKINH
CLKIN allowed high level
2
5
V
VCLKINL
CLKIN allowed low level
0
1.3
V
VLNM
LNM selection level
2
5
V
VLCM
LCM selection level
0
1.3
V
TLNM/LCM
Minimum allowed delay between
LNM to LCM or LCM to LNM
dynamic selection
14
µs
Reset
VRSTTHR
VRSTHYST
RST release threshold
TJ = 25 °C
90
(VOUT/VREF)
-40 °C ≤ TJ ≤ 125 °C (3)
88
RST hysteresis
TRSTDLY
Delay from VRSTTHR threshold
detection and RST pin release
VRSTLOW
RST open collector output
IRSTLKG
RST leakage current
92
94
96
%
2
2.0
ms
VOUT/VREF = 80%, 4 mA sinking current
0.3
0.4
2 < VIN < VINH, 4 mA sinking current
0.5
0.8
VIN = 60 V, VOUT/VREF = 110%
0.2
V
µA
Thermal shutdown
TSHDWN
THYS
Thermal shutdown threshold
(4)
165
Thermal shutdown hysteresis
(4)
30
°C
1. Parameter tested in static condition during testing phase. Parameter value may change over dynamic
application condition.
2. LCM enables SLEEP mode at light load.
3. Specifications in the -40 to +125 °C temperature range are assured by characterization and statistical
correlation.
4. Not tested in production.
DS13354 - Rev 1
page 8/43
L7983
Functional description
5
Functional description
The L7983 device is a monolithic step-down (“buck”) DC-DC voltage regulator based on a peak current mode,
constant frequency architecture, with integrated control loop compensation network.
The main internal blocks are shown in Figure 2 and can be summarized as follows:
•
Power section, including high-side and low-side power MOSFETs, gate driver and current sensing
•
Control loop blocks, including the trans-conductor (gm), the PWM comparator and the slope generator
•
The control logic for low noise mode (LNM) or low consumption mode (LCM) operation selection and
synchronization to external clock
•
The frequency programming circuitry for device configuration
•
Input voltage monitor and enable circuit with soft-start management and RST output signal for sequencing
programming
•
The low drop-out linear regulator (LDO) and switchover block to improve the power conversion efficiency.
The fault management, including the overcurrent (OCP), the overvoltage (OVP) and overtemperature (OTP)
protection
5.1
Power section
The L7983 integrates both power MOSFETs for synchronous operation; one P-channel (high-side, HS) and one
N-channel (low-side, LS), optimized for fast switching transition and high efficiency over the entire load range. The
power stage is designed to deliver a continuous output current up to 0.3 A.
The HS MOSFET source is connected to the VIN pin, the LS MOSFET source is connected to the GND pin
(power ground). The HS MOSFET drain and LS MOSFET drain are connected together and to the LX pin (see
Figure 2).
The L7983 embodies an anti-shoot-through and adaptive deadtime control to minimize low-side body diode
conduction time and consequently reduce power losses. This feature is implemented by comparing LX with HS
and LS gate driving voltage.
•
Following the HS turn-off, the LS MOSFET is suddenly switched on as soon as the voltage at the LX pin
drops
•
Following the LS turn-off, the HS MOSFET is suddenly switched on as soon as the gate driving voltage of
LS drops
If the current flowing in the inductor is negative (i.e. from VOUT to VIN), the voltage on the LX pin can’t drop after
HS MOS turn-off. A watchdog controller is implemented to allow the LS MOSFET to turn on even in this case,
allowing the negative current of the inductor to flow to ground. This mechanism allows the system to regulate
even if the current is negative (if LNM mode is enabled).
5.2
Control loop and voltage programming
The L7983 is based on a constant frequency peak current mode architecture.
Thanks to integrated compensation network and slope generation, no additional external components are
necessary for loop stabilization.
DS13354 - Rev 1
page 9/43
L7983
Control loop and voltage programming
Figure 4. Control loop block diagram
Vin
HS
Power
Switches
LS
+
+ gcs
Vout
L
Ru
Cu
Reso
Slope
compensation
Current
sense
Ro
Rd
Integrated
compensation
PWM
Comparator
Cp
Co
E/A
FB
Rc
Cc
VREF
Refer to Section 5.7 for further details on power components design.
For the adjustable version (L7983PUR), the output voltage can be programmed through an external resistor
divider, from 0.85 V up to VIN.
The design equation is:
RU
VOUT = 0.85 ∙ 1 +
RD
(1)
For the fixed version (L7983PU33R or L7983PU50R), the output voltage programming is achieved by simply
shorting the VOUT(FB) pin to the output capacitor.
DS13354 - Rev 1
page 10/43
L7983
Control loop and voltage programming
Figure 5. Output voltage programming - adjustable version
RST
VIN
EN/UVLO
LX
VCC
VOUT(FB)
FSW
VBIAS
LNM/LCM
EP
RU
GND
RD
Figure 6. Output voltage programming - fixed version
RST
VIN
EN/UVLO
VCC
VOUT(FB)
FSW
VBIAS
LNM/LCM
DS13354 - Rev 1
LX
EP
GND
page 11/43
L7983
Control loop and voltage programming
5.2.1
LNM/LCM selection and synchronization
Depending on the low-side power MOSFET management, the inductor current can be allowed to reverse or not.
The choice can be performed during device operation by acting on the LNM/LCM pin.
When the low-noise mode (LNM) operation is selected, by forcing high pin LNM/LCM, the inductor current can
reverse. In this way a constant switching frequency is achieved, so limiting the output voltage ripple and providing
a prompt transient response.
Figure 7. LNM selected, no load
If the LNM/LCM pin is forced low, the low-consumption mode (LCM) is activated, with the aim of maximizing the
light load efficiency. When LCM is selected, the high-side MOSFET is turned on as soon as the FB pin is sensed
lower than VREFLCM, i.e. VREF reference voltage increased by 2% typ.:
VREFLCM = VREF ∙ 1,02 typ.
(2)
In LCM mode the HS MOS is turned on until ISKIP current is reached, then it is turned-off. The low-side MOSFET
is then turned on until one of the following conditions occurs:
•
The sensed inductor current drops to zero
•
The switching period (programmed through the FSW pin) has expired and the FB pin is still lower than the
voltage reference. In this case a new switching cycle is performed.
In LCM working mode the regulator switching frequency is load-dependent (i.e. LX pulses can be skipped) with
greater advantage to power conversion efficiency at light load.
The following waveforms are showing the switching activity in LCM working mode and different load.
DS13354 - Rev 1
page 12/43
L7983
Control loop and voltage programming
Figure 8. LCM selected, no load
Figure 9. LCM selected, 10 mA load
DS13354 - Rev 1
page 13/43
L7983
Control loop and voltage programming
Figure 10. LCM selected, 50 mA load
If an external clock is applied on the LNM/LCM pin, the L7983 switching activity is synchronized to the applied
clock and the LNM operation is enabled. The external clock must meet the electrical requirements summarized in
Table 7. In case no external clock is detected on LNM/LCM for TLNM/LCM (14 µs typ.), the free running clock
programmed on pin FSW through RFSW resistor is restored as switching frequency. Refer to
Section 5.3 Switching frequency programming and dithering.
TLNM/LCM is also the typical delay between LNM to LCM and the opposite transition.
Figure 11. LCM to LNM transition, no load
DS13354 - Rev 1
page 14/43
L7983
Switching frequency programming and dithering
5.3
Switching frequency programming and dithering
The L7983 has one programming pin, FSW (pin 4), which is used to set the regulator free running switching
frequency.
The switching frequency programming feature is performed by selecting the proper 1% accuracy resistor, to be
mounted between pin 4 and ground or VCC, as summarized in the following table. The pinstrapping is active only
before the soft-start phase to minimize the IC consumption.
Refer also to Figure 1 for reference schematic.
Table 7. FSW pin programming resistor
Dithering enabled
Dithering disabled
#
RVCC [kΩ]
RGND [kΩ]
Fsw [kHz] (1)
#
RVCC [kΩ]
RGND [kΩ]
Fsw [kHz] (1)
1
0
--
1000
1
--
0
1000
2
1,8
--
200
2
--
1,8
200
3
3,3
--
400
3
--
3,3
400
4
5,6
--
500
4
--
5,6
500
5
10
--
700
5
--
10
700
6
18
--
1500
6
--
18
1500
7
33
--
2000
7
--
33
2000
8
56
--
2200
8
--
56
2200
1. Typical value. Refer to Table 6 for details.
DS13354 - Rev 1
page 15/43
L7983
Switching frequency programming and dithering
The dithering function, enabled by connecting the proper RFSW resistor to VCC, is intended to reduce the DC-DC
electromagnetic emissions, with small impact on output voltage ripple.
Figure 12. RVCC = 0 Ω, dithering enabled, no load
Figure 13. RVCC = 0 Ω, dithering enabled, no load. Detail
The internal dithering circuitry changes the switching frequency in the range of ± 5% of the nominal value. The
device updates the frequency every clock period by fixed steps:
•
Ramps up in 63 steps from minimum to maximum switching frequency
•
Ramps down in 63 steps from maximum to minimum switching frequency
The resulting frequency modulation is almost triangular, with a frequency of:
FSW
FDitℎ =
126
DS13354 - Rev 1
(3)
page 16/43
L7983
Enable and Reset
5.4
Enable and Reset
In order to maximize both the EN threshold accuracy and the current consumption, the device implements two
different enable thresholds:
•
The wake-up threshold, VWAKEUPH = 0.5 V typ.
•
The start-up threshold, VENH = 1.2 V typ.
As soon as the EN pin is detected above VWAKEUPH and VIN voltage is higher than VINH, the regulator turns on
the internal circuitry and waits for the VENH before starting the switching activity. When this occurs, the internal
voltage reference is increased by about 2 ms (typ.) in order to limit the inrush current and perform a smooth
output capacitor charge.
Figure 14. Turn-on example
DS13354 - Rev 1
page 17/43
L7983
Enable and Reset
If the EN pin is forced lower than VENL the switching activity is stopped. The L7983 can further reduce the input
current as soon as EN is forced lower than the VWAKEUPL threshold. When this occurs the input current is reduced
to ISHTDWN = 2.3 µA (typ.).
Figure 15. Turn-off example
A divider from VIN can be used to program the input voltage threshold for controlled power-up, as shown in
Figure 16.
The EN pin is VIN compatible.
Figure 16. Input voltage turn-on threshold programming
RST
VIN
EN/UVLO
LX
VCC
VOUT(FB)
FSW
VBIAS
LNM/LCM
EP
GND
During the soft-start, the L7983 is not allowed to sink current from the output, also if LNM operation is selected.
This feature is intended to guarantee the proper power-up also in case of output voltage pre-bias condition.
Following the L7983 turn-on, if the output voltage (sensed through the VOUT(FB) pin) is detected higher than the
VRSTTHR threshold, the RST pin is left floating.
During the operation, the RST pin is asserted low if the output voltage is found lower than the VRSTTHR VRSTHYST threshold, i.e. a typical 2% hysteresis is implemented.
DS13354 - Rev 1
page 18/43
L7983
VCC and switchover
In case of overvoltage detection (OVP), the RST pin is asserted low. A 2% hysteresis (typ.) is required before
releasing RST.
Figure 17. Output voltage and RST behavior
VOUT
VTHR
VTHR-HYST
RST
Td
A built-in 2 ms typ. delay is always implemented before releasing RST.
5.5
VCC and switchover
The internal LDO (low drop-out) linear regulator is turned on when VIN is higher than the VINH threshold and EN
pin is detected above VWAKEUPH. The output voltage is available on pin VCC, which must be properly bypassed to
GND by 470 nF ceramic capacitor. No external load is expected on VCC pin.
The switchover function is enabled in case VBIAS is detected higher than the SWO threshold (refer to Table 7).
When this occurs, the internal LDO power supply is switched from VIN to VBIAS, so increasing the power
conversion efficiency. This is the typical case when VBIAS is connected to the regulator output.
If the programmed output voltage is lower than the SWO threshold and no auxiliary rail lower than VIN is
available, VBIAS must be connected to GND (refer to Figure 29, Figure 35 and Figure 41 for no load input current
in typical application conditions).
5.6
Fault management
The L7983 fault management is continuously monitoring the inductor current, the output voltage and the device
junction temperature.
Furthermore, thanks to the input UVLO (undervoltage lock-out) circuitry, the switching activity is guaranteed only
with the proper VIN level. All the protections are auto-recovery.
DS13354 - Rev 1
page 19/43
L7983
Fault management
5.6.1
Overcurrent protection (OCP)
In normal operation the HS MOS is turned off when the sensed current is equal to programmed current (refer to
Figure 2). The maximum available current is limited by the internal OCP (overcurrent protection) comparator,
cycle by cycle. The IPK threshold is gradually reduced during the switching period by slope contribution, as shown
in Figure 18.
Figure 18. Peak current limit
IPK
ILX
TON_min
The inductor current is also monitored during LS MOS on-time. This feature, also known as “valley current
limitation”, is effective in case of current runaway due to HS MOS minimum on-time limitation and very low
VOUT / VIN ratio. This protection can avoid the HS MOS turn-on if the inductor current, sensed during LS MOS
on-time, is higher than the IVY threshold (Figure 19).
Figure 19. Valley current limit
IPK
ILX
IVY
TON_min
DS13354 - Rev 1
page 20/43
L7983
Fault management
In LNM mode, the L7983 can sink current from the output. However, to protect the power components, a negative
current limit is implemented. If the sensed current is found lower than the INEG threshold, the low-side MOS is
promptly turned off and the high-side one is turned on until the inductor is discharged. When this occurs, the LS
MOS is allowed to turn on again.
Figure 20. Negative current limit example
DS13354 - Rev 1
page 21/43
L7983
Fault management
5.6.2
Overvoltage protection (OVP)
In case the VOUT(FB) pin is detected above the VOVP threshold, the output overvoltage protection is triggered.
When this occurs, the RST pin is forced low and the L7983 actively discharges the output voltage by sinking
current (refer to Section 5.6.1 Overcurrent protection (OCP)).
Figure 21. Overvoltage protection
VOUT
VOVP
VOVP-HYST
RST
INEG
ILX
As soon as the OVP cause is removed, the proper switching activity is restored and RST output is released, with
the delay and threshold described in Section 5.4 .
5.6.3
Overtemperature protection (OTP)
If the device junction temperature increases above TSHDWN (165 °C typ.) the switching activity is inhibited until a
temperature drop of THYS (30 °C typ.) is detected.
When the switching activity is resumed, a soft-start is implemented. The OTP protection is always active.
DS13354 - Rev 1
page 22/43
L7983
Application design guidelines
5.7
5.7.1
Application design guidelines
Input capacitor selection
The input capacitor must be rated for the maximum input operating voltage and the maximum expected RMS
input current.
Since the step-down converters' input current is a sequence of pulses from 0A to IOUT, the input capacitor must
absorb the equivalent RMS current which can be up to the load current divided by two (worst case, with duty cycle
of 50%). For this reason, the quality of these capacitors must be very high to minimize the power dissipation
generated by the internal ESR, thereby improving system reliability and efficiency.
The RMS input current (flowing through the input capacitor) is roughly estimated by:
ICIN, RMS ≅ IOUT ⋅ D ⋅ 1 − D
(4)
Considering D = VOUT / VIN the theoretical DC-DC conversion ratio, the above equation provides a maximum
value equal to IOUT / 2 when D = 0.5.
The amount of the input voltage ripple can be roughly estimated by Eq. (5).
VIN, PP =
D ⋅ 1 − D ⋅ IOUT
+ RES, IN ⋅ IOUT
CIN ⋅ FSW
(5)
In case of MLCC ceramic input capacitors, the equivalent series resistance (RES,IN) is almost negligible.
The suggested component is a ceramic MLCC capacitor with value 1 µF or higher, with adequate voltage rating
(100 V typ.), placed as close as possible to the VIN and GND pins.
Very fast VIN transitions must be avoided to guarantee the proper operation. Additional input voltage filtering must
be implemented in case of expected VIN transitions faster than 0.1 V/μs.
5.7.2
Inductor selection
In low consumption mode (LCM) the light load operation is implemented with constant current pulses (ISKIP = 80
mA typ., as described in Section 5.2.1 ). In LCM, to achieve a smooth transition from discontinuous to
continuous operation, i.e. from pulse skipping to constant frequency working mode, the inductor should be
selected assuming a target current ripple close to ISKIP.
VOUT
VOUT ⋅ 1 −
VIN
L=
ISKIP ⋅ FSW
(6)
In low noise mode (LNM) the inductance value is typically selected in order to keep the current ripple in the range
20% - 40% of the maximum DC output current. However, in order to prevent the sub-harmonic instability in the
peak current mode control loop, a fixed slope compensation mechanism is implemented in L7983 by adding a
current ramp to the sensed current (see Figure 4). This approach is effective if the inductor current ripple, in the
expected input voltage range, is comparable with the above-mentioned added slope.
In conclusion, Eq. (6) is the reference design equation for inductor selection, independent of selected working
mode (LNM or LCM).
5.7.3
Output capacitor selection
In LNM working mode, the current in the output capacitor has a triangular waveform which generates a voltage
ripple across it. This ripple is due to the capacitive component (charge and discharge of the output capacitor) and
the resistive component (due to the voltage drop across its ESR). The output capacitor must be selected in order
to have a voltage ripple compliant with the application requirements.
The amount of the voltage ripple can be estimated starting from the current ripple obtained by the inductor
selection. Assuming ∆IL is the inductor current ripple, the output voltage ripple is roughly estimated by Eq. (7).
ΔIL
ΔVOUT, PP, LNM ≈ ΔIL ⋅ RES, OUT +
8 ⋅ FSW ⋅ COUT
(7)
The ESR contribution is usually negligible in case of multi-layer ceramic capacitor (MLCC), which is the most
common choice for the L7983 typical solution. Neglecting the ESR contribution, the minimum value of the output
capacitor to guarantee the target output voltage ripple specification in LNM is estimated by:
DS13354 - Rev 1
page 23/43
L7983
Application design guidelines
ΔIL
COUT, LNM ≥
8 ⋅ FSW ⋅ ΔVOUT, PP, LNM
(8)
In case of light load and LCM working mode, the theoretical output voltage ripple is estimated by:
2
L ∙ ISKIP
VIN
ΔVOUT, PP, LCM =
∙
2 ⋅ COUT VOUT ∙ VIN − VOUT
(9)
The output capacitor selection is important also to guarantee the control loop stability.
A minimum capacitance value is necessary to limit the system bandwidth, FBW. A reasonable limit for FBW is the
minimum between FSW/8 and 150 kHz, which provides the following design equation:
0.8 A
COUT, BW ≥
FBW, MAX ⋅ VOUT
(10)
In the peak current mode architecture, working in LNM, there is a close relationship between the programmed
inductor peak current and the error amplifier input error (i.e. the difference between the output voltage sensed on
the FB pin and the internal reference voltage, VREF).
During a load transient, ΔIOUT, the theoretical loop response depends on output capacitor and designed system
bandwidth:
∆ VOUT, LTR ≈
∆ IOUT
2π ∙ FBW ⋅ COUT
(11)
The L7983 implements a fixed integrated compensation network so the output capacitor selection, as highlighted
by Eq. (10), directly impacts the system bandwidth and, at the end, also the expected load transient performance
as described by Eq. (11).
The above listed design suggestions are summarized in Table 8 below which considers the most common voltage
conversions.
Table 8. Reference applications – VIN = 24 V, CIN = 1 µF, CVCC = 470 nF
VOUT [V]
1.5
3.3
5
12
5.7.4
FSW [kHz]
L [µH]
COUT [µF]
RFSW [kΩ]
200
100
22
1.8
500
33
10
5.6
1000
22
4.7
0
200
220
10
1.8
500
68
4.7
5.6
1000
47
2.2
0
1500
22
2.2
18
200
330
6.8
1.8
500
100
3.3
5.6
1000
47
2.2
0
2200
22
2.2
56
200
330
3.3
1.8
500
150
2.2
5.6
1000
68
1
0
2200
33
1
56
RU [kΩ]
RD [kΩ]
43
56
VBIAS = GND
180
62
L7983PU33R to avoid RU and
RD. VBIAS = VOUT
300
62
L7983PU50R to avoid RU and
RD. VBIAS = VOUT
510
39
VBIAS = VOUT
Note
Layout considerations
The PCB layout of the switching DC-DC regulators minimizes the noise injected in high impedance nodes and
interference generated by the high current switching loops.
DS13354 - Rev 1
page 24/43
L7983
Application design guidelines
In a step-down converter, the input loop (including the input capacitor, the DC-DC regulator and ground
connection) is the most critical one due to high value pulsed currents flowing through it. In order to minimize the
EMI, this loop must be as short as possible with an adequate input capacitor placed very close to L7983 VIN and
GND (pin 8 and 10 respectively).
The feedback pin (FB) connection to the external resistor divider is a high impedance node, so the interference
can be minimized by placing the routing of the feedback node as far as possible from the high current paths. To
reduce the pick-up noise, the resistor divider must be placed very close to the device.
Thanks to the exposed pad of the device, the ground plane helps to reduce the junction to ambient thermal
resistance, so a wide ground plane enhances the thermal performance of the converter, allowing the high-power
conversion.
Refer to Section 6 Evaluation board for an example of the PCB layout.
5.7.5
Thermal considerations
The thermal design prevents the thermal shutdown of the device if junction temperature goes above 165 °C (typ.).
The three different sources of losses within the device are:
•
Conduction losses due to the non-negligible RDS(on) of the integrated power switches; these are equal to
2
2
PCOND = RHS, ON ∙ D ∙ IOUT
+ RLS, ON ∙ 1 − D ∙ IOUT
(12)
where D is the duty cycle of the application and RHS,ON and RLS,ON are the maximum resistance overtemperature
of the power switches. Note that the duty cycle is theoretically given by the ratio between VOUT and VIN but
actually it is higher in order to compensate the losses of the regulator, so the conduction losses increase
compared with the ideal case;
•
Switching losses due to power MOSFETs turn-ON and OFF; these can be calculated as:
PSW = VIN ∙ IOUT ∙
TRISE + TFALL
∙ FSW = VIN ∙ IOUT ∙ TTR ∙ FSW
2
(13)
where TRISE and TFALL are the overlap times of the voltage across the high-side power switch (VDS) and the
current flowing into it during turn-ON and turn-OFF phases. TTR is the equivalent switching time. For this device
the typical value for the equivalent switching time is 10 ns.
•
Quiescent current losses, calculated as follows:
PQ = VIN ∙ IQVIN + VBIAS ∙ IQVBIAS
(14)
where IQVIN and IQVBIAS are the L7983 quiescent currents in case of separate bias supply.
If VBIAS = VOUT the L7983 power conversion efficiency ηL7983 must be included in the previous equation:
VBIAS
1
PQ VBIAS = VOUT = VIN ∙ IQVIN, VBIAS = 3.3V +
∙
ηL7983 VIN
(15)
∙ IQVBIAS, VBIAS = 3.3V
If the switch-over feature is not used the total quiescent current losses are represented by:
PQ VBIAS = GND = VIN ∙ IQVIN, VBIAS = GND
(16)
PLOSS = PCOND + PSW + PQ
(17)
T J = TA + PLOSS ∙ RTH, JA
(18)
The L7983 total power losses are given by:
The junction temperature TJ can be estimated with the following equation:
where TA is the ambient temperature. RTH,JA is the equivalent thermal resistance junction to ambient of the
device; it can be calculated as the parallel of many paths of heat conduction from the junctions to the ambient. For
this device the path through the exposed pad is the one conducting the largest amount of heat. The RTH.JA
measured on the demonstration board described in the following section is about 50 °C/W.
DS13354 - Rev 1
page 25/43
L7983
Evaluation board
6
Evaluation board
6.1
Schematic and PCB layout
Figure 22. Evaluation board schematic
TP5
LX
R9
1
1
VOUT
TP4
GND
R10
3
VCC
R3
C3
2
470nF
FSW
4
LNM-LCM
5
VOUT/FB
VBIAS
LX
VCC
VIN
FSW
LNM/LCM
R8
R4
GND
EN/UVLO
EP
RESET
C4
10
L1
9
8
VOUT
VIN
7
C1
1uF
6
TP2
VIN
C2
VIN
VIN
11
100k
TP3
VOUT
R1
1
1
VBIAS
100nF
R2
L7983
1
U1
C6
R5
100k
ENABLE
+
C10
1
LNM-LCM
C5
NM
DS13354 - Rev 1
100k
ENABLE
1
VBIAS
R6
R7
TP8
GND
TP9
RESET
1
TP7
LNM-LCM
TP12
VBIAS
1
VCC
1
TP11
VCC
VIN
1
TP6
ENABLE
1
TP1
GND
RESET
N.M.
page 26/43
L7983
Schematic and PCB layout
Figure 23. PCB layout (Top)
DS13354 - Rev 1
Figure 24. PCB layout (Bottom)
page 27/43
L7983
L7983PUR - Evaluation board
6.2
L7983PUR - Evaluation board
In this section the L7983PUR (adjustable VOUT) evaluation board is described.
The board schematic is shown in Figure 22 and the PCB layout is depicted in Figure 23 and Figure 24.
The main features are:
•
Programmed VOUT = 12 V
•
Max. IOUT = 300 mA
•
Selected FSW = 1 MHz
•
VBIAS = VOUT (switch-over enabled)
Table 9. L7983PUR evaluation board component list (BOM)
Reference
Part
Package
Details
Manufacturer P/N
C1
1 μF
1206
X7R/100V/10%
TDK C3216X7R2A105K
C2
1 μF
1206
X7R/100V/10%
TDK C3216X7R2A105K
0603
X7R/16V/10%
C3
470 nF
C4, C5, C10
N.M.
C6
100 nF
0603
X7R/16V/10%
L1
68 μH
4x4 mm
0.46 A sat/ 950 mΩ
R1
510 kΩ
0603
1% tolerance
R2
39 kΩ
0603
1% tolerance
R3, R7
N.M.
R4, R9, R10
0
0603
R5, R6, R8
100 kΩ
0603
U1
L7983
DFN10_3x3
COILCRAFT LPS4018-683M
1% tolerance
STM L7983PUR
Figure 25. 12 V efficiency (LCM)
Figure 26. 12 V load regulation (LCM)
100
12.1
90
18V
70
60
18V
50
40
24V
30
36V
20
48V
10
60V
0
0.0001
0.001
0.01
Output current [A]
DS13354 - Rev 1
0.1
Output voltage [V]
Efficiency %
80
12.05
24V
36V
12
48V
60V
11.95
11.9
11.85
0
0.05
0.1
0.15
0.2
0.25
0.3
Output current [A]
page 28/43
L7983
L7983PUR - Evaluation board
Figure 27. 12 V efficiency (LNM)
Figure 28. 12 V load regulation (LNM)
100
11.92
90
11.91
Output voltage [V]
70
60
18V
50
24V
40
36V
30
48V
20
60V
10
11.9
11.89
11.88
18V
11.87
24V
11.86
36V
11.85
48V
11.84
60V
11.83
0
0
0.05
0.1
0.15
0.2
0.25
0
0.3
0.05
0.1
Figure 29. 12 V input current - LCM
7
Input current [mA]
Shutdown
40
30
20
10
IIN
6
1030
FSW
5.5
1020
5
4.5
1010
4
1000
3.5
3
990
2.5
2
25
30
35
40
45
Input voltage [V]
0.3
1040
6.5
Quiescent
50
Input current [uA]
0.25
Figure 30. 12 V input current and FSW - LNM
60
DS13354 - Rev 1
0.2
Output current [A]
Output current [A]
0
20
0.15
50
55
60
Switching frequency [kHz]
Efficiency %
80
980
20
25
30
35
40
45
50
55
60
Input voltage [V]
page 29/43
L7983
L7983PU33R - Evaluation board
6.3
L7983PU33R - Evaluation board
In this section the L7983PU33R (VOUT=3.3 V fixed) evaluation board is described.
The board schematic is shown in Figure 22 and the PCB layout is depicted in Figure 23 and Figure 24.
The main features are:
•
Programmed VOUT = 3.3 V (fixed)
•
Max. IOUT = 300 mA
•
Selected FSW = 1 MHz
•
VBIAS = VOUT (switch-over enabled)
Table 10. L7983PU33R evaluation board component list (BOM)
Reference
Part
Package
Details
Manufacturer P/N
C1
1 μF
1206
X7R/100V/10%
TDK C3216X7R2A105K
C2
2.2 μF
0805
X7R/16V/10%
TDK C2012X7R1C225K
0603
X7R/16V/10%
C3
470 nF
C4, C5, C10
N.M.
C6
100 nF
0603
X7R/16V/10%
L1
47 μH
4x4 mm
0.56 A sat/ 650 mΩ
R1, R4, R9
0Ω
0603
R2, R3, R7, R10
N.M.
R5, R6, R8
100 kΩ
0603
U1
L7983
DFN10_3x3
1% tolerance
STM L7983PU33R
Figure 31. 3.3 V fix efficiency (LCM)
Figure 32. 3.3 V fix load regulation (LCM)
3.37
90
3.36
80
Efficiency %
70
60
50
12 V
40
24 V
30
36 V
20
48 V
10
60 V
3.35
12V
3.34
24V
3.33
36V
0.001
0.01
0.1
48V
3.32
60V
3.31
3.3
3.29
Output current [A]
DS13354 - Rev 1
Output voltage [V]
100
0
0.0001
COILCRAFT LPS4018-473M
0
0.05
0.1
0.15
0.2
0.25
0.3
Output current [A]
page 30/43
L7983
L7983PU33R - Evaluation board
Figure 33. 3.3 V fix efficiency (LNM)
Figure 34. 3.3 V fix load regulation (LNM)
100
3.35
90
3.34
Output voltage [V]
70
60
12V
50
40
24V
30
36V
20
48V
10
60V
0
12V
3.33
24V
36V
3.32
48V
3.31
60V
3.3
3.29
0
0.05
0.1
0.15
0.2
0.25
0
0.3
0.05
0.1
0.15
0.2
Figure 35. 3.3 V fix input current, no load (LCM)
Figure 36. 3.3 V fix input current, no load (LNM)
20
4
1200
18
IIN
16
Quiescent
14
Shutdown
3.5
Input current [mA]
Input current [µA]
0.3
Output current [A]
Output current [A]
12
10
8
6
4
2
1000
FSW
3
800
2.5
600
2
400
1.5
200
1
0
0
10
10
15
20
25
30
35
40
Input voltage [V]
DS13354 - Rev 1
0.25
45
50
55
Switching frequency [kHz]
Efficiency %
80
15
20
25
30
35
40
45
50
55
60
60
Input voltage [V]
page 31/43
L7983
L7983PU50R - Evaluation board
6.4
L7983PU50R - Evaluation board
In this section the L7983PU50R (VOUT = 5 V fixed) evaluation board is described.
The board schematic is shown in Figure 22 and the PCB layout is depicted in Figure 23 and Figure 24.
The main features are:
•
Programmed VOUT = 5 V (fixed)
•
Max. IOUT = 300 mA
•
Selected FSW = 1 MHz
•
VBIAS = VOUT (switch-over enabled)
Table 11. L7983PU50R evaluation board component list (BOM)
Reference
Part
Package
Details
Manufacturer P/N
C1
1 μF
1206
X7R/100V/10%
TDK C3216X7R2A105K
C2
2.2 μF
0805
X7R/16V/10%
TDK C2012X7R1C225K
0603
X7R/16V/10%
C3
470 nF
C4, C5, C10
N.M.
C6
100 nF
0603
X7R/16V/10%
L1
47 μH
4x4 mm
0.56 A sat/ 650 mΩ
R1, R4, R9
0Ω
0603
R2, R3, R7, R10
N.M.
R5, R6, R8
100 kΩ
0603
U1
L7983
DFN10_3x3
1% tolerance
STM L7983PU50R
Figure 37. 5 V fix efficiency (LCM)
Figure 38. 5 V fix load regulation (LCM)
100
5.1
90
60
12 V
50
40
24 V
30
36 V
20
48 V
10
60 V
Output voltage [V]
Efficiency %
70
24V
5.06
36V
48V
5.04
60V
5.02
5
4.98
0
0.001
0.01
Output current [A]
DS13354 - Rev 1
12V
5.08
80
0
0.0001
COILCRAFT LPS4018-473M
0.05
0.1
0.15
0.2
0.25
0.3
0.1
Output current [A]
page 32/43
L7983
L7983PU50R - Evaluation board
Figure 40. 5 V fix load regulation (LNM)
100
5.07
90
5.06
80
5.05
70
60
12V
50
24V
40
36V
30
48V
20
60V
Output voltage [V]
12V
24V
5.04
36V
5.03
48V
5.02
60V
5.01
5
4.99
10
4.98
0
0
0.05
0.1
0.15
0.2
0.25
0
0.3
0.05
0.1
0.2
0.25
0.3
Output current [A]
Output current [A]
Figure 41. 5 V fix input current, no load (LCM)
Figure 42. 5 V fix input current, no load (LNM)
35
30
Quiescent
25
Input current [mA]
Input current [µA]
0.15
Shutdown
20
15
10
4
1200
3.5
1000
3
800
2.5
600
2
1.5
IIN
400
FSW
200
5
0
10
1
15
20
25
30
35
40
Input voltage [V]
DS13354 - Rev 1
45
50
55
60
Switching frequency [kHz]
Efficiency %
Figure 39. 5 V fix efficiency (LNM)
0
10
15
20
25
30
35
40
45
50
55
60
Input voltage [V]
page 33/43
L7983
Package information
7
Package information
In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK packages,
depending on their level of environmental compliance. ECOPACK specifications, grade definitions and product
status are available at: www.st.com. ECOPACK is an ST trademark.
DS13354 - Rev 1
page 34/43
L7983
DFN10 (3 x 3 x 0.8 mm) package information
7.1
DFN10 (3 x 3 x 0.8 mm) package information
Figure 43. DFN10 (3 x 3 x 0.8 mm) package outline
BOTTOM VIEW
SIDE VIEW
TOP VIEW
DS13354 - Rev 1
page 35/43
L7983
DFN10 (3 x 3 x 0.8 mm) package information
Table 12. DFN10 (3 x 3 x 0.8 mm) mechanical data
SYMBOL
Dimensions (mm)
Min.
Typ.
Max.
A
0.70
0.75
0.80
A1
0.0
0.02
0.05
A3
b
0.20 Ref.
0.16
D
D2
0.23
0.28
3.00 BSC
0.27
0.42
e
0.50 BSC
E
3.0 BSC
0.52
E2
0.63
0.78
0.88
L
0.30
0.40
0.50
K
0.20
N
10
NE
5
Figure 44. DFN10 (3 x 3 x 0.8 mm) recommended footprint
DS13354 - Rev 1
page 36/43
L7983
Ordering information
8
Ordering information
Table 13. Order codes
DS13354 - Rev 1
Part numbers
Output voltage
L7983PUR
Adjustable
L7983PU33R
Fixed 3.3 V
L7983PU50R
Fixed 5.0 V
Package
Packaging
DFN10
Tape and reel
page 37/43
L7983
Revision history
Table 14. Document revision history
DS13354 - Rev 1
Date
Revision
01-Oct-2020
1
Changes
Initial release.
page 38/43
L7983
Contents
Contents
1
Application schematic and block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
1.1
Application circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
2
Pin settings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
3
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
3.1
Thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
3.2
ESD protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
3.3
Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
4
Electrical characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
5
Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
5.1
Power section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
5.2
Control loop and voltage programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
5.2.1
5.3
Switching frequency programming and dithering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
5.4
Enable and Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
5.5
VCC and switchover . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
5.6
Fault management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
5.7
6
LNM/LCM selection and synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
5.6.1
Overcurrent protection (OCP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
5.6.2
Overvoltage protection (OVP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
5.6.3
Overtemperature protection (OTP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Application design guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
5.7.1
Input capacitor selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
5.7.2
Inductor selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
5.7.3
Output capacitor selection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
5.7.4
Layout considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
5.7.5
Thermal considerations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Evaluation board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
6.1
Schematic and PCB layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
6.2
L7983PUR - Evaluation board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
6.3
L7983PU33R - Evaluation board. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
DS13354 - Rev 1
page 39/43
L7983
Contents
6.4
7
Package information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34
7.1
8
L7983PU50R - Evaluation board. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
DFN10 (3x3) package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38
DS13354 - Rev 1
page 40/43
L7983
List of tables
List of tables
Table 1.
Table 2.
Table 3.
Table 4.
Table 5.
Table 6.
Table 7.
Table 8.
Table 9.
Table 10.
Table 11.
Table 12.
Table 13.
Table 14.
Pin description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . .
Thermal data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
ESD performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Recommended operating conditions. . . . . . . . . . . . . . . . . . . . .
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
FSW pin programming resistor . . . . . . . . . . . . . . . . . . . . . . . .
Reference applications – VIN = 24 V, CIN = 1 µF, CVCC = 470 nF.
L7983PUR evaluation board component list (BOM) . . . . . . . . . .
L7983PU33R evaluation board component list (BOM) . . . . . . . .
L7983PU50R evaluation board component list (BOM) . . . . . . . .
DFN10 (3 x 3 x 0.8 mm) mechanical data . . . . . . . . . . . . . . . . .
Order codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DS13354 - Rev 1
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. 4
. 5
. 5
. 5
. 6
. 7
15
24
28
30
32
36
37
38
page 41/43
L7983
List of figures
List of figures
Figure 1.
Figure 2.
Figure 3.
Figure 4.
Figure 5.
Figure 6.
Figure 7.
Figure 8.
Figure 9.
Figure 10.
Figure 11.
Figure 12.
Figure 13.
Figure 14.
Figure 15.
Figure 16.
Figure 17.
Figure 18.
Figure 19.
Figure 20.
Figure 21.
Figure 22.
Figure 23.
Figure 24.
Figure 25.
Figure 26.
Figure 27.
Figure 28.
Figure 29.
Figure 30.
Figure 31.
Figure 32.
Figure 33.
Figure 34.
Figure 35.
Figure 36.
Figure 37.
Figure 38.
Figure 39.
Figure 40.
Figure 41.
Figure 42.
Figure 43.
Figure 44.
DS13354 - Rev 1
Typical application circuit . . . . . . . . . . . . . . . . .
Block diagram . . . . . . . . . . . . . . . . . . . . . . . .
Pin connection (top view) . . . . . . . . . . . . . . . . .
Control loop block diagram. . . . . . . . . . . . . . . .
Output voltage programming - adjustable version
Output voltage programming - fixed version . . . .
LNM selected, no load . . . . . . . . . . . . . . . . . . .
LCM selected, no load . . . . . . . . . . . . . . . . . . .
LCM selected, 10 mA load . . . . . . . . . . . . . . . .
LCM selected, 50 mA load . . . . . . . . . . . . . . . .
LCM to LNM transition, no load. . . . . . . . . . . . .
RVCC = 0 Ω, dithering enabled, no load. . . . . . .
RVCC = 0 Ω, dithering enabled, no load. Detail. .
Turn-on example. . . . . . . . . . . . . . . . . . . . . . .
Turn-off example. . . . . . . . . . . . . . . . . . . . . . .
Input voltage turn-on threshold programming . . .
Output voltage and RST behavior . . . . . . . . . . .
Peak current limit . . . . . . . . . . . . . . . . . . . . . .
Valley current limit. . . . . . . . . . . . . . . . . . . . . .
Negative current limit example . . . . . . . . . . . . .
Overvoltage protection. . . . . . . . . . . . . . . . . . .
Evaluation board schematic . . . . . . . . . . . . . . .
PCB layout (Top). . . . . . . . . . . . . . . . . . . . . . .
PCB layout (Bottom) . . . . . . . . . . . . . . . . . . . .
12 V efficiency (LCM) . . . . . . . . . . . . . . . . . . .
12 V load regulation (LCM). . . . . . . . . . . . . . . .
12 V efficiency (LNM) . . . . . . . . . . . . . . . . . . .
12 V load regulation (LNM). . . . . . . . . . . . . . . .
12 V input current - LCM . . . . . . . . . . . . . . . . .
12 V input current and FSW - LNM . . . . . . . . . .
3.3 V fix efficiency (LCM) . . . . . . . . . . . . . . . . .
3.3 V fix load regulation (LCM) . . . . . . . . . . . . .
3.3 V fix efficiency (LNM) . . . . . . . . . . . . . . . . .
3.3 V fix load regulation (LNM) . . . . . . . . . . . . .
3.3 V fix input current, no load (LCM). . . . . . . . .
3.3 V fix input current, no load (LNM). . . . . . . . .
5 V fix efficiency (LCM) . . . . . . . . . . . . . . . . . .
5 V fix load regulation (LCM) . . . . . . . . . . . . . .
5 V fix efficiency (LNM) . . . . . . . . . . . . . . . . . .
5 V fix load regulation (LNM) . . . . . . . . . . . . . .
5 V fix input current, no load (LCM) . . . . . . . . . .
5 V fix input current, no load (LNM) . . . . . . . . . .
DFN10 (3 x 3 x 0.8 mm) package outline . . . . . .
DFN10 (3 x 3 x 0.8 mm) recommended footprint .
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L7983
IMPORTANT NOTICE – PLEASE READ CAREFULLY
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