L7987

L7987 61 V 3 A asynchronous step-down switching regulator with adjustable current limitation Datasheet - production data Description HTSSOP16 (RTH = 40 °C/W) Features  3 A DC output current  4.5 V to 61 V operating input voltage  RDS,ON = 250 m typ.  Adjustable fSW (250 kHz - 1.5 MHz)  Low IQ-SHD (11 µA typ. from VIN)  Low IQ (1 mA typ. - VIN 24 V - VOUT 3.3 V)  Output voltage adjustable from 0.8 V to VIN  Synchronization  Adjustable soft-start time  Adjustable current limitation  Low dropout operation (12 µs max.) The L7987 device is a step-down monolithic switching regulator able to deliver up to 3 A DC. The output voltage adjustability ranges from 0.8 V to VIN. The wide input voltage range and the 100% duty cycle capability meet the fail safe specifications for industrial systems. The embedded switchover feature on the VBIAS pin maximizes the efficiency at light load. The adjustable current limitation, designed to select the inductor RMS current accordingly with the nominal output current, and the high switching frequency capability make the size of the application compact. Pulse-by-pulse current sensing with digital frequency foldback implements an effective constant current protection over the different application conditions. The peak current foldback decreases the stress of the power components in heavy short-circuit condition. The PGOOD open collector output can also implement output voltage sequencing during the power-up phase. Multiple devices can be synchronized sharing the SYNCH pin to prevent beating noise in low noise applications like sensors with A/D conversion.  VBIAS improves efficiency at light load  PGOOD open collector output  Output voltage sequencing  Digital frequency foldback in short-circuit  Peak current foldback in short-circuit  Auto-recovery thermal shutdown Applications  Designed for 24 V bus  Fail safe tolerant system  Programmable logic controllers (PLCs) March 2015 This is information on a product in full production. DocID025589 Rev 3 1/37 www.st.com Contents L7987 Contents 1 Application schematic and block diagram . . . . . . . . . . . . . . . . . . . . . . . 4 2 Pin settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 2.1 Pin connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 2.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2.3 Maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2.4 Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2.5 ESD protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 3 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 4 Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 5 4.1 Oscillator and synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 4.2 Soft-start . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 4.3 Error amplifier and light-load management . . . . . . . . . . . . . . . . . . . . . . . 16 4.4 Low VIN operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 4.5 Overcurrent protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 4.6 Overtemperature protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 5.1 Input capacitor selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 5.2 Output capacitor selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 5.3 Inductor selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 5.4 Compensation network . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 5.4.1 Type II compensation network . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 5.4.2 Type III compensation network . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 5.5 Thermal considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 5.6 Layout considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 6 Demonstration board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 7 Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 2/37 DocID025589 Rev 3 L7987 Contents 8 Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 9 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 DocID025589 Rev 3 3/37 37 Application schematic and block diagram 1 L7987 Application schematic and block diagram Figure 1. Application schematic 5 3*22' 8  6$@                          3URJUDPPLQJ UHVLVWRU >N @ $0 The minimum programmed current limit can't be lower than ISKIP = 0.5 A (typical), also in case of foldback detection. 4.6 Overtemperature protection It is recommended that the device never exceeds the maximum allowable junction temperature. This temperature increase is mainly caused by the total power dissipated from the integrated Power MOSFET. To avoid any damage to the device when reaching high temperature, the L7987 device implements a thermal shutdown feature: when the junction temperature reaches 170 °C (typ.) the device turns off the Power MOSFET and shuts down. When the junction temperature drops to 155 °C (typ.), the device restarts with a new softstart sequence. DocID025589 Rev 3 19/37 37 Application information L7987 5 Application information 5.1 Input capacitor selection The input capacitor must be rated for the maximum input operating voltage and the maximum RMS input current. Since the step-down converters input current is a sequence of pulses from 0 A to IOUT, the input capacitor must absorb the equivalent RMS current which can be up to the load current divided by two (worst case, with duty cycle of 50%). For this reason, the quality of these capacitors must be very high to minimize the power dissipation generated by the internal ESR, thereby improving system reliability and efficiency. The RMS input current (flowing through the input capacitor) is roughly estimated by: Equation 7 I CIN RMS  I OUT  D   1 – D  Actual DC/DC conversion duty cycle, D = VOUT/VIN, is influenced by a few parameters: Equation 8 V OUT + V F D MAX = ---------------------------------------------------V IN MIN – V SW MAX V OUT + V F D MIN = ---------------------------------------------------V IN MAX – V SW MIN where VF is the freewheeling diode forward voltage and VSW the voltage drop across the internal high-side MOSFET. Considering the range DMIN to DMAX it is possible to determine the maximum ICIN,RMS flowing through the input capacitor. The input capacitor value must be dimensioned to safely handle the input RMS current and to limit the VIN and VCC ramp-up slew-rate to 0.5 V/s maximum, in order to avoid the device active ESD protections turn-on. Different capacitors can be considered:  Electrolytic capacitors These are the most commonly used due to their low cost and wide range of operative voltage. The only drawback is that, considering ripple current rating requirements, they are physically larger than other capacitors.  Ceramic capacitors If available for the required value and voltage rating, these capacitors usually have a higher RMS current rating for a given physical dimension (due to the very low ESR). The drawback is their high cost.  Tantalum capacitors Small, good quality tantalum capacitors with very low ESR are becoming more available. However, they can occasionally burn if subjected to very high current, for example when they are connected to the power supply. The amount of the input voltage ripple can be roughly overestimated by Equation 9. 20/37 DocID025589 Rev 3 L7987 Application information Equation 9 D   1 – D   I OUT V IN PP = ---------------------------------------------- + R ES IN  I OUT C IN  F SW In case of MLCC ceramic input capacitors, the equivalent series resistance (RES,IN) is negligible. In addition to the above considerations, a ceramic capacitor with an appropriate voltage rating and with a value 1 F or higher should always be placed across VIN and power ground and across VCC and the IC GND pins, as close as possible to the L7987device. This solution is necessary for spike filtering purposes. 5.2 Output capacitor selection The output capacitor is very important in order to satisfy the output voltage ripple requirement. Using a small inductor value is useful to reduce the size of the choke but increases the current ripple. So, to reduce the output voltage ripple, a low ESR capacitor is required. Nevertheless, the ESR of the output capacitor introduces a zero in the open loop gain, which helps to increase the phase margin of the system. If the zero goes to very high frequency, typical drawback in case of ceramic output capacitor application, a type III compensation network must be designed. The current in the output capacitor has a triangular waveform which generates a voltage ripple across it. This ripple is due to the capacitive component (charge and discharge of the output capacitor) and the resistive component (due to the voltage drop across its ESR). So the output capacitor must be selected in order to have a voltage ripple compliant with the application requirements. The amount of the voltage ripple can be estimated starting from the current ripple obtained by the inductor selection. Assuming IL the inductor current ripple, the output voltage ripple is roughly overestimated by Equation 10. Equation 10 I L V OUT PP  I L  R ES OUT + ----------------------------------------8  F SW  C OUT Usually the resistive component of the ripple is much higher than the capacitive one, if the output capacitor adopted is not a multi-layer ceramic capacitor (MLCC) with very low ESR value. The output capacitor is important also for loop stability: it fixes the double LC filter pole and the zero due to its ESR. The output capacitor is also the key component that provides the current to the load during a load transient which exceeds the system bandwidth. So, if the high slew rate load transient is required by the application, the output capacitor must be designed in order to sustain the load transient or absorbs the energy stored in the inductor until the converter reacts. In fact, even if the controller detects immediately the load variation and sets the duty cycle at 100% or 0%, the output current slope is limited by the inductor value, the input and output voltage. DocID025589 Rev 3 21/37 37 Application information L7987 The output voltage has a drop or overshoot that depends on the ESR and capacitive charge/discharge, as roughly estimated in Equation 11: Equation 11 L  I OUT V OUT –LT  I OUT  R ES OUT + I OUT  ---------------------------------------2  C OUT  V L where VL is the voltage applied to the inductor during the load appliance or load release. Equation 12   D MAX   V IN – V OUT  V L =   V OUT  MLCC capacitors have typically low ESR to minimize the ripple but also have low capacitance that does not minimize the voltage deviation during dynamic load variations. Electrolytic capacitors, on the other hand, have a large capacitance which minimizes voltage deviation during load transients whereas they do not show the same ESR values as the MLCCs, resulting then in higher ripple voltages. A mix between an electrolytic and MLCC capacitor can be used to minimize ripple as well as reducing voltage deviation in dynamic mode. The high bandwidth error amplifier of the L7987 and external compensation feature let design a wide range of output filter configurations (including all MLCC solutions) and perform fast transient response. 5.3 Inductor selection The inductance value fixes the current ripple flowing through the output capacitor. So the minimum inductance value, in order to have the expected current ripple, must be selected. The rule to fix the current ripple value is to have a ripple at 20% - 40% of the output current. In the continuous conduction mode (CCM), the required inductance value can be calculated by Equation 13: Equation 13 V OUT V OUT   1 – --------------  V IN  L = -------------------------------------------------I L  F SW In order to guarantee a maximum current ripple in every condition, Equation 13 must be evaluated in case of maximum input voltage, assuming VOUT fixed. Increasing the value of the inductance help to reduce the current ripple but, at the same time, strongly impacts the converter response time to a dynamic load change. The response time is the time required by the inductor to change its current from the initial to the final value. Until the inductor has finished its charging (or discharging) time, the output current is supplied (or recovered) by the output capacitors. Further, if the compensation network is properly designed, during a load variation the device is able to properly change the duty cycle so improving the control loop transient response. When this condition is reached the response time is only limited by the time required to change the inductor current, basically by VIN, VOUT and L. Minimizing the response time, at the end, can help to decrease the output filter total cost and to reduce the application area. 22/37 DocID025589 Rev 3 L7987 5.4 Application information Compensation network The compensation network must assure stability and good dynamic performance. The loop of the L7987 device is based on the voltage mode control. The error amplifier is an operational amplifier with high bandwidth. So, by selecting the compensation network the E/A is considered as ideal, that is, its bandwidth is much larger than the system one. Figure 10. Switching regulator control loop simplified model / 9,1 ,QWHUQDO VZLWFK 5 '& 3RZHU VHFWLRQ 5 (6 52 &2 3:0 =6 96 58 95() ($ &203 =) 5' &RPSHQVDWLRQ QHWZRUN $0 The transfer function of the PWM modulator, from the error amplifier output (COMP pin) to the LX pin results in an almost constant gain, due to the voltage feed-forward which generates a sawtooth with amplitude VS directly proportional to the input voltage: Equation 14 V IN 1 G PWO = --------- = --------- = 30 VS k FF The synchronization of the device with an external clock provided through the SYNCH pin can modify the PWM modulator gain (see Section 4.1 on page 11 to understand how this gain changes and how to keep it constant in spite of the external synchronization). DocID025589 Rev 3 23/37 37 Application information L7987 The transfer function of the power section (i.e. the L-CO filters and the output load) is the ratio of the parallel of CO and RO and the sum of L and the parallel of CO and RO, including L and CO parasitics: Equation 15 1    CO s S RE RO RO  C  RD S  RO    RE CO  1   C 1      C D       RD    L R s S SRE RE CO CO s CO s C S RD RE RO RO O C RO L s  S  RE 2 RO CO L s  s C GL ︵ ︶     given L, RDC, CO, RES and RO the parameters shown in Figure 10. The power section transfer function can be rewritten as follows: Equation 16 s 1 + --------------------------2  f zESR G LC  s  = G LCO  ----------------------------------------------------------------------------2- ; s s 1 + ------------------------------- +  -------------------- 2  f LC 2  Q  f LC RO G LCO = --------------------------  1 R O + R DC Equation 17 1 f zESR = -------------------------------- ; 2  C O R ES 1 1 f LC = ------------------------------------------------------  ----------------------------------------------------R O + R ES R O + R ES 2 LC O -------------------------- 2 LC O ------------------------R O + R DC RO Equation 18 LC O  R O + R DC  R O + R ES LC O  R O   R O + R ES  Q = -----------------------------------------------------------------------------------------------------------  ------------------------------------------------------------------------L + C O   R O R DC + R O R ES + R ES R DC  L + C O R O R ES with the assumption that the inductor parasitic resistance, RDC, is negligible compared to RO. The closed loop gain is then given by: Equation 19 GLOOP(s) = GLC(s) • GPWO(s) • GCOMP(s) As noted in Section 5.2 on page 21, two different kinds of network can compensate the loop, depending on the value of fzESR, lower or higher than the regulator required bandwidth. In Section 5.4.1 and Section 5.4.2 the guidelines to select the type II and type III compensation network are illustrated. 24/37 DocID025589 Rev 3 L7987 5.4.1 Application information Type II compensation network If the equivalent series resistance (RES) of the output capacitor introduces a zero with a frequency lower than the desired bandwidth (that is: 2• RES • CO > 1/BW), this zero helps stabilize the loop. Electrolytic capacitors show non-negligible ESR (> 30 m typically), so with this kind of output capacitor the type II network combined with the zero of the ESR allows to stabilize the loop. Figure 11. Type II compensation network 9 287 95() 58 ($ &203 )% 5) 5' &) &3 =) $0 The type II compensation network transfer function, from VOUT to COMP, is computed in Equation 20. Equation 20 GCOMPII ( s )   Z F (s) 1 1  sC F RF    RU RU s  (C F  C P )  1  sC F  C P RF  s 2  f Z 1  s    1  2   f P1   1 s 2  f P 0 Equation 21 f Z1  1 ; 2  C F  RF f P0  1 ; 2  C F  C P   RU f P1  1 2  C F  C P  RF The following suggestions can be followed for a quite common compensation strategy, assuming that CP