L8150

L8150 Brushless motor predriver Feature ■ ■ ■ ■ ■ ■ ■ ■ Integrated Predriver IC for 3 phase BL motor. Integrated Smooth driving concept with sinusoidal driving waveforms. BCD5 technology 0.6mm. Package: SO28. Three Hall effects, differential input comparators. Integrated Undervoltage lockout (VCC). PWM output duty (voltage) control / Torque optimizer / protection functions PWM carrier 17kHz min / integrated dead time ■ ■ ■ ■ SO28 External HVIC bootstrap capacitor refresh function during 120 degree drive (rectangular drive). This means both upper and lower chopping and low side current recirculation for rectangular drive. Current limiter circuit VCC lower voltage protection / VDC over voltage protection circuit / Hall sensor fail protection FAULT signal output Functions ■ ■ ■ ■ ■ ■ ■ C-MOS level predriver output (high active) Free Run function Dead time (3 values selectable) Sinusoidal waveform PWM logic Detected rotation speed (FG) output terminal PWM duty control by analog input (KVAL control) Forward/backward rotation input terminal (FR) / rotation direction detection output terminal (DM) Thermistor connection terminal (thermal protection) Torque optimizer terminal controlled by analog voltage input V regulator output terminalExternal HVIC bootstrap capacitor pre-charge function ■ Description The L8150 device is a motor predriver intended to drive brushless fan motors with Hall effect sensors. The device, realized in BCD5 0.6mm mixed technology, is characterized by a mostly digital architecture assuring high integration density and high test coverage. The L8150 with few external components forms a complete control circuit, since the smooth driver logic is fully integrated: its peculiar driving solution (smooth driving) allows a very low current ripple and speed control even at low rotation speeds. ■ ■ ■ Order codes Part number E-L8150 E-L8150TR Temp range, °C -20 to 95 -20 to 95 Package SO28 SO28 Packing TUBE Tape & Reel March 2006 Rev 1 1/37 www.st.com 1 Contents L8150 Contents 1 Block diagram & pins description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 1.1 1.2 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Pins description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2 Electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.1 2.2 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Operating condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 3 4 Electrical characteristcs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 General description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 4.1 4.2 4.3 4.4 4.5 4.6 4.7 4.8 4.9 4.10 Drive stage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 I/O . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Hall Sensor Input Terminals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Protection Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 PWM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 System Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 External HVIC Bootstrap Capacitor Initialization . . . . . . . . . . . . . . . . . . . 14 Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Others . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 5 Operating description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 5.1 5.2 5.3 Free-Run (FS) and Reset (SD) functions . . . . . . . . . . . . . . . . . . . . . . . . . 16 Smooth Drive and Control logic description . . . . . . . . . . . . . . . . . . . . . . . 16 Speed Control Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 6 Precharge and hall effects filtering time description . . . . . . . . . . . . . . 24 6.1 6.2 Startup sequence with FS signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Startup sequence with SD signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 7 Application example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 2/37 L8150 Contents 8 9 10 Input Output Pins Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 3/37 List of tables L8150 List of tables Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 11. Table 12. Table 13. Table 14. Table 15. Table 16. Table 17. Table 18. Table 19. Table 20. Table 21. Table 22. Table 23. Pins description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Operating condition. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Supply Voltage Terminal VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Regulator Output Terminal Vreg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Driver Output Terminal UH,VH,WH,UL,VL,WL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Dead Time Select Terminal SD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Hall Sensor Input Terminal HUP,HUN,HVP,HVN,HWP,HWN . . . . . . . . . . . . . . . . . . . . . . . 9 Torque Optimizer Input Terminal T.O. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Over Current Sense Input Terminal R . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Forward Backward Select Terminal FR (note 7). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Thermal Sense Input Terminal TSD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 FG Output Terminal FG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 OSC Terminal OSC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 OP Amp Input Output Terminal INTin+, INTin-, INTout (note 3, note 4). . . . . . . . . . . . . . . 10 Over Voltage Protection Terminal OV . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Low Voltage Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 FAULTS Output Terminal FAULTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Rotation Direction Detection Terminal DM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 KVAL Contro . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Phase Shift . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 7 different values of the signal Pos . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 4/37 L8150 List of figures List of figures Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Figure 10. Figure 11. Figure 12. Figure 13. Figure 14. Figure 15. Figure 16. Figure 17. Figure 18. Figure 19. Figure 20. Figure 21. Figure 22. Figure 23. Figure 24. Figure 25. Figure 26. Figure 27. Figure 28. Figure 29. Figure 30. Figure 31. Figure 32. Figure 33. Figure 34. Figure 35. Figure 36. Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Pins connection (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Kval control by VSP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 External circuit for Vsp control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 16 bit counter operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Smooth drive pattern (forward) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Phase shift vs input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Smooth Drive Pattern (Reverse). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Rectangular drive pattern (forward) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Rectangular Drive Pattern (Reverse) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Filtering circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Filter Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Duty cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Startup sequence forced by FS comparator, assuming the motor is not rotating . . . . . . . . 24 Startup sequence forced by FS comparator, supposing the motor rotating quickly in the direction imposed by the FR signal: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Startup sequence forced by FS comparator, supposing the motor rotating quickly in the direction opposite to that imposed by the FR signal . . . . . . . . . . . . . . . . . . . . . . . . . 26 Startup sequence forced by FS comparator, supposing the motor rotating too quickly . . . 27 Startup sequence forced by SD, supposing the motor stopped . . . . . . . . . . . . . . . . . . . . . 28 Startup sequence forced by SD, supposing the motor rotating quickly in the direction imposed by the FR signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Startup sequence forced by SD, supposing the motor rotating quickly in the direction not imposed by the FR signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Startup sequence forced by SD signal, supposing the motor rotating too quickly . . . . . . . 30 Basic motor control circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 3 phases motor control circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Pins: TSD, OV, SDT, INTinN, INTinP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Pins: TO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Pins: RF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Pins: INTout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Pins: OSC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Pins: FG, DM, FAULT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 ESD clamping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Recirculation diode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Pins: FR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Pins: HWN, HWP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Pins: HUN, HUVP, HVN, HVP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Pins: UH, UL, VH, VL, WH, WL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 SO-28 Mechanical data & package dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 5/37 Block diagram & pins description L8150 1 1.1 Figure 1. Block diagram & pins description Block diagram Block diagram 1.2 Figure 2. Pins description Pins connection (top view) RF WH WL VH VL UH UL SDT HUP UHN HVP HVN HWP HWN 1 2 3 4 5 6 7 8 9 10 11 12 13 14 D01IN1259 28 27 26 25 24 23 22 21 20 19 18 17 16 15 GND VCC VREG TO INTOUT INTINN INTINP FAULT OSC FR TSD OV DM FG 6/37 L8150 Table 1. N° 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 Block diagram & pins description Pins description Pin RF WH WL VH VL UH UL SDT HUP HUN HVP HVN HWP HWN FG DM OV TSD FR OSC FAULT INTinP INTinN INTout TO VREG VCC GND External sense resistance pin W bridge high-side MOS output command W bridge low-side MOS output command V bridge high-side MOS output command V bridge low-side MOS output command U bridge high-side MOS output command U bridge low-side MOS output command Dead time selection input pin Hall sensor differential input Hall sensor differential input Hall sensor differential input Hall sensor differential input Hall sensor differential input Hall sensor differential input Multiplexed Hall effects output Motor direction detected output Over-voltage comparator input External thermal shutdown input Forward/backward rotation input External 20.5kΩ polarization resistance pin Fault signal output Error amplifier reference input pin Error amplifier negative input pin Error amplifier output Torque optimizer analog input Internal 5V regulator output External 15V supply Ground pin Function 7/37 Electrical specifications L8150 2 2.1 Table 2. No. 1 2 3 4 5 6 7 Electrical specifications Absolute maximum ratings Absolute maximum ratings Item VCC supply voltage FG terminal voltage FAULT terminal voltage DM terminal voltage FG, FAULT, DM currents RF voltage Other pin voltage Symbol VCC VFG VFAULT VDM Iod VRF VCC FG FAULT DM FG, FAULT, DM RF SDT,HUP,HUN,HVP HVN,HWP,HWN,OV,TSD FR,INTinN,INTinP,TO SDT,HUP,HUN,HVP HVN,HWP,HWN,OV,TSD FR,INTinN,INTinP,TO Topg Tj Tstg all pin all pin ±2000 V Human body model Terminal Value 20 -0.3/20 -0.3/20 -0.3/20 15 -5 to VREG -0.3 / 6 Unit V V V V mA V V Maximum current Remark 8 Inject current Operating ambient temp. Junction temp. Storage temp. Latch up tolerance ESD tolerance 5 mA 9 10 11 12 13 -20/+95 150 -55/+150 ±200 ±200 °C °C °C mA V Machine model 2.2 Table 3. No. remark 1 Operating condition Operating condition item symbol terminal MIN TYPE MAX unit supply voltage VCC VCC 12.75 15 17.25 V 8/37 L8150 Electrical characteristcs 3 Electrical characteristcs Tamb = 25 °C, VCC =15V, VREG = 5V unless otherwise specified Table 4. No. 1 Supply Voltage Terminal VCC Item Symbol ICC1-1 Terminal VCC Min Typ 10.0 Max 20.0 Unit mA Remark current consumption 1-1 Table 5. NO. 1 2 3 4 Regulator Output Terminal Vreg Item Symbol VREG ∆VREG1 ∆VREG2 ∆VREG3 Terminal VREG VREG VREG VREG Min 4.7 Typ 5.0 40 5 0 Max 5.3 100 30 Unit V mV mV mV/°C VCC1=12.75 to 17.25V IO=5 TO 20mA (note 1) Remark output voltage voltage variation load variation thermal coefficient Table 6. No. 2 4 Driver Output Terminal UH,VH,WH,UL,VL,WL Item Symbol VOH VOL Terminal UH,… UH,… Min 3.70 0.40 Typ Max Unit V V Remark IOH=-2.5mA IOL=2.5mA H level output voltage 2 L level output voltage 2 T Table 7. No. 1 2 3 Dead Time Select Terminal SD Item Symbol VSDTH VSDTM VSDTL Terminal SDT SDT SDT Min 9/10 Vreg 4/10 Vreg 0 Typ Max Vreg 6/10 Vreg 1/10 Vreg Unit V V V Remark dead time =0 usec dead time=1.5usec (Tdeadtime=15xTck) dead time=1.0usec (Tdeadtime=10xTck) H level input voltage M level input voltage L level input voltage Table 8. No. 1 2 3 4 5 6 7 Hall Sensor Input Terminal HUP,HUN,HVP,HVN,HWP,HWN Item Symbol IHB(HA) VICM VI ∆VIN(HA) VSLH(HA) VSHL(HA) Terminal HUP,… HUP,… HUP,… HUP,… HUP,… HUP,… HUP,… Min -2 0.50 0.00 50 20 5 -25 30 15 -15 50 25 -5 3.00 5.00 Typ Max Unit uA V V mVp-p mV mV mV for hall device for hall IC, note 2 Remark input bias current common mode input range input voltage range hall input sensitivity hysteresis width hysteresis L -> H hysteresis H -> L 9/37 Electrical characteristcs Table 9. No. 1 2 3 L8150 Torque Optimizer Input Terminal T.O. Item Symbol Terminal T.O. T.O. T.O. Min Typ 15/25Vreg 0 100 mV Max Unit Remark max analog conversion input min analog conversion input hysteresis Table 10. No. 1 Over Current Sense Input Terminal R Item Symbol VRF Terminal RF Min 0.45 Typ 0.50 Max 0.55 Unit V Remark over current sense level Table 11. No. 1 2 3 4 Forward Backward Select Terminal FR (note 7) Item Symbol VIH (FR) VIL (FR) Ru (FR) VIS (FR) Terminal FR FR FR FR Min 2.0 0.0 -20% 0.2 50.0 0.3 Typ Max VREG 1.0 +20% 0.4 Unit V V kOhm V Remark H level input voltage L level input voltage pull-up resistor to VREG hysteresis width Table 12. No. 1 2 Thermal Sense Input Terminal TSD Item Symbol VIH (TSD) Vhy (TSD) Terminal TSD TSD Min 2.60 0.20 Typ Max 3.00 0.30 Unit V V Remark TSD Threshold Hysteresis Table 13. No. 1 2 FG Output Terminal FG Item Symbol VFGL IFGleak Terminal FG FG Min Typ Max 0.50 10 Unit V uA Remark Io=15mA, open drain Vo=16.5V Output saturation voltage Output leak current Table 14. No. 1 2 OSC Terminal OSC Item Symbol Vosc Fpwm Terminal OSC 18k Min Typ 1.235 20.4k Max Unit V Hz Remark R=20.5kohm (Class E96), Fsys=512*Fpwm 17kHz - 21kHz for Tj=0 to 125 deg Current setting PWM frequency Table 15. No. 1 2 3 4 OP Amp Input Output Terminal INTin+, INTin-, INTout (note 3, note 4) Item Symbol VoH (INT) VoL (INT) IB (INT) Terminal INTout INTout INTin+, -0.2 Min 4.0 Typ Vreg2-0.2 Max Vreg 1.0 0.2 Unit V V uA V Remark Io=1mA Io=1mA H level output voltage L level output voltage input bias current offset 10/37 L8150 Table 16. No. 1 2 Electrical characteristcs Over Voltage Protection Terminal OV Item H level input voltage (operative) Hysteresis width Symbol VIH (OV) VIS (OV) Terminal OV OV Min -6% 0.3 Typ 3.0 Max +6% 0.4 Unit V V Remark Table 17. No. 1 2 3 Low Voltage Protection Item Symbol VIL (LV) VIH (LV) VIS (LV) Terminal LV LV LV Min 10 10.35 0.35 Typ 11 11.50 0.50 Max 12 12.65 0.65 Unit V V V Remark operation voltage release voltage hysteresis width Table 18. No. 1 2 FAULTS Output Terminal FAULTS item symbol VFaultsL IFaultsleak terminal FAULTS FAULTS MIN TYP MAX 0.50 10 unit V uA remark Io=15mA, open drain Vo=17.25V output saturation voltage output leak current Table 19. No. 1 2 Rotation Direction Detection Terminal DM Item Symbol VDML IDMleak Terminal DM DM Min Typ Max 0.50 10 Unit V uA Remark Io=15mA, open drain Vo=17.25V output saturation voltage output leak current Table 20. No. 1 2 3 4 KVAL Contro Item Symbol Terminal INTout INTout INTout INTout Min -3% -3% -7% Typ 4.5Vreg/5 3.7Vreg/5 0.7Vreg/5 70.0 Max +3% +3% +7% Unit V V V mV Remark Note 3 Note 3 Note 3 l FS threshold voltage KVAL Min voltage KVAL max voltage FS Hysteresis Note: 1 2 3 If 20mA is a problem for design because of power dissipation etc., it can be reduced to something like 5mA one input is set at 2.5V by means of a resistor divider. The other input moves from 0V to Vreg. The Hall comparator must operate correctly for all its input range. Opamp need to be designed to meet with Kval control by VSP. External circuit for Vsp control (example) is shown in following Figure 4. The tolerance at Vsp including external resistor (E96) is as follows: mini typ max V1(V) 0.85 1.23 1.6 V2(V) 1.7 2.1 2.5 V3(V) 4.9 5.4 6.1 FR and INTin+ are used to set test mode as follows: Test mode is set by 8 events (clock rising edges) on FR during INTin+>4.5 (Power is kept as high-impedance for INTin+ > 4.5 until 7th event occur) (counter for FR is reset by INTin+ < 4.5) 4 11/37 Electrical characteristcs Figure 3. Kval control by VSP L8150 Figure 4. External circuit for Vsp control INT amp network (suggested) 90.9K Vsp 53.6K 46.4K Vo 22.1K Vreg 31.6K 12/37 L8150 General description 4 4.1 General description Drive stage Voltage-controlled PWM drive. Smooth drive architecture (see following dedicated paragraph). External sense resistor as current limiter. FR terminal: Low = Forward, High or Open = Backward. 4.2 Output U, V, W upper and lower arm power transistors control output (6 outputs) CMOS level (Low: 0V, High: 5V, need output buffer) dead time (0, 1usec, 1.5usec selectable). 4.3 I/O FG output: multiplexed by Hall signal (open drain) (Hall signal after digital filter are used) Forward/backward control FAULT output: monitor signal for protection operation (low active, open drain), active if one of over voltage, lower voltage, thermal protection, Hall sensor fail protection is operative Torque optimizer: controlled by analog input DM output is the monitor signal of Hall input sequence: – – – IF UVW hall signal sequence is as the direction set by FR, DM=H IF UVW hall signal sequence is opposite for the direction set by FR, DM=L Reset or some case in which UVW sequence can not be monitored, DM=H (Hall signals after digital filter are used for this control). 4.4 Hall Sensor Input Terminals There are 2 types of application, Hall device and Hall IC Hall Device application: differential inputs with some bias Hall IC application: one input is fixed around VREG/2 by resistor divider between VREG and GND the other input comes from Hall IC whose span is between 0 and 5V. 13/37 General description L8150 4.5 Protection Functions – – Over-current protection: Low side current recirculation for both smooth and rectangular drive in normal working condition. Over-voltage protection: compare motor supply VDC (140V, 280V) and IC internal reference. All power transistor OFF (all 6 outputs = GND) during over-voltage. Return to normal operation if VDC is recovered from over-voltage condition. An hysteresis is present. Lower voltage protection: all power TR OFF (all 6 outputs = GND), if VCC is lower than a defined voltage threshold (All power Transistors OFF if VCC is between 0 to the defined voltage threshold). Return to normal operation if VCC is recovered from lower voltage condition. An hysteresis is present. Thermal protection: all power transistors OFF by external thermal sense signal. If signal is high (exceeds Vth), the power is OFF (all 6 output = GND). Hall sensor fail protection: all power transistor OFF (all output = GND) if Hall signals are HHH or LLL (Hall signals after digital filter are used). Power ON reset (SD): internal logic reset when power ON or recovery from short time Power OFF. All power transistor OFF (all 6 outputs = GND) during reset. 4.6 PWM carrier frequency: 17-21kHz for Tj = 0 to 125 deg, 18kHz - 20.4kHz for Tj = 25 °C. 4.7 System Clock Internal oscillator: Fsys =1/Tck= 9.8 MHz typical value. One pin for external resistor sets the clock frequency (OSC pin). 4.8 External HVIC Bootstrap Capacitor Initialization Lower arm ALL ON (3 outputs for low side are High, 3 outputs for High side are GND) when VSP becoming ON (free run release), (while this initialization should not be done when VSP becoming OFF) initializing time is 0.333 - 0.5 msec. 4.9 Package 28 pins SO28. It is suitable for both reflow and flow soldering. 4.10 Others Upper and lower arm PWM during rectangular drive; it means both side (upper and lower) chopping, not one side chopping, during rectangular drive). 14/37 L8150 General description A maximum current of 5mA can be injected into OV protection terminal in case VCC = OFF and VDC = ON without damaging the device. Moreover the output does not cause malfunctioning (all power Transistors are OFF). A maximum current of 5mA can be injected into TO terminal from external circuit during VCC OFF without damaging the device. The output does not cause malfunctioning (all power Transistors are OFF). A maximum current of 5mA can be injected into INTinN terminal by VSP abnormal operation without damaging the device. The output does not cause malfunctioning (in particular it is needed to avoid VDC short-circuit by Power Transistor cross-conduction). OSC pin sets the main bias currents for the whole device, including system clock. 15/37 Operating description L8150 5 5.1 Operating description Free-Run (FS) and Reset (SD) functions This device does not have an actual startup signal, the working or standby condition depends on two internally-generated signals: ● ● FS signal; SD (shut down) signal. The first one (FS) is related to the Vsp external signal in the following way. Given the transfer function of the INTAMP network shown below, which is obtained from the suggested INTamp feedback network (see note 6 on Electrical characteristics section): Vo[V] = 5.617V - 0.909 · Vsp[V] we have that when Vsp=1.23V, Vo equals to 4.5V; this signal (amplifier output) is fed to a comparator (FScomp) whose threshold is set at 4.5V (plus some hysteresis). When Vo is greater than 4.5V the device is in the so called "free running" mode, that is all the power outputs are in high impedance; when the threshold is crossed the logic signal FS commutates from High to Low, thus enabling normal device operation. The second one (SD) switches from High to Low, thus enabling normal device operation. When SD is High it acts as a reset signal for the whole logic block and as a stand-by signal for the system oscillator and the speed amplifier. SD = High is generated by a low voltage condition on VREG. 5.2 Smooth Drive and Control logic description Two basic driving techniques are applied according to different conditions: ● ● rectangular driving sinusoidal driving (Smooth Drive) The first one is used during startup phase or when the motor is rotating in the opposite direction with respect to FR signal or T>TMAX, while Smooth Drive is used in normal operation. If a DC brushless motor has BEMF voltage with a sinusoidal-like shape, also the currents in the windings are sinusoidal-like, if the applied voltage is sinusoidal. This means that the torque is almost constant and the ripple is very small, allowing acoustic noise reduction and lower EMI. Smooth Drive basically applies three voltage patterns to the motor windings, each 120 electrical degrees out of phase with respect to the other, taking as reference the period measured during the last electrical period. In order to do this, an internal 16-bit counter (Period counter) is provided which is triggered (current value is stored in a register and the counter is reset) at every rising edge of signal coming from U phase Hall sensor (HallU). This kind of behavior is sketched in the picture (Figure 5), where the synchronization control is represented by HallU rising edge. The clock of the counter is the system clock (Fsys) divided by 36: this results in a maximum value of the electrical period that the device can measure and consequently a minimum speed at which Smooth Drive can work; this maximum period is: TMAX = 36*38656*Tck " 141.5 msec, with Tck = 101.7ns (Typical target value) 16/37 L8150 Figure 5. 16 bit counter operation Operating description Smooth Drive basic functionality is to apply to the motor the voltage waveforms represented in the following pictures (Figure 6) in case of forward rotation (CW). Figure 6. Smooth drive pattern (forward) This kind of profile, which realizes waveforms that are differentially sinusoids, is digitally described by a table of 36 8-bit samples stored in a decoding circuit. The final amplitude of the voltage applied on the outputs is obtained by multiplying each sample by a value generated through an 8-bit ADC, whose input is coming from the speed control. The motor is controlled in voltage mode, so no current control compensation network is required. Actuation is done on motor windings through a fixed frequency PWM conversion. Since Smooth Drive is basically a voltage mode driving there can be the need of shifting the applied profile with respect to the BEMF (here sensed through the Hall sensors). This applied phase shift is called Torque Optimizer. The value (expressed in electrical degrees, hereafter referred to as degrees) can be chosen applying an analog voltage to TO pin, that will be internally converted using a 4-bit A/D. The phase shift range is from 2.5 to 40 degrees with a 2.5-degrees step. As a reference the correspondence between phase shift values and analog voltages is reported in Table 21. 17/37 Operating description Table 21. Phase Shift Analog low threshold [V]