L8202

L8202 MULTIFUNCTION ANALOG ASIC 1 ■ FEATURES Flexible Motor Driver configuration – 4 DC Motor drivers (1.5A Peak Current) or – 2 DC Motor drivers & 1 Dual Full Bridge Stepper Motor driver Figure 1. Package TQFP64 ■ ■ ■ ■ ■ ■ 2 Switching Voltage regulators 6 Open Drain Drivers Serial Input Port 4 Operational amplifiers Low voltage Supervisor Thermal Protection Table 1. Order Codes Part Number L8202 Package TQFP64 (Exposed Pad Down) 2 DESCRIPTION The regulated Voltages are: VCC that can be either 3.3V or +5V and VDD, programmable by a resistor divider network from +3V to +17V It is possible to increase the Output Current capability of the VDD regulator by adding an external discrete Power DMOS. An internal regulator is present in the IC in order to supply several internal blocks. The 5V output voltage is filtered on pin V5 (Typical filter capacitor = 100nF) . L8202 is a multifunction analog ASIC designed for MFP Inkjet printer applications. L8202 integrates 4 full H Bridge drivers, 2 switching Buck type voltage regulators, 4 operational amplifiers, 6 open drain drivers, Reset Generation circuitry and over temperature protection circuitry. Figure 2. Block Diagram PWM gen. L8202 DC motor DC MTR #1 H Drive OP. Amps LM358 like DC MTR #2 H Drive DC motor Phase A H Drive VPH regulator 1 Stepper motor or 2 DC motor Phase B H Drive Vcc regulator 3.3V or 5V SERIAL INTERFACE LED Drivers Sleep mode Vcc switch Reset gen. February 2005 Rev. 2 1/15 L8202 Table 2. Pin Description N° 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 Vs(DC1) DC1B PH_BR_Sense_B PH_B+ Vs(DC4) Vs(Vcc) Vcc_out ODD 6 Vcc_Select Vcc_FB DC4_PWM DC3_PWM DC1_PWM DC2_PWM Analog_GND Vcc_Switch_Out Vcc_In V5 Test VDD_gate VDD_source1 VDD_source2 VDD_drain1 VDD_drain2 Vs(VDD) VDD_FB Pin PH_A+ R_Sense_A PH_AStepper Motor Driver Output A plus Phase A Stepper Motor Driver Current Sense Resistor Stepper Motor Driver Output A minus No Connection This pin is used to measure internal Temperature of ASIC. Gate drive pin for external Power DMOS. N/C when internal FET is used. Source pin #1 for VDD internal FET. Used as differential input when external Power DMOS is used. Source pin #2 for VDD internal FET. Used as differential input when external Power DMOS is used. Drain pin #1 for VDD internal FET. N/C when an external Power DMOS is used. Drain pin #2 for VDD internal FET. N/C when an external Power DMOS is used. VDD regulator Supply voltage. Feedback for VDD Regulator No Connection Stepper Motor Driver Output B minus Phase B Stepper Motor Driver Current Sense Resistor Stepper Motor Driver Output B plus DC4 or Stepper PH_B Supply voltage. Source pin for Vcc Regulator. Internally tied to other Vs. Output pin for Vcc Regulator Open Drain Driver #6 This pin is used to select 5V or 3.3V for Vcc Feedback for Vcc Regulator PWM input for DC motor driver #4 PWM input for DC motor driver #3 PWM input for DC motor driver #1 PWM input for DC motor driver #2 Analog Ground. Vcc switched output pin. Vcc input pin. 5V output pin. No Connection. DC1 Supply voltage. Negative output for DC motor driver #1 Function 2/15 L8202 Table 2. (continued) N° 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 Pin GND(DC1) DC1A ODD 5 ODD 4 ODD 3 ODD 2 ODD1 nCS SCLK SDI nRESET GND(Logic) DC2A GND(DC2) DC2B Vs(DC2) OA_GND OA4OA4+ OA4Out OA3OA3+ OA3Out OA2OA2+ OA2Out OA1OA1+ OA1Out OA_Supply Vs(DC3) DC1 Ground. Positive output for DC motor driver #1 Open Drain Driver #5. Open Drain Driver #4. Open Drain Driver #3. Open Drain Driver #2. Open Drain Driver #1. Chip Select, active Low Serial Clock Serial Data In nRESET pin. Logic Ground Positive output for DC motor driver #2 DC2 Ground. Negative output for DC motor driver #2 DC2 Supply voltage. Ground for Op-Amps Inverting Input for Op-Amp #4 Non-Inverting Input For Op-Amp #4 Output for Op-Amp #4. Inverting Input for Op-Amp #3 Non-Inverting Input for Op-Amp #3 Output for Op-Amp #3 Inverting Input for Op-Amp #2 Non-Inverting Input for Op-Amp #2 Output for Op-Amp #2. Inverting Input for Op-Amp #1 Non-Inverting Input for Op-Amp #1 Output for Op-Amp #1. Op Amp Supply voltage. DC3 or Stepper PH_A Supply voltage. Function 3/15 L8202 Table 3. Absolute Maximum Ratings Symbol Vs VOD Vcc_IN, Vcc_FB VDD Max IVDD VCCOpAmp VDIFF OpAmp Vmaxrst* Tj Tstg Parameter Supply voltage, including ripple Differential Voltage between Power pins, Supply pins and Ground VCC VDD Voltage (@IVDD = 0.0A) VDD Output current Op Amp Supply Voltage Op Amp Differential Voltage Maximum voltage on nRESET Junction Temperature Storage Temperature Value 44 44 7 17 3 7 7 Vcc_in 150 -55 to 150 Unit V V V V A V V V °C °C Table 4. Recommended Operating Conditions (Tj = 25°C, VS= 32V, unless otherwise specified) Symbol Vs IVs Vcc_IN, Vcc_FB Ivcc_in Parameter Supply voltage, including ripple Vs Standby Current Vcc voltage Vcc input current nReset = 0, Ivcc_switch = 0 In the stand by mode(sleep=1) Vcc = 3.3V Vcc = 5.0V Vcc = 3.3V Vcc = 5.0V 3.15 4.8 Test Conditions Min. 24 Typ. 30 3 3.3 5.0 2 Max. 38 15 3.45 5.25 5 Unit V mA V mA Figure 3. Pin Connections OA_SUPPLY OA1OUT OA_GND OA2OUT OA3OUT OA4OUT Vs (DC3) OA1+ 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 PH_A+ R_SENSE_A PH_A1 2 3 4 TEXT VDD_GATE VDD_SOURCE1 VDD_SOURCE2 VDD_DRAIN1 VDD_DRAIN2 Vs (VDD) VDD_FB 5 6 7 8 9 10 11 12 13 PHBR_SENSE PH_B 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 VCC_FB DC4_PWM DC3_PWM DC1_PWM DC2_PWM Vcc_SWITCH_OUT ANALOG_GND Vcc_IN V5 VCC_SELECT. Vs (DC4) Vs_(VCC) VCC_OUT Vs (DC1) ODD6 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 DC2B GND (DC2) DC2A GND (LOGIC) nRESET SDI SCLK nCS ODD1 ODD2 ODD3 ODD4 ODD5 DC1A GND (DC1) DC1B OA1- OA3- Vs (DC2) D04IN1529 OA2+ OA3+ OA4+ OA2- 4/15 OA4- L8202 3 SERIAL INTERFACE L8202 Analog ASIC integrates an SPI interface (write only) for data exchange with the Digital ASIC. The Input word is 19 bits long. 3 Input Pins are dedicated to the Serial Interface: nCS (Chip Select, active Low), SDI (Serial Data In), SCLK (Serial Clock). nCS must be pulled low to activate a Serial Input command. Data present at the SDI pin are shifted into the L8202 on the 19 rising edges of SCLK. The first bit present at the SDI, after the nCS is pulled low, and shifted into the L8202 at the first SCLK rising edge is the LSB. ( SDI will remain at the value presented with the last bit of data ). The low to high transition of nCS, after the 19th Sclk rising edge, loads the data into the internal L8202 ASIC input register. The serial interface is cleared by nRESET. Figure 4. SPI Operation LSB SDI 0 1 2 3 4 5 6 7 17 MSB 18 nCS Tdelay cs_sck Tdelay sck_cs Table 5. SPI Timing specifications (Tamb = 25 °C, VS = 32 V, unless otherwise specified) Symbol Fck Tckhw Tcklw Tdelay_cs-sck Tdelay_sck-cs Tdata_setup Tdata_hold Tdelay_cs Tr_data Tf_data Tr/f_sck Parameter Serial clock frequency SCLK high width SCLK low width Delay nCS falling to first SCLK rising Delay last SCLK rising edge to nCS rising Data valid to SCLK set up time Data hold time Delay required from (n-1)CS to nCS SDI rise time SDI fall time SCLK rise/fall time Min. 6 30 30 10 10 10 10 10 0 0 0 20 20 20 Typ. 8 Max. 12 Unit MHz ns ns ns ns ns ns ns ns ns ns 5/15 L8202 Table 6. SPI Bit Definition BIT # 0 Symbol STAND_BY RESET VALUE 1 DESCRIPTION A Logic “1” inhibits OpAmps and Motors, and puts the L8202 into a lower power state. Chip must power up with Stand By Mode active. VDD regulators operate independently from Stand By Mode. A logic "1" enables the VDD regulator. Chip must power up with the VDD regulators inactive. Controls the direction of current flow through the DC motor windings. A high level causes current to flow from DC1A(source) to DC1B(sink). Controls the direction of current flow through the DC motor windings. A high level causes current to flow from DC2A(source) to DC2B(sink). A high level causes the 5V switch turn on. Chip must power up with the 5V switch closed. Controls Open Drain Driver. A high level causes Open Drain Driver Turn On. Controls Open Drain Driver. A high level causes Open Drain Driver Turn On. Controls Open Drain Driver. A high level causes Open Drain Driver Turn On. Controls Open Drain Driver. A high level causes Open Drain Driver Turn On. Controls Open Drain Driver. A high level causes Open Drain Driver Turn On. Controls Open Drain Driver. A high level causes Open Drain Driver Turn On. Selection of motor type. A high level selects DC motor. A logic 0 level selects Step motor. This input and I0_PH_B select the output of three comparators to set the current level. Current also depends on the sensing resistor and reference voltage. See I1_PH_B This TTL-compatible logic input sets the direction of current flow through the load. A high level causs current to flow from OUT A (source) to OUT B(sink). A Schmitt triger on this input provides good noise immunity and a delay circuit prevents output stage short circuits during switching. This input and I0_PH_A select the output of three comparators to set the current level. Current also depends on the sensing resistor and reference voltage. See I1_PH_A See D_PH_B A high level forces the device to enter in Test Mode. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 VDD_EN MDC1_D MDC2_D VSW_EN ODD 1 ODD 2 ODD 3 ODD 4 ODD 5 ODD 6 SEL_MTR I1_PH_B I0_PH_B D_PH_B 0 0 0 1 0 0 0 0 0 0 0 1 1 0 15 16 17 18 I1_PH_A I0_PH_A D_PH_A Test 1 1 0 0 6/15 L8202 4 DC/DC CONVERTERS SPECIFICATION L8202 contains 2 DC/DC converters. VCC converter is programmable by the Vcc_Select pin for an Output Voltage rated at 3.3V or 5V (1.2A max.). VDD voltage is programmable by a resistor divider network to voltages from +3V to +17V. The switching frequency of the two converters is 200KHz. The Vcc and the VDD regulators are protected by thermal protection circuit with thermal hysteresys (Output Voltages are switched off during thermal protection event). The output voltages, Vcc and VDD are short circuit protected. 4.1 VCC Regulator Table 7. Electrical Characteristcs (Tj = 25 °C, VS = 32 V, unless otherwise specified) Symbol VCC_o Parameter Vcc Regulator Output Voltage. Vcc value selected by Vcc_select pin. Over current Threshold level Blankig time for overcurrent detect Vcc external load current Operating frequency Tamb = 10 to 55°C 10 175 200 Test Conditions Vcc = 3.3V From 10mA to 1.2A Vcc = 5V From 10mA to 1.2A Min. 3.23 4.90 1.6 400 1200 225 Typ. 3.3 5 Max. 3.37 5.20 4.8 Unit V V A ns mA KHz IOC_detect IOC_BK time IVcc_load fck 4.2 VDD Regulator Table 8. Electrical Characteristcs (Tj = 25 °C, VS = 32 V, unless otherwise specified) Symbol VDD_O Vref IVDD_load IOC_det_SU IOC_det_SC VSen_VDD Parameter VDD Regulator Output Voltage range Internal reference voltage for error amp Vcc external load current Over current detect level Over current detect level Current sense voltage During start up During short circuit Using external Power DMOS, this is a voltage of Ext. resistor between Vs and VDD_source Test Conditions 24V≤ Vs ≤ 38V Min. 3 -2% 0.01 2.0 4.0 -20% 3.2 5.5 250 +20% 1.24 Typ. Max. 17 +2% 3.0 Unit V V A A A mV IOC_BK time VGS_C TFull_LOAD IST_UP fck Blankig time for overcurrent detect Gate to source clamp voltage Transient time after which max load can be applied to VDD regulator Maximum load current appliable during start up. Operating Frequency Tamb = 10 to 55°C 175 Vs high, ASIC receives command to turn on VDD Reg Vs-15 75 300 Vs-10 ns V ms 1.2 A KHz 200 225 7/15 L8202 5 DC MOTOR DRIVERS OPERATIONS L8202 provides PWM bi-directional drive for two DC motors. The PWM modulation is provided by the MDx_PWM input, and the current direction into the motor by the MDCx_D bit in the serial input port. The driver is protected versus overloads on the output lines to a max. current of 2 Amps peak. The current protection circuit is implemented only on the High Side Drivers, so current protection is provided to motor currents only, but not to shorts between Motor Outputs to GND or Vs. A blanking period following a current turn-on event is included to prevent false current protection. The H Bridges are protected versus cross-conduction. Thermal protection with hysteresys is provided to the Motor Drivers. During thermal protection event the Bridge Outputs are forced into a high impedance status. If nReset is low the motor drive outputs are forced in high impedance Table 9. Absolute Maximum Ratings (Tj = 25°C, VS = 32V, unless otherwise specified) Symbol IDC_O Parameter Pulsed Output Current DC Motor Overcurrent Threshold Test Conditions Min. 2 Typ. Max. 1.5 Unit A A Table 10. Electrical Characteristcs (Tj = 25 °C, VS = 32 V, unless otherwise specified) Symbol RDS(ON) Parameter ON Resistance Test Conditions ILOAD = -0.75A (from output to GND) or ILOAD = +0.75A (from Vs to output) @Tamb =25° 10 500 1 99 Min. Typ. 0.31 0.32 30 KHz ns % Max. Unit W fPWM Ton,Toff min. DCPWM PWM frequency Minimum Ton and Toff time PWM Duty Cycle range Table 11. Truth Table Internal Thermal Bit MDCx_D L L L H H H X Inputs DCx_PWM L H L H X DCxA H L H H Outputs DCxB H H H L All transistors turned off All transistors turned off 8/15 L8202 6 STEPPER MOTOR DRIVER OPERATIONS Two H Bridges are provided to implement current control through the two widings of a Bipolar Stepper Motor. The phase and current level information are programmed over the serial input port (see Serial Interface Bits definition section). Four current levels (0%,33%,66%,100%) are programmable through the status of IN0 and IN1 bits in the Input Serial Port. This drive enters the fast current decay mode when both the I0_PH_X and I1_PH_X inputs set to the high logic level (current is recirculated from GND to Vs supply). A blanking period following a current turn-on event is included to prevent false current protection. The H Bridges are protected versus cross-conduction. Thermal protection with hysteresys is provided to the Motor Drivers. During thermal protection event the Bridge Outputs are forced into a high impedance status. Table 12. Absolute Maximum Ratings (Tj = 25°C, VS = 32V, unless otherwise specified) Symbol ISTEP_O Parameter Pulsed Output Current Test Conditions Min. Typ. Max. 1.5 Unit A Table 13. Electrical Characteristcs (Tj = 25°C, VS = 32V, unless otherwise specified) Symbol RDS(ON) Parameter ON Resistance Test Conditions ILOAD = -0.6 A (from output to GND) or ILOAD = +0.6 A (from Vs to output) @Tamb = 25°C I0_PH_x = 0 I1_PH_x = 0 I0_PH_x = 1 I1_PH_x = 0 I0_PH_x = 0 I1_PH_x = 1 VoOFF = 5V I0_PH_x = 1 I1_PH_x = 1 20 140 20 Min. Typ. 0.55 0.4 500 333 167 0.5 mV mV mV mA Max. Unit W VComp_HT VComp_MT VComp_LT ILEAK_VOFF Comparator High Threshold Voltage Comparator Medium Threshold Voltage Comparator Low Threshold Voltage VoOFF Output Leakage Current for Stepper Motor Driver Outputs Off time Thermal shutdown Stepper Motor driver thermal enable junction temperature hysterisys Toff Tj Tj(enable_ hysterisys) 30 40 µs °C °C Table 14. Truth Table I0_PH_x L H L H I1_PH_x L L H H ISTEP_O_PH_x 100% 66 % 33 % 0% Notes: 1. The 100% current is fixed by the sense resistor, and the Maximum Threshold of the Voltage Comparator 9/15 L8202 7 OPERATIONAL AMPLIFLIERS L8202 contains four general purpose Op-Amps,with their own Supply rail and Gnd rail. OpAmps are inhibited when L8202 is in sleep mode Table 15. Absolute Maximum Ratings (Tj = 25°C, VS = 32V, unless otherwise specified) Symbol Vcc Vid Parameter Supply Voltage Differential Input Voltage Test Conditions Min. 3.2 Typ. Max. 5.2 5.2 Unit V V Table 16. Electrical Characteristcs (Tj = 25°C, VS = 32V, unless otherwise specified) Symbol Vio Avd Vicm Parameter Input Offset Voltage Large Signal Voltage Gain Input Common Mode Voltage Range Common Mode Rejection Ratio Output Current Source Full range 0 Test Conditions Vinp = Vcc-1.5 Min. -9 130 Vcc1.5 Typ. Max. 9 Unit mV V/mV V CMR DC 70 dB Isource Vcc = 5/3.3V Vo = Vcc-2V Vcc = 5/3.3V, Vo = 2V Sourcing 2mA, Vcc = 5.2V, full range Sinking 2mA, Vcc=5.2V, full range Full Range Cload = 100pF 10 20 mA Isink VOH Output Sink Current High Level Output Voltage 10 Vcc0.5 20 mA V VOL Low Level Output Voltage 0.5 V V/µs SR Slew Rate 0.3 GBP Gain Bandwidth Product * Guaranted by design 8 OPEN DRAIN DRIVERS L8202 contains 6 open Drain Drivers. These drivers are controlled by the Serial Interface by the bit ODD1/ 6, each driver is able to sink 30mA from either 3.3V or 5v Supply. Table 17. Electrical Characteristics (Tj = 25°C, VS = 32V, unless otherwise specified) Symbol IODD_H VODD_L Parameter High State Output Current Low State Output Voltage Test Conditions ODDx = 0, Vcc = 5.0V or 3.3V ODDx = 1, Vcc = 5.0V or 3.3V, Iload = 30mA Min. Typ. Max. 1 300 Unit µA mV 10/15 L8202 9 VOLTAGE SUPERVISOR nRESET is an Output/Input signal (active low), that is used both to provide the information about the status of Vcc and Vs supplies, both to provide a Reset signal to the internal logic when driven "low" from an external source for a period > 30µs. When nRESET is asserted, Motor Drivers and VDD regulator are forced in the inactive state and the Serial Input Port is loaded with the "Reset Value". To avoid false assertion due to glitches, nRESET is released to the "high" state with a delay of 100ms. Delay period is calculated from the moment Vcc is passing the Vcc threshold. At power down no delay is present, and nRESET is asserted low by Vcc or Vs falling low respect to their thresholds Figure 5. Vs A V TH_VCC Vcc nRESET Td Tdeglitch Td Note A. L8202 ignores very brief transients. This should be less than Tdeglitch Table 18. Electrical Characteristics (Tj = 25°C, VS = 32V, unless otherwise specified) Symbol Vout_high Vout_low Rp_up VTH_VCC Parameter High-level output voltage at nRESET Low-level output voltage at nRESET Internal pull-up resistance between Vcc_in and nRESET Threshold voltage at Vcc & Vcc_in Test Conditions Ioh = -0.1 mA Min. Vcc0.5V Typ. Max. Unit V V KΩ V Vcc< VTH_VCC Vs=38V 2 Vcc = 3.3V Vcc_in = 3.3V Vcc = 5.0V Vcc_in = 3.3V Vcc > VTH_VCC Vs decreasing Vcc > VTH_VCC Vs increasing ( VTH_Vs+ ) -( VTH_Vs-) 2.87 2.82 4.35 2.87 18.0 19.25 1.2 3 0.2 5 3.07 3.10 4.65 3.10 20.0 21.25 VTH_VsVTH_Vs+ VHYST_Vs Low threshold voltage at Vs High threshold voltage at Vs Hysteresis Voltage V V V Table 19. Switching Characteristics (Tj = 25 °C, VS = 32V, unless otherwise specified) Symbol Td Tdeglitch Trise Tfall Parameter nRESET delay Vcc out of tolerance persistence time Rise Time at nRESET Fall Time at nRESET Test Conditions Vcc >= VTH_VCC nRESET deasserted Vcc < VTH_VCC 10 to 90%, 50pF Load 90 to 10%, 50pF Load Min. 70 10 Typ. 100 20 Max. 130 30 750 50 Unit ms µs ns ns 11/15 L8202 10 APPLICATION CIRCUIT Figure 6. V_bulk U1 C1 + C2 Vcc 63 62 61 60 59 58 57 56 55 54 53 52 51 50 OpAmp_Supply OA1Out OA1+ OA1OA2Out OA2+ OA2OA3Out OA3+ OA3OA4Out OA4+ OA4OpAmp_GND L8202 DC MTR #1 H Drive OP. Amps DC MTR #2 H Drive L1 VPH 150uH 3A rms R1 C3 V_bulk(DC1) DC1_PWM DC1A DC1B GND(DC1) V_bulk(DC2) DC2_PWM DC2A DC2B GND(DC2) V_bulk(DC3) DC3_PWM PH_A+ PH_AR_Sense_A V_bulk(DC4) DC4_PWM PH_B+ PH_BR_sense_B LED1 LED2 LED3 LED4 LED5 LED6 32 25 35 33 34 49 26 46 48 47 64 24 1 3 2 17 23 16 14 15 40 39 38 37 36 20 V_bulk PWM1 DC motor V_bulk PWM2 DC motor 1 V_bulk + R2 C5 2 C4 2200uF D1 V_bulk 11 7 8 6 9 10 12 18 19 21 22 42 43 41 V_bulk(VPH) VPH_source1 VPH_source2 VPH_gate VPH_drain1 VPH_drain2 VPH_FB Vbulk(Vcc) Vcc_drain Vcc_select Vcc_FB SCLK SDATA nCS Phase A H Drive VPH regulator 3A DC Load Phase B H Drive Vcc regulator 3.3V or 5V Stepper motor V_bulk V_bulk Vcc L4 Vcc 220uH 1.2A rms, 4.8A sat 1 + C7 2 C6 1000uF D2 SCLK SDATA nCS R3 0.62 ohm R4 0.62 ohm SERIAL INTERFACE LED Drivers Reset Vcc_Switch_Out Analog_GND GND(logic) nRESET PAD Vcc_In Test 5 45 27 65 44 29 28 From microcontroller 1 2 3 4 5 SCLK SDATA nCS PWM1 PWM1 PWM2 R5 1K 30 C8 100nF Figure 7. V_bulk U1 C1 + C2 Vcc 63 62 61 60 59 58 57 56 55 54 53 52 51 50 OpAmp_Supply OA1Out OA1+ OA1OA2Out OA2+ OA2OA3Out OA3+ OA3OA4Out OA4+ OA4OpAmp_GND V_bulk(DC1) DC1_PWM DC1A DC1B GND(DC1) V_bulk(DC2) DC2_PWM DC2A DC2B GND(DC2) V_bulk(DC3) DC3_PWM PH_A+ PH_AR_Sense_A V_bulk(DC4) DC4_PWM PH_B+ PH_BR_sense_B LED1 LED2 LED3 LED4 LED5 LED6 32 25 35 33 34 49 26 46 48 47 64 24 1 3 2 17 23 16 14 15 40 39 38 37 36 20 V_bulk PWM1 DC motor L8202 DC MTR #1 H Drive OP. Amps DC MTR #2 H Drive L1 VPH R1 C3 V5 V_bulk PWM2 DC motor R2 1 C5 R3 + 2 V_bulk PWM3 DC motor V_bulk PWM4 C4 D1 V_bulk 11 7 8 6 9 10 12 18 19 21 22 42 43 41 V_bulk(VPH) VPH_source1 VPH_source2 VPH_gate VPH_drain1 VPH_drain2 VPH_FB Vbulk(Vcc) Vcc_drain Vcc_select Vcc_FB SCLK SDATA nCS Phase A H Drive VPH regulator 3A DC Load Phase B H Drive Vcc regulator 3.3V or 5V V_bulk Vcc L2 Vcc 220uH 1.2A rms, 4.8A sat 1 + 2 C6 1000uF D2 SCLK SDATA nCS DC motor SERIAL INTERFACE LED Drivers C7 Reset Vcc_Switch_Out Analog_GND GND(logic) nRESET PAD Vcc_In Test 5 45 27 65 44 29 28 From microcontroller 1 2 3 4 5 6 7 SCLK SDATA nCS PWM1 PWM2 PWM3 PWM4 R4 1K 30 C8 100nF 12/15 V5 L8202 Figure 8. TQFP64 Mechanical Data & Package Dimensions mm DIM. MIN. A A1 A2 b c D D1 D2 D3 E E1 E2 E3 e L L1 k ccc 0˚ 0.45 11.80 9.80 2.00 7.50 0.50 0.60 1.00 3.5˚ 7˚ 0.080 0˚ 0.75 0.05 0.95 0.17 0.09 11.80 9.80 2.00 7.50 12.00 10.00 12.20 10.20 0.464 0.386 0.787 0.295 0.0197 0.0177 0.0236 0.0295 0.0393 3.5˚ 7˚ 0.0031 12.00 10.00 1.00 0.22 TYP. MAX. 1.20 0.15 1.05 0.27 0.20 12.20 10.20 0.002 MIN. TYP. MAX. 0.0472 0.006 inch OUTLINE AND MECHANICAL DATA 0.0374 0.0393 0.0413 0.0066 0.0086 0.0086 0.0035 0.464 0.386 0.787 0.295 0.472 0.394 0.480 0.401 0.472 0.394 0.0078 0.480 0.401 TQFP64 (10x10x1.0mm) Exposed Pad Down 7278840 B 13/15 L8202 Table 20. Revision History Date January 2005 February 2005 Revision 1 2 First Issue Changed the maturity from Preliminary Data to Final Datasheet. Description of Changes 14/15 L8202 Information furnished is believed to be accurate and reliable. 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