L9222

L9222 QUAD INVERTING TRANSISTOR SWITCH 1 ■ FEATURES ■ ■ OUTPUT VOLTAGE TO 50V OUTPUT CURRENT TO 1.2A VERY LOW SATURATION VOLTAGE TTL COMPATIBLE INPUTS INTEGRAL SUPPRESSION DIODE Figure 1. Packages ) s ( t c u d o s) r ( P t c e u t e l od o s Pr b O ete l ) o s ( s t b c u -O d o s) r P ( t e uc t e l od o s Pr b O te e l o s b ■ ■ Powerdip (12+2+2) Table 1. Order Codes Part Number 2 DESCRIPTION The L9222 monolithic quad transistor switch is designed for high current, high voltage switching applications. Each of the four switches is controlled by a logic input and all four are controlled by a common enable input. All inputs are TTL-compatible for direct connection to logic circuits. Each switch consists of an open-collector transistor plus a clamp diode for applications with inductive loads. SO20L L9222 L9222 D Package (PDIP12+2+2) (SO20L) The emitters of the four switches are connected together to GND. The switches of the same device may be paralled. The device is intended to drive coils such as relays, solenoids, unipolar stepper motors, LED etc. Figure 2. BLOCK DIAGRAM O May 2004 REV. 3 1/7 L9222 Table 2. ABSOLUTE MAXIMUM RATINGS Symbol Parameter VOUT Output Voltage VCC Logic Supply Voltage Vi Tj, TST Input Voltage Value Unit – 0.7 to 50 V 7 V – 0.7 to VCC + 0.3 V – 55 to 150 °C Junction and Storage Temperature Range ) s ( t c u d o s) r ( P t c e u t e l od o s Pr b O ete l ) o s ( s t b c u -O d o s) r P ( t e uc t e l od o s Pr b O te e l o s b Figure 3. PIN CONNECTION (Top view) DIP16 SO20L Table 3. TRUTH TABLE Enable Input Power Out H L ON H H OFF L X OFF For each input : H= High level L= Low level X = Don’t care O Table 4. THERMAL DATA Symbol Parameter Value Unit Rth j-amb Thermal Resistance Junction to ambient Max 90 °C/W Rth-J-case Thermal Resistance Junction to case Max 14 °C/W 2/7 L9222 Table 5. ELECTRICAL CHARACTERISTICS VCC = 5Vdc ± 5% VEN = 5V – 40 ≤ Tj ≤ 125°C unless otherwise specified Symbol VCE(sus) ICEX Parameter Test Condition Min. Output Sustaining Voltage VIN = 2V VEN= 2V, IOUT = 100mA 46 Output Leakage Current VCE = 50V VIN = 2V, VEN = 0.8V CE(sat) Collector Emitter Saturation V Typ. Max. Unit 1 mA 0.3 0.5 0.8 V V V V VIN ≥ 0.8V IOUT = 0.1A IOUT = 0.3A IOUT = 0.6A; – 40 + 105 °C VIL Input Low Voltage IIL Input Low Current VIH Input High Voltage IIH Input High Current VIN ≥ 2.0V IS Logic Supply Current All Outputs ON IOUT = 06A 50 All Outputs OFF 10 IR Clamp Diode Leakage Current VR = 50V Diode Reverse Voltage VF Clamp Diode Forward Voltage IF = 0.6A 1.8 V IF = 1.2A 2.0 V 0.8 VIN = 0.4V V – 15 µA 2.0 V – 15 µA ) s ( t c u d o s) r ( P t c e u t e l od o s Pr b O ete l ) o s ( s t b c u -O d o s) r P ( t e uc t e l od o s Pr b O te e l o s b mA 20 mA 100 µA IOUT Output Current VIN = 0.4V, R = 10Ω , VS = 13V TPHL Propagation Delay Time (high to low transition) Tj = 25°C IL = 600mA 20 µs TPHL Propagation Delay Time (low to high transition) IL = 600mA Tj = 25°C 20 µs VENL Low Enable Voltage 0.8 V IENL Low Enable Current VENH High Enable Voltage IENH High Enable Voltage VEN = 0.4V VEN ≥ 2.0V 0.9 90 1.2 A – 15 µA 2.0 V – 15 15 µA O 3/7 L9222 Figure 4. Powerdip (12+2+2 0Mechanical Data & Package Dimensions mm DIM. MIN. a1 0.51 B 0.85 b b1 TYP. inch MAX. MIN. TYP. MAX. OUTLINE AND MECHANICAL DATA 0.020 1.40 0.033 0.50 0.38 0.055 0.020 0.50 0.015 0.020 ) s ( t c u d o s) r ( P t c e u t e l od o r sPowerdip P b 16 e O t e l ) o s ( t bs c u -O d o s) r P ( t e uc t e l od o s Pr b O te e l o s b D 8.80 0.346 e 2.54 0.100 e3 17.78 0.700 F 7.10 0.280 I 5.10 0.201 Z 4/7 0.787 E L O 20.0 3.30 0.130 1.27 0.050 L9222 Figure 5. SO20L Mechanical Data & Package Dimensions mm inch DIM. MIN. TYP. MAX. MIN. TYP. MAX. A 2.35 2.65 0.093 0.104 A1 0.10 0.30 0.004 0.012 B 0.33 0.51 0.013 0.200 C 0.23 0.32 0.009 0.013 OUTLINE AND MECHANICAL DATA ) s ( t c u d o s) r ( P t c e u t e l od o r s SO20 P b O ete l ) o s ( s t b c u -O d o s) r P ( t e uc t e l od o s Pr b O te e l o s b D (1) 12.60 13.00 0.496 0.512 E 7.40 7.60 0.291 0.299 e 1.27 0.050 H 10.0 10.65 0.394 0.419 h 0.25 0.75 0.010 0.030 L 0.40 1.27 0.016 0.050 k ddd 0˚ (min.), 8˚ (max.) 0.10 0.004 (1) “D” dimension does not include mold flash, protusions or gate burrs. Mold flash, protusions or gate burrs shall not exceed 0.15mm per side. O 0016022 D 5/7 L9222 Table 6. Revision History Date Revision Description of Changes March 2004 2 Second Issue May 2004 3 Stylesheet update. No content change ) s ( t c u d o s) r ( P t c e u t e l od o s Pr b O ete l ) o s ( s t b c u -O d o s) r P ( t e uc t e l od o s Pr b O te e l o s b O 6/7 L9222 ) s ( t c u d o s) r ( P t c e u t e l od o s Pr b O ete l ) o s ( s t b c u -O d o s) r P ( t e uc t e l od o s Pr b O te e l o s b Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. 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