L9301

L9301 Automotive octal low side driver or quad low side plus quad high side driver Datasheet - production data Description The L9301 is a SPI (Serial Peripheral Interface) controlled octal channel with 4 high/low and 4 low side drivers with the possibility to use four integrated PowerMOS as recirculation diodes for PWM load driving. L9301 contains 12 PowerMOS: 4 configurable High/Low side drivers with Ronmax = 0.6 Ω (DRN1-4, SRC1-4), 4 low side drivers with Ronmax = 0.6 Ω (OUT1-4) and 4 low side drivers with Ronmax = 0.3 Ω (OUT5-8). GAPGPS00337 PowerSSO36 The power DRN/SRC1-4 and OUT1-4 can be connected in parallel outside the device in order to get 4 low-side drivers with Ronmax = 0.3 Ω: DRN1//DRN2, DRN3//DRN4, OUT1//OUT2, OUT3//OUT4. Features  AEC-Q100 qualified  Eight integrated PowerMOS configurable as: – 8 low side ON-OFF with RON(max) = 0.3 Ω @ Tj = 175 °C – High/low side PWM with RON(max) = 0.6 Ω @ Tj = 175 °C and 4 Low side with RON(max) = 0.3 Ω @ Tj = 175 °C In this way there is a total of 8 LS channels for ON-OFF mode with Ronmax = 0.3 Ω.  Operating battery supply voltage 5 V to 18 V There is also the possibility to connect the OUT14 and OUT5-8 in order to drive in PWM mode a load connected to VB or GND without the necessity of a freewheeling diode. In this case the Ronmax = 0.6 Ω.  Operating Vdd supply voltage 4.75 V to 5.25 V  Logic inputs TTL/CMOS-compatible The above configuration can be driven by parallel input or SPI command.  Output voltage clamping 37 V typ. in low-side configuration Through the SPI it is possible to configure the device parameters like configuration, Slew-rate, Overcurrent threshold, to send the drivers commands and to read back the diagnosis results.  SPI interface for outputs control and for diagnosis data communication  Additional PWM inputs for 8 outputs  Over temperature protection .  Open load, short to GND, short to VB  Overcurrent diagnostics in latched or unlatched mode for each channel Table 1. Device summary Order code Package Packing L9301-TR PowerSSO36 (Exp. pad opt.B) Tape & Reel  Controlled SR for improved EMC behavior December 2020 This is information on a product in full production. DS11400 Rev 8 1/54 www.st.com Contents L9301 Contents 1 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 3 Electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 4 5 3.1 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 3.2 ESD protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 3.3 Operating range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 3.4 Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Supply pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 4.1 VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 4.2 VB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 4.3 VDD_IO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Discrete inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 5.1 Output enable EN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 5.2 Output enable input IN1 to IN8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 5.3 Reset input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 6 Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 7 Configuration 1: 8 low side drivers . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 8 7.1 Configuration 2: 4 low-side PWM mode and 4 low-side drivers . . . . . . . . 18 7.2 Configuration 3: 4 high-side PWM mode and 4 low-side drivers . . . . . . . 19 7.3 Configuration 4: 4 configurable drivers and 8 low-side drivers . . . . . . . . . 21 Configurable high/low side driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 8.1 9 2/54 Electrical characteristics DRN/SRC1-4 . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Low side driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 9.1 Electrical characteristics OUT1-4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 9.2 Electrical characteristics OUT5-8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 DS11400 Rev 8 L9301 Contents 9.3 9.4 Driver diagnostic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 9.3.1 Thermal protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 9.3.2 Overcurrent protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 9.3.3 Output status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 9.3.4 Charge Pump (CP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 9.3.5 DLOSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 9.3.6 OFF state diagnostic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 9.3.7 Over current (OC) comparator self-test . . . . . . . . . . . . . . . . . . . . . . . . . 31 9.3.8 Electrical characteristics related to diagnosis . . . . . . . . . . . . . . . . . . . . 31 Combined diagnosis (configuration 1, 2 & 3) . . . . . . . . . . . . . . . . . . . . . . 34 10 Logic BIST . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 11 Analog BIST . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 12 Clock monitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 13 SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 14 15 13.1 CS, SCK, MOSI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 13.2 MISO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 13.3 SPI frame . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 13.4 SPI registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 13.5 SPI timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 14.1 PowerSSO-36 (exposed pad) package information . . . . . . . . . . . . . . . . . 49 14.2 PowerSSO-36 (exp. pad) marking information . . . . . . . . . . . . . . . . . . . . . 52 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 DS11400 Rev 8 3/54 3 List of tables L9301 List of tables Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 11. Table 12. Table 13. Table 14. Table 15. Table 16. Table 17. Table 18. Table 19. Table 20. Table 21. Table 22. Table 23. Table 24. Table 25. Table 26. Table 27. Table 28. Table 29. Table 30. Table 31. Table 32. 4/54 Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 ESD protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Operating range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Thermal data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Thermal resistance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 VB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 VDDIO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Output enable input IN1 to IN8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Electrical characteristic of EN, IN1...8, RES pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Config 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Config 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Config 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Config 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Configurable high/low side drivers 1-4 electrical characteristics. . . . . . . . . . . . . . . . . . . . . 23 Low-side drivers OUT1-4 electrical characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Low-side drivers OUT5-8 electrical characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Charge pump . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 LS diagnostic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 HS diagnostic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Electrical characteristics related to diagnosis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Configuration 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Configuration 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Clock monitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 CS, SCK, MOSI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 MISO. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 SPI timing characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 PowerSSO-36 (exposed pad) package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . 50 Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 DS11400 Rev 8 L9301 List of figures List of figures Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Figure 10. Figure 11. Figure 12. Figure 13. Figure 14. Figure 15. Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Pin connection diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Device assembled on 2s2p PCB with high density vias in contact with a metal plate . . . . 10 Configuration 1: 8 Low side drivers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Configuration 2: 4 low-side PWM mode and 4 low-side drivers . . . . . . . . . . . . . . . . . . . . . 19 Configuration 3: 4 high-side PWM mode and 4 low-side drivers . . . . . . . . . . . . . . . . . . . . 20 Configuration 4: 4 configurable drivers and 8 low-side drivers . . . . . . . . . . . . . . . . . . . . . 22 Configurable high/low side driver diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Low side driver diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 LS configuration diagnostic. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 HS configuration diagnostic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Analog BIST self-test . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 SPI timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 PowerSSO-36 (exposed pad) package outline. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 PowerSSO-36 (exp. pad) marking information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 DS11400 Rev 8 5/54 5 Block diagram 1 L9301 Block diagram Figure 1. Block diagram L9301 3.3V low dop Internal regulator Vbg VDD 4 x config . HS/LS drivers VB and VDD 5 monitoring chip _enb 0.6ȍ, 3A, 40V VB DRN1 SPI Diag & Ctrl S_CHK DRN2 DRN3 DRN4 Charge pump CP SRC1 SRC2 SRC3 SRC4 IN1 IN2 IN3 4 x LS drivers IN4 Logic 0,6ȍ, 3A, 40V IN5 S_CHK IN6 SPI SPI IN7 Diag & Ctrl OUT1 OUT2 OUT3 OUT4 IN8 RES 4 x LS drivers CS SCK MOSI MISO 0,3ȍ, 3A, 40V EN CLP CLN SPI SPI S_CHK SPI DIP S_CHK OUT5 OUT6 OUT7 OUT8 VDD_I/O EN Diag & Ctrl Oscillator Oscillator Safety Vbg 2 GND1 Vbg 1 Bandgap 1 Bandgap 2 Voltage control Voltage control GND2 GAPG2808151033PS 6/54 DS11400 Rev 8 L9301 2 Pin description Pin description Figure 2. Pin connection diagram 1 36 OUT1 OUT5 2 35 OUT2 OUT6 3 34 SRC1 GND EN 4 33 DRN1 RES 5 32 DRN2 MOSI 6 31 SRC2 SCK 7 30 VDD5 MISO 8 29 IN1 VDD_I/O 28 IN2 CS 10 27 IN3 9 PSSO36 VB 11 26 IN4 CP 12 25 IN5 SRC3 13 24 IN6 DRN3 14 23 IN7 DRN4 15 22 IN8 SRC4 16 21 OUT7 OUT3 17 20 OUT8 OUT4 18 19 GND GAPG2808151125PS Table 2. Pin description Pin Symbol Function 1 GND Power ground of OUT1,2,5,6 2 OUT5 Output 5 3 OUT6 Output 6 4 EN 5 RES Reset input (active low) 6 MOSI SPI data in 7 SCK SPI serial clock input 8 MISO SPI data out 9 VDD_I/O 10 CS SPI chip select (active low) 11 VB Battery supply voltage 12 CP Charge pump 13 SRC3 Source pin of configurable driver #3 14 DRN3 Drain pin of configurable driver #3 Enable Microcontroller logic interface voltage DS11400 Rev 8 7/54 53 Pin description L9301 Table 2. Pin description (continued) 8/54 Pin Symbol Function 15 DRN4 Drain pin of configurable driver #4 16 SRC4 Source pin of configurable driver #4 17 OUT3 Output 3 18 OUT4 Output 4 19 GND Power ground of OUT3,4,7,8 20 OUT8 Output 8 21 OUT7 Output 7 22 IN8 Discrete input used to PWM output driver #8 23 IN7 Discrete input used to PWM output driver #7 24 IN6 Discrete input used to PWM output driver #6 25 IN5 Discrete input used to PWM output driver #5 26 IN4 Discrete input used to PWM output driver #4 27 IN3 Discrete input used to PWM output driver #3 28 IN2 Discrete input used to PWM output driver #2 29 IN1 Discrete input used to PWM output driver #1 30 VDD5 5 Volt supply input 31 SRC2 Source pin of configurable driver #2 32 DRN2 Drain pin of configurable driver #2 33 DRN1 Drain pin of configurable driver #1 34 SRC1 Source pin of configurable driver #1 35 OUT2 Output 2 36 OUT1 Output 1 EP GND Exposed pad: connected to GND DS11400 Rev 8 L9301 Electrical specifications 3 Electrical specifications 3.1 Absolute maximum ratings Table 3. Absolute maximum ratings Symbol VB Parameter Value [DC voltage] Unit -0.3 to 35 V Supply voltage VDD, VDD_I/O Stabilized supply voltage -0.3 to 18((1) V VCS, VSCK, VMOSI, VMISO, VEN, VIN1-8, VRES Logic input/output voltage range -0.3 to 18(1) V OUT1-8 - -1 to VCL V SRC1-4 - -1 to VB V DRN1-4 - -1 to VCL V CP - -0.3 to (VB+CP_DELTA) V GND - -0.3 to +0.3 V 1. Short to 18 V for 100 h max. Note: A suitable device to clamp the voltage during ‘load dump’ event to a value ≤35 V must be present at application level. 3.2 ESD protection Table 4. ESD protection Parameter Value Unit ESD according to Human Body Model (HBM), Q100-002 for pins (100 pF/1.5 kΩ) ±4000 V ESD according to Human Body Model (HBM), Q100-002 for all other pins; (100 pF/1.5 kΩ) ±2000 V ESD according to Charged Device Model (CDM), Q100- 011 Corner pins ±750 V ESD according to Charged Device Model (CDM), Q100-011 Noncorner pins ±500 V (1); 1. VB, DRN1-4, SRC1-4, OUT1-8. DS11400 Rev 8 9/54 53 Electrical specifications 3.3 L9301 Operating range Table 5. Operating range Symbol Parameter VB Max. Unit VB_UV 18 V VDD_UV VDD_OV V 3.0 5.5 V Supply voltage VDD Stabilized supply voltage VDD_IO 3.4 Min. Logic output supply voltage Thermal data Table 6. Thermal data Symbol Parameter Min. Typ. Max. Unit Operating ambient temperature -40 - 125 °C Tstg Storage temperature -40 - 150 °C Tj Junction temperature -40 - 175 °C Thermal shutdown temperature 180 - 195 °C - 10 - °C Tamb(1) Tsd Thermal shutdown temperature hysteresis Tsd-hys 1. For information only, in any case Tj limits must not exceed. Table 7. Thermal resistance Symbol Value Unit 2s2p (4L) board; Natural convection(1) 27 °C/W 2s2p (4L) board on ECU metal plate(2) 8 °C/W Junction to bottom case Bottom cold plate(3) 1 °C/W Rth j-top case Junction to top case Top cold plate(4) 21 °C/W Psij-top case Psi Junction to top case 2s2p (4L) board; Natural convection (1) 2 °C/W Rth j-amb Rth j-bottom case Parameter Junction to ambient Working conditions 1. Jedec STD. JESD51. 2. Package assembled on 2s2p (4L) board. The board bottom side is in contact with a metal plate as per typical automotive application (ECU system). See Figure 3. 3. Thermal resistance between the die and the bottom case surface in ideal contact and measured by cold plate as per Jedec best practice guidelines (JESD51). 4. Thermal resistance between the die and the top case surface in ideal contact and measured by cold plate as per Jedec best practice guidelines (JESD51). Figure 3. Device assembled on 2s2p PCB with high density vias in contact with a metal plate 10/54 DS11400 Rev 8 L9301 Supply pins 4 Supply pins 4.1 VDD An external +5.0 ±0.25 VDC supply provided from an external source is the primary power source to the L9301. This supply is used as the power source for all of its internal logic circuitry and other miscellaneous functions. The VDD is monitored for under and over voltage and a dedicated SPI flag of each event is set to report those conditions. Once the fault flag is asserted it will be latched until a clear operation, writing 0, is performed. The device behavior in case of VDD fault detection can be defined using the proper configuration bit (CR0: vdduv_conf, vddov_conf) that allows to choose if the OUT must be disabled or not. 5 V ≤ VB < 18 V; -40 °C ≤ Tj ≤ 175 °C unless otherwise specified. Table 8. VDD Pin Symbol VDD_UV VDD_uv_filt VDD undervoltage detection threshold Test condition VDD decreasing VDD undervoltage filter Tested by scan time for output disable Min. Typ. Max. Unit 4.5 - 4.7 V 90 - 145 µs VDD overvoltage detection threshold VDD increasing 5.25 - 5.5 V VDD_ov_filt VDD overvoltage filter time for output disable Tested by scan 90 - 145 µs VDD_Istby VDD standby current consumption VDD = 5.25 V EN = 0; RES = 0 - - 7.5 mA VDD_Ibias VDD current consumption VDD = 5.25 V EN = 1; RES = 1 - - 13.8 mA VDD_OV VDD 4.2 Parameter VB This input is the supply for the on board charge pump and it shall be connected to protect battery line. In case of high-side configuration, to get the specified Ron value this pin must be connected to the same VB where the loads are connected. If it is present an additional voltage drop between the two VB, the Rdson of that given output will be higher than the specified maximum. The VB is monitored for under and over voltage and a dedicated SPI flag of each event is set to report those conditions. Once the fault flag is asserted it will be latched until a clear operation, writing 0, is performed. The device behavior in case of VB fault detection can be defined using the proper configuration bit that allows to choose if the OUT must be disabled or not. 5 V ≤ VB < 18 V; -40 °C ≤ Tj ≤ 175 °C unless otherwise specified. DS11400 Rev 8 11/54 53 Supply pins L9301 Table 9. VB Pin Symbol Test condition Min. Typ. Max. Unit VB_UV VB undervoltage detection threshold VB decreasing 3.5 - 4 V VB_UV_on VB undervoltage detection threshold VB increasing 4 - 4.5 V VB_UV_hys VB undervoltage hysteresis - 0.1 - 1 V VB_UV_filt VB undervoltage filtering time Tested by scan 90 - 145 us VB_OV VB overvoltage detection threshold VB increasing 19 - 22 V VB_OV_on VB overvoltage detection threshold VB decreasing 19 - 21 V VB_UV_hys VB overvoltage hysteresis - 0.1 - 1 V VB_OV_filt VB overvoltage filtering Tested by scan time 90 - 145 µs VB 4.3 Parameter VB_Istby VB standby current consumption VB = 18 V EN = 0; RES = 0 - - 0.19 mA VB_Ibias VB current consumption VB = 18 V EN = 1; RES = 1 - - 0.55 mA VDD_IO This pin is used to supply the discrete MISO output stage of L9301 and must be connected to the same voltage used to supply the peripherals of the processor interfaced to L9301. Table 10. VDDIO Pin Symbol Test condition Min. Typ. Max. Unit VDDIO_Istby VDDIO standby current VDDIO = 5.25 V consumption EN = 0; RES = 0 - - 0.96 mA VDDIO_Ibias VDDIO current consumption - - 0.82 mA VDDIO 12/54 Parameter VDDIO = 5.25 V EN = 1; RES = 1 DS11400 Rev 8 L9301 Discrete inputs 5 Discrete inputs 5.1 Output enable EN The EN pin is the general output enable which allows the µC to immediately switch off the output in case of need. Output driving is allowed only if this pin is driven to high level. The device configuration can be changed only with EN pin is driven to low level. An internal pull down is present on the pin. 5.2 Output enable input IN1 to IN8 These inputs allow the outputs, depending on the configuration selected, to be enabled without the use of the SPI. The SPI command and the IN1-8 input are logically OR'd together. A logic ‘1’ on this input will enable the correspondent output no matter what the status of the SPI command register is. A logic ‘0’ on this input will disable this output if the SPI command register is not commanding this output on. These pins can be left ‘open’ if the internal power stages are controlled only via the SPI. This input has a nominal 100 kΩ pull down resistor to GND, which will pull this pin to ground if an open circuit condition occurs. This input is ideally suited for loads that are pulse width modulated (PWM'd). This allows PWM control without the use of the SPI inputs. Table 11. Output enable input IN1 to IN8 EN RESET INx OUTx/DRNx/SRCx X 0 X OFF 0 X X OFF 1 1 0 OFF 1 1 1 ON DS11400 Rev 8 13/54 53 Discrete inputs 5.3 L9301 Reset input When this input goes low it resets all the internal registers and switches off all the output stages. This input has a nominal 100 kΩ resistor connected from this pin to the internal 3.3 V regulator, which will pull this pin to 3.3 V if an open circuit condition occurs. No filter is present on this input so spurious pulse must be avoided. 5 V ≤ VB < 18 V; -40 °C ≤ Tj ≤ 175 °C unless otherwise specified. Table 12. Electrical characteristic of EN, IN1...8, RES pin Pin Symbol Parameter V_IH Logic input high voltage - V_IL Logic input low voltage V_Ihys IN1...8, EN RES IN1...8, EN, RES 14/54 Test condition Max. Unit 1.75 VDD+0.3 V - -0.3 0.75 V Logic input hysteresis - 100 1000 mV Ri_pd Pull down resistor Tested at 1.5 V 50 100 150 kΩ Ri_pu Pull up resistor Tested at 1.5 V,  R = (3.3-1.5)/Imeasure 50 100 150 kΩ DS11400 Rev 8 Min. Typ. L9301 Configuration 6 Configuration The selected configuration can be configured by SPI, there are 2 bits dedicated to configuration selection: Table 13. Configuration Bit1 Bit0 Configuration Input → Output 0 0 1 0 1 2 IN1-4 → OUT1-4 IN5-8 → OUT5-8 4 low side channels with Rdson = 0.6 Ω 4 low side channels with Rdson = 0.3 Ω 1 0 3 IN1-4 → SRC1-4, IN5-8 → OUT5-8 4 high side channels with Rdson = 0.6 Ω 4 low side channels with Rdson = 0.3 Ω 1 1 4 IN1-4 → OUT1-4, IN5-8 → OUT5-8, SPI → DRN/SRC1-4 4 low side channels with Rdson = 0.6 Ω 4 low side channels with Rdson = 0.3 Ω 4 low/high side ch. with Rdson = 0.6 Ω IN1-4 → DRN1-4, OUT1-4 (paralleled) IN5-8 → OUT5-8 Description 8 low side channels with Rdson = 0.3 Ω The configuration is enabled only when EN pin is logic 0. In configuration 4, the output DRN/SRC1-4 can be controlled by SPI only; for those outputs the selection between high side and low side configuration can be done through the dedicated bit (bit8 of Device general configuration register). DS11400 Rev 8 15/54 53 Configuration 1: 8 low side drivers 7 L9301 Configuration 1: 8 low side drivers In this configuration there are 8 low side drivers available that can be driven by SPI or by the parallel input: IN1-4 control both DRAIN1-4 and OUT1-4 that must be turned on and off simultaneously while IN5-8 control OUT5-8. Parallelized output must be externally connected to each other to ensure correct functionality and diagnostic. The corresponding relations are: Table 14. Config 1 16/54 INx SPI: CR13 Output IN1 Cmd1 OUT1//OUT2 IN2 Cmd2 OUT3//OUT4 IN3 Cmd3 DRN1//DRN2 IN4 Cmd4 DRN3//DRN4 IN5 Cmd5 OUT5 IN6 Cmd6 OUT6 IN7 Cmd7 OUT7 IN8 Cmd8 OUT8 DS11400 Rev 8 L9301 Configuration 1: 8 low side drivers Figure 4. Configuration 1: 8 Low side drivers VB LOAD1 VB L9301 CP Charge pump VB Internal Supply DRAIN1-2 HS/LS Driver 9ȍ LOAD2 SOURCE1-2 DRAIN3-4 Diagnostic VB SOURCE3-4 VB LOAD3 LOAD4 VB LOGIC OUT1-2 LS Driver 9ȍ OUT3-4 VB LOAD9-12 RES VDD_I/O LS Driver 9ȍ CS SCK OUT5-8 SPI MOSI GND MISO GND GAPG0109151248PS Note: pwm_en bit has no effect in this configuration DS11400 Rev 8 17/54 53 Configuration 1: 8 low side drivers 7.1 L9301 Configuration 2: 4 low-side PWM mode and 4 low-side drivers In this configuration there are 4 low side drivers with integrated free-wheeling diodes and 4 low side drivers available. All the channels can be driven by SPI or by the parallel input. To enable the OUT1-4 driving, the PWM enable SPI bit for OUT1-4 and SRC1-4 must be set. The IN1-4 control the low side power OUT1-4 used to drive the LOAD1-4 and the device assures that when the low-side is switched off, the high-side, acting as a free-wheeling diode, must be turned on. To avoid cross conduction the LS VGS voltage is monitored. When OUT1-4 are commanded ON either by INx or SPI, the L9301 switches off the HS first, then with 2 µs delay after detecting HS VGS low, it switches on LS. When OUT1-4 are commanded OFF either by INx or SPI, the L9301 switches off the LS first, then with 2 µs delay after detecting LS VGS low, it switches on the HS. IN5-8 control OUT5-8 The selected configuration must be configured by SPI and the wanted channel must be enabled using pwm_en bit in the corresponding register. The corresponding relations are: Table 15. Config 2 18/54 INx SPI: CR13 Output IN1 Cmd1 OUT1 SRC2 IN2 Cmd2 OUT2 SRC1 IN3 Cmd3 OUT3 SRC4 IN4 Cmd4 OUT4 SRC3 IN5 Cmd5 OUT5 IN6 Cmd6 OUT6 IN7 Cmd7 OUT7 IN8 Cmd8 OUT8 DS11400 Rev 8 L9301 Configuration 1: 8 low side drivers Figure 5. Configuration 2: 4 low-side PWM mode and 4 low-side drivers VB L9301 CP VB LOAD 1- 4 Charge pump HS/LS Driver 9ȍ Internal Supply DRN1-4 SRC1-4 V5V Diagnostic EN IN1 OUT1-4 IN2 LS Driver 9ȍ IN3 IN4 IN5 VB LOGIC IN6 LOAD 5-8 IN7 IN8 LS Driver 9ȍ RES VDD_I/O OUT5-8 CS SCK SPI MOSI GND MISO GND GAPG0109151552PS 7.2 Configuration 3: 4 high-side PWM mode and 4 low-side drivers In this configuration there are 4 high side drivers with integrated free-wheeling diodes and 4 low side drivers available. All the channels can be driven by SPI or by the parallel input. To enable the SRC1-4 driving, the PWM enable SPI bit for SRC1-4 and OUT1-4 must be set. The IN1-4 control the high side power SRC1-4 used to drive the LOAD1-4 and the device assures that when the high-side is switched off, the low-side, acting as a free-wheeling diode, must be turned on. To avoid cross conduction the HS VGS voltage is monitored. When SRC1-4 is commanded ON either by INx or SPI, the L9301 switches off the LS first, then with 2 µs delay after detecting LS VGS low, it switches on HS. When SRC1-4 is commanded OFF either by INx or SPI, the L9301 switches off the HS first, then with 2 µs delay after detecting HS VGS low, it switches on the LS. IN5-8 control OUT5-8 The selected configuration must be configured by SPI and the wanted channel must be enabled using pwm_en bit in the corresponding register. The corresponding relations are: DS11400 Rev 8 19/54 53 Configuration 1: 8 low side drivers L9301 Table 16. Config 3 INx SPI: CR13 Output IN1 Cmd1 SRC1 OUT2 IN2 Cmd2 SRC2 OUT1 IN3 Cmd3 SRC3 OUT4 IN4 Cmd4 SRC4 OUT3 IN5 Cmd5 OUT5 IN6 Cmd6 OUT6 IN7 Cmd7 OUT7 IN8 Cmd8 OUT8 Figure 6. Configuration 3: 4 high-side PWM mode and 4 low-side drivers VB L9301 CP Charge pump VB Internal Supply HS/LS Driver 9ȍ DRN1-4 SRC1-4 V5V LOAD1- 4 Diagnostic EN IN1 OUT1-4 IN2 LS Driver 9ȍ IN3 IN4 IN5 VB LOGIC IN6 LOAD5-8 IN7 IN8 LS Driver 9ȍ RES VDD_I/O OUT5-8 CS SCK SPI MOSI GND MISO GND GAPG0309150951PS 20/54 DS11400 Rev 8 L9301 7.3 Configuration 1: 8 low side drivers Configuration 4: 4 configurable drivers and 8 low-side drivers In this configuration there are 4 HS/LS drivers and 8 low side drivers available. All the LS can be driven by SPI or by the parallel input. The IN1-8 control OUT1-8 while the configurable driver can only be controlled by SPI. The four configurable drivers (DRN1-4, SRC1-4) can be configured separately as LS or HS using the dedicated SPI bit. Table 17. Config 4 INx SPI: CR13 Output IN1 Cmd1 OUT1 IN2 Cmd2 OUT2 IN3 Cmd3 OUT3 IN4 Cmd4 OUT4 IN5 Cmd5 OUT5 IN6 Cmd6 OUT6 IN7 Cmd7 OUT7 IN8 Cmd8 OUT8 - Cmd9 DRN1 - SRC1 - Cmd10 DRN2 - SRC2 - Cmd11 DRN3 - SRC3 - Cmd12 DRN4 - SRC4 DS11400 Rev 8 21/54 53 Configuration 1: 8 low side drivers L9301 Figure 7. Configuration 4: 4 configurable drivers and 8 low-side drivers L9301 CP Charge pump VB Internal Supply DRN1-4 Driver SRC1-4 VB Diagnostic LS Driver OUT1-4 VB LOGIC LS Driver RES OUT5-8 CS SCK SPI MOSI GND MISO GND GAPG0309151058PS Note: 22/54 pwm_en bit has no effect in this configuration DS11400 Rev 8 L9301 8 Configurable high/low side driver Configurable high/low side driver The channels 1 to 4 can be configured as high or low side using SPI CR0: conf4_lshs. In the low side configuration an internal clamp is present. In high side configuration, the DRNx are connected to VB pin on PCB. To guarantee the OC (over current) function, the DRNx voltage has to be within the range of (VB-1 V, VB+1 V). Figure 8. Configurable high/low side driver diagram DRNx VB Vcp Charge pump Driver VDD5 dropout reg. SRCx EN INx Logic protection cmd _X RES SPI GAPG0309151213PS 8.1 Electrical characteristics DRN/SRC1-4 5 V ≤ VB < 18 V; -40°C ≤ Tj ≤ 175°C unless otherwise specified. Table 18. Configurable high/low side drivers 1-4 electrical characteristics Pin Symbol DRN1-4 RDS-on_HLS SRC1-4 Parameter Test condition HS/LS configuration VB = 13.5 V; I_load = 1 A DS11400 Rev 8 Min. Typ. Max. Unit - - 0.6 Ω 23/54 53 Configurable high/low side driver L9301 Table 18. Configurable high/low side drivers 1-4 electrical characteristics (continued) Pin Symbol Parameter Test condition Min. Typ. Max. Unit HS configuration DRNx = 13.5 V; SRCx = 0 V - - 10 µA LS configuration DRNx = 13.5 V; SRCx = 0 V - - 10 µA V_S/RS HS/LS configuration VB 13.5 V Voltage S/R on/off slow Load: 8 Ω, 10 nF – From 80% to 30% of DRNx(SRCx) 2 4 6 V/µs V_S/Rf HS/LS configuration VB 13.5 V Load: 8 Ω, 10 nF – From 80% to 30% of DRNx(SRCx) 5 10 15 V/µs HS configuration VB 13.5 V From command to 10% SRCx Load: 8 Ω, 10 nF - - 3 µs LS configuration VB 13.5 V From command to 90% DRNx Load: 8 Ω, 1 0nF - - 3 µs HS configuration VB 13.5 V From command to 90% SRCx Load: 8 Ω, 10 nF - - 3 µs LS configuration VB 13.5 V From command to 10% DRNx Load: 8 Ω, 10 nF - - 3 µs Note for application - - 28 µs LS configuration I_load= 0.6 A T = 130 °C 34 37.5 41 LS configuration I_load = 0.6 A, T = -40 °C and 25 °C 35 37.5 41 LS configuration I_load = 0.7 A, Tj = 150 °C, 100 kpulses - - 5 LS configuration I_load = 0.7 A, Tj = 150 °C - IOUT_LK_HLS Output leakage current Voltage S/R on/off fast Tturn-on_HLS Turn-on delay time DRN1-4 SRC1-4 Tturn-off_HLS Turn-off delay time Min_duty VCL_LS Minimum ON/OFF time of INx or SPI CMDx Output clamping voltage EclampSP_LS Energy repetitive pulse EclampSP_LS Single pulse energy 24/54 DS11400 Rev 8 V mJ - 10 L9301 9 Low side driver Low side driver The channels OUT1 to 8 are low side drivers with internal clamp. Figure 9. Low side driver diagram OUTx VDD5 3,3V low dropout reg. EN INx V33 Driver cmd _outX Diagnosis & protection Logic cmd _X RES SPI GAPG0409150811PS 9.1 Electrical characteristics OUT1-4 5 V ≤ VB < 18 V; -40 °C ≤ Tj ≤ 175 °C unless otherwise specified. Table 19. Low-side drivers OUT1-4 electrical characteristics Pin OUT1-4 Symbol Parameter Test condition Min. Typ. Max. Unit RDS-on_LS Drain–source resistance I_load = 1 A - - 0.6 Ω IOUT_LK_LS Output leakage current OUTx = 13.5 V - - 10 µA VS/R_s_LS Voltage S/R on/off “slow” VB = 13.5 V Load: 8 Ω, 10 nF – From 80% to 30% of OUTx 2 4 6 V/µs VS/R_f_LS Voltage S/R on/off “fast” VB = 13.5 V Load: 8 Ω, 10 nF – From 80% to 30% of VOUT 5 10 15 V/µs DS11400 Rev 8 25/54 53 Low side driver L9301 Table 19. Low-side drivers OUT1-4 electrical characteristics (continued) Pin Symbol Test condition Min. Typ. Max. Unit Tturn-on_LS Turn-on delay time From command to 80% OUTx, VB = 13.5 V Load: 8 Ω, 10 nF - - 3 µs Tturn-off_LS Turn-off delay time From command to 30% OUTx, VB = 13.5 V Load: 8 Ω, 10nF - - 3 µs Min_duty Minimum ON/OFF time of INx or SPI CMDx Note for application - - 28 µs I_load = 0.6 A T = 130 °C 34 37.5 41 I_load = 0.6A T= -40 °C and 25 °C 35 37.5 41 - 5 OUT1-4 VCL_LS Output clamping voltage EclampSP_LS Energy repetitive pulse LS configuration I_load = 0.7 A, Tj = 150 °C, 100 kpulses - Single pulse energy LS configuration I_load = 0.7 A, Tj = 150 °C - EclampSP_LS 26/54 Parameter DS11400 Rev 8 V mJ - 10 L9301 9.2 Low side driver Electrical characteristics OUT5-8 5 V ≤ VB < 18 V; -40 °C ≤ Tj ≤ 175 °C unless otherwise specified. Table 20. Low-side drivers OUT5-8 electrical characteristics Pin OUT5-8 Symbol Parameter Test condition Min. Typ. Max. Unit RDS-on_LS Drain–source resistance I_load = 2 A - - 0,3 Ω IOUT_LK_LS Output leakage current OUTx = 13.5 V - - 10 µA VS/R_s_LS Voltage S/R on/off “slow” VB = 13.5 V Load: 8 Ω, 10 nF – From 80% to 30% of OUTx 2 4 6 V/µs VS/R_f_LS Voltage S/R on/off “fast” VB = 13.5 V Load: 8 Ω, 10 nF – From 80% to 30% of VOUT 5 10 15 V/µs Tturn-on_LS Turn-on delay time From command to 80% OUTx Load: 8 Ω, 10 nF - - 3 µs Tturn-off_LS Turn-off delay time From command to 30% OUTx Load: 8 Ω, 10 nF - - 3 µs Min_duty Minimum ON/OFF time of INx or SPI CMDx Note for application - - 28 µs I_load = 1.25 A T = 130 °C 34 37.5 41 I_load = 1.25 A T= -40 °C and 25 °C 35 37.5 41 - 15 mJ 18.1 mJ VCL_LS Output clamping voltage EclampSP_LS Energy repetitive pulse LS configuration I_load = 2.2 A, Tj = 150 °C, 100 kpulses - EclampSP_LS Single pulse energy LS configuration I_load = 2.2 A, Tj = 150 °C - 9.3 Driver diagnostic 9.3.1 Thermal protection V Each solenoid channel has a dedicated temperature sensor that continuously monitors the temperature of the PowerMOS. In case the shutdown temperature Tsd is reached the related channel is turned off and the dedicated diagnostic bits are set. t_sdl_x is the bit that latches the thermal shut down and it is cleared after sending dedicated SPI to clear the bit, t_sd_x is the other thermal shut down bit and once it is set by thermal shut down condition it is cleared only when the Tj decreases below the thermal shut down threshold (hysteresis). If the microcontroller, when the device DS11400 Rev 8 27/54 53 Low side driver L9301 is still in temperature shut down condition (t_sd_x = 1), clears the t_sdl_x and tries to turn on the output, the actuation is not performed and the t_sdl_x will be set again. To avoid these multiple interrupts the microcontroller can poll the t_sd_x bit and enable the next actuation only when the bit is zero. To re-switch on the channel after thermal shut down, the SPI needed to switch off the channel is required. 9.3.2 Overcurrent protection An overcurrent protection is present for each driver OUT1-8 and DRN/SRC1...4. The overcurrent threshold is selectable through oc_thres_x (where x indicates the channel). In case of overcurrent the output driver is turned off and a dedicated diagnostic bit is set oc_x where x indicates the channel where the fault occurred. If bit oc_restart = 0, to restart the channel the microcontroller has to clear the fault bit (writing 0 in the corresponding SPI flag), and to write to 1 the SPI command bit or to provide a rising edge on the parallel input command. If bit oc_restart = 1, the restart function is activated. The slew rate of the channel in fault condition is automatically set to the higher value to limit dissipation issue then to restart the channel the microcontroller has to write to 1 the SPI command bit or to provide a rising edge on the parallel input command. The diagnostic bit oc_x can be cleared only by writing it to 0 in the corresponding driver status register by SPI however the channel can be restarted as described above. 9.3.3 Output status During the ON phase, the output voltage is compared with the VTopen threshold voltage in order to verify if the output status is aligned with the ON command: 9.3.4  in case of low side usage if the DRNx voltage is above the VTopen threshold a dedicated bit (SRx: bit 8 os) is set to indicate the anomaly  in case of high side usage if the SRCx voltage is below the VTopen threshold a dedicated bit is (SRx: bit 8 os) set to indicate the anomaly  if OUTx voltage is above VTopen threshold a dedicated bit (SRx: bit 8 os) is set to indicate the anomaly Charge Pump (CP) The charge pump is enabled when the selected configuration includes high side drivers (like configuration 2, 3, 4). In configuration 1 the charge pump is internally shorted to VB. On the CP pin it's required to connect a 100 nF capacitor toward the VB line. The charge pump is ON if VB > UV threshold & VDD > UV threshold The charge pump is OFF if VB< UV threshold or VDD< UV threshold. The CP voltage is equal to VB-Vbe. When the CP is ON, the low CP diagnosis is enabled. When any HS is switched on but CP voltage is not high enough to switch on HS, low CP fault is detected and stored in cpl SPI flag. In order to reset the flag a 0 has to be written by microcontroller. A SPI bit allows configuring the actions to be taken in case of low CP fault. 5 V ≤ VB < 18 V; -40 °C ≤ Tj ≤ 175 °C unless otherwise specified. 28/54 DS11400 Rev 8 L9301 Low side driver Table 21. Charge pump Pin CP 9.3.5 Symbol Parameter Test condition CP_DELTA Delta voltage CP-VB VB>5V Min. Typ. Max. Unit 3 - 6 V DLOSS When the L9301 is configured with low side and external diodes are used for freewheeling, there is the possibility through a dedicated SPI bit to enable the ‘diode loss’ diagnosis that is used to detect if the external diode is no more connected checking if during the OFF phase the internal clamp is activated. In case of fault is stored in DLOSS SPI flag. In order to reset the flag a 0 has to be written by microcontroller. Another SPI bit allows configuring the actions to be taken in case of DLOSS fault. When the L9301 is configured as high side and internal/external diodes are used for freewheeling, there is the possibility through a dedicated SPI bit to enable the ‘diode loss’ diagnosis that is used to detect if the diode is no more connected checking if during the OFF phase the HS is forced to switch on. In case of fault is stored in DLOSS SPI flag. In order to reset the flag a 0 has to be written by microcontroller. Another SPI bit allows configuring the actions to be taken in case of DLOSS fault. In addition, diode loss on LS (including configurable channels configured as LS) is only detected when VBOV is not present. 9.3.6 OFF state diagnostic The device provides the off-state diagnostic for each channel. In low-side configuration the short to ground and open load faults can be detected. The fault is reported in a SPI register. The pull-up current on the single channel can be disabled using the dis_source bit in registers CR1-CR12. The OFF diagnostic can be disabled using the dis_diag_off bit in registers CR1-CR12. Figure 10. LS configuration diagnostic VB VTOPEN ILOADx DIAGOL I_LS_PU VOUTOPEN gm DRNx I_LS_PD VTGND DIAGLV GATE DRIVER off state SRCx GAPG0309151526PS DS11400 Rev 8 29/54 53 Low side driver L9301 Table 22. LS diagnostic DIAGOL DIAGLV FAULT DETECTION 0 0 no fault 0 1 not possible 1 0 open load 1 1 short to ground In high-side configuration the short to battery and open load faults can be detected. The fault is reported in a SPI register. Figure 11. HS configuration diagnostic VB DRNx GATE DRIVER off state VTVBAT DIAGOL I_HS_PU VOUTOPEN gm SRCx I_HS_PD VTOPEN DIAGLV ILOADx GAPG0309151534PS Table 23. HS diagnostic DIAGOL DIAGLV FAULT DETECTION 0 0 short to battery 0 1 not possible 1 0 open load 1 1 no fault The diagnostic blanking time is configurable through the dedicated diagoff_blank_sel bit. The OFF diagnosis is triggered at driver OFF CMD and will not be refreshed after clearing the flags. To recover the OFF diagnosis in OFF stage, send SPI to disable OFF diagnosis and then enable it. 30/54 DS11400 Rev 8 L9301 9.3.7 Low side driver Over current (OC) comparator self-test L9301 provides driver OC (over current) comparator self-test function. During OFF phase, the OC comparator still works and the expected result is '1' due to high drain-source voltage. If L9301 detects OC '0' during OFF phase, the SPI bit oc_comparator_f is set to '1'. For DRN1-4, when they are configured as LS, a Short To Ground (STG) fault will not trigger OC '1', so L9301 will report both STG and OC comparator self-test fail, when they are configured as HS, a short-to-battery (STB) fault will not trigger OC '1', so L9301 will report both STB and OC comparator self-test fail. For OUT1-8, if a STG is present at OFF phase, the OC comparator inputs are still forced to have OC '1'. 9.3.8 Electrical characteristics related to diagnosis 5 V ≤ VB < 18 V; -40 °C ≤ Tj ≤ 175 °C unless otherwise specified. Table 24. Electrical characteristics related to diagnosis Pin Symbol Parameter Test condition Min. Typ. Max. Unit TOver_temperature_blanking Over temperature blanking time Tested by scan 1 - 1.5 µs TOver_temperature_filter Over temperature filter time Tested by scan 2 - 5 µs TCharge_pump_low Charge pump low filter time Tested by scan 3 - 5 µs TCharge_pump_low_blanking Charge pump low blanking time Tested by scan 25 - 40 µs Diode loss filter time Tested by scan 3 - 5 µs Min. resistor value open load detection Not tested 10 - IOC_HLS Over current threshold 1 - 1 2 3 A IOC_HLS Over current threshold 2 - 3 4 5 A Over current filtering Tested by scan time 3 - 5 µs TFLT_diagoff_HLS Filtering open load and short to GND diag. off Tested by scan 55 - 80 µs Td_blank0_HLS Diagnosis blanking time after switch-off Tested by scan 900 - 1300 µs Td_blank1_HLS Diagnosis blanking time after switch-off Tested by scan 450 - 650 µs HS configuration 1.9 2.1 2.3 V LS configuration 2.7 2.9 3.1 V Tdiode_loss_filter_time Ropen_load_HLS DRN1-4 SRC1-4 TFLT_OC_HLS VTOPEN_HS VTOPEN_LS Open load threshold voltage DS11400 Rev 8 kΩ 31/54 53 Low side driver L9301 Table 24. Electrical characteristics related to diagnosis (continued) Pin Symbol Min. Typ. Max. Unit HS and LS configuration Open load condition 2,3 - 2,7 V VTVBAT_HS Output short-circuit to VB voltage threshold (HS configuration) HS configuration 2.7 - 3.1 V VTGND_LS Output short-circuit to GND voltage threshold (LS configuration) LS configuration 1.9 - 2.3 V HS configuration DRNx =13.5V SRCx =5V 210 245 300 µA 40 70 100 µA HS configuration DRNx =13.5V SRCx =1.5V 40 70 100 µA LS configuration DRNx =1.5V SRCx =0V 50 75 100 µA - Application note Minimum OFF time NOT TESTED for correct diagnostic (ESD cap < 12nF, (Blank time 0) Bit_blank=0) - 1380 - µs - Application note Minimum OFF time NOT TESTED for correct diagnostic (ESD cap < 6nF, (Blank time 1) Bit_blank=1) - 730 - µs IOUT_PD_HLS SRC1-4 IOUT_PU_HLS 32/54 Test condition Open load output voltage VOUTOPEN_HLS DRN1-4 Parameter Output diagnostic pull- down current @ LS configuration OFF STATE DRNx =5V SRCx =0V Output diagnostic pull-up current @ OFF STATE DS11400 Rev 8 L9301 Low side driver Table 24. Electrical characteristics related to diagnosis (continued) Pin Symbol Test condition Min. Typ. Max. Unit TOver_temperature_blanking Over temperature blanking time Tested by scan 1 - 1.5 µs TOver_temperature_filter Over temperature filter time Tested by scan 2 - 5 µs Min. resistor value open load detection Not tested 50 - - kΩ Output current Not tested - 2.2 - A IOVC1_OUT1-4 Over current threshold1 OUT1-4 - 1 2 3 A IOVC2_ OUT1-4 Over current threshold2 OUT1-4 - 3 4 5 A IOVC1_OUT5-8 Over current threshold1 OUT5-8 - 2 4 6 A IOVC2_ OUT5-8 Over current threshold2 OUT5-8 - 6 8 10 A TFLT_OVC_LS Over current filtering Tested by scan time 3 - 5 µs TFLT_diagoff_LS Filtering open load and short to GND diag. off Tested by scan 55 - 80 µs Td_blank0_LS Diagnosis blanking time after switch-off Tested by scan 600 - 900 µs Td_blank1_LS Diagnosis blanking time after switch-off Tested by scan 300 - 450 µs VTOPEN_LS Open load threshold voltage 2.7 - 3.1 V Ropen_load_LS IMAX_LS OUT1-8 Parameter DS11400 Rev 8 33/54 53 Low side driver L9301 Table 24. Electrical characteristics related to diagnosis (continued) Pin Symbol Parameter Test condition Min. Typ. Max. Unit Open load output voltage Open load condition 2,3 2.5 2,7 V VTGND_LS Output short-circuit to GND voltage threshold - 1.9 - 2.3 V IOUT_PD_LS Output diagnostic pull- down current @ OUTx = 5 V OFF STATE 40 70 100 µA IOUT_PU_LS Output diagnostic pull-up current @ OFF STATE 50 75 100 µA VOUTOPEN_LS OUT1-8 9.4 OUTx=1.5 V - Minimum OFF time Application note for correct diagnostic (ESD cap < 12 (Blank time 0) nF, Bit_blank = 0) 980 - - µs - Minimum OFF time Application note for correct diagnostic (ESD cap < 6 nF, (Blank time 1) Bit_blank = 1) 530 - - µs Combined diagnosis (configuration 1, 2 & 3) In configuration 1, there are four couples of drivers in parallel to get four channels with lower RdsON: OUT1 with OUT2, OUT3 with OUT4, DRN1 with DRN2, and DRN3 with DRN4. For each couple, only one driver off diagnosis is enabled (OUT1, OUT3, DRN1, DRN3) while the off diagnosis results are stored in both drivers registers. The other diagnosis of the two drivers in parallel, as over-current, over-temperature and DLOSS, are both enabled. The correct effect of the diagnosis can be guaranteed only if the drivers are correctly parallelized externally. In configuration 2 the off diagnosis is enabled for OUT1-4 only. Considering that the diagnosis blanking time can be longer than the off time of PWM, the diagnosis results can be affected. The short to GND fault can be detected by the HS OC fault when it is switched on. The Open Load Fault can be detected when PWM is disabled (PWM disable SPI bit = 1) only because in such a condition both HS and LS are OFF. In this condition the OUTx is pulled down by LS off diagnosis pull down current (typical 70 µA) and it's necessary to wait the time needed to discharge OUTx to get Open Load (OL) detection. The time to be considered starts from the PWM disable bit writing. 34/54 DS11400 Rev 8 L9301 Low side driver Table 25. Configuration 2 Parameter Test condition Min. Typ. Max. Unit Minimum OFF time for correct diagnostic (Blank time 0) Application note NOT TESTED (ESD cap < 12 nF, Bit_blank = 0) 4140 - - µs Minimum OFF time for correct diagnostic (Blank time 1) Application note NOT TESTED (ESD cap < 6 nF, Bit_blank=1) 2190 - - µs In configuration 3 the off diagnosis is enabled for HS1-4 only. Considering that the diagnosis blanking time can be longer than the off time of PWM, the diagnosis results can be affected. The short to VB fault can be detected by the OC fault when it is switched on. The Open Load Fault can be detected when PWM is disabled (PWM disable SPI bit = 1) only because in such a condition both HS and LS are OFF. In this condition the OUTx is pulled up by HS off diagnosis pull up current (typical 75 µA) and it's necessary to wait the time needed to discharge OUTx to get Open Load (OL) detection. The time to be considered starts from the PWM disable bit writing. Table 26. Configuration 3 Parameter Test condition Min. Typ. Max. Unit Minimum OFF time for Application note NOT TESTED correct diagnostic (Blank (ESD cap < 12 nF, Bit_blank = 0) time 0) 980 - - µs Minimum OFF time for Application note NOT TESTED correct diagnostic (Blank (ESD cap < 6 nF, Bit_blank=1) time 1) 530 - - µs In configuration 2 and 3, unless the PWM enable SPI bit for OUT1-4 and DRN/SRC1-4 are set, the eight drivers are all switched off. DS11400 Rev 8 35/54 53 Logic BIST 10 L9301 Logic BIST After VDD power on with RES = Hi, SCK = Lo a digital logic BIST (built-in self-test) it's started and it takes max 11ms to be completed. In case of RES = Hi and SCK = Hi the BIST will be not executed. The BIST status register (0x1E) contains three bits to reflect the status of BIST. The purpose of logic BIST is to test the control and diagnosis logic. If the BIST ends with an error, the device is no longer reliable. While the BIST is running, the device is not operative. The oscillator FLL (Spread Spectrum) is enabled after BIST run (clkch_en bit). 36/54 DS11400 Rev 8 L9301 11 Analog BIST Analog BIST Over current, over/under voltage, open load circuitry is checked through analog BIST selftest implementation controlled by SPI command (CR14 dr_s_chk). The check can be implemented by microcontroller after POR by SPI command or also at run-time depending on the application requirement. Figure 12. Analog BIST self-test 9'' 95()BRY  9''B6(/ 95()BXY  6,/ )DLOXUHVLQWKLVUHJLRQDUHGHWHFWHG DS11400 Rev 8 37/54 53 Clock monitor 12 L9301 Clock monitor For safety reasons the device has two clock signals: main clock and diagnosis clock. The diagnosis clock is a redundant oscillator which has been introduced with the aim to perform a frequency check with the main clock. A dedicated digital block is present to accomplish this task. If a clock signal is running out of range, a status bit is set (clkbad). In case the main clock stops working, a digital internal reset is asserted, until POR or RES clears it. If the main clock is running 25% faster or slower than diagnosis clock, the bit clkbad is set. If the main clock is running 85% slower than diagnosis clock, a digital internal reset is asserted, the device is put to reset state, all drivers are off and no response to any input signal is given, until power off or RES pin assert (RES pin set to '0') to clear it. 5 V ≤ VB < 18 V; -40 °C ≤ Tj ≤ 175 °C unless otherwise specified. Table 27. Clock monitor Parameter Main clock frequency 38/54 Test condition FLL not active DS11400 Rev 8 Min. Typ. Max. Unit 4.5 5 5.5 MHz L9301 13 SPI SPI The SPI interface is used to configure the device, control the output and read the diagnostic and output status registers. Every time a bit in one of the SPI registers is set by the L9301 (for example when an error is detected) it will not be reset until the corresponding registers have been wrote to 0 by SPI. The bit will not be reset if an SPI error occurs during access to register by the µC or while L9301 sends the content of the register as an answer. 13.1 CS, SCK, MOSI 5 V ≤ VB < 18 V; -40 °C ≤ Tj ≤ 175 °C unless otherwise specified. Table 28. CS, SCK, MOSI Pin CS, SCK, MOSI Symbol Parameter Test condition Min. Typ. Max. Unit V_IH Logic input high voltage - 1.75 - VDD+0.3 V V_IL Logic input low voltage - -0.3 - 0.75 V Logic input hysteresis - 100 - 1000 mV Input current - - - 5 µA Pull up resistor Tested at 1.5 V,  R = (3.3-1.5)/Imeasure 50 - 250 kΩ V_Ihys Iin Ri_pu DS11400 Rev 8 39/54 53 SPI 13.2 L9301 MISO Back supply current into supply pin of MISO is not allowed. Back to Back structure: in case of an over-voltage condition at the MISO output, the HS path (Back to Back) is switched off after tOFF_PROT by analog circuitry to avoid back supply current into supply pin of SDO. 5 V ≤ VB < 18 V; -40 °C ≤ Tj ≤ 175 °C unless otherwise specified. Table 29. MISO Pin Symbol Test condition V_OH Logic output high voltage V_OL Logic output low voltage Isource = 2 mA MISO 40/54 Parameter Isink = 2 mA VOV_MISO Over voltage detection threshold at MISO output tOFF_PROT Turn OFF delay for over voltage reverse supply protection - DS11400 Rev 8 Min. Typ. Max. Unit VDD_I/O-0.4 - - V - 0.4 V VDDIO+0.05 - VDDIO+0.2 V 0 - 1.5 µs L9301 SPI 13.3 SPI frame MOSI 31 30 29 28 W/R 15 27 26 25 24 ADD 14 13 12 11 23 22 21 20 RES 10 9 8 7 19 18 16 1 0 DATA[19..13] 6 5 4 3 2 DATA[12..0] W/R 17 CRC[2..0] 1 = Write 0 = Read ADD Address RES Reserved DATA Data CRC CRC: Polynomial is x3+x2+x+1 MISO 31 30 29 28 27 SPIErr[2..0] 15 14 26 25 24 23 22 21 20 CHExcp[5..0] 13 12 11 10 9 19 18 17 16 1 0 DATA[19..13] 8 7 6 5 4 DATA[12..0] SPIErr[2] SPI Short Frame: a less-than-32bit SPI frame was received SPIErr[1] SPI Long Frame: a more-than-32bit SPI frame was received SPIErr[0] SPI CRC Error: SPI CRC checksum error CHExcp[5] gf: bit 6 of General device diagnostic register CHExcp[4] got: bit 4 of General device diagnostic register CHExcp[3] vdduv: bit 3 of General device diagnostic register CHExcp[2] vddov: bit 2 of General device diagnostic register CHExcp[1] vbuv: bit 1 of General device diagnostic register CHExcp[0] vbov: bit 0 of General device diagnostic register DATA Data CRC CRC: Polynomial is x3+x2+x+1 DS11400 Rev 8 3 2 CRC[2..0] 41/54 53 SPI L9301 SPI registers 14 13 12 RESERVED 11 10 9 8 conf4_lshs 7 6 5 4 3 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) [19:12] RESERVED: Reserved [11] conf4_lshs[3] 0 = HS is configured as high side driver during configuration4 1 = HS is configured as low side driver during configuration4 [10] conf4_lshs[2] 0 = HS is configured as high side driver during configuration4 1 = HS is configured as low side driver during configuration4 [9] conf4_lshs[1] 0 = HS is configured as high side driver during configuration4 1 = HS is configured as low side driver during configuration4 [8] conf4_lshs[0] 0 = HS is configured as high side driver during configuration4 1 = HS is configured as low side driver during configuration4 [7] dloss_conf 0 = no auto shut driver when freewheeling diode loss 1 = auto shut driver when freewheeling diode loss [6] cpl_conf 0 = no auto shut driver when charge pump low 1 = auto shut driver when charge pump low [5] vdduv_conf 0 = no auto shut driver when vdduv 1 = auto shut driver when vdduv [4] vddov_conf 0 = no auto shut driver when vddov 1 = auto shut driver when vddov 42/54 DS11400 Rev 8 1 0 output_conf[1:0] 15 vbov_conf 16 vbuv_conf 17 vddov_conf 18 vdduv_conf 19 Device general configuration register cpl_conf CR0(0x00) dloss_conf 13.4 0 (R/W) L9301 SPI [3] vbuv_conf 0 = no auto shut driver when vbuv 1 = auto shut driver when vbuv [2] vbov_conf 0 = no auto shut driver when vbov 1 = auto shut driver when vbov [1:0] output_conf (1) output_conf[1] output_conf[0] Configuration 0 0 1 0 1 2 1 0 3 1 1 4 1. Output_conf bits can only be modified when EN pin is logic 0 12 11 10 9 RESERVED 8 7 6 5 4 3 2 1 0 slew_rate 13 oc_thres 14 oc_restart 15 diagoff_blank_sel 16 dloss_act 17 dis_source 18 dis_diagoff 19 Device configuration register pwm_en CR1-CR12 (0x01-0x0C) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) [19:8] RESERVED: Reserved [7] pwm_en 0 = driver is disabled 1 = driver is enabled available only in LS4-1 and HS4-1 [6] dis_diagoff 0 = enable OFF diagnosis 1 = disable OFF diagnosis [5] dis_source 0 = enable OFF diagnosis pull up current 1 = disable OFF diagnosis pull up current [4] dloss_act 0 = disable the dloss signal diagnosis 1 = enable the dloss signal diagnosis [3] diagoff_blank_sel 0 = long blanking time 1 = short blanking time DS11400 Rev 8 43/54 53 SPI L9301 [2] oc_restart 0 = restart the channel only after clearing the fault bit 1 = restart the channel without clearing the fault bit [1] oc_thres 0 = normal over current threshold 1 = enable double over current threshold [0] slew_rate 0 = slew rate is low 1 = slew rate is high Note: Address 0x01 is for LS1, 0x02 is for LS2… 0x09 is for HS1, 0x0A is for HS2 and so on. pwm_en is only available in 0x01-0x04, 0x09-0x0C. 10 9 8 7 6 5 4 3 2 1 0 cmd3 cmd2 cmd1 RESERVED 11 cmd4 12 cmd5 13 cmd6 14 cmd7 15 cmd8 16 cmd9 17 cmd10 18 cmd11 19 Driver command register cmd12 CR13 (0x0D) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) [19:12] RESERVED: Reserved [11] cmd12 Command HS4 (no effect in Config 1) [10] cmd11 Command HS3 (no effect in Config 1) [9] cmd10 Command HS2 (no effect in Config 1) [8] cmd9 Command HS1 (no effect in Config 1) [7] cmd8 Command OUT8 [6] cmd7 Command OUT7 [5] cmd6 Command OUT6 [4] cmd5 Command OUT5 [3] cmd4 Command OUT4 (in Configuration1 controls DRN/SRC3 DRN/SRC4) [2] cmd3 Command OUT3 (in Configuration1 controls DRN/SRC1 DRN/SRC2) [1] cmd2 Command OUT2 (in Configuration1 controls OUT3/OUT4) [0] cmd1 Command OUT1 (in Configuration1 controls OUT1/OUT2) 44/54 DS11400 Rev 8 L9301 SPI 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 RESERVED 1 0 clkch_en 19 MCU controlled comparator test and clock check register dr_s_chk CR14 (0x0E) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) [19:2] RESERVED: Reserved [1] dr_s_chk 0 = normal 1 = invert hv/lv and OC comparator input used in MCU controlled comparator test [0] clkch_en 0 = disable clock check block 1 = enable clock check block RESERVED 11 10 9 8 7 6 5 4 3 2 1 0 vbov 12 vbuv 13 vddov 14 vdduv 15 got 16 cpl 17 gf 18 RESERVE 19 General device status register clkbad SR0 (0x10) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) [19:9] RESERVED: Reserved [8] clkbad 0 = main clock and diagnosis clock frequency deviation within 25% 1 = main clock and diagnosis clock frequency deviation over 25% [7] RESERVE: Reserve [6] gf 0 = no fault in all the channels 1 = logic OR combination of bit 1/2/3/4/5/6/8 of all the Driver status register [5] cpl 0 = no charge pump low 1 = charge pump low [4] got 0 = no over temperature 1 = logic OR combination of bit 0 of all the Driver status register [3] vdduv 0 = no VDD under voltage 1 = VDD under voltage DS11400 Rev 8 45/54 53 SPI L9301 [2] vddov 0 = no VDD over voltage 1 = VDD over voltage [1] vbuv 0 = no VB under voltage 1 = VB under voltage [0] vbov 0 = no VB over voltage 1 = VB over voltage Note: bit4 and bit6 cannot be directly written '0'. They are only cleared when the relating bits get cleared RESERVED 10 9 8 0 0 0 0 0 0 0 0 0 0 0 0 (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) 7 0 (R) 6 5 4 3 2 1 0 t_sd 11 t_sdl 12 oc 13 dloss 14 shgnd 15 shvb 16 ol 17 cs 18 os 19 Driver status register oc_comp_f SR1-SR12 (0x11-0x1C) 0 0 0 0 0 0 0 (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) [19:10] RESERVED: Reserved [9] oc_comp_f 0 = no comparator self test fail 1 = over current comparator self test fail [8] os: output status 0 = driver status is aligned to the command in on state 1 = driver output is not aligned to the command in on state [7] cs: command status 0 = CR13 or pin IN1-8 put driver to off status 1 = CR13 or pin IN1-8 put driver to on status [6] ol: open load 0 = no open load 1 = open load [5] shvb: short to VB 0 = no short to VB 1 = short to VB available only in SR9-SR12 [4] shgnd: short to GND 0 = no short to GND 1 = short to GND [3] dloss: diode loss 0 = no diode loss 1 = diode loss 46/54 DS11400 Rev 8 L9301 SPI [2] oc: over current 0 = no over current 1 = over current [1] t_sdl 0 = no over temperature 1 = over temperature [0] t_sd 0 = no over temperature occurring 1 = over temperature occurring (live bit) Note: address 0x11 is for LS1, 0x12 is for LS2… 0x19 is for HS1, 0x1A is for HS2 and so on. SR13 (0x1D) 19 18 17 IC version register 16 15 14 13 12 11 10 9 8 7 6 5 4 RESERVE 0 (R) 0 (R) 0 (R) 0 (R) 0 (R) 0 (R) 0 (R) 3 2 1 0 0 (R) 0 (R) silicon version 0 (R) 0 (R) 0 (R) 0 (R) 0 (R) 0 (R) 0 (R) 0 (R) 0 (R) 0 (R) 0 (R) [19:6] RESERVE: Reserve [5:0] silicon version: silicon version (AB=100010) 17 16 15 14 13 12 10 9 8 7 6 5 4 3 2 lbist pass 18 lbist end 19 Bist status register lbist run SR14 (0x1E) 11 0 (R) 0 (R) 0 (R) 0 (R) 0 (R) 0 (R) 0 (R) 0 (R) 0 (R) 0 (R) 0 (R) RESERVE 0 (R) 0 (R) 0 (R) 0 (R) 0 (R) 0 (R) 0 (R) 0 (R) 0 (R) 1 0 [19:3] RESERVE: Reserve [2] lbist run 0 = bist is not currently running 1 = bist is currently running [1] lbist end 0 = bist unfinished yet 1 = bist finished [0] lbist pass 0 = bist is not finished yet or finished with error 1 = bist finished without error DS11400 Rev 8 47/54 53 SPI L9301 13.5 SPI timings Figure 13. SPI timing diagram 1 4 5 3 15 2 6 9 10 MSB OUT 7 8 LSB OUT DATA 13 14 DATA MSB IN LSB IN GAPG0809150846PS Table 30. SPI timing characteristics No Symbol Min Max Units 1 fop Transfer frequency Design Information - 6 MHz 2 tsclk SCLK period Design Information 167 - ns 3 tlead Enable lead time Design Information 750 - ns 4 tlag Enable lag time Design Information 100 - ns 5 tsclkhs SCLK high time Design Information 75 - ns 6 tsclkls SCLK low time Design Information 75 - ns 7 tsus MOSI input setup time Design Information 30 - ns 8 ths MOSI input hold time Design Information 30 - ns 9 ta MISO access time 50 pF load - 100 ns 10 tdis MISO disable time 50 pF load - 100 ns 11 tvs MISO output valid time 50 pF load - 70 ns 12 tho MISO output hold time 50 pF load 10 - ns 13 tr MISO rise time 50 pF load - 50 ns 14 tf MISO fall time 50 pF load - 50 ns 15 tcsn CS negated time Design Information 750 - ns 16 tsh SCLK Hold Time Design Information 100 - ns 48/54 Parameter Conditions DS11400 Rev 8 L9301 14 Package information Package information In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK packages, depending on their level of environmental compliance. ECOPACK specifications, grade definitions and product status are available at: www.st.com. ECOPACK is an ST trademark. PowerSSO-36 (exposed pad) package information Figure 14. PowerSSO-36 (exposed pad) package outline Bottom view ggg M C A-B D D1 ggg M CA-B D G3 G3 E2 E4 G3 D3 e // eee C A2 A ccc C SEATING PLANE A1 b Section A-A C ddd M CD h ș1 h 2x ș2 f f f C A-B D R1 H D2 A N B (see Section B-B) R GAUGE PLANE L2 B L D A S ș1 ș 14.1 L1 index area (0.25D x 0.75E1) G1x2 E1 E3 pin 1 indicator Section B-B E (b) WITH PLATING G2 c c1 2x aaa CD b1 BASE METAL 2x N/2 TIPS bbb C 1 2 3 Top view B A (see Section A-A) N/2 GAPGPS03424 7587131_I_EH DS11400 Rev 8 49/54 53 Package information L9301 Table 31. PowerSSO-36 (exposed pad) package mechanical data Dimensions Ref Inches(1) Millimeters Min. Typ. Max. Min. Typ. Max. Ө 0° - 8° 0° - 8° Ө1 5° - 10° 5° - 10° Ө2 0° - - 0° - - A 2.15 - 2.45 0.0846 - 0.0965 A1 0.0 - 0.1 0.0 - 0.0039 A2 2.15 - 2.35 0.0846 - 0.0925 b 0.18 - 0.32 0.0071 - 0.0126 b1 0.13 0.25 0.3 0.0051 0.0098 0.0118 c 0.23 - 0.32 0.0091 - 0.0126 c1 0.2 0.2 0.3 0.0079 0.0079 0.0118 (2) 10.30 BSC D 0.4055 BSC D1 VARIATION D2 - 3.65 - - 0.1437 - D3 - 4.3 - - 0.1693 - e 0.50 BSC 0.0197 BSC E 10.30 BSC 0.4055 BSC 7.50 BSC 0.2953 BSC (2) E1 E2 50/54 VARIATION E3 - 2.3 - - 0.0906 - E4 - 2.9 - - 0.1142 - G1 - 1.2 - - 0.0472 - G2 - 1 - - 0.0394 - G3 - 0.8 - - 0.0315 - h 0.3 - 0.4 0.0118 - 0.0157 L 0.55 0.7 0.85 0.0217 - 0.0335 L1 1.40 REF 0.0551 REF L2 0.25 BSC 0.0098 BSC N 36 1.4173 R 0.3 - - 0.0118 - - R1 0.2 - - 0.0079 - - S 0.25 - - 0.0098 - - DS11400 Rev 8 L9301 Package information Table 31. PowerSSO-36 (exposed pad) package mechanical data (continued) Dimensions Ref Inches(1) Millimeters Min. Typ. Max. Min. Typ. Max. Tolerance of form and position aaa 0.2 0.0079 bbb 0.2 0.0079 ccc 0.1 0.0039 ddd 0.2 0.0079 eee 0.1 0.0039 ffff 0.2 0.0079 ggg 0.15 0.0059 VARIATIONS Option A D1 6.5 - 7.1 0.2559 - 0.2795 E2 4.1 - 4.7 0.1614 - 0.1850 D1 4.9 - 5.5 0.1929 - 0.2165 E2 4.1 - 4.7 0.1614 - 0.1850 D1 6.9 - 7.5 0.2717 - 0.2953 E2 4.3 - 5.2 0.1693 - 0.2047 Option B Option C 1. Values in inches are converted from mm and rounded to 4 decimal digits. 2. Dimensions D and E1 do not include mold flash or protrusions. Allowable mold flash or protrusions is ‘0.25 mm’ per side D and ‘0.15 mm’ per side E1. D and E1 are maximum plastic body size dimensions including mold mismatch. DS11400 Rev 8 51/54 53 Package information 14.2 L9301 PowerSSO-36 (exp. pad) marking information Figure 15. PowerSSO-36 (exp. pad) marking information Marking area Last two digits ES: Engineering sample : Commercial sample PowerSSO-36 TOP VIEW (not in scale) Note: GAPG2904151300PS_ES Engineering Samples: these samples are clearly identified by the last two digits ‘ES’ in the marking of each unit. These samples are intended to be used for electrical compatibility evaluation only; usage for any other purpose may be agreed only upon written authorization by ST. ST is not liable for any customer usage in production and/or in reliability qualification trials. Commercial Samples: Fully qualified parts from ST standard production with no usage restrictions. 52/54 DS11400 Rev 8 L9301 15 Revision history Revision history Table 32. Document revision history Date Revision Changes 30-Nov-2015 1 Initial release. 14-Dec-2015 2 Corrected: – Section 9.3: Driver diagnostic on page 27; – Section 9.4: Combined diagnosis (configuration 1, 2 & 3) on page 34; – Section 13: SPI on page 39; – CR0(0x00) on page 42 ([2] and [1:0]); – SR13 (0x1D) on page 47. 21-Jan-2016 3 Updated Section 9.3.4: Charge Pump (CP) on page 28. 04-Mar-2016 4 Updated Section 3.4: Thermal data on page 10. 11-Apr-2016 5 Modified in cover page: Title and Features bullet. Updated Table 8: VDD on page 11. 18-Apr-2016 6 ST Restricted watermark removal for ST web site publication. 14-Oct-2019 7 Added: – Section 11: Analog BIST. Minor text changes. 17-Dec-2020 8 Updated Table 10: VDDIO. DS11400 Rev 8 53/54 53 L9301 IMPORTANT NOTICE – PLEASE READ CAREFULLY STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on ST products before placing orders. ST products are sold pursuant to ST’s terms and conditions of sale in place at the time of order acknowledgement. Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or the design of Purchasers’ products. No license, express or implied, to any intellectual property right is granted by ST herein. Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product. ST and the ST logo are trademarks of ST. For additional information about ST trademarks, please refer to www.st.com/trademarks. All other product or service names are the property of their respective owners. Information in this document supersedes and replaces information previously supplied in any prior versions of this document. © 2020 STMicroelectronics – All rights reserved 54/54 DS11400 Rev 8