L9374

L9374 Four channel valve driver Data Brief Features ■ ■ ■ ■ ■ ■ ■ ■ Four low-side output drivers with protection diagnostic – 2 PWM controlled channels (0.2Ω typ) – 2 current controlled channels with 6% accuracy (0.3Ω typ) All outputs with 35V Zener clamp Programmable channel timer Clock monitor Integrated recirculation diodes Serial Peripheral Interface with 16bits, up to 5MHz with diagnosis Battery compatible supply voltage Detailed Load diagnosis – Over load protection – Open Load – Under-current – Under Voltage – Temperature Warning and Shutdown – Power or Signal GND loss – Freewheeling diode loss – Silent valve driver test PowerSO-36 PowerSSO-36 are stored in the PWM and in the Counter Configuration Register respectively. The PWM Controller translates the programmed digital duty cycle value in a PWM signal which controls the output. For the current controlled channels the target current value is programmed. It is also possible to program two different target currents. The target current is compared with the real load current. The output duty cycle is then calculated with an Arithmetic Logic Unit. As base for the calculation a load model is used respecting the resistivity of the load, the supply voltage as well as the internal recirculation path. To check the plausibility of the current controller all measured and calculated values are available and accessible via SPI. All channels are equipped with a load Diagnostic. This allows to detect an open load in off condition as well as an under current in on condition. The power stage is protected against over current and over temperature. A weak connection in power ground or in the recirculation path is monitored. All monitored functions can be read out in a serial diagnostic protocol dedicated for each channel via SPI.. Table 1. Order code L9374 L9374XP Description The L9374 is a four channel low side driver with integrated recirculation diodes. The switching of the channels is programmable via a SPI (Serial Peripheral Interface). The main time base is given by an external clock via CLKin. The Clock Unit monitors this external clock and provides the system clock for all timings. A Synchronization Unit is used to monitor the SPI communication and provides a sync signal for the channel activation. The Output Duty Cycle for each channel can be programmed individually and will be activated by the Set Point Unit. Is possible to program two output Duty Cycles per channel with a block of 16 SPI commands as well as an individual Duration Time for each channel actuation. Both information Device summary Package PowerSO-36 (slug down) PowerSSO-36 (exp. pad) Packing Tube Tube July 2007 Rev 2 1/10 www.st.com 10 For further information contact your local STMicroelectronics sales office. 1 Power-on Reset Current Detection Q3 DAC PWM Unit PGND3/4 Configure Register PWM controlled valve PWM controlled valve Current regulated valve Current regulated valve Set Point Unit Under Current PWM Controller Open Load Q1 CLKIN Clock Unit Diagnose Register CLK/SYNC/SPI/Test-Modi / Standard CLK/SYNC/SPI/Test-Modi / Standard Error Detection Error Detection PGND1/2 D2/D4 EN Synchronization Unit Channel 4 Q4 PGND3/4 SPICLK MOSI MISO SPICS SPI Channel 2 Q2 PGND1/2 Current regulated valve Channel 1 PWM controlled valve Signal / Power GND loss Communication SGND Count Configuration Register PWM Configuration Register 2/10 Block diagram Figure 1. Ignition switch Vbatt Reverse polarity protection Channel 3 Under Current Open Load D1/D3 Safety switch Vs Block diagram Block diagram Supply Voltage L9374 L9374 Pins description 2 Pins description Figure 2. PowerSSO36 pins connection (top view) NC Q3 Q3 D1/D3 D1/D3 Q1 Q1 PGND1 PGND12 PGND2 Q2 Q2 NC D4/D2 D4/D2 Q4 Q4 NC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 D06AT546A 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 PGND3 NC NC NC NC SGND EN SPICS MISO MOSI SPICLK CLKIN VS NC NC NC NC PGND4 Figure 3. PowerSO36 pins connection (top view) PGND Q3 Q3 D1/D3 D1/D3 Q1 Q1 PGND1 PGND12 PGND2 Q2 Q2 NC D4/D2 D4/D2 Q4 Q4 PGND 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 AC00419 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 PGND3 NC NC NC NC SGND EN SPICS MISO MOSI SPICLK CLKIN VS NC NC NC NC PGND4 3/10 Pins description Table 2. Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 L9374 Pins description PwSSO36 N.C. Q3 Q3 D1/D3 D1/D3 Q1 Q1 PGND1 PGND12 PGND2 Q2 Q2 N.C. D4/D2 D4/D2 Q4 Q4 N.C. PGND4 N.C. N.C. N.C. N.C. VS CLKIN SPICLK MOSI MISO SPICS EN SGND N.C. N.C. N.C. N.C. PGND3 PwSO36 PGND Q3 Q3 D1/D3 D1/D3 Q1 Q1 PGND1 PGND12 PGND2 Q2 Q2 N.C. D4/D2 D4/D2 Q4 Q4 PGND PGND4 N.C. N.C. N.C. N.C. VS CLKIN SPICLK MOSI MISO SPICS EN SGND N.C. N.C. N.C. N.C. PGND3 Description Not connected/Power ground Output. Output. Free wheeling diode. Free wheeling diode. Output. Output. Power ground of the output driver 1& 2. Power ground of the output driver 1& 2. Power ground of the output driver 1& 2. Output. Output. Not connected. Free wheeling diode. Free wheeling diode. Output. Output. Not connected/Power ground Power ground of the output driver 4. Not connected. Not connected. Not connected. Not connected. Supply pin Input for precise clock. SPI communication CLocK. Master Out Slave In for SPI communication. Master In Slave Out for SPI communication. SPI Chip Select. Enable Signal ground. Not connected. Not connected. Not connected. Not connected. Power ground of the output driver 3. 4/10 L9374 Absolute maximum ratings 3 Absolute maximum ratings Table 3. Symbol Vs VDx VQx VEN VSPICLK VSPICS VMOSI VMISO VCLKIN IQ1; 2 IQ3; 4 IEN_CL ISPICLK_ CL Absolute maximum ratings Parameter Supply voltage Freewheeling diode voltage Output voltage Enable voltage SPI clock voltage SPI chip select voltage SPI MOSI voltage SPI MISO voltage SPI clock input voltage Output current at reversal voltage -2 A Min -0.3 -0.3 -0.3 Max 38 35 35 Unit V V V -0.3 6 V -4 A ISPICS_C Input clamping currents (static) Input clamping currents (dynamic) L IMOSI_CL ICLKIN_C L -3 -10 +3 +10 mA Definition: Current from outside into the L9374-> " + " Current from L9374 towards external components -> " - " Warning: Transients beyond this limit will cause currents into ESD structures which must be limited externally to ±10 mA (maximum energy to be dissipated: 2 mJ). 5/10 ESD susceptibility L9374 4 4.1 ESD susceptibility HBM ESD susceptibility HBM according to EIA/JESD 22-A 114B otherwise defined. Table 4. HBM Pin All Pins Output pins DX; QX; PGND12, PGND3, PGND4, LGND and GND are connected together. Condition Min ±2 ±4 Max Unit kV kV 4.2 MM ESD susceptibility according to EIA/JESD22-A115-A Table 5. MM Condition All pins Min ± 250 Max Unit V Parameter Machine Model (MM) 6/10 L9374 Package informations 5 Package informations In order to meet environmental requirements, ST offers this device in ECOPACK® package. This package has a Lead-free second level interconnect. The category of second level Interconnect is marked on the package and on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. ECOPACK is an ST trademark. ECOPACK specifications are available at: www.st.com. Figure 4. PowerSO-36 (slug down) mechanical data and package dimensions DIM. A a1 a2 a3 b c D D1 E E1 E2 E3 e e3 G H h L N s 0.8 0 15.50 5.80 0.65 11.05 0.10 15.90 0.6102 1.10 1.10 0.0315 10˚ (max) 8˚ (max) 0 0.22 0.23 15.80 9.40 13.90 10.90 0.10 mm MIN. TYP. MAX. 3.60 0.30 3.30 0.10 0.38 0.32 9.80 14.5 2.90 6.20 0.2283 0.0256 0.4350 0.0039 0.6260 0.0433 0.0433 0.0087 0.0091 0.3701 0.5472 0.0039 MIN. inch TYP. MAX. 0.1417 0.0118 0.1299 0.0039 0.0150 0.0126 0.6299 0.3858 0.5709 0.4370 0.1142 0.2441 OUTLINE AND MECHANICAL DATA 16.00 0.6220 11.10 0.4291 PowerSO-36 Note: “D and E1” do not include mold flash or protusions. - Mold flash or protusions shall not exceed 0.15mm (0.006”) - Critical dimensions are "a3", "E" and "G". 0096119 C 7/10 Package informations Figure 5. L9374 PowerSSO-36 (exposed pad) mechanical data and package dimensions DIM. A A2 a1 b c D (1) E (1) e e3 F G G1 H h L M N O Q S T U X Y MIN. 2.15 2.15 0 0.18 0.23 10.10 7.4 0.50 8.50 2.3 0.10 0.06 10.50 0.40 0.85 4.3 10˚ (max) 1.2 0.8 2.9 3.65 1.0 4.10 6.50 4.70 7.10 0.161 0.256 0.047 0.031 0.114 0.144 0.039 0.185 0.279 mm TYP. MAX. 2.47 2.40 0.075 0.36 0.32 10.50 7.6 MIN. 0.084 0.084 0 0.007 0.009 0.398 0.291 0.020 0.035 0.090 0.004 0.002 0.413 0.016 0.033 0.169 inch TYP. MAX. 0.097 0.094 0.003 0.014 0.012 0.413 0.299 OUTLINE AND MECHANICAL DATA 10.10 0.55 0.398 0.022 (1) “D and E” do not include mold flash or protusions. Mold flash or protusions shall not exceed 0.15mm (0.006”) (2) No intrusion allowed inwards the leads. (3) Flash or bleeds on exposed die pad shall not exceed 0.4 mm per side PowerSSO-36 (exposed pad) 7587131 A 8/10 L9374 Revision history 6 Revision history Table 6. Date 4-Jun-2007 31-Jul-2007 Document revision history Revision 1 2 Initial release. Updated Section 1: Block diagram , Section 2: Pins description and Section 4: ESD susceptibility. Changes 9/10 L9374 Please Read Carefully: Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any time, without notice. All ST products are sold pursuant to ST’s terms and conditions of sale. Purchasers are solely responsible for the choice, selection and use of the ST products and services described herein, and ST assumes no liability whatsoever relating to the choice, selection or use of the ST products and services described herein. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted under this document. 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