L9678P
L9678P-S
Automotive user configurable airbag and battery cut-off IC
Datasheet - production data
– High and low side driver FET tests
– Safing FET test
User customizable safing logic
Two channel PSI-5 remote sensor interface
(asynchronous mode), [only for L9678P-S
version]
Four channel hall-effect, resistive or switch
sensor interface
GAPGPS00313
LQFP64 (10x10x1.4mm)
ISO9141 transceiver
Dual channel configurable high-side/low-side
LED driver
Features
Watchdog timer
AEC-Q100 qualified
Energy reserve voltage power supply
– High frequency boost regulator, 1.882 MHz
– Output voltage user selectable, 23 V or
33 V ±5%
Two integrated oscillators: 7.5/16 MHz
Temperature sensor
32 bit SPI communications
Minimum operating voltage = 6 V
User configurable linear power supplies
– 5.0 V and 7.2 V ±4% output voltages
– External pass transistor
Operating temperature, -40 °C to 95 °C
Fully integrated 3.3 V ±4% linear regulator
Applications
Battery voltage monitor and shutdown control
with wake-up control
Low end airbag systems
System voltage diagnostics with integrated
ADC
Pyro Fuse/Pyroswitch management
Packaging - 64 pin
Cut-off battery systems
Crossover switch
– Crossover performance, max 3 Ω, 600 mA
max.
Squib/pyroswitch deployment drivers
– 4 channel HSD/LSD
– 25 V maximum deployment voltage
– 1.2 A @ 2 ms and 1.75 A @ 0.5/0.7 ms
deployment profiles
– Integrated safing FET linear regulator,
20 V/25 V nominal
– Current monitoring
– Rmeasure, STB, STG and leakage
diagnostics
November 2021
This is information on a product in full production.
DS11626 Rev 5
1/210
www.st.com
Contents
L9678P, L9678P-S
Contents
1
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
2
Absolute and operative maximum ratings . . . . . . . . . . . . . . . . . . . . . . 13
2.1
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
2.2
Operative maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
2.3
Pin-out description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
3
Overview and block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
4
Start-up power control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
4.1
Power supply overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
4.2
Power mode control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
4.3
4.4
5
4.2.1
Power_off mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
4.2.2
Sleep mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
4.2.3
Active mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
4.2.4
Passive mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
4.2.5
Power-up and power-down sequence . . . . . . . . . . . . . . . . . . . . . . . . . . 24
4.2.6
Operating states . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Configurable system power control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
4.3.1
ERBOOST switching regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
4.3.2
Energy reserve capacitor charging circuit . . . . . . . . . . . . . . . . . . . . . . . 30
4.3.3
ER switch and COVRACT pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
4.3.4
VDD5 linear regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
4.3.5
VDD3V3 linear regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
4.3.6
VSUP linear regulator (optional) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
4.3.7
VSF linear regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Reset functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
SPI interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
5.1
Global SPI register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Read/write register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
2/210
5.1.1
Fault status register (FLTSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
5.1.2
System configuration register (SYS_CFG) . . . . . . . . . . . . . . . . . . . . . . 55
5.1.3
System control register (SYS_CTL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
DS11626 Rev 5
L9678P, L9678P-S
Contents
5.1.4
SPI Sleep command register (SPI_SLEEP) . . . . . . . . . . . . . . . . . . . . . 58
5.1.5
System status register (SYS_STATE) . . . . . . . . . . . . . . . . . . . . . . . . . . 59
5.1.6
Power state register (POWER_STATE) . . . . . . . . . . . . . . . . . . . . . . . . . 60
5.1.7
Deployment configuration registers (DCR_x) . . . . . . . . . . . . . . . . . . . . 63
5.1.8
Deployment command (DEPCOM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
5.1.9
Deployment configuration registers (DSR_x) . . . . . . . . . . . . . . . . . . . . 66
5.1.10
Deployment current monitor status registers (DCMTSxy) . . . . . . . . . . . 67
5.1.11
Deploy enable register (SPIDEPEN) . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
5.1.12
Squib/pyroswitch ground loss register (LP_GNDLOSS) . . . . . . . . . . . . 68
5.1.13
Device version register (VERSION_ID) . . . . . . . . . . . . . . . . . . . . . . . . . 69
5.1.14
Watchdog retry configuration register (WD_RETRY_CONF) . . . . . . . . 69
5.1.15
Watchdog timer configuration register (WDTCR) . . . . . . . . . . . . . . . . . 70
5.1.16
WD1 timer control register (WD1T) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
5.1.17
WD1 state register (WDSTATE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
5.1.18
Clock configuration register (CLK_CONF) . . . . . . . . . . . . . . . . . . . . . . . 72
5.1.19
Scrap state entry command register (SCRAP_STATE) . . . . . . . . . . . . . 73
5.1.20
Safing state entry command register (SAFING_STATE) . . . . . . . . . . . . 73
5.1.21
WD1 test command register (WD1_TEST) . . . . . . . . . . . . . . . . . . . . . . 74
5.1.22
System diagnostic register (SYSDIAGREQ) . . . . . . . . . . . . . . . . . . . . . 74
5.1.23
Diagnostic result register for deployment loops (LPDIAGSTAT) . . . . . . 76
5.1.24
Loops diagnostic configuration command register for low level diagnostic
(LPDIAGREQ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
5.1.25
Loops diagnostic configuration command register for high level diagnostic
(LPDIAGREQ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
5.1.26
DC sensor diagnostic configuration command register (SWCTRL) . . . . 83
5.1.27
ADC request and data registers (DIAGCTRL_x) . . . . . . . . . . . . . . . . . . 84
5.1.28
GPO configuration register (GPOCR) . . . . . . . . . . . . . . . . . . . . . . . . . . 87
5.1.29
GPO configuration register (GPOCTRLx) . . . . . . . . . . . . . . . . . . . . . . . 88
5.1.30
GPO fault status register (GPOFLTSR) . . . . . . . . . . . . . . . . . . . . . . . . . 89
5.1.31
ISO fault status register (ISOFLTSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
5.1.32
Remote sensor configuration register (RSCRx) . . . . . . . . . . . . . . . . . . 91
5.1.33
Remote sensor control register (RSCTRL) . . . . . . . . . . . . . . . . . . . . . . 92
5.1.34
Remote sensor data/fault registers w/o fault (RSDRx) . . . . . . . . . . . . . 93
5.1.35
Safing algorithm configuration register (SAF_ALGO_CONF) . . . . . . . . 97
5.1.36
Arming signals register (ARM_STATE) . . . . . . . . . . . . . . . . . . . . . . . . . 98
5.1.37
ARMx assignment registers (LOOP_MATRIX_ARMx) . . . . . . . . . . . . . 99
5.1.38
ARMx pulse stretch registers (AEPSTS_ARMx) . . . . . . . . . . . . . . . . . 100
5.1.39
Safing records enable register (SAF_ENABLE) . . . . . . . . . . . . . . . . . 101
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Contents
6
L9678P, L9678P-S
5.1.41
Safing records request target registers (SAF_REQ_TARGET_x) . . . . 103
5.1.42
Safing records response mask registers (SAF_RESP_MASK_x) . . . . 104
5.1.43
Safing records response target registers (SAF_RESP_TARGET_x) . . 105
5.1.44
Safing records data mask registers (SAF_DATA_MASK_x) . . . . . . . . 106
5.1.45
Safing records threshold registers (SAF_THRESHOLD_x) . . . . . . . . . 107
5.1.46
Safing control registers (SAF_CONTROL_x) . . . . . . . . . . . . . . . . . . . 108
5.1.47
Safing record compare complete register (SAF_CC) . . . . . . . . . . . . . 111
Control logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .112
6.1.1
Deployment current selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
6.1.2
Deploy command expiration timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
6.1.3
Deployment control flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
6.1.4
Deployment success . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
6.2
Energy reserve - deployment voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . .116
6.3
Deployment ground return . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .116
6.4
Deployment driver protections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .116
6.5
6.4.1
Delayed low-side deactivation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
6.4.2
Low-side voltage clamp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
6.4.3
Short to battery . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
6.4.4
Short to ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
6.4.5
Intermittent open squib/pyroswitch . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
Diagnostics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .117
6.5.1
Low level diagnostic approach . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
6.5.2
High level diagnostic approach . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
Remote sensor interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
7.1
7.2
4/210
Safing records request mask registers (SAF_REQ_MASK_x) . . . . . . 102
Deployment drivers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
6.1
7
5.1.40
PSI-5 protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
7.1.1
Functional description - remote sensor modes . . . . . . . . . . . . . . . . . . 128
7.1.2
RSU data fields and CRC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
7.1.3
Detailed description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
Remote sensor interface fault protection . . . . . . . . . . . . . . . . . . . . . . . . 132
7.2.1
Short to ground, current limit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132
7.2.2
Short to battery . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132
7.2.3
Cross link . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132
7.2.4
Leakage to battery, open condition . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
DS11626 Rev 5
L9678P, L9678P-S
8
Contents
7.2.5
Leakage to ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
7.2.6
Thermal shutdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
Watchdog timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134
8.1
Temporal watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134
8.1.1
Watchdog timer configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136
8.1.2
Watchdog timer operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136
8.2
Watchdog reset assertion timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137
8.3
Watchdog timer disable input (WDT/TM) . . . . . . . . . . . . . . . . . . . . . . . . 137
9
DC sensor interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138
10
Safing logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141
10.1
Safing logic overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141
10.2
SPI sensor data decoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142
10.3
In-frame and out-of-frame responses . . . . . . . . . . . . . . . . . . . . . . . . . . . 149
10.4
Safing state machine operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150
10.4.1
Simple threshold comparison operation . . . . . . . . . . . . . . . . . . . . . . . 150
10.5
Safing engine output logic (ARMxINT) . . . . . . . . . . . . . . . . . . . . . . . . . . 151
10.6
Arming pulse stretch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154
10.7
Additional communication line . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154
11
General purpose output (GPO) drivers . . . . . . . . . . . . . . . . . . . . . . . . 156
12
ISO9141 transceiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159
13
System voltage diagnostics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160
13.1
Analog to digital algorithmic converter . . . . . . . . . . . . . . . . . . . . . . . . . . 164
14
Temperature sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166
15
Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167
16
15.1
Application circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167
15.2
BOM (Bill Of Materials) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170
16.1
Configuration and control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170
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Contents
L9678P, L9678P-S
16.2
Internal analog reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172
16.3
Internal regulators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173
16.4
Oscillators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173
16.5
Watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174
16.6
Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174
16.7
SPI interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175
16.8
ER boost . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177
16.9
ER charge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179
16.10 ER switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179
16.11 COVRACT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180
16.12 VDD5 regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180
16.13 VDD3V3 regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182
16.14 VSUP regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183
16.15 VSF regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184
16.16 Deployment drivers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185
16.17 Squib/pyroswitch diagnostic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188
16.17.1 Squib/pyroswitch resistance measurement . . . . . . . . . . . . . . . . . . . . . 188
16.17.2 Squib/pyroswitch leakage test (VRCM) . . . . . . . . . . . . . . . . . . . . . . . . 189
16.17.3 High/low side FET test . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190
16.17.4 Deployment timer test . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191
16.18 Remote sensor interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192
16.19 DC sensor interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194
16.20 Safing engine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195
16.21 General purpose output drivers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197
16.22 ISO9141 interface (K-LINE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199
16.22.1 Analog to digital converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201
16.23 Voltage diagnostics (analog Mux) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202
16.24 Temperature sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202
17
Quality information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203
17.1
18
Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204
18.1
6/210
OTP trim bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203
LQFP64 (10x10x1.4 mm) package information . . . . . . . . . . . . . . . . . . . 204
DS11626 Rev 5
L9678P, L9678P-S
18.2
Contents
LQFP64 (10x10x1.4) marking information . . . . . . . . . . . . . . . . . . . . . . . 206
19
Errata sheet . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207
20
Order codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 208
21
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209
DS11626 Rev 5
7/210
7
List of tables
L9678P, L9678P-S
List of tables
Table 1.
Table 2.
Table 3.
Table 4.
Table 5.
Table 6.
Table 7.
Table 8.
Table 9.
Table 10.
Table 11.
Table 12.
Table 13.
Table 14.
Table 15.
Table 16.
Table 17.
Table 18.
Table 19.
Table 20.
Table 21.
Table 22.
Table 23.
Table 24.
Table 25.
Table 26.
Table 27.
Table 28.
Table 29.
Table 30.
Table 31.
Table 32.
Table 33.
Table 34.
Table 35.
Table 36.
Table 37.
Table 38.
Table 39.
Table 40.
Table 41.
Table 42.
Table 43.
Table 44.
Table 45.
Table 46.
Table 47.
Table 48.
8/210
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Operative maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Functions disabling by state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
SPI register R/W . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Global SPI register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Global status word (GSW) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Short between loops diagnostics decoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
Watchdog timer status description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135
Records results comparison against two threshold . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149
Diagnostics control register (DIAGCTRLx) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161
Diagnostics divider ratios . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163
Bill Of Materials . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168
Configuration and control DC specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170
Configuration and control AC specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172
Open ground detection DC specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172
Open ground detection AC specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172
Internal analog reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172
Internal regulators DC specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173
Internal regulators AC specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173
Oscillators AC specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173
Temporal watchdog timer AC specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174
Reset DC specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174
Reset AC specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174
SPI DC specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175
SPI AC specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176
ER Boost converter DC specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177
ER boost converter AC specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178
ER boost converter external components (Design Info) . . . . . . . . . . . . . . . . . . . . . . . . . . 178
ER current generator DC specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179
ER current generator AC specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179
ER switch DC specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179
ER switch AC specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179
COVRACT DC Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180
COVRACT AC specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180
VDD5 regulator DC specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180
VDD5 regulator AC specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181
VDD5 regulator external components (Design Info) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181
VDD3V3 regulator DC specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182
VDD3V3 regulator AC specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182
VDD3V3 regulator external components (design info) . . . . . . . . . . . . . . . . . . . . . . . . . . . 182
VSUP regulator DC specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183
VSUP AC specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183
VSUP regulator external components (Design Info) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183
VSF regulator DC specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184
VSF regulator AC specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184
Deployment drivers - DC specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185
Deployment drivers - AC specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187
Deployment drivers diagnostics (Squib/pyroswitch resistance) . . . . . . . . . . . . . . . . . . . . 188
DS11626 Rev 5
L9678P, L9678P-S
Table 49.
Table 50.
Table 51.
Table 52.
Table 53.
Table 54.
Table 55.
Table 56.
Table 57.
Table 58.
Table 59.
Table 60.
Table 61.
Table 62.
Table 63.
Table 64.
Table 65.
Table 66.
Table 67.
List of tables
Squib/pyroswitch leakage test (VRCM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189
High/low side FET test . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190
Deployment timer test . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191
Remote sensor I/F DC parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192
PSI-5 remote sensor transceiver - AC specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193
DC sensor interface specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194
Arming interface - DC specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195
Arming interface - AC specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196
GPO interface DC specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197
GPO Driver Interface - AC specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198
ISO9141 interface DC specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199
ISO9141 interface transceiver AC specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200
Analog to digital converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201
Voltage diagnostics (Analog MUX) DC specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . 202
Temperature sensor specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202
LQFP64 (10x10x1.4 mm) package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205
Errata sheet . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207
Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 208
Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209
DS11626 Rev 5
9/210
9
List of figures
L9678P, L9678P-S
List of figures
Figure 1.
Figure 2.
Figure 3.
Figure 4.
Figure 5.
Figure 6.
Figure 7.
Figure 8.
Figure 9.
Figure 10.
Figure 11.
Figure 12.
Figure 13.
Figure 14.
Figure 15.
Figure 16.
Figure 17.
Figure 18.
Figure 19.
Figure 20.
Figure 21.
Figure 22.
Figure 23.
Figure 24.
Figure 25.
Figure 26.
Figure 27.
Figure 28.
Figure 29.
Figure 30.
Figure 31.
Figure 32.
Figure 33.
Figure 34.
Figure 35.
Figure 36.
Figure 37.
Figure 38.
Figure 39.
Figure 40.
Figure 41.
Figure 42.
Figure 43.
Figure 44.
Figure 45.
Figure 46.
Figure 47.
Figure 48.
10/210
Pin-out description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Functional block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Power control state flow diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Wake-up input signal behaviour . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Normal power-up sequence - WAKEUP controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Normal power-up sequence - VIN controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Normal power down sequence - WAKEUP and SPI controlled . . . . . . . . . . . . . . . . . . . . . 26
Normal power down sequence - VIN controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
System operating state diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
ERBOOST block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
ERBOOST control behaviour . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
ER cap charging circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
ER switch control behaviour . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
VDD5 control behavior . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
VDD3V3 control behaviour . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
VSUP control behavior . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
VSF control logic. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Internal voltage errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Reset control diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Deployment driver control blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
Deployment driver control logic - Enable signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
Deployment driver control logic - Turn-on signals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
Deployment driver block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
Global SPI deployment enable state diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
Deployment loop diagnostics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
SRx pull-down enable logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
Deployment timer diagnostic sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
High level loop diagnostic flow1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124
High level loop diagnostic flow2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
Remote sensor interface logic blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
Remote sensor interface block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
PSI-5 remote sensor protocol (10-bit, 1-bit parity) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128
Manchester bit encoding. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128
Manchester decoder state diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130
Remote sensor current sensing auto adjust . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131
Watchdog state diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134
Watchdog timer refresh diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137
Switch sensor interface block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138
Top level safing engine flow chart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141
Safing engine - 16-bit message decoding flow chart . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142
Safing engine - 32-bit message decoding flow chart . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143
Safing engine - validate data flow chart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144
Safing engine - combine function flow chart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145
Safing engine threshold comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146
Safing engine - compare complete . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147
In-frame example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150
Out of frame example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150
Safing Engine Arming flow diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152
DS11626 Rev 5
L9678P, L9678P-S
Figure 49.
Figure 50.
Figure 51.
Figure 52.
Figure 53.
Figure 54.
Figure 55.
Figure 56.
Figure 57.
Figure 58.
Figure 59.
Figure 60.
Figure 61.
Figure 62.
List of figures
Safing engine diagnostic logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153
ARM output control logic. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153
Pulse stretch timer example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154
Scrap ACL state diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155
Disposal PWM signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155
GPO driver block diagram - LS configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156
GPO driver block diagram - HS configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157
ISO9141 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159
ADC conversion time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165
Airbag application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167
SPI timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176
Deployment drivers diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187
LQFP64 (10x10x1.4 mm) package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204
LQFP64 (10x10x1.4) marking information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206
DS11626 Rev 5
11/210
11
Description
1
L9678P, L9678P-S
Description
The L9678P IC is a system chip solution targeted for emerging market applications. Base
system designs can be completed with the L9678P, SPC560Px microcontroller and an onboard acceleration sensor or PSI5 sensor.
Energy reserve voltage is derived through a cost effective high frequency boost regulator.
High frequency operation allows the user to pick up low value and cheap inductance. The
voltage is programmable to 23 V or 33 V nominal.
Battery voltage is sensed through the VBATMON pin providing start-up and shutdown
control for the system. Once battery voltage drops below the minimum operating voltage,
the device enables the integrated crossover switch to permit orderly shutdown.
L9678P offers two linear regulators (5 V with external pass transistor and fully integrated
3.3 V). User can use one of these regulators to supply µC. Input/output pins are compatible
with both ranges by dedicated supply pin VDDQ. External pass transistor gives the flexibility
to easily address different current loads in case of different micro-controllers.
One optional 7.2 V linear regulator with external pass transistor can be used to supply
remote sensor interface.
External acceleration data is received through the PSI-5 remote sensor interface. Both
channels have independent decoders. Sensor data and diagnostics are available via SPI.
The safing logic monitors inertial sensors (remote sensors via PSI-5 or on-board sensors via
SPI) to determine if a crash event is in progress, thereby enabling deployment to occur.
Parameters for sensor configuration and thresholds are user programmable.
Squib/pyroswitch/pyroswitch deployment uses four independent high and low side drivers,
capable of deploying at 25 V max. Diagnostic data control is provided through the SPI
interface.
The Hall-effect, resistive or switch sensor interface can be used to determine the state of
external switch devices, such as buckle switches, seat track position sensors, weight
sensors, deactivation switches.
The integrated clock module provides a fixed clock signal for the microcontroller. The clock
module provides the user the option of deleting the commonly used resonator or crystal.
12/210
DS11626 Rev 5
L9678P, L9678P-S
Absolute and operative maximum ratings
2
Absolute and operative maximum ratings
2.1
Absolute maximum ratings
Warning:
This part may be irreparably damaged if taken outside the
specified absolute maximum ratings. Operation above the
absolute maximum ratings may also cause a decrease in
reliability.
Table 1. Absolute maximum ratings
Pin #
Pin name
1
RESET
2
Pin function
Min.
Max.
Unit
Reset output
-0.3
VDDQ+0.3 6.5
V
SPI_MISO
SPI interface data out / Safing sensor data in
-0.3
VDDQ+0.3 6.5
V
3
SPI_MOSI
SPI interface data in
-0.3
VDDQ+0.3 6.5
V
4
SPI_SCK
SPI interface clock
-0.3
VDDQ+0.3 6.5
V
5
SPI_CS
SPI interface chip select
-0.3
VDDQ+0.3 6.5
V
6
WDT/TM
Watchdog disable (Not for application)
-0.3
20
V
7
VDD3V3
3.3 V regulator output
-0.3
4.6
V
-
-
-
Not connected
(1)
8
NC
9
CVDD
Internal 3.3 V regulator output
-0.3
4.6
V
10
GNDD
Digital ground
-0.3
0.3
V
11
SR0
Squib/pyroswitch 0 low-side pin
-0.3
40
V
12
SF0
Squib/pyroswitch 0 high-side pin
-1.0
40
V
13
SG01
Squib/pyroswitch 0 & 1 deployment ground pin
-0.3
0.3
V
14
SS01
Squib/pyroswitch 0 & 1 deployment supply pin
-0.3
40
V
15
SF1
Squib/pyroswitch 1 high-side pin
-1.0
40
V
16
SR1
Squib/pyroswitch 1 low-side pin
-0.3
40
V
17
DCS3
Sensor switch interface channel 3
-1.0
40
V
18
DCS2
Sensor switch interface channel 2
-1.0
40
V
19
DCS1
Sensor switch interface channel 1
-1.0
40
V
20
DCS0
Sensor switch interface channel 0
-1.0
40
V
21
VRESDIAG
Reserve voltage diagnostic input
-0.3
40
V
22
RSU0/NC
PSI-5 Ch. 0 remote sensor output (only L9678PS), NC on L9678P
-1.0
40
V
23
RSU1/NC
PSI-5 Ch. 1 remote sensor output (only L9678PS), NC on L9678P
-1.0
40
V
24
VSUP/NC
Remote sensor power supply (only L9678P-S),
NC(1) on L9678P
-0.3
40
V
DS11626 Rev 5
13/210
209
Absolute and operative maximum ratings
L9678P, L9678P-S
Table 1. Absolute maximum ratings (continued)
Pin #
Pin name
Pin function
Min.
Max.
Unit
25
BVSUP/NC
VSUP external transistor control (only L9678P-S),
NC(1) on L9678P
-0.3
40
V
26
GPOD0
GPO driver 1 drain output pin
-1.0
40
V
27
GPOS0
GPO driver 1 source output pin
-1.0
40
V
28
GPOS1
GPO driver 0 source output pin
-1.0
40
V
29
GPOD1
GPO driver 0 drain output pin
-1.0
40
V
-
-
-
ISO9141 bus pin (K-LINE)
-18.0
40
V
Substrate ground
-0.3
0.3
V
Not connected
(1)
30
NC
31
ISOK
32
GNDSUB1
33
SR3
Squib/pyroswitch 3 low-side pin
-0.3
40
V
34
SF3
Squib/pyroswitch 3 high-side pin
-1.0
40
V
35
SS23
Squib/pyroswitch 2 & 3 deployment supply pin
-0.3
40
V
36
SG23
Squib/pyroswitch 2 & 3 deployment ground pin
-0.3
0.3
V
37
SF2
Squib/pyroswitch 2 high-side pin
-1.0
40
V
38
SR2
Squib/pyroswitch 2 low-side pin
-0.3
40
V
39
GNDA
Analog ground
-0.3
0.3
V
40
ISORX
ISO9141 receiver pin
-0.3
VDDQ+0.3 6.5
V
41
ISOTX
ISO9141 transmit pin
-0.3
VDDQ+0.3 6.5
V
42
FENL
LS driver FET control input
-0.3
VDDQ+0.3 6.5
V
43
FENH
HS driver FET control input
-0.3
VDDQ+0.3 6.5
V
44
SAF_CS0
SPI interface safing sensor chip select
-0.3
VDDQ+0.3 6.5
V
45
SAF_CS1
SPI interface safing sensor chip select
-0.3
VDDQ+0.3 6.5
V
-
-
-
46
NC
47
WAKEUP
Wake-up control input
-0.3
40
V
48
VBATMON
Battery line voltage monitor
-18
40
V
49
VSF
Safing regulator supply output
-0.3
ERBOOST+0.3 40
V
50
VIN
Battery connection
-0.3
40
V
51
VER
Reserve voltage
-0.3
40
V
52
ERBOOST
Energy reserve regulator output
-0.3
40
V
53
ERBSTSW
Boost switching output
-0.3
40
V
-
-
-
Boost regulator ground
-0.3
0.3
V
EOL disposal control input
-0.3
40
V
VDD5 external transistor control
-0.3
40
V
-
-
-
-0.3
6.5
V
-
-
-
54
NC
55
BSTGND
56
ACL
57
BVDD5
58
NC
59
VDD5
60
14/210
NC
Not connected
(1)
Not connected
(1)
Not connected
5V regulator output
Not connected
(1)
DS11626 Rev 5
L9678P, L9678P-S
Absolute and operative maximum ratings
Table 1. Absolute maximum ratings (continued)
Pin #
Pin name
61
COVRACT
62
VDDQ
63
ARM
64
GNDSUB2
1.
Pin function
Min.
Max.
Unit
External crossover switch control
-0.3
VDDQ+0.3 6.5
V
I/O supply
-0.3
6.5
V
Arming Output
-0.3
VDDQ+0.3 6.5
V
Substrate ground
-0.3
0.3
V
Not connected internally, should be connected to GND externally.
2.2
Operative maximum ratings
Within the operative ratings the part operates as specified and without parameter
deviations. Once taken beyond the operative ratings and returned back within, the part will
recover with no damage or degradation.
Additional supply-voltage and temperature conditions are given separately at the beginning
of each specification table.
Table 2. Operative maximum ratings
Pin #
Pin name
1
RESET
2
Pin function
Min.
Max.
Unit
Reset output
-0.1
VDDQ+0.1 5.5
V
SPI_MISO
SPI interface data out / Safing sensor data in
-0.1
VDDQ+0.1 5.5
V
3
SPI_MOSI
SPI interface data in
-0.1
VDDQ+0.1 5.5
V
4
SPI_SCK
SPI interface clock
-0.1
VDDQ+0.1 5.5
V
5
SPI_CS
SPI interface chip select
-0.1
VDDQ+0.1 5.5
V
6
WDT/TM
Watchdog disable
-0.1
20
V
7
VDD3V3
3.3V regulator output
-0.1
3.6
V
8
NC
-
-
-
9
CVDD
Internal 3.3V regulator output
-0.1
3.6
V
10
GNDD
Digital ground
-0.1
0.1
V
11
SR0
Squib/pyroswitch 0 low-side pin
-0.1
VER
V
12
SF0
Squib/pyroswitch 0 high-side pin
-1.0
VER
V
13
SG01
Squib/pyroswitch 0 & 1 deployment ground pin
-0.1
0.1
V
14
SS01
Squib/pyroswitch 0 & 1 deployment supply pin
-0.1
40
V
15
SF1
Squib/pyroswitch 1 high-side pin
-1.0
VER
V
16
SR1
Squib/pyroswitch 1 low-side pin
-0.1
VER
V
17
DCS3
Sensor switch interface channel 3
-1.0
VDCS_L
V
18
DCS2
Sensor switch interface channel 2
-1.0
VDCS_L
V
19
DCS1
Sensor switch interface channel 1
-1.0
VDCS_L
V
20
DCS0
Sensor switch interface channel 0
-1.0
VDCS_L
V
21
VRESDIAG
Reserve voltage diagnostic input
-0.1
35
V
22
RSU0/NC
PSI-5 Ch. 0 remote sensor output (only L9678PS), NC on L9678P
-1.0
VSUP
V
Not connected(1)
DS11626 Rev 5
15/210
209
Absolute and operative maximum ratings
L9678P, L9678P-S
Table 2. Operative maximum ratings (continued)
Pin #
Pin name
Pin function
Min.
Max.
Unit
23
RSU1/NC
PSI-5 Ch. 1 remote sensor output (only L9678PS), NC on L9678P
-1.0
VSUP
V
24
VSUP/NC
Remote sensor power supply (only L9678P-S,
NC(1) on L9678P)
-0.1
VIN
V
25
BVSUP/NC
VSUP external transistor control (only L9678P-S,
NC(1) on L9678P)
-0.1
VIN
V
26
GPOD0
GPO driver 1 drain output pin
-0.1
40
V
27
GPOS0
GPO driver 1 source output pin
-1.0
VIN
V
28
GPOS1
GPO driver 0 source output pin
-1.0
VIN
V
29
GPOD1
GPO driver 0 drain output pin
-0.1
40
V
-
-
-
Not connected
(1)
30
NC
31
ISOK
ISO9141 bus pin
-1.0
40
V
32
GNDSUB1
Substrate ground
-0.1
0.1
V
33
SR3
Squib/pyroswitch 3 low-side pin
-0.1
VER
V
34
SF3
Squib/pyroswitch 3 high-side pin
-1.0
VER
V
35
SS23
Squib/pyroswitch 2 & 3 deployment supply pin
-0.1
40
V
36
SG23
Squib/pyroswitch 2 & 3 deployment ground pin
-0.1
0.1
V
37
SF2
Squib/pyroswitch 2 high-side pin
-1.0
VER
V
38
SR2
Squib/pyroswitch 2 low-side pin
-0.1
VER
V
39
GNDA
Analog ground
-0.1
0.1
V
40
ISORX
ISO9141 receiver pin
-0.1
VDDQ+0.1 5.5
V
41
ISOTX
ISO9141 transmit pin
-0.1
VDDQ+0.1 5.5
V
42
FENL
LS driver FET control input
-0.1
VDDQ+0.1 5.5
V
43
FENH
HS driver FET control input
-0.1
VDDQ+0.1 5.5
V
44
SAF_CS0
SPI interface safing sensor chip select
-0.1
VDDQ+0.1 5.5
V
45
SAF_CS1
SPI interface safing sensor chip select
-0.1
VDDQ+0.1 5.5
V
-
-
-
46
NC
47
WAKEUP
Wake-up control input
-0.1
VIN
V
48
VBATMON
Battery line voltage monitor
-0.1
18
V
49
VSF
Safing regulator supply output
-0.1
27
V
50
VIN
Battery connection
-0.1
35
V
51
VER
Reserve voltage
-0.1
35
V
52
ERBOOST
Energy reserve regulator output
-0.1
35
V
53
ERBSTSW
Boost switching output
-0.1
ERBOOST+1
V
-
-
-
Boost regulator ground
-0.1
0.1
V
EOL disposal control input
--0.1
40
V
VDD5 external transistor control
-0.1
VIN
V
54
NC
55
BSTGND
56
ACL
57
BVDD5
16/210
Not connected
(1)
Not connected
(1)
DS11626 Rev 5
L9678P, L9678P-S
Absolute and operative maximum ratings
Table 2. Operative maximum ratings (continued)
Pin #
Pin name
58
NC
59
VDD5
NC
61
COVRACT
62
VDDQ
63
ARM
64
GNDSUB2
Not connected (1)
5V regulator output
Min.
Max.
Unit
-
-
-
-0.1
5.5
V
(1)
-
-
-
External crossover switch control
-0.1
VDDQ+0.1 5.5
V
I/O supply
-0.1
5.5
V
Arming Output
-0.1
VDDQ+0.1 5.5
V
Substrate ground
-0.1
0.1
V
Not connected
Not connected internally, should be connected to GND externally.
Pin-out description
The L9678P-S/L9678P pin-out is shown below. The package is a LQFP 64-pin full plastic
package.
VSF
VIN
VER
ERBOOST
ERBSTSW
NC (**)
BSTGND
ACL
BVDD5
NC (**)
VDD5
NC (**)
COVRACT
VDDQ
ARM
Figure 1. Pin-out description
GNDSUB2
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
RESET
1
48
VBATMON
SPI_MISO
2
47
WAKEUP
SPI_MOSI
3
46
NC (**)
SPI_SCKI
4
45
SAF_CS1
SPI_CS
5
44
SAF_CS0
WDT/TM
6
43
FENH
VDD3V3
7
42
FENL
NC (**)
8
41
ISOTX
CVDD
9
40
ISORX
GNDD
10
39
GNDA
SR0
11
38
SR2
SF0
12
37
SF2
SG01
13
36
SG23
SS01
14
35
SS23
SF1
15
34
SF3
SR1
16
33
SR3
ISOK
GNDSUB1
NC
(**)
GPOS1
GPOD1
GPOS0
GPOD0
(*) VSUP/NC (**)
DS11626 Rev 5
(*) BVSUP/NC (**)
(*) RSU1/NC (**)
RSU0/NC (**)
(*)
(*) Those pins are NC in the L9678 version.
(**) Not connected internally, should be connected to GND externally.
VRESDIAG
DCS0
DCS1
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
DCS2
2.3
DCS3
1.
60
Pin function
GAPGPS01105
17/210
209
Overview and block diagram
3
L9678P, L9678P-S
Overview and block diagram
The L9678P is a unique solution specifically targeted for entry level airbag or cut-off battery
systems while permitting the system designer significant flexibility in configuring the system
power and management block. The configurable methodology allows cost versus
performance trade-off without changing devices or circuit board designs. The L9678P
contains the base functionality required for entry level systems and can complete a system
design with a microcontroller and acceleration sensor. The high level block diagram is
shown below Figure 2.
Basic features include a configurable power supply & management block, 4 channel
squib/pyroswitch drivers, 2 channel HS/LS GPO drivers, 4 channel sensor interface, safing
logic, watchdog timer, ISO9141 communications and temperature sensor. The L9678P-S
device is pin compatible to the L9678P and includes two PSI-5 remote sensor interface
channels and a dedicated regulator for remote sensor.
18/210
DS11626 Rev 5
L9678P, L9678P-S
Overview and block diagram
Figure 2. Functional block diagram
361
0.47
Vbat
10μH, 0.5
100nF
2.2uF
SS16
1A
2.2uF
100μF, 4
+ 100nF
10nF
1mF to 10mF
ERBSTSW
ERBOOST
VER
VBatMon
uC_FLEN
ER Charge
ER
Boost
BSTGND
VIN
100nF
3k
BVDD5
BCP53
VDD5
Safing
regulator
ER Switch
VDD5
linear
regulator
VSF
GNDSUBx
4.7nF
GPOD0
4.7 F
VDD3V3
4.7 F
WAKEUP
VIgn
VDDQ
CVDD
VDD3V3
linear reg .
GPOS0
GPOD1
GPO
drivers
supply
VINT3V3
reg . for
analog
block s
GPOS1
Digital
Outputs
VRESDIAG
100nF
CVDD reg for
digital block s
GNDD
SS01
GNDA
3k
BVSUP
BCP53
SS23
VSUP
linear
regulator
Digital
block
VSUP
SF0
SF1
4.7 F
Satellite Driver &
Decoder
Optional
L9678-S
SF2
22nF
SF3
Enable
Control
FENH
HV analog MUX
and
AtoD converter
(10 bits )
FENL
SR0
SR1
Decoder
RSU0
SR2
L9678-S
RSU1
SR3
22nF
DC / Hall sensor interface
22nF
SG01
Enable
Control
Squib drivers
and
Diagnostic
DCS0
Safing
Logic
DCS1
SG23
ACL
ARM
DCS2
22nF
DCS3
System control
&
configuration
ISO9141
transceiver
GNDSUB2
COVRACT
WDTDIS/TM
SPI_MOSI
RESET
SPI_SCK
SPI_MISO
SAF_CS0
SAF_CS1
SPI_CS
ISOTX
ISORX
510
GNDISO
ISOK
Vbat
GAPGPS01106
DS11626 Rev 5
19/210
209
Start-up power control
L9678P, L9678P-S
4
Start-up power control
4.1
Power supply overview
The L9678P IC contains a complete power management system able to provide all
necessary voltages for an entry level airbag or cut-off battery application. Moreover L9678P
power supply is user configurable allowing the design engineer to balance cost and
performance as per their particular application. The power supply block contains the
following features:
20/210
Two 3.3 V internal regulators for operating internal logic (CVDD) and analog circuits
(VINT3V3). An external CVDD pin is used to provide filtering capacitance to digital
section supply rail.
Energy reserve supply (ERBOOST) achieved through an integrated switching boost
regulator. The design of this boost regulator is intended to be a cost effective solution
with respect to traditional boost regulators because it makes use of a low value
inductor with an operative frequency of 1.882 MHz. Switching output is ERBSTSW pin,
while voltage feedback input pin is ERBOOST. The output voltage could be set to either
23 V±5% or 33 V±5%.
Energy reserve capacitor connected to VER pin. To control in-rush current, a dedicated
current generator is implemented between ERBOOST pin and VER pin.
Capability to drive an external safing FET (n-ch type) by means of an internal voltage
regulator on VSF pin, where a 20 V level is given (configurable to 25V via SPI
command).
The integrated current limited ER switch requires no external components. This switch
is controlled through the integrated power control state machine and is enabled either
once a loss of battery is detected or a shutdown command is received. Under the same
conditions also the discrete digital pin COVRACT is activated allowing the control of an
external optional cross-over switch.
One linear regulator VDD5 (5 V nominal, ±4% tolerance) requiring external power
transistor and capacitors. VDD5 is used as micro-controller supply (in case of 5 V
family controllers) and, in any case, as supply for VDD3V3 rail.
One integrated linear regulator VDD3V3 (3.3 V nominal, ±4% tolerance) requiring
external capacitors. VDD3V3 is used as micro-controller supply (in case of 3.3 V family
controllers).
VDDQ pin to provide output voltage rail reference. VDDQ could be connected to either
VDD5 or VDD3V3 to enable 5 V or 3.3 V digital communication between device and
micro-controller.
Capability to drive an external power transistor connected to VIN to provide a 7.2 V rail
on VSUP pin. This voltage rail could be used to supply PSI-5 remote sensor.
Battery voltage sense input comparator with hysteresis connected to VBATMON pin.
Power-up and operation states are carefully handled with respect to the battery level to
provide the most effective power supply configuration.
All voltage rails (VIN, ERBOOST, VER, VRESDIAG, VDD5, VDD3V3, VSUP and VSF)
can be monitored through internal ADC diagnostics.
DS11626 Rev 5
L9678P, L9678P-S
4.2
Start-up power control
Power mode control
Start-up and power down of the L9678P are controlled by the WAKEUP pin, VBATMON pin,
VIN pin device status and the SPI interface. There are four main power modes: power-off,
sleep, active and passive mode.
Each power mode is described below and represented in the state flow diagram shown in
Figure 3. The descriptions include references to conditions and sometimes nominal values.
The absolute values for each condition are listed in the electrical specifications section.
Figure 3. Power control state flow diagram
From
any state
POR
POWER
OFF
state
POWER-OFF MODE
(All supplies disabled)
WAKEUP <
WU_mon
WAKEUP>
WU_mon
WAKEUP
MONITOR
state
WAKEUP >
WU_on
[(WAKEUP < WU_off) AND
(WakeUpFilt = 0)]
AWAKE
State
WakeUpFilt= 1
AND
VINVINGOOD
Twakeup > 9ms
WakeUpFilt = 0
AND SPI_SLEEP
RUN
state
VBAT mon > VBGOOD
(blanking time 10ms)
ACTIVE MODE
VIN < VINGOOD
POWERMODE
SHUTDOWN
state
ER
state
WakeUpFilt = 0
AND SPI_SLEEP
Twakeup Timer: Cleared if (State = WAKEUP MONITOR or AWAKE) and WakeUpFilt=0
DS11626 Rev 5
PASSIVE MODE
GAPGPS01108
21/210
209
Start-up power control
4.2.1
L9678P, L9678P-S
Power_off mode
During the Power-off mode all supplies are disabled keeping the system in a quiescent state
with very low current draw from battery. As soon as WAKEUP > WU_mon the IC will move
to Sleep mode.
4.2.2
Sleep mode
During the Sleep mode the VINT3V3 and CVDD internal regulators are turned on and the IC
is ready for full activation of all the other supplies. As soon as battery voltage is over a
minimum threshold, all the other supplies are turned on and the IC enters the Active mode.
4.2.3
Active mode
This is the normal operating mode for the system.
All power supplies are enabled and the energy reserve boost converter starts to increase
the voltage at ERBOOST. Likewise, the VDD5 regulator is turned on. Once the VDD5 has
reached a good value, the VDD3V3 regulator starts up. Once the VDD3V3 regulator is in
regulation, RESET is released allowing the system microcontroller and other components to
begin their power-on sequence. Among these, also the ER charge current generator can be
enabled by the microcontroller via a dedicated SPI command.
The active mode can be left when either WAKEUP pin or VIN voltage drop down. For the
very first 9 ms after having entered the active mode, the WAKEUP pin low would
immediately cause the IC to switch back to sleep mode. After that time, WAKEUP pin low
must be first confirmed by a MCUSPI_SLEEP command prior to cause the system to switch
to passive mode. Passive mode is also entered in case of VIN voltage low.
4.2.4
Passive mode
In this state, the energy reserve charge current is disabled and the ERBOOST boost
converter is disabled only if the SYS_CFG(KEEP_ERBST_ON)=0. When in passive mode
the device automatically activates both the COVRACT output pin and the integrated ER
switch to allow VIN to be connected to the ER capacitor. In this time, VIN is supposed to be
increased up to almost VER level and the system operation relies on energy from the ER
capacitor. Two scenarios are possible: high or low battery. If VIN < VINGOOD, the device
moved from RUN state in ACTIVE mode to the ER state. Here, the ER capacitor is depleted
while supplying all the regulators until the POR on internal regulator occurs. The threshold
to decide the ER switch activation is based on VIN, because VIN is the supply voltage rail
for all regulators. If the device has still a good battery level, it entered the POWERMODE
SHUTDOWN thanks to WAKEUP pin and MCU command to switch off. In this case, the
VER node will be discharged down to approximately VIN level, which then will be supplied
out of the battery line. System will continue to run up to a dedicated SPI command which will
lead the device to enter the POWEROFF state.
The wake-up pin is filtered to suppress undesired state changes resulting from transients or
glitches. Typical conditions are shown in the chart below and summarized by state.
22/210
DS11626 Rev 5
L9678P, L9678P-S
Start-up power control
Figure 4. Wake-up input signal behaviour
ACTIVE MODE
SLEEP MODE
PASSIVE MODE
1
2
3
5
4
6
WU_on
WU_off
WAKEUP
t
WU_on
VBBAD
-
-
-
VBATMON bad pin status
Set and cleared based on voltage
1 VBATMON < VBBAD
0 VBATMON > VBBAD
NOT_VBGOOD
-
-
-
VBATMON good pin status
Set and cleared based on voltage
1 VBATMON < VBGOOD
0 VBATMON > VBGOOD
VINBAD
-
-
-
VIN bad pin status
Set and cleared based on voltage
0 VIN > VINBAD
1 VIN < VINBAD
NOT_VINGOOD
-
-
-
VIN good pin status
Set and cleared based on voltage
0 VIN > VINGOOD
1 VIN < VINGOOD
VDD3V3_UV
60/210
-
-
-
VDD3V3 bad pin status
DS11626 Rev 5
L9678P, L9678P-S
SPI interface
Set based on voltage, cleared on SPI read
0 VDD3V3 > VDD3V3_UV
1 VDD3V3 < VDD3V3_UV
VDD3V3_OV
-
-
-
VDD3V3 bad pin status
Set based on voltage, cleared on SPI read
0 VDD3V3 < VDD3V3_OV
1 VDD3V3 > VDD3V3_OV
ER_BST_NOK
-
-
-
ERBOOST pin status
Set and cleared based on voltage
1 V_ERBOOST < ERBOOST_OK
0 V_ERBOOST > ERBOOST_OK
VDD5_UV
-
-
-
VDD5_UV status
Set based on voltage, cleared on SPI read
0 VDD5 > VDD5_UV
1 VDD5 < VDD5_UV
VDD5_OV
-
-
-
VDD5_OV status
Set based on voltage, cleared on SPI read
0 VDD5 < VDD5_OV
1 VDD5 > VDD5_OV
VSUP_NOK
-
-
-
VSUP status
Set and cleared based on voltage
0 VSUP > VSUP_OK
1 VSUP < VSUP_OK
ER_BST_ON
0
-
-
ERBOOST_ON state
Updated according to ER_BOOST Control Behavior diagram
0 RBOOST_OFF or ERBOOST_OT state or ER_BST_STBY state (boost
not running)
1 ERBOOST_ON state (boost running)
ER_CHRG_ON
0
0
0
ERCHARGE_ON state
Updated according to ER_CHARGE Power Mode Control diagram
0 ERCHARGE_ON = 0
1 ERCHARGE_ON = 1
DS11626 Rev 5
61/210
209
SPI interface
ER_SW_ON
L9678P, L9678P-S
0
-
-
ER_SWITCH State
Updated according to ER Switch state diagram
0 ER_SWITCH_OFF
1 ER_SWITCH_ON
VDD5_ACT
0
-
-
VDD5 Active state
Updated according to VDD5 Power Mode Control state diagram
0 VDD5 supply in VDD5_OFF or VDD5_SHUTDOWN states
1 VDD5 supply in VDD5_RAMPUP or VDD5_ON states
VSUP_ACT
0
0
0
VSUP Active state
Updated according to VSUP Power Mode Control state diagram
0 VSUP supply in VSUP_OFF or VSUP_SHUTDOWN states
1 VSUP supply in VSUP_RAMPUP or VSUP_ON states
VDD3V3_ACT
0
-
-
VDD3V3 Active state
Updated according to VDD3V3 Power Mode Control state diagram
0 VDD3V3 supply in VDD3V3_OFF or VDD3V3_SHUTDOWN states
1 VDD3V3 supply in VSUP_ON state
VSF_ACT
0
0
0
VSF Active state
Updated according to VSF Control Logic diagram
0 VSF_EN = 0
1 VSF_EN = 1
62/210
DS11626 Rev 5
L9678P, L9678P-S
5.1.7
SPI interface
Deployment configuration registers (DCR_x)
Channel 0 (DCR_0)
Channel 1 (DCR_1)
Channel 2 (DCR_2)
-
0
0
0
0
15
14
13
12
11
10
9
8
X
X
X
X
X
X
X
X
0
0
0
0
0
0
0
0
RW
Buffer:
$0600 (DCR_0)
$0700 (DCR_1)
$0800 (DCR_2)
$0900 (DCR_3)
Reset:
$000C (DCR_0)
$000E (DCR_1)
$0010 (DCR_2)
$0012 (DCR_3)
Deploy_Time[1:0]
SSM
Type:
WSM
06 (DCR_0)
07 (DCR_1)
08 (DCR_2)
09 (DCR_3)
POR
Address:
00
00
00 Default deployment time select
7
6
5
4
3
2
Dep_expire_time Dep_expire_time
MISO
16
Dep_Current
MOSI
17
Dep_Current
18
Deploy_Time
19
Deploy_Time
Channel 3 (DCR_3)
1
0
X
X
0
0
Updated by SSM_RESET or SPI write while in DIAG state
00 Unused (no deploy, 8 us pulse output on ARM1 pin during PULSE TEST)
01 0.5 ms
10 0.7 ms
11 2.0 ms
Dep_Current[1:0]
00
00
00 Deployment Current limit select
Updated by SSM_RESET or SPI write while in DIAG state
00 Unused (no deploy)
DS11626 Rev 5
63/210
209
SPI interface
L9678P, L9678P-S
01 1.75A min
10 1.2A min
11 Unused (no deploy)
Dep_expire_time[1:
0]
00
00
00 Deploy command expiration timer select
Updated by SSM_RESET or SPI write while in DIAG state
00 500ms
01 250ms
10 125ms
11 0ms
64/210
DS11626 Rev 5
L9678P, L9678P-S
-
MISO
0
0
0
12
Type:
RW
Buffer:
$1200
Reset:
$0024
POR
Address:
CHxDEPREQ
0
15
14
13
12
11
10
9
8
7
6
5
4
X
X
X
X
X
X
X
X
X
X
X
X
0
0
0
0
0
0
0
0
0
0
0
0
3
2
1
0
CH0DEP CH0DEPREQ
16
WSM
MOSI
17
CH1DEP CH1DEPREQ
18
CH2DEP CH2DEPREQ
19
CH3DEP CH3DEPREQ
Deployment command (DEPCOM)
SSM
5.1.8
SPI interface
N/A N/A N/A Channel x Deploy Request - non-latched channel-specific deploy request
0 No change to deployment control for channel x
1 Clear and start Expiration timer if in ARMING or SAFING state and in
DEPLOY_ENABLED state
CHxDEP
0
0
0
Channel x deployment expiration timer enable
Set when SPI_DEPCOM(CHxDEPREQ=1) AND in ARMING or SAFING state
AND in DEP_ENABLED state
Cleared on SSM_RESET OR when in DEP_DISABLED state OR when
Deploy Expiration Timer x reaches time-out threshold
0 Expiration timer enabled - Deploy command still valid
1 Expiration Timer disabled - Deploy command no more valid
DS11626 Rev 5
65/210
209
SPI interface
5.1.9
L9678P, L9678P-S
Deployment configuration registers (DSR_x)
Channel 0 (DSR_0)
Channel 1 (DSR_1)
Channel 2 (DSR_2)
-
MISO
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
0
0
0
0
0
0
R
Buffer:
$1300 (DSR_0)
$1400 (DSR_1)
$1500 (DSR_2)
$1600 (DSR_3)
Reset:
-
CHxDS
SSM
Type:
WSM
13 (DSR_0)
14 (DSR_1)
15 (DSR_2)
16 (DSR_3)
POR
Address:
0
0
0
DEP_CHx_ExpTimer
16
DCRxERR
MOSI
17
CHxDD
18
CHxSTAT
19
CHxDS
Channel 3 (DSR_3)
Channel x deployment successful
Updated according to Deployment Driver Control Logic
(set when deployment terminates on ch x due to deploy timer time-out,
cleared on SSM_RESET OR when deployment starts on ch x)
0 Deployment not successful
1 Deployment successful
CHxSTAT
0
0
0
(set when deployment starts on ch x, cleared on SSM_RESET OR when
deployment terminates due to deploy timer time-out, LS Over current OR
GND Loss)
0 Deployment not in progress
1 Deployment in progress
CHxDD
0
0
0
Default Deploy Flag on Channel x
Updated by SSM_RESET, or when the Deployment Configuration Register is
written with an incorrect configuration
66/210
DS11626 Rev 5
L9678P, L9678P-S
SPI interface
0 Correct Time/Current combination selected
1 Incorrect Time/Current combination selected (default time/current is set)
DCRxERR
0
0
0
Deployment configuration register err
0 Deploy configuration change accepted and stored in memory
1 Deploy configuration change rejected because deploy is in progress
(or DEP_EXPIRE_TIME changed when in DEP_ENABLED state)
DEP_CHx_ExpTimer 0000 0000 0000 Channel x Deployment Expiration Timer value 8ms/count
[5:0] 00 00 00 Updated according to Deployment Driver Control Logic
(Cleared on SSM_RESET OR when Exp Timer times out OR when
SPI_DEPREQx is received while in DEP_ENABLED state AND in ARMING
or SAFING states)
5.1.10
Deployment current monitor status registers (DCMTSxy)
Channels 0, 1 (DCMTS01)
Channels 2, 3 (DCMTS23)
19
18
0
0
MOSI
MISO
17
16
0
0
-
15
14
X
X
11
10
9
8
7
6
X
X
X
X
X
X
X
X
R
Buffer:
$1F00 (DCMTS01)
$2000 (DCMTS23)
Reset:
-
5
4
3
2
1
0
X
X
X
X
X
X
Current_Mon_Timer_x[7:0]
SSM
Type:
WSM
1F (DCMTS01))
20 (DCMTS23)
POR
12
Current_Mon_Timer_y[7:0]
Address:
Current_Mon_Time
r_y[7:0]
13
$00 $00 $00 Channel y current monitor timer value corresponding to SPI command
DCMTSxy.
Set to default (cleared) on SSM_RESET or when a new deployment starts on
channel y. Increments each 16µs while deployment current exceeds monitor
threshold on channel y
Current_Mon_Time
r_x[7:0]
$00 $00 $00 Channel x current monitor timer value corresponding to SPI command
DCMTSxy.
Set to default (cleared) on SSM_RESET or when a new deployment starts on
channel x. Increments each 16µs while deployment current on channel x
exceeds monitor threshold
DS11626 Rev 5
67/210
209
SPI interface
Deploy enable register (SPIDEPEN)
19
18
0
0
MOSI
MISO
17
16
0
0
15
14
13
12
11
10
9
-
7
6
5
4
3
2
1
0
DEPEN_WR[15:0
25
Type:
RW
Buffer:
$2500
Reset:
$004A
DEPEN_STATE[15:0]
POR
WSM
Address:
DEPEN_WR[15:0]
8
SSM
5.1.11
L9678P, L9678P-S
N/A N/A N/A Non-latched encoded value for LOCK / UNLOCK command
$0FF0 LOCK - enter DEP_DISABLED state
$F00F UNLOCK - enter DEP_ENABLED state
DEPEN_STATE[15:
$0FF0$0FF0$0FF0Deploy Enabled State
0]
Updated according to Global SPI Deployment Enable State Diagram
$0FF0 In DEP_DISABLED state
$F00F In DEP_ENABLED state
MISO
17
16
-
0
0
0
R
Buffer:
$2600
Reset:
-
GNDLOSSx
68/210
12
11
10
9
8
7
6
5
4
3
2
1
0
X
X
X
X
X
X
X
X
X
X
X
X
X
X
0
0
0
0
0
0
0
0
0
0
0
0
SSM
Type:
13
X
WSM
26
14
X
POR
Address:
0
15
GNDLOSS0
18
GNDLOSS1
19
MOSI
GNDLOSS2
Squib/pyroswitch ground loss register (LP_GNDLOSS)
GNDLOSS3
5.1.12
0
0
0
Loop x Squib/pyroswitch Ground loss
DS11626 Rev 5
L9678P, L9678P-S
SPI interface
Cleared upon SSM_RESET or SPI read. Set when GND loss is detected
during deployment or loop diag's (HS sw test, LS sw test, squib/pyroswitch
resistance)
0 Loss of ground not detected
1 Loss of ground detected
5.1.13
Device version register (VERSION_ID)
19
18
MOSI
17
16
-
MISO
0
0
0
0
R
Buffer:
$2700
Reset:
-
DEVICE ID
12
11
10
9
8
7
6
5
4
3
2
1
0
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
0
0
0
0
0
0
0
1
0
SSM
Type:
13
WSM
27
14
POR
Address:
15
-
-
-
DEVICE ID
VERSN
Identification of the device
Static value - never updated
001 Low end
010 Medium end
011 High end
VERSN
-
-
-
Identification of the silicon version
000011
other codes
5.1.14
Watchdog retry configuration register (WD_RETRY_CONF)
19
18
17
16
15
14
13
12
MOSI
MISO
CB version
previous versions
11
10
9
8
7
6
5
4
3
0
0
0
0
0
0
0
0
0
2
WD1_RETRY_TH
0
0
DS11626 Rev 5
0
0
0
0
0
0
WD1_RETRY_TH
69/210
209
SPI interface
L9678P, L9678P-S
RW
Buffer:
$2800
Reset:
$0050
WD1_RETRY_TH
7
-
WD1 retry counter threshold (number of WD errors permitted before latching
WD1_LOCKOUT=1)
Watchdog timer configuration register (WDTCR)
19
18
MOSI
MISO
7
17
16
-
0
0
14
X
0
0
RW
Buffer:
$2A00
Reset:
$0054
SSM
Type:
WSM
2A
0
POR
Address:
WD1_MODE
15
13
12
WD1_MODE WD1_MODE
5.1.15
SSM
Type:
WSM
28
POR
Address:
0
0
-
11
10
9
8
7
6
5
4
3
2
WDTMIN[6:0]
WDTDELTA[6:0]
WDTMIN[6:0]
WDTDELTA[6:0]
1
0
WD1 Mode
Updated by WSM_RESET or SPI write while in WD1_INIT state
0 Fast WD1 mode - nominal 8µs timer resolution (2ms max value)
1 Slow WD1 mode - nominal 64µs timer resolution (16.3ms max value)
WDTMIN[6:0]
$32 $32
-
WD1 window minimum value - resolution according to WD1_MODE bit ($32 =
400µs in WD1 fast mode)
Updated by WSM_RESET or SPI write while in WD1_INIT state
WDTDELTA[6:0]
$19 $19
-
WD1 window delta value - WDTMAX=WDTMIN+WDTDELTA - resolution
according to WD1_MODE bit ($19 = 200µs in WD1 fast mode)
Updated by WSM_RESET or SPI write while in WD1_INIT state
70/210
DS11626 Rev 5
L9678P, L9678P-S
5.1.16
WD1 timer control register (WD1T)
19
18
0
0
MOSI
MISO
SPI interface
17
16
0
0
-
W
Buffer:
$2B00
Reset:
$0056
WD1CTL[1:0]
X
X
X
12
11
10
9
8
7
6
5
4
3
2
X
X
X
X
X
X
X
X
X
X
X
WD1CTL[1:0]
0
0
0
0
0
0
WD1CTL[1:0]
WD1_TIMER
SSM
Type:
13
WSM
2B
14
POR
Address:
15
00
00
00 WD1 Control command
1
0
Updated by SSM_RESET or SPI write
00 NOP
01 Code 'A'
10 Code 'B'
11 NOP
WD1_TIMER
$00 $00 $00 WD1 Window timer value
Cleared by SSM_RESET or by WD1 refresh, incremented every 8µs or 64µs
while in WD1_RUN or WD1_TEST states
WD1 state register (WDSTATE)
18
MOSI
MISO
17
16
0
0
0
0
2C
Type:
R
Buffer:
$2C00
Reset:
POR
Address:
WD1_ERR_CNT[3:0] 000 000
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
0
0
0
0
0
0
0
0
0
WD1_ERR_CNT[3:0]
WD_STATE[2:0]
SSM
19
WSM
5.1.17
-
Watchdog error counter
Updated according to Watchdog State Diagram
WD1_STATE[2:0] 000 000
-
Watchdog state
Updated according to Watchdog State Diagram
000 INITIAL
DS11626 Rev 5
71/210
209
SPI interface
L9678P, L9678P-S
001 RUN
010 TEST
011 RESET
100 OVERRIDE
MISO
16
-
0
0
0
0
RW
Buffer:
$2D00
Reset:
$005A
AUX_SS_DIS
12
11
10
9
8
7
6
5
4
X
X
X
X
X
X
X
X
X
X
X
X
0
0
0
0
0
0
0
0
0
0
0
0
SSM
Type:
13
WSM
2D
14
POR
Address:
15
1
-
-
Auxiliary 3.75MHz oscillator Spread Spectrum disable
Updated by POR or SPI write while in INIT state
0 Spread Spectrum enabled
1 Spread Spectrum disabled
MAIN_SS_DIS
0
-
-
Main 16MHz oscillator Spread Spectrum disable
Updated by POR or SPI write while in INIT state
0 Spread Spectrum enabled
1 Spread Spectrum disabled
ERBST_F_SEL[1:0] 00
-
-
ER Boost switching frequency select
Updated by POR or SPI write while in INIT state
00 1.88 MHz
01 2.13 MHz
10 2.00 MHz
11 2.00 MHz
72/210
DS11626 Rev 5
3
2
1
0
ERBST_F_SEL ERBST_F_SEL[1:0]
MOSI
17
MAIN_SS_DIS
18
MAIN_SS_DIS
19
AUX_SS_DIS
Clock configuration register (CLK_CONF)
AUX_SS_DIS
5.1.18
L9678P, L9678P-S
Scrap state entry command register (SCRAP_STATE)
19
18
0
0
MOSI
MISO
17
16
15
14
13
12
11
10
9
8
0
0
0
0
0
0
0
0
0
0
-
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
$3535
30
Type:
W
Buffer:
-
Reset:
$0060
POR
WSM
Address:
SSM
5.1.19
SPI interface
N/A N/A N/A
Non-latched Scrap State entry command
Enter Scrap state from DIAG state
Safing state entry command register (SAFING_STATE)
19
18
MISO
16
15
14
13
12
11
10
9
0
0
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
$ACAC
0
31
Type:
W
Buffer:
-
Reset:
$0062
POR
Address:
0
0
0
0
0
0
0
0
0
0
SSM
MOSI
17
WSM
5.1.20
N/A N/A N/A
Non-latched Safing State entry command
Enter safing state from DIAG state and clear arming pulse stretch counter (if
received in DIAG or SAFING state)
DS11626 Rev 5
73/210
209
SPI interface
5.1.21
L9678P, L9678P-S
WD1 test command register (WD1_TEST)
19
18
0
0
16
15
14
13
12
0
0
0
0
0
0
-
MISO
11
10
9
8
0
0
0
0
$3C
35
Type:
W
Buffer:
-
Reset:
$006A
POR
WSM
Address:
7
6
5
4
3
2
1
0
X
X
X
X
X
X
X
X
0
0
0
0
0
0
0
0
SSM
MOSI
17
N/A N/A N/A
Non-latched WD1 Test Command
WD1_TEST SPI command as described in Figure 36: Watchdog state
diagram.
System diagnostic register (SYSDIAGREQ)
19
18
16
-
MISO
0
0
0
0
36
Type:
RW
Buffer:
$3601
Reset:
$006C
POR
Address:
WSM
MOSI
17
15
14
13
12
11
10
9
8
7
6
5
4
3
X
X
X
X
X
X
X
X
X
X
X
X
DSTEST[3:0]
0
0
0
0
0
0
0
0
0
0
0
0
DSTEST[3:0]
SSM
5.1.22
DSTEST[3:0] 0000 0000 0000 Diagnostic State Test selection
Updated by SSM_RESET or SPI write while in DIAG state
0000 = all outputs inactive
0001 = ARM pin active
0010 = all outputs inactive
0011 = all outputs inactive
0100 = all outputs inactive
0101 = all outputs inactive
0110 = VSF regulator active
74/210
DS11626 Rev 5
2
1
0
L9678P, L9678P-S
SPI interface
0111 = HS squib/pyroswitch driver FET active
1000 = LS squib/pyroswitch driver FET active
1001 = Output deployment timing pulses on ARM1 (separated by 8 ms)
1010 = ST reserved
1011 - 1111 = all outputs inactive
DS11626 Rev 5
75/210
209
SPI interface
R
Buffer:
$3700
Reset:
-
DIAG_LEVEL
9
8
7
6
5
4
3
2
1
0
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
STB
SQP
0
0
0 Diagnostic mode selector
Not present for low level diagnostic
Updated by SSM_RESET or SPI write to LPDIAGREQ
0 low level mode
1 high level mode
TIP
0
0
0 High level diagnostic test is running
Updated by SSM_RESET or Loops diagnostic state machine
0 High level
diagnostic
test is not running
1 High level
diagnostic
test is running
FP
0
0
0 Fault present before requested diagnostic
Updated by SSM_RESET
or Loops diagnostic state
machine
0 Fault not present
before requested
diagnostic
1 Fault present before
requested
diagnostic
FETON
76/210
0
0
0 FET activation during diagnostic
DS11626 Rev 5
LEAK_CHSEL
10
SSM
Type:
11
WSM
37
12
POR
Address:
13
STG
FP
14
SBL
0
15
RES_MEAS_CHSEL/
HIGH_LEV_DIAG_SELECTED
TIP
MISO
16
-
DIAG_LEVEL
MOSI
17
HSR_LO
18
HSR_HI
19
ST_reserved
Diagnostic result register for deployment loops (LPDIAGSTAT)
FETON
5.1.23
L9678P, L9678P-S
L9678P, L9678P-S
SPI interface
Updated by SSM_RESET or Loops diagnostic state machine or when HS or
LS FET is activated during DIAG state
0 FET is off during
diagnostic
1 FET is on during
diagnostic
ST_reserved
0
0
0 ST_reserved
HSR_HI
0
0
0
HSR Diagnostic - HIGH Range
Updated by SSM_RESET or Loops diagnostic state machine or when
squib/pyroswitch resistance test is run
0 HSR measurement
< HSR HIGH value
1 HSR measurement
> HSR HIGH value
HSR_LO
0
0
0 HSR Diagnostic - Low Range
Updated by SSM_RESET or Loops diagnostic state machine or when
squib/pyroswitch resistance test is run
1 HSR measurement< HSR LOW value
0 HSR measurement > HSR LOW value
RES_MEAS_CHSEL 0000 0000 0000 Channel selected for resistance measurement
[3:0]
Updated by SSM_RESET or Loops diagnostic state machine or as
determined by squib/pyroswitch resistance channel selected
0000 = Ch 0
0001 = Ch 1
0010 = Ch 2
0011 = Ch 3
0100 - 1111 None Selected
HIGH_LEV_DIAG_ 0000 0000 0000
SELECTED[3:0]
0000 No diagnostic selected
0001 VRCM CHECK
0010 Leakage CHECK
0011 Short Between Loops CHECK
0100 ER cap ESR measure
0101 Squib/pyroswitch resistance range CHECK
0110 Squib/pyroswitch resistance measurement
0111 FET test
1000 - 1111 Unused
DS11626 Rev 5
77/210
209
SPI interface
L9678P, L9678P-S
SBL
0
0
0 Short between loop state
Updated by SSM_RESET or Loops diagnostic state machine
0 Short between squib/pyroswitch loops is not present
1 Short between squib/pyroswitch loops is present
STG
0
0
0 Short to Ground Test Status
Updated by SSM_RESET or Loops diagnostic state machine or as
determined by squib/pyroswitch leakage diagnostic
0 STG not detected
1 1 STG detected
STB
0
0
0 Short to Battery Test Status
Updated by SSM_RESET or Loops diagnostic state machine or as
determined by squib/pyroswitch leakage diagnostic
0 STB not detected
1 STB detected
SQP
0
0
0 Squib/pyroswitch PIN where leakage test has been performed
Updated by SSM_RESET or Loops diagnostic state machine or as
determined by squib/pyroswitch leakage diagnostic
0 SRx
1 SFx
LEAK_CHSEL[3:0] 0000 0000 0000 Channel selected for leakage measurement
Updated by SSM_RESET or Loops diagnostic state machine or as
determined by squib/pyroswitch leakage diagnostic
0000 = Ch 0
0001 = Ch 1
0010 = Ch 2
0011 = Ch 3
0100 - 1111 None Selected
78/210
DS11626 Rev 5
L9678P, L9678P-S
Loops diagnostic configuration command register for low level
diagnostic (LPDIAGREQ)
RW
Buffer:
$3800
Reset:
$0070
DIAG_LEVEL
SSM
Type:
WSM
38
POR
Address:
0
0
0
5
4
3
2
1
0
LEAK_CHSEL[3:0]
6
LEAK_CHSEL[3:0]
7
RES_MEAS_CHSEL[3:0]RES_MEAS_CHSEL[3:0]
8
VRCM[1:0]
9
VRCM[1:0]
10
ISINK
0
11
ISINK
0
12
ISRC [1:0]
0
13
ISRC [1:0]
0
-
MISO
14
PD_CURR
15
PD_CURR
16
ISRC_CURR_SEL
MOSI
17
ISRC_CURR_SEL
18
DIAG_LEVEL
19
DIAG_LEVEL
5.1.24
SPI interface
Diagnostic mode selector
Updated by SSM_RESET or SPI write
0 low level mode
1 N/A - see description below
ISRC_CURR_SEL
0
0
0
Selection of ISRC current value
0 40mA
1 8mA
PD_CURR
0
0
0
Pull down current control
Updated by SSM_RESET or SPI write
0 Request OFF only for channels connected to VRCM or ISINK or ISRC,
ON for all other channels
1 Request OFF for all channels
ISRC [1:0]
00
00
00 High side current source for channel selected in RES_MEAS_CHSEL[3:0]
Updated by SSM_RESET or SPI write
00 = OFF
01 = ON 40 mA current for channel selected in RES_MEAS_CHSEL,
OFF on all other channels
DS11626 Rev 5
79/210
209
SPI interface
L9678P, L9678P-S
10 = ON bypass current for channel selected in RES_MEAS_CHSEL,
OFF ON all other channels
11 = OFF
ISINK
0
0
0
Low Side current sink control (max 50mA)
Updated by SSM_RESET or SPI write
0 All channels OFF
1 ON for channel selected by RES_MEAS_CHSEL[3:0], OFF on all other
channels
VRCM[1:0]
00
00
00 Voltage Regulator Current Monitor control
Updated by SSM_RESET or SPI write
00 VRCM not connected
01 VRCM connected to SFx of channel selected by LEAK_CHSEL[3:0]
10 VRCM connected to SRx of channel selected by LEAK_CHSEL[3:0]
and pull down current of the same channel disabled
11 VRCM connected to SRx of channel selected by LEAK_CHSEL[3:0]
and pull down current of the same channel enabled (ISINK and ISRC
must be switched OFF)
RES_MEAS_CHS 0000 0000 0000 Squib/pyroswitch Resistance Measurement Channel select - selects the
EL[3:0]
channel and muxes for the resistance test, and the channel for HS driver test
(full path fet test) activation
Updated by SSM_RESET or SPI write
0000 Channel 0
0001 Channel 1
0010 Channel 2
0011 Channel 3
0100 - 1111 None Selected
LEAK_CHSEL[3:0]
0000 0000 0000
Squib/pyroswitch Leakage Measurement Channel select - selects the
channel and muxes for the leakage test, and the channel for HS/LS FET test
activation.
Updated by SSM_RESET or SPI write
0000 Channel 0
0001 Channel 1
0010 Channel 2
0011 Channel 3
0100 - 1111 None Selected
80/210
DS11626 Rev 5
L9678P, L9678P-S
-
0
0
0
RW
Buffer:
$3800
Reset:
$0070
DIAG_LEVEL
12
11
10
9
8
X
X
X
X
X
X
X
0
0
0
0
0
0
0
SSM
Type:
13
WSM
38
14
POR
Address:
0
15
0
0
0
7
6
5
4
3
2
1
0
LOOP_DIAG_CHSEL[3:0] LOOP_DIAG_CHSEL[3:0]
MISO
16
SQP
MOSI
17
SQP
18
HIGH_LEVEL_DIAG_SEL HIGH_LEVEL_DIAG_SEL
19
DIAG_LEVEL
Loops diagnostic configuration command register for high level
diagnostic (LPDIAGREQ)
DIAG_LEVEL
5.1.25
SPI interface
Diagnostic mode selector
0 0 N/A - see description above
1 1 high level mode
HIGH_LEVEL_DIAG 000 000 000
Selection of high level squib/pyroswitch diagnostic
_SEL
Updated by SSM_RESET or SPI write
000 No diagnostic selected
001 VRCM CHECK
010 Leakage CHECK
011 Short Between Loops CHECK
100 ER cap ESR measure
101 Squib/pyroswitch resistance range CHECK
110 Squib/pyroswitch resistance measurement
111 FET test
SQP
0
0
0
Squib/pyroswitch pin select for all leakage diagnostic
Updated by SSM_RESET or SPI write
DS11626 Rev 5
81/210
209
SPI interface
L9678P, L9678P-S
0 SRx
1 SFx
LOOP_DIAG_CHSE 0000 0000 0000 Channel select - selects the channel and muxes for all squib/pyroswitch
L[3:0]
diagnostic.
Updated by SSM_RESET or SPI write
0000 Channel 0
0001 Channel 1
0010 Channel 2
0011 Channel 3
0100 - 1111 None Selected
82/210
DS11626 Rev 5
L9678P, L9678P-S
16
-
MISO
0
0
0
RW
Buffer:
$3900
Reset:
$0072
DCS_PDCURR
12
11
10
9
8
X
X
X
X
X
X
X
X
0
0
0
0
0
0
0
0
SSM
Type:
13
WSM
39
14
POR
Address:
0
15
0
0
0
7
6
5
4
X
X
CHID[3:0]
MOSI
17
0
0
CHID[3:0]
18
SWOEN
19
SWOEN
DC sensor diagnostic configuration command register (SWCTRL)
DCS_PDCURR DCS_PDCURR
5.1.26
SPI interface
3
2
1
0
Disable of all pull down current for DC sensor
Updated by SSM_RESET or SPI write
0 OFF for channel under voltage or current measurement, ON for all other
channels
1 OFF for all channels
SWOEN
0
0
0
Switch Output Enable
Updated by SSM_RESET or SPI write
0 OFF
1 ON (40mA)
CHID[3:0] 0000 0000 0000 Channel ID - selects DC sensor channel for output activation
Updated by SSM_RESET or SPI write
0000 Channel 0
0001 Channel 1
0010 Channel 2
0011 Channel 3
0100 - 1111 None Selected
DS11626 Rev 5
83/210
209
SPI interface
5.1.27
L9678P, L9678P-S
ADC request and data registers (DIAGCTRL_x)
ADC A control command (DIAGCTRL_A)
19
18
MISO
17
16
NEWDATA_A
MOSI
0
15
14
13
12
11
10
9
8
7
X
X
X
X
X
X
X
X
X
0
6
3A
Type:
RW
Buffer:
$3A00
Reset:
$0074
4
3
2
1
0
1
0
1
0
ADCREQ_A[6:0]
ADCREQ_A[6:0]
Address:
5
ADCRES_A[9:0]
ADC B control command (DIAGCTRL_B)
19
18
MISO
16
NEWDATA_B
MOSI
17
0
15
14
13
12
11
10
9
8
7
X
X
X
X
X
X
X
X
X
0
6
3B
Type:
RW
Buffer:
$3B00
Reset:
$0076
4
3
2
ADCREQ_B[6:0]
ADCREQ_B[6:0]
Address:
5
ADCRES_B[9:0]
ADC C control command (DIAGCTRL_C)
19
18
MISO
17
16
NEWDATA_C
MOSI
0
0
Address:
3C
Type:
RW
Buffer:
$3C00
Reset:
$0078
84/210
15
14
13
12
11
10
9
8
7
X
X
X
X
X
X
X
X
X
ADCREQ_C[6:0]
DS11626 Rev 5
6
5
4
3
2
ADCREQ_C[6:0]
ADCRES_C[9:0]
L9678P, L9678P-S
SPI interface
ADC D control command (DIAGCTRL_D)
19
18
MISO
17
16
NEWDATA_D
MOSI
0
14
13
12
11
10
9
8
7
X
X
X
X
X
X
X
X
X
0
RW
Buffer:
$3D00
Reset:
$007A
SSM
Type:
WSM
3D
6
ADCREQ_D[6:0]
POR
Address:
NEWDATA_x
15
0
0
0
5
4
3
2
1
0
ADCREQ_D[6:0]
ADCRES_D[9:0]
New data available from convertion
Updated by SSM_RESET or ADC state machine
0 cleared on read
1 convertion finished
ADCREQ_x[6:0]
$00 $00 $00 ADC Request select command
Updated by SSM_RESET or SPI write to DIAGCTRL_x
Measurement
$00 Unused
$01 Ground Ref
$02 Full scale Ref
$030 DCSx voltage
$04 DCSx current
$05 DCSx resistance
$06 Squib/pyroswitch x resistance
$07 Internal BG reference voltage (BGR)
$080 Internal BG monitor voltage (BGM)
$09 Unused
$0A Temperature
$0B DCS 0 voltage
$0C DCS 1 voltage
$0D DCS 2 voltage
$0E DCS 3 voltage
$20 VBATMON pin voltage
$21 VIN pin voltage
$22 Internal analog supply voltage (VINT)
$23 Internal digital supply voltage (VDD)
DS11626 Rev 5
85/210
209
SPI interface
L9678P, L9678P-S
$24 ERBOOST pin voltage
$25 Unused
$26 VER pin voltage
$27 VSUP voltage
$28 VDDQ voltage
$29 WAKEUP pin voltage
$2A VSF pin voltage
$2B WDTDIS pin voltage
$2C GPOD0 pin voltage
$2D GPOS0 pin voltage
$2E GPOD1 pin voltage
$2F GPOS1 pin voltage
$30 Unused
$31 Unused
$32 RSU0 pin Voltage
$33 RSU1 pin Voltage
$34 Unused
$35 Unused
$36 SS0 pin voltage
$37 SS1 pin voltage
$38 SS2 pin voltage
$39 SS3 pin voltage
$3A Unused
$3B Unused
$3C Unused
$3D Unused
$3E Unused
$3F Unused
$40 Unused
$41 Unused
$42 VRESDIAG voltage
$43 VDD5 voltage
$44 VDD3V3 voltage
$45 ISOK voltage
$46 SF0
$47 SF1
$48 SF2
$49 SF3
$4A - $7F Unused
ADCRES_x[9:0] $000 $000 $000 10-bit ADC result value corresponding to ADCREQ_x request
Updated by SSM_RESET or ADC state machine
86/210
DS11626 Rev 5
L9678P, L9678P-S
GPO configuration register (GPOCR)
18
MOSI
MISO
17
16
-
0
0
0
RW
Buffer:
$4200
Reset:
$0084
GPOxLS
12
11
10
9
8
7
6
5
4
3
2
X
X
X
X
X
X
X
X
X
X
X
X
X
X
0
0
0
0
0
0
0
0
0
0
0
0
0
0
SSM
Type:
13
WSM
42
14
POR
Address:
0
15
0
0
0
1
0
GPO0LSGPO0LS
19
GPO1LSGPO1LS
5.1.28
SPI interface
GPO driver configuration bit
Updated by SSM_RESET or SPI write
0 High-side Driver configuration for GPOx (ER_BOOST_OK is required to
enable GPO as HS)
1 Low-side Driver configuration for GPOx (ER_BOOST_OK is not
required to enable GPO as LS)
DS11626 Rev 5
87/210
209
SPI interface
5.1.29
L9678P, L9678P-S
GPO configuration register (GPOCTRLx)
Channel 0 (GPOCTRL0)
Channel 1 (GPOCTRL1)
19
18
MOSI
17
16
-
MISO
0
0
0
0
15
14
13
12
11
10
9
8
7
6
X
X
X
X
X
X
X
X
X
X
GPOxPWM[5:0]
0
0
0
0
0
0
0
0
0
0
GPOxPWM[5:0]
Address:
43 (GPOCTRL0)
44 (GPOCTRL1)
Type:
RW
Buffer:
$4300 (GPOCTRL0)
$4400 (GPOCTRL1)
Reset:
$0086 (GPOCTRL0)
$0088 (GPOCTRL1)
POR
GPOxPWM
WSM
5
3
2
SSM
000000 000000 000000 6 bit value for PWM% with scaling of 1.6% per count
Updated by SSM_RESET or SPI write
88/210
4
DS11626 Rev 5
1
0
L9678P, L9678P-S
R
Buffer:
$4600
Reset:
-
GPO1DISABLE
11
10
9
8
7
6
5
4
3
2
1
0
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
0
0
0
0
0
0
0
GPO0OPN
0
0
SSM
Type:
12
WSM
46
13
POR
Address:
0
14
GPO0LIM
0
GPO0DISABLE
MISO
15
GPO0TEMP
16
GPO1DISABLE
MOSI
17
GPO1OPN
18
GPO1LIM
19
GPO1TEMP
GPO fault status register (GPOFLTSR)
GPO_NOT_CONF
5.1.30
SPI interface
1
1
1
GPO 1 disable state
0 GPO enable to work
1 GPO disabled due to thermal fault or configuration not received or
ERBOOST not OK (only HS mode)
GPO0DISABLE
1
1
1
GPO 0 disable state
0 GPO enable to work
1 GPO disabled due to thermal fault or configuration not received or
ERBOOST not OK (only HS mode)
GPO_NOT_CONF
1
1
1
GPO configuration status
0 GPO HS/LS configured (activation is permitted)
1 GPO not yet configured (activation is denied)
GPO1TEMP
0
0
0
GPO 1 Thermal Fault
Cleared by SSM_RESET or SPI read, set by detection circuit
0 Fault not detected
1 Fault detected
GPO1LIM
0
0
0
GPO 1 Current Limit Flag
Cleared by SSM_RESET or SPI read, set by detection circuit while ON
0 Fault not detected
1 Fault detected
GPO1OPN
0
0
0
GPO 1 Open Detection
Cleared by SSM_RESET or SPI read, set by detection circuit while ON
0 Fault not detected
DS11626 Rev 5
89/210
209
SPI interface
L9678P, L9678P-S
1 Fault detected
GPO0TEMP
0
0
0
GPO 0 Thermal Fault
Cleared by SSM_RESET or SPI read, set by detection circuit
0 Fault not detected
1 Fault detected
GPO0LIM
0
0
0
GPO 0 Current Limit Flag
OK Cleared by SSM_RESET or SPI read, set by detection circuit while ON
0 Fault not detected
1 Fault detected
GPO0OPN
0
0
0
GPO 0 Open Detection
OK Cleared by SSM_RESET or SPI read, set by detection circuit while ON
0 Fault not detected
1 Fault detected
19
18
MOSI
17
16
-
MISO
0
0
0
R
Buffer:
$4700
Reset:
-
ISOTEMP
12
11
10
9
8
7
6
5
4
3
2
1
0
X
X
X
X
X
X
X
X
X
X
X
X
X
X
0
0
0
0
0
0
0
0
0
0
0
0
0
0
SSM
Type:
13
X
WSM
47
14
X
POR
Address:
0
15
ISOLIM
ISO fault status register (ISOFLTSR)
ISOTEMP
5.1.31
0
0
0
ISO Thermal Fault
Cleared by SSM_RESET or SPI read, set by detection circuit
0 Fault not detected
1 Fault detected
ISOLIM
0
0
0
ISO Current Limit Flag
Cleared by SSM_RESET or SPI read, set by detection circuit while ON (ISOK=0)
0 Fault not detected
1 Fault detected
90/210
DS11626 Rev 5
L9678P, L9678P-S
5.1.32
SPI interface
Remote sensor configuration register (RSCRx)
Remote sensor configuration register 1 (RSCR1)
0
0
0
0
X
0
RW
Buffer:
$4A00 (RSCR1)
$4B00 (RSCR2)
Reset:
$0094 (RSCR1)
$0096 (RSCR2)
SLOWTRACK
SSM
Type:
WSM
4A (RSCR1)
4B (RSCR2)
POR
Address:
0
0
0
13
12
11
10
9
8
7
6
5
4
X
X
X
X
X
X
X
X
STSx[3:0]
MISO
14
0
0
0
0
0
0
0
0
STSx[3:0]
-
15
BLKTxSEL
16
BLKTxSEL
MOSI
17
STARTbitsMEAS_DISABLE STARTbitsMEAS_DISABLE
18
SLOWTRACK
19
SLOWTRACK
Remote sensor configuration register 2 (RSCR2)
3
2
1
0
Reduce frequency of base current tracking
0 8µs/1µs
1 16µs/2µs
STARTbitsMEAS_
DISABLE
0
0
0
Disable of start bits period measure to decode data bits
0 Period of start bits used to decode following data bits
1 Period of start bits not used to decode following data bits
BLKTxSEL
0
0
0
Current limiting blanking time select for channel x
Updated by SSM_RESET or SPI write
0 Blanking time = 5ms
1 Blanking time = 10ms
DS11626 Rev 5
91/210
209
L9678P, L9678P-S
SSM
POR
WSM
SPI interface
STSx[3:0] 0000 0000 0000 Remote sensor type select
Updated by SSM_RESET or SPI write
0000 Async PSI5, parity, 8-bit, 125k (A8P-228/1L)
0001 Async PSI5, parity, 8-bit, 189k (A8P-228/1H)
0010 Async PSI5, parity, 10-bit, 125k (A10P-228/1L)
0011 Async PSI5, parity, 10-bit, 189k (A10P-228/1H)
0100-1111 Async PSI5, parity, 10-bit, 189k (A10P-228/1H)
Remote sensor control register (RSCTRL)
18
MOSI
MISO
17
16
0
0
0
0
R/W
Buffer:
$4E00
Reset:
$009C
CHxEN
12
11
10
9
8
7
6
5
4
X
X
X
X
X
X
X
X
X
X
X
X
0
0
0
0
0
0
0
0
0
0
0
0
SSM
Type:
13
WSM
4E
14
POR
Address:
15
0
0
0
Channel x Output enable
Updated by SSM_RESET or SPI write
0 Off
1 On
92/210
DS11626 Rev 5
3
2
X
0
1
CH0EN CH0EN
19
CH1EN CH1EN
5.1.33
0
X
0
L9678P, L9678P-S
5.1.34
SPI interface
Remote sensor data/fault registers w/o fault (RSDRx)
Remote sensor 0 data and fault flag register (RSDR0)
Remote sensor 1 data and fault flag register (RSDR1)
Note:
The value in Bit15 (FLT) will re-define the use of the other bits, hence the information below
is divided into two groups.
Bit 15 = 0 NO FAULT condition
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
R
Buffer:
$5000 (RSDR0)
$5100 (RSDR1)
Reset:
SSM
Type:
WSM
50 (RSDR0)
51 (RSDR1)
POR
Address:
DATA [9:0]
0
15
LCID [3:0]
MISO
16
CRC
MOSI
17
On/Off
18
FLT=0
19
CRC[2:0] 000 000 000 CRC based on bits [16:0]
Updated based on bits [16:0]
FLT
1
1
1
Fault Status - Depending on Fault Status, the DATA bits are defined differently
Cleared when all of the following bits are '0': STG, STB, CURRENT_HI,
OPENDET, RSTEMP, NODATA
Set when any of the following bits are '1': STG, STB, CURRENT_HI,
OPENDET, RSTEMP, NODATA
0 No fault
1 Fault
On/Off
0
0
0
Channel On/Off Status
Cleared by SSM_RESET or when channel is commanded OFF via SPI
RSCTRL or when the STG bit is set or the RSTEMP bit is set
Set when channel is commanded ON by SPI RSCTRL
0 Off
1 On
LCID[0:3] 0000 0000 0000 Logical Channel ID
DS11626 Rev 5
93/210
209
SPI interface
L9678P, L9678P-S
Updated based on SPI read request
0000 RSU0
0100 RSU1
DATA[9:0] $000 $000 $000 10-bit data from Manchester decoder
Cleared by SSM_RESET or SPI read or when channel is commanded OFF
via SPI RSCTRL
updated when a valid PSI5 frame is received
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
STB
CURRENT_HI
OPENDET
RSTEMP
INVALID
NODATA
X
15
STG
MISO
16
-
CRC
MOSI
17
0
X
X
R
Buffer:
$5000 (RSDR0)
$5100 (RSDR1)
Reset:
SSM
Type:
WSM
50 (RSDR0)
51 (RSDR1)
POR
Address:
LCID [3:0]
18
On/Off
19
FLT=1
Bit 15 = 1 FAULTED condition
CRC[2:0] 000 000 000 CRC based on bits [16:0]
Updated based on bits [16:0]
FLT
1
1
1
Fault Status - Depending on Fault Status, the DATA bits are defined differently
Cleared when all of the following bits are '0': STG, STB, CURRENT_HI,
OPENDET, RSTEMP, NODATA
Set when any of the following bits are '1': STG, STB, CURRENT_HI,
OPENDET, RSTEMP, NODATA
0 No fault
1 Fault
On/Off
0
0
0
Channel On/Off Status
Cleared by SSM_RESET or when channel is commanded OFF via SPI
RSCTRL or when the STG bit is set or the RSTEMP bit is set
Set when channel is commanded ON by SPI RSCTRL
0 Off
94/210
DS11626 Rev 5
L9678P, L9678P-S
SPI interface
1 On
LCID[0:3] 0000 0000 0000 Logical Channel ID
Updated based on SPI read request
0000 RSU0
0100 RSU1
STG
0
0
0
Short to Ground (in current limit condition)
Cleared by SSM_RESET or when channel is commanded OFF via SPI
RSCTRL
0 No fault
1 Fault
STB
0
0
0
Short to Battery
Cleared by SSM_RESET or SPI read or when channel is commanded OFF
via SPI RSCTRL - not cleared by channel OFF caused by STG or RSTEMP
Set when channel voltage exceeds VSUP for a time greater than TSTBTH
0 No fault
1 Fault
CURRENT_HI
0
0
0
Current High
Cleared by SSM_RESET or SPI read or when channel is commanded OFF
via SPI RSCTRL
Set when channel current exceeds ILKGG for a time determined by an
up/down counter
0 No fault
1 Fault
OPENDET
0
0
0
Open Sensor Detected
Cleared by SSM_RESET or SPI read or when channel is commanded OFF
via SPI RSCTRL
Set when channel current exceeds ILKGB for a time determined by an
up/down counter
0 No fault
1 Fault
RSTEMP
0
0
0
Over temperature detected
Cleared by SSM_RESET or when channel is commanded OFF via SPI
RSCTRL
Set when over-temp condition is detected
0 No fault
1 Fault
DS11626 Rev 5
95/210
209
SPI interface
INVALID
L9678P, L9678P-S
0
0
0
Invalid Data
Cleared by SSM_RESET or SPI read or when channel is commanded OFF
via SPI RSCTRL or if one of the following is set: STG, STB, CURRENT_HI,
OPEN_DET, RSTEMP
Set when two valid start bits are received and a Manchester error (# of bits,
bit timing) or parity error is detected
0 No fault
1 Fault
NODATA
1
1
1
No Data in buffer
Cleared when a valid PSI frame is received or if one of the following is set:
STG, STB, CURRENT_HI, OPEN_DET, RSTEMP
Set upon SPI read of RSDRx if FIFO empty and none of the following bits are
set: STG, STB, CURRENT_HI, OPEN_DET, RSTEMP
0 No fault
1 Fault
96/210
DS11626 Rev 5
L9678P, L9678P-S
Safing algorithm configuration register (SAF_ALGO_CONF)
-
MISO
0
0
0
0
R/W
Buffer:
$6600
Reset:
$00CC
NO_DATA
SSM
Type:
WSM
66
14
POR
Address:
15
0
0
0
X
0
13
12
11
10
9
8
7
6
5
4
3
2
1
0
ADD_VAL ADD_VAL
16
SUB_VAL SUB_VAL
MOSI
17
ARMP_TH ARMP_TH
18
ARMN_TH ARMN_TH
19
NO_DATA NO_DATA
5.1.35
SPI interface
Event counter no data select
Updated by SSM_RESET or SPI write while in DIAG state
0 Event counter reset to 0 if CC=0 when SPI read of SAF_CC bit is
performed (end of sample cycle)
1 Event counter decremented by SUB_VAL if CC=0 when SPI read of
SAF_CC bit is performed (end of sample cycle)
ARMN_TH 0011 0011 0011 Negative event counter threshold to assert arming
Updated by SSM_RESET or SPI write while in DIAG state
0000 Negative event counter disabled
ARMP_TH 0011 0011 0011 Positive event counter threshold to assert arming
Updated by SSM_RESET or SPI write while in DIAG state
0000 Positive event counter disabled
SUB_VAL
011 011 011 Decremental step size of the event counter
Updated by SSM_RESET or SPI write while in DIAG state
ADD_VAL
001 001 001 Incremental step size of the event counter
Updated by SSM_RESET or SPI write while in DIAG state
DS11626 Rev 5
97/210
209
SPI interface
-
MISO
0
0
0
0
R
Buffer:
$6A00
Reset:
-
ACL_VALID
12
11
10
9
8
7
6
5
4
3
2
1
0
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
0
0
0
0
0
0
0
0
0
0
SSM
Type:
13
WSM
6A
14
POR
Address:
15
FENH
16
FENL
MOSI
17
ARMINT_1
18
ARMINT_2
19
ACL_VALID
Arming signals register (ARM_STATE)
ACL_PIN_STATE
5.1.36
L9678P, L9678P-S
0
0
0
Valid ACL detection
0 Cleared when ACL_BAD=2
1 Set when ACL_GOOD=3
ACL_PIN_STATE
-
-
-
Echo of ACL pin
ARMINT_x
0
0
0
State of armint signals
Updated per Safing Engine output logic diagram
FENH/FENL
-
-
-
State of external arming control signals
Updated based on pin state
98/210
DS11626 Rev 5
L9678P, L9678P-S
5.1.37
SPI interface
ARMx assignment registers (LOOP_MATRIX_ARMx)
Assignment of ARM1 to specific loops (LOOP_MATRIX_ARM1)
16
-
MISO
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
X
X
X
X
X
X
X
X
X
X
X
X
0
0
0
0
0
0
0
0
0
0
0
0
RW
Buffer:
$6E00 (LOOP_MATRIX_ARM1)
$6F00 (LOOP_MATRIX_ARM2)
Reset:
$00DC (LOOP_MATRIX_ARM1)
$00DE (LOOP_MATRIX_ARM2)
ARMx_Ly
SSM
Type:
WSM
6E (LOOP_MATRIX_ARM1)
6F (LOOP_MATRIX_ARM2)
POR
Address:
0
0
0
3
2
1
0
ARMx_L0 ARMx_L0
MOSI
17
ARMx_L1 ARMx_L1
18
ARMx_L2 ARMx_L2
19
ARMx_L3 ARMx_L3
Assignment of ARM2 to specific loops (LOOP_MATRIX_ARM2)
Configures ARMx for Loop_y
Updated by SSM_RESET or SPI write while in DIAG state
0 ARMx signal is not associated with Loopy
1 ARMx signal is associated with Loopy
DS11626 Rev 5
99/210
209
SPI interface
5.1.38
L9678P, L9678P-S
ARMx pulse stretch registers (AEPSTS_ARMx)
ARM1 enable pulse stretch timer status (AEPSTS_ARM1)
ARM2 enable pulse stretch timer status (AEPSTS_ARM2)
19
18
MOSI
MISO
17
16
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
0
0
0
0
0
0
RW
Buffer:
$7300 (AEPSTS_ARM1)
$7400 (AEPSTS_ARM2)
Reset:
- (AEPSTS_ARM1)
- (AEPSTS_ARM2)
SSM
Type:
WSM
73 (AEPSTS_ARM1)
74 (AEPSTS_ARM2)
POR
Address:
Timer Count[9:0]
Timer Count 0000 0000 0000 10-bit ARMing Enable Pulse Stretcher timer value
Cleared by SSM_RESET
Loaded with initial value based on ARMx bit and DWELL[1:0] of
SAF_CONTROL_y while safing is met for record y provided current value is <
DWELL[1:0] value
Decremented every 2ms while > 0
Contains remaining pulse stretcher timer value
100/210
DS11626 Rev 5
L9678P, L9678P-S
MOSI
17
16
-
MISO
0
0
0
0
RW
Buffer:
$7F00
Reset:
$00FE
EN_SAFx
12
11
10
9
8
7
6
5
4
X
X
X
X
X
X
X
X
X
X
X
X
0
0
0
0
0
0
0
0
SSM
Type:
13
WSM
7F
14
POR
Address:
15
0
0
0
3
2
1
0
EN_SAF1 EN_SAF1
18
EN_SAF2 EN_SAF2
19
EN_SAF3 EN_SAF3
Safing records enable register (SAF_ENABLE)
EN_SAF4 EN_SAF4
5.1.39
SPI interface
Safing Record enable
Updated by SSM_RESET or SPI write
0 Disable
1 Enable
DS11626 Rev 5
101/210
209
SPI interface
5.1.40
L9678P, L9678P-S
Safing records request mask registers (SAF_REQ_MASK_x)
Safing record request mask for record 1 (SAF_REQ_MASK_1)
Safing record request mask for record 2 (SAF_REQ_MASK_2)
Safing record request mask for record 3 (SAF_REQ_MASK_3)
Safing record request mask for record 4 (SAF_REQ_MASK_4)
19
18
MOSI
MISO
17
16
15
14
13
12
0
0
11
10
9
8
7
6
5
4
3
2
1
0
SAF_REQ_MASKx[15:0]
0
0
SAF_REQ_MASKx[15:0]
RW
Buffer:
$8000 (SAF_REQ_MASK_1)
$8100 (SAF_REQ_MASK_2)
$8200 (SAF_REQ_MASK_3)
$8300 (SAF_REQ_MASK_4)
Reset:
$8000 (SAF_REQ_MASK_1)
$8002 (SAF_REQ_MASK_2)
$8004 (SAF_REQ_MASK_3)
$8006 (SAF_REQ_MASK_4)
SSM
Type:
WSM
80 (SAF_REQ_MASK_1)
81 (SAF_REQ_MASK_2)
82 (SAF_REQ_MASK_3)
83 (SAF_REQ_MASK_4)
POR
Address:
SAF_REQ_MASKx 0000 0000 0000 Safing Request Mask for safing record x - 16-bit request mask that is bit-wise
[15:0]
ANDed with MOSI data from SPI monitor
Updated by SSM_RESET or SPI write while in DIAG state
102/210
DS11626 Rev 5
L9678P, L9678P-S
5.1.41
SPI interface
Safing records request target registers (SAF_REQ_TARGET_x)
Safing record request mask for record 1 (SAF_REQ_TARGET_1)
Safing record request mask for record 2 (SAF_REQ_TARGET_2)
Safing record request mask for record 3 (SAF_REQ_TARGET_3)
Safing record request mask for record 4 (SAF_REQ_TARGET_4)
19
18
MOSI
MISO
17
16
15
14
13
12
11
0
0
10
9
8
7
6
5
4
3
2
1
0
SAF_REQ_TARGETx[15:0]
0
0
SAF_REQ_TARGETx[15:0]
RW
Buffer:
$9300 (SAF_REQ_TARGET_1)
$9400 (SAF_REQ_TARGET_2)
$9500 (SAF_REQ_TARGET_3)
$9600(SAF_REQ_TARGET_4)
Reset:
$8026 (SAF_REQ_TARGET_1)
$8028 (SAF_REQ_TARGET_2)
$802A (SAF_REQ_TARGET_3)
$802C (SAF_REQ_TARGET_4)
SSM
Type:
WSM
93 (SAF_REQ_TARGET_1)
94 (SAF_REQ_TARGET_2)
95 (SAF_REQ_TARGET_3)
96 (SAF_REQ_TARGET_4)
POR
Address:
SAF_REQ_TARGETx 0000 0000 0000 Safing Request target for safing record x - 16-bit request target that is
[15:0]
compared to the bit-wise AND result of the SAF_REQ_MASKx and MOSI
data from SPI monitor
Updated by SSM_RESET or SPI write while in DIAG state
DS11626 Rev 5
103/210
209
SPI interface
5.1.42
L9678P, L9678P-S
Safing records response mask registers (SAF_RESP_MASK_x)
Safing record response mask for record 1 (SAF_RESP_MASK_1)
Safing record response mask for record 2 (SAF_RESP_MASK_2)
Safing record response mask for record 3 (SAF_RESP_MASK_3)
Safing record response mask for record 4 (SAF_RESP_MASK_4)
19
18
MOSI
MISO
17
16
15
14
13
12
11
0
0
10
9
8
7
6
5
4
3
2
1
0
SAF_RESP_MASKx[15:0]
0
0
SAF_RESP_MASKx[15:0]
RW
Buffer:
$A600 (SAF_RESP_MASK_1)
$A700 (SAF_RESP_MASK_2)
$A800 (SAF_RESP_MASK_3)
$A900 (SAF_RESP_MASK_4)
Reset:
$804C (SAF_RESP_MASK_1)
$804E (SAF_RESP_MASK_2)
$8050 (SAF_RESP_MASK_3)
$8052 (SAF_RESP_MASK_4)
SSM
Type:
WSM
A6 (SAF_RESP_MASK_1)
A7 (SAF_RESP_MASK_2)
A8 (SAF_RESP_MASK_3)
A9 (SAF_RESP_MASK_4)
POR
Address:
SAF_RESP_MASKx 0000 0000 0000 Safing Response Mask for safing record x - 16-bit response mask that is bit[15:0]
wise ANDed with MISO data from SPI monitor
Updated by SSM_RESET or SPI write while in DIAG state
104/210
DS11626 Rev 5
L9678P, L9678P-S
5.1.43
SPI interface
Safing records response target registers (SAF_RESP_TARGET_x)
Safing record response target for record 1 (SAF_RESP_TARGET_1)
Safing record response mask for record 2 (SAF_RESP_TARGET_2)
Safing record response mask for record 3 (SAF_RESP_TARGET_3)
Safing record response mask for record 4 (SAF_RESP_TARGET_4)
19
18
0
0
MOSI
MISO
17
16
0
0
15
14
13
12
11
-
10
9
8
7
6
5
4
3
2
1
0
SAF_RESP_TARGETx[15:0]
SAF_RESP_TARGETx[15:0]
RW
Buffer:
$B900 (SAF_RESP_TARGET_1)
$BA00 (SAF_RESP_TARGET_2)
$BB00 (SAF_RESP_TARGET_3)
$BC00 (SAF_RESP_TARGET_4)
Reset:
$8072 (SAF_RESP_TARGET_1)
$8074 (SAF_RESP_TARGET_2)
$8076 (SAF_RESP_TARGET_3)
$8078 (SAF_RESP_TARGET_4)
SSM
Type:
WSM
B9 (SAF_RESP_TARGET_1)
BA (SAF_RESP_TARGET_2)
BB (SAF_RESP_TARGET_3)
BC (SAF_RESP_TARGET_4)
POR
Address:
SAF_RESP_TARGETx 0000 0000 0000 Safing Response target for safing record x - 16-bit response target that is
[15:0]
compared to the bit-wise AND result of the SAF_RESP_MASKx and MISO
data from SPI monitor
Updated by SSM_RESET or SPI write while in DIAG state
DS11626 Rev 5
105/210
209
SPI interface
5.1.44
L9678P, L9678P-S
Safing records data mask registers (SAF_DATA_MASK_x)
Safing record data mask for record 1 (SAF_DATA_MASK_1)
Safing record data mask for record 2 (SAF_DATA_MASK_2)
Safing record data mask for record 3 (SAF_DATA_MASK_3)
Safing record data mask for record 4 (SAF_DATA_MASK_4)
19
18
0
0
MOSI
MISO
17
16
0
0
15
14
13
12
11
-
10
9
8
7
6
5
4
3
2
1
SAF_DATA_MASKx[15:0]
SAF_DATA_MASKx[15:0]
RW
Buffer:
$CC00 (SAF_DATA_MASK_1)
$CD00 (SAF_DATA_MASK_2)
$CE00 (SAF_DATA_MASK_3)
$CF00 (SAF_DATA_MASK_4)
Reset:
$8098 (SAF_DATA_MASK_1)
$809A (SAF_DATA_MASK_2)
$809C (SAF_DATA_MASK_3)
$809E (SAF_DATA_MASK_4)
SSM
Type:
WSM
CC (SAF_DATA_MASK_1)
CD (SAF_DATA_MASK_2)
CE (SAF_DATA_MASK_3)
CF (SAF_DATA_MASK_4)
POR
Address:
SAF_DATA_MASKx[ 0000 0000 0000 Safing Data Mask for safing record x - 16-bit data mask that is bit-wise
15:0]
ANDed with MISO data from SPI monitor
Updated by SSM_RESET or SPI write while in DIAG state
106/210
DS11626 Rev 5
0
L9678P, L9678P-S
5.1.45
SPI interface
Safing records threshold registers (SAF_THRESHOLD_x)
Safing record threshold for record 1 (SAF_THRESHOLD_1)
Safing record threshold for record 2 (SAF_THRESHOLD_2)
Safing record threshold for record 3 (SAF_THRESHOLD_3)
Safing record threshold for record 4 (SAF_THRESHOLD_4)
19
18
0
0
MOSI
MISO
17
16
0
0
15
14
13
12
11
-
10
9
8
7
6
5
4
3
2
1
0
SAF_THRESHOLDx[15:0]
SAF_THRESHOLDx[15:0]
RW
Buffer:
$DF00 (SAF_THRESHOLD_1)
$E000 (SAF_THRESHOLD_2)
$E100 (SAF_THRESHOLD_3)
$E200 (SAF_THRESHOLD_4)
Reset:
$80BE (SAF_THRESHOLD_1)
$80C0 (SAF_THRESHOLD_2)
$80C2 (SAF_THRESHOLD_3)
$80C4 (SAF_THRESHOLD_4)
SSM
Type:
WSM
DF (SAF_THRESHOLD_1)
E0 (SAF_THRESHOLD_2)
E1 (SAF_THRESHOLD_3)
E2 (SAF_THRESHOLD_4)
POR
Address:
SAF_THRESHOLDx $FFFF$FFFF $FFFF Safing threshold for safing record x - 16-bit threshold used for safing data
[15:0]
comparison
Updated by SSM_RESET or SPI write while in DIAG state
DS11626 Rev 5
107/210
209
SPI interface
5.1.46
L9678P, L9678P-S
Safing control registers (SAF_CONTROL_x)
Safing control register for record 1 (SAF_CONTROL_1)
Safing control register for record 2 (SAF_CONTROL_2)
Safing control register for record 3 (SAF_CONTROL_3)
RW
Buffer:
$EF00 (SAF_CONTROL_1)
$F000 (SAF_CONTROL_2)
$F100 (SAF_CONTROL_3)
$F200 (SAF_CONTROL_4)
Reset:
$80DE (SAF_CONTROL_1)
$80E0 (SAF_CONTROL_2)
$80E2 (SAF_CONTROL_3)
$80E4 (SAF_CONTROL_4)
ARMSELx
6
X
X
ARM2x
ARM1x
CSx[2:0]
IFx
0
0
ARM1x
CSx[2:0]
IFx
5
4
3
2
1
0
SSM
Type:
7
WSM
$EF (SAF_CONTROL_1)
$F0 (SAF_CONTROL_2)
$F1 (SAF_CONTROL_3)
$F2 (SAF_CONTROL_4)
8
POR
Address:
9
ARM2x
10
DWELLx[1:0] DWELLx[1:0]
0
11
COMBx
0
12
COMBx
0
13
LIM Enx
0
14
LIM Enx
-
MISO
15
LIM SELx
16
SPIFLDSELx SPIFLDSELx
MOSI
17
ARMSELx
18
ARMSELx
19
LIM SELx
Safing control register for record 4 (SAF_CONTROL_4)
00
00
00 ARMINT select for safing record x - correlates ARMINT 1 and ARMINT2 (as
determined by ARM1x and ARM2x bits) to ARMP and ARMN
Updated by SSM_RESET or SPI write while in DIAG state
00 ARMP OR ARMN
01 ARMP
10 ARMN
11 ARMP OR ARMN
SPIFLDSELx
108/210
0
0
0
SPI field select for safing record x - determines which 16-bit field in long SPI
messages (>31 bit) to use for response on MISO of SPI monitor. In case of
messages less than 32 bits this bit is don't care.
DS11626 Rev 5
L9678P, L9678P-S
SPI interface
Updated by SSM_RESET or SPI write while in DIAG state
0 First 16 bits of SPI MISO frame used for Response Mask and Data
Mask bit-wise AND
1 Last 16 bits of SPI MISO frame used for Response Mask and Data
Mask bit-wise AND
LIM SELx
0
0
0
Data range limit select for safing record x - When enabled, determines the
range limit used for incoming sensor data
Updated by SSM_RESET or SPI write while in DIAG state
0 8-bit data range limit - incoming |data| >120d is not recognized as valid
data
1 10-bit data range limit - incoming |data| > 480d is not recognized as
valid data
LIM Enx
0
0
0
Data range limit enable for safing record x
Updated by SSM_RESET or SPI write while in DIAG state
0 Data range limit disabled
1 Data range limit enabled
COMBx
0
0
0
Combine function enable for safing record x
Updated by SSM_RESET or SPI write while in DIAG state
0 Combine function disabled
1 Combine function enabled
For record pairs = x,x+1, the comparison for record x uses |data(x) +
data(x+1)| and the comparison for record x+1 uses |data(x) - data(x+1)|
Record pairs are 1,2 and 6,7
DWELLx[1:0]
00
00
00 Safing dwell extension time select for safing record x
Updated by SSM_RESET or SPI write while in DIAG state
00 2048 ms
01 256 ms
10 32 ms
11 0 ms
ARM2x
0
0
0
ARM2INT select for safing record x - correlates safing result to ARM2INT
Updated by SSM_RESET or SPI write while in DIAG state
0 Safing record x not assigned to ARM2INT
1 Safing record x assigned to ARM2INT
ARM1x
0
0
0
ARM1INT select for safing record x - correlates safing result to ARM1INT
Updated by SSM_RESET or SPI write while in DIAG state
DS11626 Rev 5
109/210
209
SPI interface
L9678P, L9678P-S
0 Safing record x not assigned to ARM1INT
1 Safing record x assigned to ARM1INT
CSx[2:0]
000 000 000 SPI Monitor CS select for safing record x
Updated by SSM_RESET or SPI write while in DIAG state
000 None selected for record x
001 SAF_CS0 selected for record x
010 SAF_CS1 selected for record x
011 None selected for record x
100 None selected for record x
101 SPI_CS selected for record x
110 None selected for record x
111 None selected for record x
IFx
0
0
0
SPI format select for safing record x - selects response protocol for SPI
monitor
Updated by SSM_RESET or SPI write while in DIAG state
0 Out of frame response for record x
1 In Frame response for record x
110/210
DS11626 Rev 5
L9678P, L9678P-S
5.1.47
Safing record compare complete register (SAF_CC)
19
18
0
0
MOSI
MISO
SPI interface
17
16
0
0
-
R
Buffer:
$FF00
Reset:
-
CC_xx
12
11
10
9
8
7
6
5
4
X
X
X
X
X
X
X
X
X
X
X
X
0
0
0
0
0
0
0
0
0
0
0
0
SSM
Type:
13
WSM
FF
14
POR
Address:
15
0
0
0
3
2
1
0
X
X
X
X
CC_4 CC_3 CC_2 CC_1
Indicates compare complete status of each of the 4 safing records, and
defines the end of the sample cycle for safing
Cleared by SSM_RESET or SPI read, set by safing engine when request,
response mask and target registers match the incoming SPI frame
0 Compare not completed for record x
1 Compare completed for record x
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Deployment drivers
6
L9678P, L9678P-S
Deployment drivers
The squib/pyroswitch deployment block consists of 4 independent high side drivers and 4
independent low side drivers. Squib/pyroswitch deployment logic requires a deploy
command received through SPI communications and either an arming condition processed
by safing logic or a proper FENH and FENL input pin assessment, depending on whether
the internal safing engine is used or not. FENH signal is used to enable high side
squib/pyroswitch drivers and is active high, while FENL enables low side drivers and is
active low. Both conditions must exist in order for the deployment to occur. Once a
deployment is initiated, it can only be terminated by a RESET event.
L9678P allows all 4 squib/pyroswitch loops to be deployed at the very same time or in other
possible timing sequence. Deployment drivers are capable of granting a successful
deployment also in case of short to ground on low-side circuit (SRx pins). Firing voltage
capability across high side circuit is maximum 25 V. High side and low side drivers account
for a maximum series total resistance of 2 Ω. Each loop is granted for a minimum number of
deployments of 50, under all normal operating conditions and with a deployment repetition
time higher than 10s.
6.1
Control logic
A block diagram representing the deployment driver logic is shown below. Deployment
driver logic features include:
Deploy command logic
Deployment current selection
Deployment current monitoring and deploy success feedback
Diagnostic control and feedback
Figure 20. Deployment driver control blocks
DCR
Deployment Configuration
Register
DEPCOM
Deployment
Command Register
Deploy
Request
Validation
FENH X
High
Side
FET
X SFx
DCMTSx
Deploy Current
Monitor Status
Deployment
Control &
Timing
intclk
ITHDEPL
DCR
DCR
Deployment
Configuration
Register
Int/Ext safing engine
Current
Monitor
DSRx
Deployment
Configuration
Register
Deployment Status
Register
Low
Side
FET
FENL X
X SRx
ARM X
Safing Engine
Programmable
Loop
Assignments
Int/Ext safing engine
GAPGPS01124
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DS11626 Rev 5
L9678P, L9678P-S
Deployment drivers
Figure 21. Deployment driver control logic - Enable signal
ARMING STATE
Analog
DIAG STATE
Deployment
LPDIAGREQ(LEAK_CHSELx)
DSTEST(HSFET_TEST)
Block
SAFESEL
FENH
ENABLE_HSx
ARM1INT
ARM1_Lx
ARM2INT
ARM2_Lx
FENL
SAFING STATE
ARM_EN
ENABLE_LSx
DIAG STATE
LPDIAGREQ(LEAK_CHSELx)
DSTEST(LSFET_TEST)
GAPGPS01656
Figure 22. Deployment driver control logic - Turn-on signals
ARMING STATE
Expiration
Timer
SAFING STATE
DEP_ENABLED STATE
S
UpCtr
EXP_Thresh
EN
SPI_DEPREQx
R
SSM RESET
DEP_DISABLED STATE
=
CLR
CHxDEP
CHxSTAT
S
R
DEP_Thresh
UpCtr
ENABLE_HSx
ENABLE_LSx
S
DIAG STAT E
DSTEST(PULSE)
R
=
EN
CLR
LS_OVER_CURx
GND_LOSSx
Deploy
Timer
SSM RESET
S
S
CHxDS
R
R
HS_ONx
DSTEST(HSFET_TEST)
LPDIAGREQ(LEAK_CHSELx)
LS_ONx
DSTEST(LSFET_TEST)
ANALOG
Deployment BLOCK
GAPGPS01641
The high level block diagram for the deployment drivers is shown below:
DS11626 Rev 5
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Deployment drivers
L9678P, L9678P-S
Figure 23. Deployment driver block
SSxy
R/2000
(50mΩ)
95%R
OP with switching
Offset compensation
Enable_HSx
5%R
+
OPphase
OPphase
+
R
2000 x IREF
-
SFx
Open to short comp
22nF
To deploy
current >90%
counter
Rsquib
SRx
Vclamp >35V
Ipulldown
3V3
HS_OFF
22nF
Same power
transistor
LS_ON
IREF= 1mA
EN_ISINK
Ilimit > 3A typ
+
Enable_LSx
LS_OC_Comp
-
Ilimit = 70mA typ
SGxy
+
Loss ground
diode
LS_Loss _Gnd
-
GNDSUB1&2
GAPGPS01126
6.1.1
Deployment current selection
Deployment current is programmed for all channels using the Deploy Configuration Register
(DCRx) shown in “Deployment Configuration register (DCRx).
If 1.75 A deployment current is selected, the 2 ms deployment time cannot be chosen. If a
SPI command with 2 ms and 1.75 A selection is received, L9678P will discard it and switch
to a 500 µs and 1.2 A selection instead. This misuse is flagged with the CHxDD bit in the
Deploy Status Register (DSR).
6.1.2
Deploy command expiration timer
Deploy commands are received for all channels using SPI communications. Once a deploy
command is received, it will remain valid for a specified time period selected in the Deploy
Configuration Register (DCRx). The deploy status and deploy expiration timer can be read
through the Deploy Status Register (DSRx). The deploy expiration timer is 6 bits and the
maximum time is 500 ms nominal.
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DS11626 Rev 5
L9678P, L9678P-S
6.1.3
Deployment drivers
Deployment control flow
Deployment control logic requires the following conditions to be true to successfully operate
a deployment:
POR = 1
SSM to be either in Safing State or Arming State
a valid arming condition processed by safing logic or FENH and FENL signals to be set
(depending on selection of internal or external safing engine)
"channel-specific deploy command request bits to be set via SPI in the Deploy
command Register (DEPCOM)
a global deployment state has to be active, as described in the following figure.
Figure 24. Global SPI deployment enable state diagram
SSM_Reset
DEP_DISABLED
SPI_SPIDEPEN(DEPEN_WR)
=
UNLOCK
SPI_SPIDEPEN(DEPEN_WR)
=
LOCK
DEP_ENABLED
GAPGPS01127
In case a multiple deployment request would be needed, i.e. deploying the same channel in
sequence, a toggle on DEP_DISABLED has to be performed and a new DEPCOM
command on the same channel has to be sent.
The SPI DEPCOM command is ignored if the device is in the DEP_DISABLED state and the
deploy command is not set. While in DEP_ENABLED state, the following functionalities that
could be active are forced to their reset state:
All squib/pyroswitch and DC sensor diagnostic current or voltage sources
All squib/pyroswitch, DC sensor and ADC diagnostic mux settings, state machine, etc.
The SPI_LOCK and SPI_UNLOCK signals are available in the SPIDEPEN command:
High-side and Low-side enablers by internal/external safing are global and apply to all
channels. The Deploy commands in the Deploy Command Register (DEPCOM) are channel
specific.
Deployment requires a valid arming command from safing logic or the FENH and FENL
signals to be set any time before, during or after the specific sequence of deploy commands
is received. It is feasible for a deploy command to be received without a valid arming
command from safing logic or the FENH and FENL being set. In this case, the deploy
command will be terminated according to the Deploy Command Expiration Timer described
in Section 6.1.2. Likewise, a valid arming command or the FENH and FENL signals can be
set without receiving a Deploy Command. In this case, the enabling signals will remain
active according to the Arming Enable Pulse Stretch Timer or the FENx enabling state. The
Arming Enable Pulse Stretch Timers is available in the AEPSTS register.
DS11626 Rev 5
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Deployment drivers
6.1.4
L9678P, L9678P-S
Deployment success
Deploy success flag is set when the deploy timer elapses. This bit (CHxDS) is contained in
the Deploy Status Register. Within the Global Status Word register (GSW), a single bit
(DEPOK) is also set once any of the four deployment channels sets a deploy success flag.
6.2
Energy reserve - deployment voltage
One deployment voltage source pin is used for channels 0 and 1 (SS01) and one for
channels 2 and 3 (SS23). These pins are directly connected to the high side drivers for each
channel.
6.3
Deployment ground return
There are dedicated power ground connections for deployment current, SGx pins. One
ground connection is sufficient for two deployments occurring simultaneously.
6.4
Deployment driver protections
6.4.1
Delayed low-side deactivation
To control voltage spikes at the squib/pyroswitch pins during drivers deactivation at the end
of a deployment, the low side driver is switched off after tDEL_SD_LS delay time with respect
to the high side deactivation.
6.4.2
Low-side voltage clamp
The low side driver is protected against overvoltage at the SRx pins by means of a clamping
structure as shown in Figure 23. When the Low side driver is turned off, voltage transients at
the SRx pin may be caused by squib/pyroswitch inductance. In this case a low side FET
drain to gate clamp will reactivate the low side FET allowing for residual inductance current
recirculation, thus preventing potential low side FET damage by overvoltage.
6.4.3
Short to battery
The low side driver is equipped with current limitation and overcurrent protection circuitry. In
case of short to battery at the squib/pyroswitch pins, the short circuit current is limited by the
Low side driver to ILIM_SR. If this condition lasts for longer than TFLT_ILIM_LS deglitch filter
time then the low and high-side drivers will be switched off and latched in this state until a
new deployment is commanded after SPI_DEPEN is re triggered.
6.4.4
Short to ground
The squib/pyroswitch driver is designed to stand a short to ground at the squib/pyroswitch
pins during deployment. In particular, the current flowing through the short circuit is limited
by the high side driver (deployment current) and the high-side FET is sized to handle the
related energy.
In case the short to ground during deployment occurs after an open circuit, a protection
against damage is also available. The high side current regulator would have normally
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L9678P, L9678P-S
Deployment drivers
reacted to the open circuit by increasing the Vgs of the high side FET. Thanks to a dedicated
fast comparator detecting the open condition, the driver is able to discharge the FET gate
quickly in order to reduce current overshoot and prevent potential driver damage when the
short to ground occurs.
6.4.5
Intermittent open squib/pyroswitch
A dedicated protection is also available in case of intermittent open load during deployment.
In this case, if load is restored after an open circuit, due to slow reaction of the high-side
current regulation loop, the current through the squib/pyroswitch is limited only to ILIMSRx by
the low side driver. If this condition lasts for longer than tLIMOS then the high side is turned
off for tHSOFFOS and then reactivated. By this feature, intermittent open squib/pyroswitch
and short to battery faults may be distinguished and handled properly by the drivers.
6.5
Diagnostics
The L9678P provides the following diagnostic feedback for all deployment channels:
High voltage leakage test for oxide isolation check on SFx and SRx
Leakage to battery and ground on both SFx and SRx pins with or without a
squib/pyroswitch
Loop to loop short diagnostics
Squib/pyroswitch resistance measurement with leakage cancellation
High squib/pyroswitch resistance with range from 500 Ω to 2000 Ω
SSxy, SFx and VER voltage status
High and low side FET diagnostics
High side driver diagnostics
Loss of ground return diagnostics
High side safing FET diagnostics
Deployment Timer diagnostic
The above diagnostic results are processed through a 10 bit Analog to digital algorithmic
converter. These tests can be addressed in two different ways, with a high level approach or
a low-level one. The main difference between the two approaches is that with the low level
approach the user is allowed to precisely control the diagnostic circuitry, also deciding the
proper timings involved in the different tests. On the other hand, the high level approach is
an automatic way of getting diagnostic results for which an internal state machine is taking
care of instructions and timings.
The following is the block diagram of the squib/pyroswitch diagnostics.
DS11626 Rev 5
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Deployment drivers
L9678P, L9678P-S
Figure 25. Deployment loop diagnostics
VER pin
(from Energy Reserve)
Safing
transistor
VRESDIAG
ISRC
40mA
SSxy
Bypass
1nF
Squib resistance measure
(system error < 8%)
Vgnd or
VBat
SFx
RLeak
Vref =2v5
22nF
xN
A to D
Squib loop
driver and
diagnostic
blocks
Rsquib
1Ω to 10Ω
+
Vout
10bit
Tot err = ±4LSB
LSB = 2.5/1024 V
Voffset
HV analog MUX
Gain = 5.25
Vgnd or
VBat
SRx
Squib resistor HIGH
Ipulldown
I=1mA
Squib resistor LOW
Short to GND
Rleak >10K Ω no detection
Rleak 10K Ω no detection
Rleak > Rsq)
G I src
where:
G = differential amplifier gain.
The simplification in the calculation method reported above can result in some amount of
error that is already incorporated in the overall tolerance of the squib/pyroswitch resistance
measurement reported in the electrical parameters table.
120/210
DS11626 Rev 5
L9678P, L9678P-S
Deployment drivers
Values of each measurement step can be required addressing the proper ADCREQx code
in the Diagnostic Control command (DIAGCTRL) on Table 10: Diagnostics control register
(DIAGCTRLx) on page 161.
This calculation is tolerant to leakages and, thanks to a dedicated EMI low-pass filter, also to
high frequency noises on squib/pyroswitch lines. Moreover, L9678P features a slew rate
control on the ISRC current generator to mitigate emissions.
High squib/pyroswitch resistance diagnostics
With this test, the device is able to understand if the squib/pyroswitch resistance value is
below 200 Ω, between 500 Ω and 2000 Ω or beyond 5000 Ω. During a high
squib/pyroswitch resistance diagnostics, VRCM and ISNK are enabled and connected
respectively to SFx and SRx on the selected channel. VREF voltage level outputs on SFx.
Current flowing on SFx is measured and compared to ISRlow and ISRhigh thresholds to
identify if the resistance is above or below RSRlow or RSRhigh levels. The results are reported
in the LPDIAGSTAT register. The relative flags (HSR_HI and HSR_LO) are not latched and
reflect the current status of the comparators.
High and low side FET diagnostics
This couple of tests can only be run during the diagnostic mode of the power-up sequence
(Figure 9). Tests are performed individually for HS driver or LS driver, with two dedicated
commands. Prior to either the HS or LS FET diagnostics being run, the VRCM has to be first
enabled. Within the command to enable the VRCM, also the channel onto which the FET
test will be run has to be selected with the LEAK_CHSEL bit field. Running the leakage
diagnostics with the appropriate delay time prior to either the HS or LS FET diagnostics will
precondition the squib/pyroswitch pin to the appropriate voltage level. When the FET
diagnostic command is issued with the Diagnostic Register SPI command (SYSDIAGREQ),
the VRCM flags will be cleared.
The device monitors the current through the VRCM. If the FET is working properly, this
current will exceed ISTB (HS test) or ISTG (LS test) and the driver under test is turned off
immediately. If the current does not exceed ISTB or ISTG then the test will be terminated and
the output is anyway turned off within TFETTIMEOUT. During TFETTIMEOUT period, the bit
stating that the FET is enabled will be set (FETON=1) and will be cleared as soon as the
FET is switched back off.
For all conditions the current on SFx/SRx will not exceed ILIM_VRCM_X, the VRCM block
current limitation value. There may be higher currents on the squib/pyroswitch lines due to
the presence of filter capacitors. During these FET tests, energy available to the
squib/pyroswitch is limited to less than EFETtest.
For high side FET diagnostics, if no faults were indicated in the preceding leakage
diagnostics then a normal result would be [STB=1, STG=0]. If the returned result for the
high side FET test is not as the previous then either the FET is not functional, a short to
ground occurred during the test, or there is a missing SSxy connection for that channel.
For low side FET diagnostics if no faults were indicated in the preceding leakage
diagnostics then a normal result would be [STB=0, STG=1]. If the returned result for the low
side FET test is not as the previous one then either the FET is not functional or a short to
battery occurred during the test. In case of SGx loss the low-side FET diagnostic would not
indicate a FETfault.
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Deployment drivers
L9678P, L9678P-S
The VRCM flags will be given in the LPDIAGSTAT register. The status of the VRCM flags
after FET test is latched and can be cleared upon either LPDIAGREQ or SYSDIAGREQ SPI
commands.
Loss of ground return diagnostics
This diagnostics is available during a squib/pyroswitch measurement or a high side driver
diagnostics. This test is based on the voltage drop across the ground return, if the voltage
drop exceeds VSGopen, ground connection is considered as lost. Should the ground
connection on the squib/pyroswitch driver circuit be missing, the bit related to the channel
under test by the two above diagnostics will be activated in the LP_GNDLOSS register. The
flag is latched after a proper filter time tSGopen and cleared upon read.
High side safing FET diagnostics
This test has to be issued during the Diag state of the power-up sequence (Figure 9). Safing
FET has to be switched on with the proper code in DSTEST bit field of the SYSDIAGREQ.
Therefore, when the command is received, the device activates VSF regulator to supply the
external safing FET controller. The user can measure the voltage levels of both the VSF
regulator and the SSxy nodes. If the safing FET is properly switched on, the voltage on
SSxy is regulated.
The measurement request is done via Diagnostic Control command (DIAGCTRLx), while
results are reported through ADCRESx bit fields, as shown in Table 10.
Deployment timer diagnostic
This test allows verifying the correct functionality and duration of the timers used to control
the deployment times. This test can be executed only when the IC is in the Diag state by
setting the appropriate code in the DSTEST field of the SYSDIAGREQ register. When the
test is launched, the IC sequentially triggers the activation of the deployment timers of the
various channels (each of them separated by 8ms idle time) and outputs the relevant
waveform to the ARM output discrete pin. See the sequence detail in Figure 27. The MCU
can therefore test the deployment times by measuring the duration of the high pulses sent
by the IC on the ARM pin. The deployment time configuration used during this test is the
latest one programmed in the DCRx registers. In case the test is run on a channel with no
DCRx deployment time previously configured, a default 8us high pulse is output on ARM for
the relevant channel.
122/210
DS11626 Rev 5
L9678P, L9678P-S
Deployment drivers
Figure 27. Deployment timer diagnostic sequence
From any state:
DIAG state & SPI_SYSREQ(DSTEST=PULSE) /
PULSE_TESTx=0
PT_TMR=8ms /
PT_TMR=0
PULSE_TESTx=0
PULSE_TEST1=1
PT_WAIT
SSM_RESET /
PULSE_TESTx=0
PT1
PT_TMR=8ms /
PT_TMR=0
PULSE_TESTx=0
PULSE_TEST2=1
PT_OFF
PT2
PT_TMR=8ms /
PULSE_TESTx=0
PT_TMR=8ms /
PT_TMR=0
PULSE_TESTx=0
PULSE_TEST3=1
PT4
PT3
PT_TMR=8ms /
PT_TMR=0
PULSE_TESTx=0
PULSE_TEST4=1
GAPGPS01995
Loop diagnostics control and results registers
Diagnostic tests and channels for each test are controlled through the Loop Diagnostic
Request Register (LPDIAGREQ), diagnostic results are stored in the Loop Diagnostic
Status Register (LPDIAGSTAT).
6.5.2
High level diagnostic approach
In this approach, the test steps described in the sections below are coded into a dedicated
state machine that helps reducing the user intervention to a minimum.
The high-level diagnostic commands are contained in the LPDIAGREQ, LOOP_DIAG_SEL,
and LOOP_DIAG_CHSEL registers. These settings are described in the SPI Table for these
commands in Read/write register.
The high-level diagnostic response is available in the LPDIAGSTAT register. These are
described in the SPI Table for this command in Read/write register.
The concept is depicted in the following figures.
DS11626 Rev 5
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Deployment drivers
L9678P, L9678P-S
Figure 28. High level loop diagnostic flow1
Low level diagnostic is selected (bit 15
of LPDIAGREQ is low) OR an invalid
high level diagnostic is selected OR we
are in DEP_ENABLED state
TIP = 0
Leakage test time elapsed
SBL flag is asserted if STG
is no more present
Leakage is detected (due to
the fact that FETs work
properly) OR FET test
timeout elapsed
DIAG_OFF
New high level diagnostic request
(bit 15 of LPDIAGREQ is high)
VRCM (check time elapsed
AND ((VRCM, CHECK test)
is selected OR VRCM fails)
TIP = 1
Wait enaugh time to
be sure that all
currents and voltages
supplies start in OFF state
WAIT_OFF
Off time = 24μs
Latch STB, STG flags
FP = 1 if LEAKAGE or
FET T tests are selected
Off time elapsed AND new
diagnostic request is
VRCM_CHECK OR
LEAKAGE OR SBL OR
FET tests
VRCM_CHECK
FET TEST
TIP = 1
FET test timeout = 200μs
Enable VRCM
Disable ISRC and ISINK
Enable HS or LS FET if also
DSTEST = 0111 or 1000
Leakage test time elapsed
AND (FET test is selected)
AND NO leakage is present
Leakage test time elapsed
AND ((LEAKAGE test) OR
(SBL and no leakage is
present) OR (FET test and
leakage is present))
Latch STB, STG flags
FP = 1 if FET test is selected
TIP = 1
LEAKAGE_TEST_2
Enable VRCM
Disable ISRC and Leakage test time = 152/600μs
ISINK
Disable ALL pull
down currents
VRCM check time = 40μs/160μs
TIP = 1
Enable VRCM
Disable ISRC and ISINK
Leakage test time elapsed
AND (SBL is selected)
AND leakage is present
LEAKAGE_TEST_1
Leakage test time = 152/600μs
TIP = 1
Enable VRCM
Disable ISRC and ISINK
GAPGPS01643
124/210
DS11626 Rev 5
L9678P, L9678P-S
Deployment drivers
Figure 29. High level loop diagnostic flow2
Low level diagnostic is selected (bit 15
of LPDIAGREQ is low) OR an invalid
high level diagnostic is selected OR we
are in DEP_ENABLED state
End of conversion
Store result in ADCRESB
DIAG_OFF
TIP = 0
Resistance range test time elapsed
Latch HSR_HI, HSR_LO flags
SQUIB RES RANGE
TEST
New high level diagnostic request
(bit 15 of LPDIAGREQ is high)
Off time elapsed AND new
diagnostic request is SQUIB
RESISTANCE RANGE test
TIP = 1
Wait enough time to
be sure that all
currents and voltages
supplies start in OFF state
WAIT_OFF
Resistance range test
setting time = 152μs/600μs
TIP = 1
Enable VRCM
Enable ISINK
Off time = 24μs
Off time elapsed AND new
diagnostic request is
SQUIB RESISTANCE measure test
SQUIB RES MEAS
CONV1
SQUIB RES MEAS
CONV12
End of conversion
Store result in ADCRESA
End of setting time
End of setting time
SQUIB RES MEAS
SETTLE1
TIP = 1
Enable ISRC on SFx
Enable ISINK
Resistance test
setting time = 304μs/1200μs
SQUIB RES MEAS
SETTLE2
TIP = 1
Resistance test
Enable ISINK
setting time = 304μs/1200μs
Enable ISRC
BYPASS ISRC on SRx
GAPGPS01644
DS11626 Rev 5
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Remote sensor interface
7
L9678P, L9678P-S
Remote sensor interface
The L9678P-S contains 2 remote sensor interfaces, capable of supporting PSI-5 protocol
(standard voltage range). A block diagram of the interface is shown below. The circuitry
consists of a power interface that demodulates current flowing in the external sensor and
transmits these current states to the decoder, which produces a digital value for each
satellite channel. Data are then output through the Remote Sensor Data Registers
(RSDRx). The power interface also contains error detection circuitry. When a fault is
detected, the error code is stored in a global SPI data buffer in the Remote Sensor Data
Registers (RSDRx).
Figure 30. Remote sensor interface logic blocks
Remote Sensor Configuration Reg.(RSCR)
Remote Sensor Data Reg.X (RSDRx)
Manchester
Decoder &
Fault
Detection
Power &
Input
Protection
X
RSUx
Remote Sensor Fault Status Reg.(RSFSR)
Fault Status Reg.(FLTSR)
GAPGPS01130
The Remote Sensor Configuration Registers (RSCRx) allow for configuration of the
particular PSI5 protocol adopted by the sensor and the transceiver current limit blanking
time.
The Remote Sensor Control Register (RSCTRL) allows for interface channels to be
switched on and off via SPI.
RSU interface has 2 registers per channel, which can report either data or fault information,
that can be readout by sending 2 consecutive Read commands of the Remote Sensor Data
Register (RSDRx). It is a FIFO, so the first SPI reading contains the oldest received data
and the next SPI reading contains the most recent one. SPI accesses both from the same
address, i.e. the MCU should do 2 reads of the same RID to get both data samples. The
couple of registers will retain only the last two received messages, regardless they have
been qualified as valid or invalid data. In case of driver fault (Short to Ground, Short to
Battery, Over-current, Open detection, Over-temperature) any message is lost. To re-start a
correct reception of messages, it is needed to have no more fault present and fault flag read
by MCU.
If the device detects an error on the sensor interface, the fault bit in RSDRx (FLTBIT) will be
set to '1' and the following bits will be used to report the detected errors. Otherwise, the
register will contain only data information. Detailed information on data and fault reporting
are explained in the following sections.
When a fault condition is detected, the RSFLT bit of the global status word (GSW) is set to
1, except in the case the register is empty for which NODATA fault bit will be set instead.
Data are cleared upon reading the RSDRx register.
RSU interface is supplied by VSUP regulator as showed in Figure 31. To avoid a too low
RSU output voltage in case of battery loss, the upper VINGOOD and VBATMOND
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DS11626 Rev 5
L9678P, L9678P-S
Remote sensor interface
thresholds must be selected. In this way the device will detect the battery loss condition in
time to guarantee the minimum RSU output voltage required.
Figure 31. Remote sensor interface block diagram
VSUP
500
5
+
-
+
-
+
RSU_OC
RSU_STB
Short to
VBAT
comp
+
2500
+
Short to
GND
comp
20mV
VREF
+
RSU_Enable
-
EMI filter
ISAT
RSUx
ISAT/100
2Ω5
2n 2F
33nF
RXSATSYNC
or
COMPBASEOUT
I base
fsample
SAT
Up/Down
counter
Digital word = Satellite
Base current
7bits
I threshold
PSI5 current comparator
7.1
GAPGPS01131
PSI-5 protocol
All channels are compliant to the PSI-5 v1.3 specification as described below:
Two-wire current interface
Manchester coded digital data transmission
High data transmission speeds of 125 kbps and 189 kbps
Variable data word length (8 & 10 bit only)
1-bit parity
Asynchronous operation mode
DS11626 Rev 5
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Remote sensor interface
L9678P, L9678P-S
An example of the data format for one possible PSI-5 protocol configuration is shown below.
Data size may vary, but the presence of 2 sync start bits (referenced below as sync bits) and
TGap time is consistent regardless the data size.
Figure 32. PSI-5 remote sensor protocol (10-bit, 1-bit parity)
Data Transmission
TGAP
frame duration
S1 S2 D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 P
"0" "0" "1" "1" "1" "0" "0" "1" "1" "1" "1" "0" "1"
Manchester Code
Transmission of 0x1E7
0x1E7 = 01 1110 0111b
TBIT
7.1.1
GAPGPS01132
Functional description - remote sensor modes
The Remote sensor Interface block provides a hardware connection between the
microcontroller and up to two remote sensors. Each channel is independent of the other,
and is not influenced by fault conditions, such as short circuits to ground or vehicle battery,
on the other channel. Each channel supplies an independently current limited DC voltage to
its remote sensor derived from VSUP, and monitors the current draw to extract encoded
data. The remote sensors modulate the current draw to transmit Manchester-encoded data
back to the receiver. The current level detection threshold for all channels is automatically
set by the integrated current adjust feature in order to adapt to the quiescent current draw of
the sensors.
All channels can be enabled or disabled independently via SPI commands. The operational
status of all channels can also be read via SPI command.
The message bits are encoded using a Manchester format, in which logic values are
determined by a current transition in the middle of the bit time. The interface supports
Manchester 2 encoding as shown in Figure 33.
Figure 33. Manchester bit encoding
Bit time
Start bits = ’00 ’
Logic '0'
Current
Logic '1'
‘0’
‘0’
‘1’
‘0’
‘1’
Manchester-2
PSI5
GAPGPS01133
The received message data are stored in input data registers that are read out by the
microcontroller via the SPI interface. All bits of these registers are simultaneously updated
upon reception of the remote sensor message to prevent partial frame data from being
sampled via the SPI interface. After the data for a given channel is read via the SPI
128/210
DS11626 Rev 5
L9678P, L9678P-S
Remote sensor interface
interface, subsequent requests for data from this channel will result in an error response
(NODATA fault).
The remote sensor interface is also able to detect faults occurring on the sensor interface.
The Remote Sensor Data Register (RSDRx) will report multiple fault flags.
When the number of bits decoded is incorrect (either too many or too few), a bit error is
indicated. When any bit error is detected (bit time, too many bits or too few bits), the
message is discarded.
Error bit INVALID is an OR-ed combination of the following errors:
Data length error or stop bit error
Parity Error of received Remote sensor Message
Bit time error (a data bit edge is not received inside the expected time window)
Should one or more of the channel faults (STG, STB, CURRENT_HI, OPENDET and
RSTEMP) be set, the INVALID and NODATA bits are cleared.
7.1.2
RSU data fields and CRC
The remote sensor interface reports both data information and fault information in the
Remote Sensor Data Register (RSDRx). Independent data registers are defined for each
remote sensor interface and the data contained therein is formatted differently based on
whether a fault is detected. See SPI command in Remote sensor data/fault registers w/o
fault (RSDRx) on page 93.
The data available in the RSDRx register is separated into several bit fields. The Logical
Channel ID is a 4-bit field to identify the satellite sensor. The DATA bits are appended to the
LCID at the output of the Manchester decoder. The 3-bit CRC bit field is computed on the
entire data packet of fields, bits[16:0], which also includes the CHxON and FLTBIT. To
satisfy safety requirements, the LCID, DATA and CRC bit fields propagate through the same
data path as a single item to the SPI output.
The polynomial calculation implemented for PSI5 data is described as in PSI5 specification
g(x)=1+x+x^3 with the initialization value equal to "111".
Below are the equations to calculate the CRC in combinatorial way:
CRC[2] = CRCext[0]+D[0]+D[1]+D[3]+D[6]+D[7]+D[8]+D[10]+D[13]+D[14]+D[15]
CRC[1] = CRCext[2]+D[0]+D[1]+D[2]+D[4]+D[7]+D[8]+D[9]+D[11]+D[14]+D[15]+D[16]
CRC[0] = CRCext[1]+CRCext[0]+D[0]+D[2]+D[5]+D[6]+D[7]+D[9]+D[12]+D[13]+D[14]+D[16]
where D[16:0]= RSDR[16:0] and CRCext[n] are the starting seed values (all '1').
7.1.3
Detailed description
Manchester decoding
The Manchester decoder will support remote sensor communication as per PSI
specification rev 1.3 for the modes configurable via the STS bits in the RSCRx registers.
The Manchester Decoder checks the duty-cycle and period of the start bits to determine
their validity, depending on the configuration of the PERIOD_MEAS_DISABLE bit in the
RSCRx registers. The expected time windows for the mid bit transitions of each subsequent
bit within the received frame is determined by means of the internal oscillator time base.
Glitches shorter than 25% of the minimum bit time duration are rejected.
DS11626 Rev 5
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209
Remote sensor interface
L9678P, L9678P-S
Figure 34. Manchester decoder state diagram
RESET_DECODER Æ
Strobe RESET_CNT
IDLE
T10
PERIOD_1_5
Strobe REC_END
Strobe RESET_CNT
(check PARITY_ERR)
T1
T11
RISING_EDGE Æ
PERIOD_1_5
Strobe RESET_CNT
Strobe RESET_CNT
T13
ANY and / PERIOD_1_5
Strobe RESET_CNT
T2a
T9
ANY and
(PERIOD_0_75 or not FIRST)
WAIT
TGAP
B
B
Strobe MANY BITS
Strobe RESET_CNT
Period_1_25
and ANY_EDGEÆ
Strobe RESET_CNT
A
T2b
ERROR
A
B
START BIT
DET.
Period_1_25 and not ANY_EDGE
E
C
T3
D
(first pulse duty cycle check:)
FALLING_EDGE before period_0_25 Æ
Strobe RESET_CNT
T4
T6a
RISING_EDGE & /Period_0_75 Æ
PERIOD_1_25 and ANY
strobe CHECK_TIME
Strobe RESET_CNT
Strobe RESET_CNT
T6b
PERIOD_1_25 and not ANY
strobe CHECK_TIME
T7
ANY and
not PERIOD_0_75 and
not FIRST_EDGE
Strobe RESET_CNT
Strobe CHECK_TIME
A
B
E
DATA REC.
T5
D
T8
ANY and
PERIOD_0_75 and STATE=C_NB
Strobe RESET_CNT
Strobe NEXT BIT
DataFilt
RISING_EDGE
FALLING_EDGE
ANY
C_NB
STATE
BitCounter
Period_1_50
Period_1_25
Period_0_75
FIRST_EDGE
RISING and PERIOD_0_75
Strobe RESET_CNT
C
:=
:=
:=
:=
:=
:=
:=
:=
:=
:=
:=
T12
(ANY and not PERIOD_1_25 and
PERIOD_0_75 and not STATE=C_NB)
Strobe RESET_CNT
Strobe NEXT BIT
Filtered Raw Data (RXSAT) from Current Demodulator (after deglitcher )
DataFilt(n+1, n) == “01”
DataFilt(n+1, n) == “10”
RISING_EDGE or FALLING_EDGE
8bit frame configurated ? 10 : 12
{0@IDLE, 1@STATBITDET, 2@T5, STATE++@T12, 0xE @WAIT, 0xF@ERROR}
RESET_CNT ? 0 : BitCounter++
BitCounter >= BitPeriod*1.5
BitCounter >= BitPeriod*1.25
BitCounter >= BitPeriod*0.75
Period_0_75? 1 : ANY? 0 : FIRST_EDGE after a delay of Tck (Remark: not a combinatorial signal )
End of message definition for use in timeslot control: EOM = T10+T9+T7+T6a+T6b
GAPGPS01645
130/210
DS11626 Rev 5
L9678P, L9678P-S
Remote sensor interface
A Manchester Decoder Error occurs if one or more of the following conditions are true:
Two valid start bits are detected, and at least one of the expected 13 mid-bit transitions
are not detected
Two valid start bits are detected, and more than 13 mid-bit transitions are detected
When the number of bits decoded is incorrect (either too many or too few), a bit error is
indicated. When any bit error is detected (bit time, too many bits, too few bits), the
decoder will revert to the minimum bit time of the selected range and the message is
discarded.
All errors are readable through the Sensor Fault Status Register and the RSFLT bit in the
Global Status Word Register.
When a valid message is correctly decoded, the 10/8 data bits are stored into the
appropriate RSDRx register together with the related LCID. The RSDRx register contains
the 10/8 bits data as they are received from the sensor (no data range check/mask is done
at this stage). The 8-bit data word is right-justified inside the 10-bit data field in the RSDRx
registers.
Current sensor with auto-adjust trip current
The current sensor is responsible for translating the current drawn by the sensor into a
digital state (refer to Figure 35). Each satellite channel has a dedicated current sensor with
hysteresis.
Figure 35. Remote sensor current sensing auto adjust
RxSat
Itrip
Isat
e.g. 20mA
13mA
Ibase
15mA
count
42
0.5μs
4μs
GAPGPS01134
The auto adjust feature uses a 7 bit D/A to converter to step up and down the threshold level
for detecting the base current through the remote sensor before start bits are transmitted.
Once start bits are received, the counter stops and the D/A value remains fixed until the
remote sensor message is received. This procedure is repeated for each cycle of the
remote sensor. The auto adjust circuit uses the following equation:
Ibase = Ioffset + (D/A counts) * 300 µA where Ioffset is fixed to 2.5 mA
DS11626 Rev 5
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Remote sensor interface
L9678P, L9678P-S
The converter default count value is 42, therefore,
Ibase = 2.5 mA + 42 * 300 µA
Ibase = 15 mA
Itrip = Ibase + threshold where threshold is a fixed at 12 mA
Thanks to this implementation, Ibase can span from 2.5 mA up to 41 mA covering PSI-5
specification range. As an example, for a remote sensor that operates at 10 mA base
current, Itrip = 23 mA.
7.2
Remote sensor interface fault protection
7.2.1
Short to ground, current limit
Each output is short circuit protected by an independent current limit circuit. Should the
output current level reach or exceed the ILIMTH for a time period greater than TILIMTH the
output stage is disabled and an internal up-down counter will count in 25 µs increment up to
TILIMTH. The filter time is chosen in order to avoid false current limit detection for in-rush
current that may happen at interface switch-on. When the output is turned off due to current
limit, the appropriate fault code STG is set in the Remote Sensor Data Register (RSDR).
The fault timer latch is cleared when the sensor channel is first disabled and then reenabled through the Remote Sensor Configuration Register (RSCR). This fault condition
does not interfere with the normal operation of the IC, nor with the operation of the other
channels. When a sensor fault is detected, the RSFLT bit of the GSW is set indicating a fault
occurred and can be decoded by addressing the RSFSR register.
In order to fulfil the blanking time requirement at channel activation as per PSI-5
specification, a dedicated masking time is applied to the current limitation fault detection
each time a channel is activated.
7.2.2
Short to battery
All outputs are independently protected against a short to battery condition. Short to battery
protection disconnects the channel from its supply rail to guarantee that no adverse
condition occurs within the IC. The short-to-battery detection circuit has input offset voltage
(10 mV, minimum) to prevent disconnecting of the output under an open circuit condition. A
short to battery is detected when the output RSUx pin voltage increases above VSUP
supply pin voltage for a TSTBTH time. An internal up-counter will count in 1.5 µs increment
up to TSTBTH. The counter will be cleared if the short condition is not present for at least
1.5 µs. Short to battery protection blocks the battery condition to guarantee that no adverse
condition occurs within the IC. The channel in short to battery is not shut down by this
condition. Other channels are not affected in case of short of one output pin. As in the case
previously described, the STB fault code can be read from RSDR bits and any fault will set
the RSFLT bit of the global status word register (GSW). The STB bit is cleared upon read.
7.2.3
Cross link
The device provides also the capability of a cross link check between outputs, in order to
reveal conditions where two output channels are in short. This functionality is allowed by
enabling one output channel, while asking for voltage measurement on any of the other
ones.
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DS11626 Rev 5
L9678P, L9678P-S
7.2.4
Remote sensor interface
Leakage to battery, open condition
The remote sensor interface offers detection of an open sensor condition. The autoadjusting counter for remote sensor current sensing will drop to 0 in case the current flowing
through RSUx pin is lower than 3 mA. The OPENDET fault flag is asserted when the fault
condition lasts for longer than TRSUOP_FILT deglitch filter time. This fault flag can be read
from RSDR bits and any fault will set the RSFLT bit of the global status word register
(GSW). The channel in this condition is not shutdown.
7.2.5
Leakage to ground
The sensor interface offers as well the detection of a leakage to ground condition, that will
possibly raise the sensor current higher than 36 mA. The CURRENT_HI fault flag is
asserted when the fault condition lasts for longer than TRSUCH_FILT deglitch filter time. This
fault flag can be read from RSDR bits and any fault will set the RSFLT bit of the global status
word register (GSW). The channel in this condition is not shutdown.
7.2.6
Thermal shutdown
Each output is protected by an independent over-temperature detection circuit. Should the
remote sensor interface thermal protection be triggered the output stage is disabled and a
corresponding thermal fault is latched and reported through the RSTEMP flag in the Remote
Sensor Data Register (RSDRx). The thermal fault flag is cleared when the sensor channel is
first disabled and then re-enabled through the Remote Sensor Configuration Register
(RSCRx).
DS11626 Rev 5
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209
Watchdog timer
8
L9678P, L9678P-S
Watchdog timer
This device offers a watchdog implementation by means of a temporal WD. Window times
are SPI programmable and a couple of specific codes has to be written within this window in
order to serve the WD control.
8.1
Temporal watchdog
The temporal watchdog ensures the system software is operating correctly by requiring
periodic service from the microcontroller at a programmable rate. This service (watchdog
refresh) must occur within a time window, and if serviced too early or too late will enter an
error state (WD1_ERROR) reported via the WD1_WDR bit of the FLTSR register.
The overall WD1 functionality is described in the state diagram reported in Figure 36.
Figure 36. Watchdog state diagram
WSM_Reset
(From any state) /
WD1_LOCKOUT=1
WD1_WDR=0
WD1_ERR_CNT=0
WD1_ERR_TH_WE=1
WDT/TM>VWD_OVERRIDE AND
SPI WD1_TEST
WD1_LOCKOUT=0
1ms /
WD1_WDR=1
500ms AND
WD1_TOVR=0 /
WD1_LOCKOUT=1
WD1_ERR_CNT++
WD1 RESET
WD1_ERROR /
WD1_LOCKOUT=1
WD1_ERR_CNT++
WD1
OVERRIDE
WD1 INITIAL
WD1 RUN
WD1 refresh OK /
WD1 refresh OK /
WD1_WDR=0
WD1_ERR_TH_WE=0
If (WD1_ERR_CNTMIN &
SPI_WD1_A /
TMR1=0
Strobe WD1 refresh OK
WD1B2
WD1A2
TMR1>MIN &
SPI_WD1_B /
TMR1=0
Strobe WD1 refresh OK
TMR1>MAX OR
[TMR1MAX OR
[TMR1= ARMP_TH?
NEG_COUNT[i]
>= ARMN_TH?
Y
ARMP = 0
N
Y
ARMP = 1
ARMN = 1
ARMSEL[i] =
00, 01, or 11?
ARMSEL[i] =
00, 10, or 11?
Y
ARMN = 0
N
Y
N
TIMER_CNTx is a 10 bit
down counter always
running at 2ms
N
ARM1[i]=1 &
TIMER_CNT1<
DWELL[i]
ARM2[i]=1 &
TIMER_CNT2<
DWELL[i]
N
TIMER_CNTx control
extends to 4 for high/mid
Y
Y
TIMER_CNT1=
DWELL[i]
TIMER_CNT2=
DWELL[i]
i++
TIMER_CNT1
> 0?
N
i = N?
TIMER_CNT2
> 0?
Y
ARM1INT=1
N=5 (L9678)
N=13 (L9679)
N=17 (L9680)
N
N
ARMxINT control extends
to 4 for high/mid
Y
ARM1INT=0
ARM2INT=1
ARM2INT=0
Y
GAPGPS02868
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DS11626 Rev 5
L9678P, L9678P-S
Safing logic
Figure 49. Safing engine diagnostic logic
SCLK_G
MOSI_G
MISO_G
CS_G
SAF_CS0
SAF_CS1
SPI Decode /
Threshold
Compare
Pulse
Stretch
DSTEST(VSF)
DIAG STATE
ARM1INT
DSTEST(ARM)
DSTEST(PULSE)
CH1PULSE
CH2PULSE
CH3PULSE
CH4PULSE
ARM2INT
ARMING STATE
GAPGPS01651
A configurable mask for each internal ARMxINT signal is available for all of the integrated
deployment loops (refer to ARMx assignment registers (LOOP_MATRIX_ARMx) on
page 99). The un-masked ARMxINT signal for each loop will enable the respective loop
drivers (refer to Figure 21).
Activation of VSF (regulation rail for High Side Safing FET) occurs upon ARMxINT or
FENH/FENL, depending on SPI configuration (refer to Figure 17). Actual High Side Safing
FET activation still requires microcontroller signal.
L9678P is able to provide arming signals to external deployment loops by means of the
discrete output ARM pin. The ARM pin can either output an arming signal generated by the
integrated safing engine or an arming signal made by the combination of FENH and FENL
input signals, coming from external safing logic.
Figure 50. ARM output control logic
WD1_RUN
WD1_LOCKOUT
SSM_RESET
ARM_EN
WD1_OVERRIDE
ARM1INT
Safing
Engine
ARM2INT
0
ARM
1
FENL
FENH
SAFESEL
GAPGPS01658
DS11626 Rev 5
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209
Safing logic
10.6
L9678P, L9678P-S
Arming pulse stretch
Upon a valid command processed by the safing logic, the Dwell bits to stretch the arming
time assertion (dwell time) apply to each safing record and is used to help safe the
deployment sequence to avoid undesired behaviour.
Once dwell time has started, it will continue, regardless of the En (Record Enable) bit. Dwell
will be truncated in case of SSM reset. Dwell values in the safing records are transferred to
the ARM signal. A dedicated counter is designed for ARM output pin. If different dwell
values are assigned to ARM, the longer value is used. Dwell times can only be extended,
not reduced. If the remaining dwell time is less than the new dwell extension setting, the
new setting will be loaded into the dwell counter.
Dwell times are user programmable.
The behavior of the pulse stretch timer is shown in Figure 51.
Figure 51. Pulse stretch timer example
Arming Safing Logic
Processed result
Arming Enable
Pulse Stretch
Pulse Stretch Time
Less Than Pulse
Stretch Time
Pulse Stretch
Time
GAPGPS01148
10.7
Additional communication line
The ACL pin is the Additional Communication Line input that provides a means of safely
activating the arming outputs (ARM and VSF) for disposal of restraints devices at the end of
vehicle life.
A valid ACL detection (as described below) allows L9678P to transition from Scrap state to
Arming state. To remain in Arming state L9678P must receive the correct ACL signal; this
must occur before the scrap time-out timer expires (TdisEOL).
While the System Operating State Machine is in Arming state, the arming outputs are
asserted (ARM=1, VSF on). If the ACL is not correctly received before the time-out expires,
the System Operating State Machine reverts back to the Scrap state, and the arming
outputs are deactivated.
154/210
DS11626 Rev 5
L9678P, L9678P-S
Safing logic
Figure 52. Scrap ACL state diagram
SSM_RESET OR
((NOT SCRAP state) AND (NOT ARMING state)) /
ACLGOOD=0
ACLBAD=0
ACLTMR=0
Rising edge /
ACLTMR= 0
ACLGOOD=0
ACLBAD++
ACLTMR > periodmin
& rising edge /
ACLGOOD ++
ACLBAD=0
ACLTMR=0
ACLHIGH
Falling edge &
ACLTMR > highmin
ACLTMR > highmax OR
Falling edge & ACLTIMER
< highmin /
ACLLOW
ACLTMR > periodmax /
ACLGOOD =0
ACLBAD ++
ACLTMR=0
Rising edge OR
ACLTMR > periodmax /
ACLTMR=0
ACLGOOD=0
ACLBAD++
ACLERROR
GAPGPS01652
A specific waveform needs to be present on this input in order to instruct L9678P to arm all
deployment loops. L9678P is designed to support the Additional Communication Line (ACL)
aspect of the ISO-26021 standard, which requires an independent hardwired signal (ACL) to
implement the scrapping feature. The disposal signal may come from either the vehicle's
service connector, or the systems main microcontroller, depending on the end customer's
requirements.
The arming function monitors the disposal PWM input (ACL pin) for a command to arm all
loops for vehicle end-of-life. The disposal signal characteristic is shown in Figure 53. To
remain in Arming state, at least three cycles of the ACL signal must be qualified. For the
device to qualify the periodic ACL signal, the period and duty cycle are checked. Two
consecutive cycles of invalid disposal signal are to be received to disqualify the ACL signal.
Figure 53. Disposal PWM signal
Cycle time
On time
GAPGPS01149
The disposal PWM signal cycle time and on time parameters can be found in the electrical
parameters tables.
DS11626 Rev 5
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209
General purpose output (GPO) drivers
11
L9678P, L9678P-S
General purpose output (GPO) drivers
The L9678P contains two GPO drivers configurable either as high-side or low-side modes,
controlled in ON-OFF mode or in PWM mode setting the desired duty cycle value through
the GPO Control Register (GPOCTRLx).
For low side driver configuration, the GPODx pin is the equivalent drain connection of the
internal MOSFET and it is the current sink for the output driver. The GPOSx pin is the
source connection of the GPO driver and is externally connected to ground.
Figure 54. GPO driver block diagram - LS configuration
VBatt
Sel GPODx
10bits
Vin
GPOFLTSR (GPOxDISABLE )
LOAD
Vref
SPI(WID=’GPOCR’ )
S
SSM_RESET
R
SET
CL R
2V5
GPODx
Q
ERBOOST
Q
GPOCR(GPOxLS )
ERBOOST_OK
OUT
EN
ON
PWM
`
CTL
PWM_CLK (125us )
6
GPOCTRLx [ 5:0]
22nF
Driver with
Slew Rate
Control
Temperature
sensor
CTL
Current
sense
+
GPOFLTSR (GPOxTEMP )
Q
SET
S
Q
Q
CL R
SET
+
- Tjsd
S
R
Q
CL R
Current limitation
R
GPOSx
GPOCTRLx [5:0]=0h
SSM_RESET
GPOFLTSR (GPOxOPN )
Q
Q
GPOFLTSR (GPOxLIM )
Q
Q
SET
CL R
SET
CL R
+
-
S
Iopenload
R
+
-
S
R
Ilim
SPI(RID=’GPOFLTSR’ )
SSM_RESET
GAPGPS01653
For high side driver configuration, the GPODx pin will be connected to battery and GPOSx
pin will be connected to the load high side.
156/210
DS11626 Rev 5
L9678P, L9678P-S
General purpose output (GPO) drivers
Figure 55. GPO driver block diagram - HS configuration
Sel GPODx
Vin
10bits
Vin
GPOFLTSR (GPOxDISABLE )
Vref
SPI(WID=’GPOCR’ )
S
SSM_RESET
R
SET
CL R
2V5
GPODx
Q
ERBOOST
Q
GPOCR(GPOxLS )
ERBOOST_OK
OUT
EN
ON
PWM
`
CTL
PWM_CLK (125us )
6
GPOCTRLx [ 5:0]
Driver with
Slew Rate
Control
Temperature
sensor
CTL
Current
sense
+
GPOFLTSR (GPOxTEMP )
Q
SET
S
Q
Q
CL R
SET
S
R
Q
CL R
+
- Tjsd
Current limitation
R
GPOSx
LOAD
GPOCTRLx [5:0]=0h
SSM_RESET
GPOFLTSR (GPOxOPN )
Q
Q
GPOFLTSR (GPOxLIM )
Q
Q
SET
CL R
SET
CL R
S
22nF
+
-
Iopenload
R
S
+
-
R
Ilim
SPI(RID=’GPOFLTSR’ )
SSM_RESET
GAPGPS01654
The drivers have to be configured in one of the two modes through the GPO Configuration
Register (GPOCR) register before being activated. This hardware configuration is only
allowed during the Init and Diag states.
When configured as high-side, the drivers need ER Boost voltage to be above the
VERBST_OK threshold to be enabled.
The default state of both drivers is off. The drivers can be independently activated via SPI
control bits on GPO Control Register (GPOCTRLx). In addition, a set point on the
GPOCTRLx will control the output drivers in PWM with a 125Hz frequency. If PWM control is
desired, user should set the needed set point in the GPOxPWM bits of the GPOCTRLx
while activating the interface. When all bits are set to '0', the GPOx output will be disabled.
PWM control is based on a 125 Hz frequency. 6 bits of GPOCTRLx are reserved to this
mode, in order to control the drivers with 64 total levels from a 0% to a full 100% duty cycle.
When both GPO channels are used in PWM Mode at the same frequency they are
synchronized to provide parallel configuration capability.
PWM control is implemented through a careful slew rate control to mitigate EMC emissions
while operating the interface. The driver output structure is designed to stand -1V on its
terminals and a +1V reverse voltage across source and drain.
The GPO driver is protected against short circuits and thermal overload conditions. The
output driver contains diagnostics available in the GPO Fault Status Register (GPOFLTSR).
All faults except for thermal overload will be latched until the GPOFLTSR register is read.
DS11626 Rev 5
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209
General purpose output (GPO) drivers
L9678P, L9678P-S
Thermal overload faults will remain active after reading the GPOFLTSR register should the
temperature remain above the thermal fault condition. For current limit faults, the output
driver will operate in a linear mode (ILIM) until a thermal fault condition is detected.
The device also offers an open load diagnostics while in ON state. The diagnostics is run
comparing the current through the output stage with a reference threshold IOpenLoad: should
the output current be lower than the threshold, the open detection flag is asserted.
158/210
DS11626 Rev 5
L9678P, L9678P-S
12
ISO9141 transceiver
ISO9141 transceiver
A block diagram of the function is shown below. Data transmitted by the main
microcontroller is sent via the ISOTX pin and data is received via the ISORX pin. The bus
output is ISOK.
Figure 56. ISO9141 block diagram
VBAT
VIN
510 Ω
ISORX
ISOK
vddq
VIH
Gate
Control
ISOTX
FLTSR1(ILIMXCVR)
Thermal
Shutdown
Filter
td
Ilin
FLTSR 1(OTXCVR)
GAPGPS01151
When the ISOTX pin is asserted, logic high, the ISOK output will be disabled (pulled high by
an external resistor). When the ISOTX pin is deasserted, logic low, the ISOK output will be
enabled (pulled low by the internal driver). This input pin contains an internal pull-up to
command the output to the disabled state in the event of an open circuit condition.
The ISORX pin has a push-pull output stage referenced to VDDQ voltage. This output is
asserted high when the voltage on the ISOK pin is above the ISOK input receiver threshold,
VBATMON, as defined in the electrical tables. This output is deasserted low when the
voltage on the ISOK pin is below the ISOK input receiver threshold with hysteresis.
ISOK output is a low side driver compatible with ISO9141 physical layer.
The output stage is protected against short circuits and diagnostics provide feedback for
current limit and thermal shutdown. While in current limit, the output stage will continue to
function until thermal limit is reached. Should thermal limit occur, the output stage will shut
down until the temperature decreases below the limit threshold with hysteresis. The fault
status is reported in the ISO9141 Fault Status Register (ISOFLTSR).
DS11626 Rev 5
159/210
209
System voltage diagnostics
13
L9678P, L9678P-S
System voltage diagnostics
L9678P has an integrated dedicated circuitry to provide diagnostic feedback and processing
of several inputs. These inputs are addressed with an internal analog multiplexer and made
available through the SPI digital interface with the Diagnostic Data commands. In order to
avoid saturation of high voltage internal signals, an internal voltage divider is used. The
diagnostics circuitry is activated by four SPI Diagnostics Control commands (DIAGCTRLx);
each of them can address all the available nodes to be monitored, except for what
mentioned in Table 10: Diagnostics control register (DIAGCTRLx) on page 161.
DIAGCTRLx SPI command bit fields are structured in the following way:
DIAGCTRL_A (ADDRESS HEX 3A)
19
18 17 16 15 14 13 12 11 10 9 8 7
MOSI
x
MISO NEWDATA_A
0
0
x
x
x
x
x
x
x
6
5
x
4
3
2
1
0
1
0
1
0
1
0
ADCREQ_A[6:0]
ADCREQ_A[6:0]
ADCRES_A[9:0]
DIAGCTRL_B (ADDRESS HEX 3B)
19
18 17 16 15 14 13 12 11 10 9 8 7
MOSI
MISO
x
NEWDATA_B
0
0
x
x
x
x
x
x
x
6
5
x
4
3
2
ADCREQ_B [6:0]
ADCREQ_B [6:0]
ADCRES_B [9:0]
DIAGCTRL_C (ADDRESS HEX 3C)
19
18 17 16 15 14 13 12 11 10 9 8 7
MOSI
x
MISO NEWDATA_C
0
0
x
x
x
x
x
x
x
6
5
x
4
3
2
ADCREQ_C [6:0]
ADCREQ_C [6:0]
ADCRES_C [9:0]
DIAGCTRL_D (ADDRESS HEX 3D)
19
18 17 16 15 14 13 12 11 10 9 8 7
x
MOSI
MISO NEWDATA_D
0
0
x
x
x
x
x
x
ADCREQ_D [6:0]
x
x
6
5
4
3
2
ADCREQ_D [6:0]
ADCRES_D [9:0]
ADCREQ[A-D] bit fields, used to address the different measurements offered, are listed in
Table 10: Diagnostics control register (DIAGCTRLx) on page 161 for reference.
L9678P diagnostics are structured to take four automatic conversions at a time. In order to
get four measurements, four different SPI commands have to be sent (DIAGCTRL_A,
DIAGCTRL_B, DIAGCTRL_C and DIAGCTRL_D), in no particular order.
160/210
DS11626 Rev 5
L9678P, L9678P-S
System voltage diagnostics
In case the voltage to be measured is not immediately available, the desired inputs for
conversion have to be programmed by SPI in advance, to allow them to attain a stable
voltage value. This case applies to the squib/pyroswitch resistance measurement and
diagnostics (refer to Loop diagnostics control and results registers) and to the switch sensor
measurement (refer to Section 9: DC sensor interface).
CONVRDY_0 bit in GSW is equal to (NEWDATA_A or NEWDATA_B), while CONVRDY_1
bit in GSW corresponds to (NEWDATA_C or NEWDATA_D).
Each NEWDATAx flag is asserted when conversion is finished and cleared when result is
read out. However result is cleared only when new result for that register is available.
When a new request is received it is queued if other conversions are ongoing. The
conversions are executed in the same order as their request arrived. The queue is 4
measures long so it's possible to send all 4 requests at the same time and then wait for the
results. If a DIAGCTLRx command is received twice, the second conversion request will
overwrite the previous one.
Requests are sent to the L9678P IC via the ADC measurement Registers (ADCREQx) as
shown in Table 10: Diagnostics control register (DIAGCTRLx) on page 161. All diagnostics
results are available on the ADCRESx registers, when addressed by the related ADCREQx
register (e.g. data requested by ADCREQA would be written to ADCRESA).
Table 10. Diagnostics control register (DIAGCTRLx)
ADC Request (ADCREQx)
ADC Results (ADCRESx)
Voltage measurement selection
Bit [6:0]
Hex
Bit [9:0]
0
0
0
0
0
0
0
0
Unused
0
0
0
0
0
0
1
1
ADC Test Pattern 1
Ground reference
0
0
0
0
0
1
0
2
ADC Test Pattern 2
Full scale reference
0
0
0
0
0
1
1
3
DC Sensor ch. selected, Voltage
0
0
0
0
1
0
0
4
DC Sensor ch. selected, Current
DCSV_selected
DCSI_selected
(1)
0
0
0
0
1
0
1
5
DC Sensor ch. selected, Resistance
DCSV and DCSI selected
0
0
0
0
1
1
0
6
Squib/pyroswitch measurement loop
selected
Voutx
0
0
0
0
1
1
1
7
Bandgap reference Voltage
VBGR
0
0
0
1
0
0
0
8
Bandgap reference monitor Voltage
VBGM
0
0
0
1
0
0
1
9
Unused
0
0
0
1
0
1
0
10
Temperature Measurement
0
0
0
1
0
1
1
11
DC Sensor ch 0, Voltage
DCSV_0
0
0
0
1
1
0
0
12
DC Sensor ch 1, Voltage
DCSV_1
0
0
0
1
1
0
1
13
DC Sensor ch 2, Voltage
DCSV_2
0
0
0
1
1
1
0
14
DC Sensor ch 3, Voltage
DCSV_3
0
0
0
1
1
1
1
15
Unused
0
0
1
0
0
0
0
16
Unused
0
0
1
0
0
0
1
17
Unused
DS11626 Rev 5
TEMP
161/210
209
System voltage diagnostics
L9678P, L9678P-S
Table 10. Diagnostics control register (DIAGCTRLx) (continued)
ADC Request (ADCREQx)
ADC Results (ADCRESx)
Voltage measurement selection
Bit [6:0]
Hex
Bit [9:0]
0
0
1
0
0
1
0
18
Unused
0
0
1
0
0
1
1
19
Unused
0
0
1
0
1
0
0
20
Unused
0
0
1
0
1
0
1
21
Unused
0
0
1
0
1
1
0
22
Unused
0
0
1
0
1
1
1
23
Unused
0
0
1
1
0
0
0
24
Unused
0
0
1
1
0
0
1
25
Unused
0
0
1
1
0
1
0
26
Unused
0
0
1
1
0
1
1
27
Unused
0
0
1
1
1
0
0
28
Unused
0
0
1
1
1
0
1
29
Unused
0
0
1
1
1
1
0
30
Unused
0
0
1
1
1
1
1
31
Unused
0
1
0
0
0
0
0
32
Battery monitor Voltage
VBATMON
0
1
0
0
0
0
1
33
Device battery Voltage
VIN
0
1
0
0
0
1
0
34
Analog internal supply Voltage
VINT3V3
0
1
0
0
0
1
1
35
Digital internal supply Voltage
CVDD
0
1
0
0
1
0
0
36
ERBOOST voltage
0
1
0
0
1
0
1
37
Unused
0
1
0
0
1
1
0
38
VER Voltage
0
1
0
0
1
1
1
39
VSUP Voltage
VSUP
0
1
0
1
0
0
0
40
VDDQ Voltage
VDDQ
0
1
0
1
0
0
1
41
WAKEUP Voltage
0
1
0
1
0
1
0
42
VSF Regulator Voltage
0
1
0
1
0
1
1
43
WDT/TM Voltage
WDTDIS
0
1
0
1
1
0
0
44
GPO Driver 0 drain Voltage
GPOD0
0
1
0
1
1
0
1
45
GPO Driver 0 source Voltage
GPOS0
0
1
0
1
1
1
0
46
GPO Driver 1 drain Voltage
GPOD1
0
1
0
1
1
1
1
47
GPO Driver 1 source Voltage
GPOS1
0
1
1
0
0
0
0
48
Unused
0
1
1
0
0
0
1
49
Unused
0
1
1
0
0
1
0
50
Remote sensor Interface Voltages ch. 0
162/210
DS11626 Rev 5
ERBOOST
VER
WAKEUP
VSF
RSU0
L9678P, L9678P-S
System voltage diagnostics
Table 10. Diagnostics control register (DIAGCTRLx) (continued)
ADC Request (ADCREQx)
ADC Results (ADCRESx)
Voltage measurement selection
Bit [6:0]
Hex
Bit [9:0]
0
1
1
0
0
1
1
51
Remote sensor Interface Voltages ch. 1
RSU1
0
1
1
0
1
0
0
52
Unused
0
1
1
0
1
0
1
53
Unused
0
1
1
0
1
1
0
54
SSxy Voltage ch. 0
SS01
0
1
1
0
1
1
1
55
SSxy Voltage ch. 1
SS01
0
1
1
1
0
0
0
56
SSxy Voltage ch. 2
SS23
0
1
1
1
0
0
1
57
SSxy Voltage ch. 3
SS23
0
1
1
1
0
1
0
58
Unused
0
1
1
1
0
1
1
59
Unused
0
1
1
1
1
0
0
60
Unused
0
1
1
1
1
0
1
61
Unused
0
1
1
1
1
1
0
61
Unused
0
1
1
1
1
1
1
63
Unused
1
0
0
0
0
0
0
64
Unused
1
0
0
0
0
0
1
65
Unused
1
0
0
0
0
1
0
66
VRESDIAG
1
0
0
0
0
1
1
67
VDD5
1
0
0
0
1
0
0
68
VDD3V3
1
0
0
0
1
0
1
69
ISOK output voltage
ISOK
1
0
0
0
1
1
0
70
SF0 voltage
SF0
1
0
0
0
1
1
1
71
SF1 voltage
SF1
1
0
0
1
0
0
0
72
SF2 voltage
SF2
1
0
0
1
0
0
1
73
SF3 voltage
SF3
VRESDIAG
VDD5
VDD3V3
1. The DC sensor resistance measurement can only be addressed through DIAGCRTL_A command. Results are available
through DIAGCTRL_A and DIAGCTRL_B, where ADCRES_A will contain DCSI and ADCRES_B will contain DCSV.
Proper scaling is necessary for various voltage measurements. The divider ratios vary by
measurement and are summarized by function in the table below.
Table 11. Diagnostics divider ratios
Divider Ratio
Measurements
15:1
VER
X
ERBOOST
X
VSF
X
10:1
DS11626 Rev 5
7.125:1
7:1
4:1
1:1
163/210
209
System voltage diagnostics
L9678P, L9678P-S
Table 11. Diagnostics divider ratios (continued)
Divider Ratio
Measurements
15:1
SSxy
X
SFx
X
VRESDIAG
X
10:1
GPODx
X
GPOSx
X
VIN
X
VBATMON
X
WAKEUP
X
7.125:1
7:1
ISOK
X
VSUP
X
WDTDIS
X
RSUx
4:1
1:1
X
DCSx
X
VDDQ
X
VDD5
X
VDD3V3
X
VINT3V3
X
Bandgap (BGR/BGM)
X
TEMP
X
For measurements other than voltage (current, resistance, temperature etc.) the ranges are
specified in the electrical parameters section of the relevant block.
13.1
Analog to digital algorithmic converter
The device hosts an integrated 10 bit Analog to Digital converter, running at a clock
frequency of 16MHz. The ADC output is processed by a D to D converter with the following
functions:
Use of trimming bits to recover ADC offset and gain errors;
Digital low-pass filtering;
Conversion from 12 to 10 bits.
10 bits data are filtered inside the digital section. The number of samples that are filtered
varies depending on the chosen conversion. As per Section 5.1.2: System configuration
register (SYS_CFG), the number of used samples in converting DC sensor,
squib/pyroswitch or temperature measurements defaults to 8. The number of samples for all
other measurements defaults to 4. The sample number can be configured by accessing the
SYS_CFG register. After low pass filter, the residual total error is ±4 LSB. This error figure
164/210
DS11626 Rev 5
L9678P, L9678P-S
System voltage diagnostics
applies to the case of a precise reference voltage: the spread of reference voltage causes a
proportional error in the conversion output. The reference voltage of the ADC is set to 2.5 V.
The conversion time is comprised of several factors: the number of measurements loaded
into the queue, the number of samples taken for any measurement, and the various settling
times. An example of conversion time calculation for a full ADC request queue is reported in
Figure 57. The timings reported in Figure 57 are nominal ones, min/max values can be
obtained by considering the internal oscillator frequency variation reported in the DC
characteristics section.
Figure 57. ADC conversion time
DIAGCTRL_ A
PreADC
S * T_SC
DIAGCTRL_B
IQ
S * T_SC
DIAGCTRL_C
IQ
S*T_SC
DIAGCTRL_D
IQ
S*T_SC
Post
ADC
Pre- AD C = Initial ADC Settling Time = 4.81 μs
S = # of Samples (default = 4 for voltage only measurements)
T_ SC = Single Sample Conversion Time = 2.25 μs
IQ = Intra- Queue Settling Time = 3.5 μs
Post- ADC = Final ADC Settling Time = 3.44 μs
GAPGPS01655
DS11626 Rev 5
165/210
209
Temperature sensor
14
L9678P, L9678P-S
Temperature sensor
The L9678P provides an internal analog temperature sensor. The sensor is aimed to have a
reference for the average junction temperature on silicon surface. The sensor is placed far
away from power dissipating stages and squib/pyroswitch deployment drivers. The output of
the temperature sensor is available via SPI through ADC conversion, as shown in Table 10.
The formula to calculate temperature from ADC reading is the following one:
ADC REF_hi
220
T C = 180 – --------------- ------------------------------- DIAGCTRLn ADCRESn – 0.739
1.652 ADC RES
2
@ DIAGCTRLn(ADCREQn) = 0Ahex
All parametric requirements for this block can be found in specification tables.
166/210
DS11626 Rev 5
L9678P, L9678P-S
15
Applications
Applications
The main applications for this IC are two:
15.1
as user configurable airbag IC
as pyro fuse manager IC
Application circuit
Figure 58. Airbag application
DS11626 Rev 5
167/210
209
Applications
15.2
L9678P, L9678P-S
BOM (Bill Of Materials)
The following table summarizes the suggested BOM valid for both applications.
Table 12. Bill Of Materials
Component
Min
Typ
Max
Unit
Requirement
C1
-
100
-
nF
50 V
Input capacitor (unprotected battery)
C2
-
2.2
-
μF
50 V
Input capacitor (protected battery)
C3
-
2.2
15
μF
50 V
ER Boost input capacitor
C4
-
100
-
nF
50 V
ER Boost ceramic output capacitor
C5
-
100
-
μF
50 V
ER Boost electrolytic output capacitor
C6
-
10
-
nF
25 V
VBATMON capacitor
C7
-
100
-
nF
50 V
VDD5 input capacitor
C8
-
10
-
μF
35 V
VDD5 output capacitor
C9
-
10
-
μF
35 V
VDD3V3 output capacitor
C10
-
100
-
nF
50 V
CVDD output capacitor
C11
-
100
-
nF
50 V
VSUP input capacitor
C12
-
10
-
μF
35 V
VSUP output capacitor
C13, C14
-
3.3
-
nF
25 V
RSUx capacitor
C15
2.2
-
4.7
mF
35 V
ER capacitor
C16
-
10
-
nF
25 V
VSF capacitor (near device)
C17
-
10
-
nF
25 V
VSF capacitor (near Safing FET gate)
C18
-
100
-
nF
50 V
Safing FET output capacitor
C19, C20
-
10
-
nF
25 V
SSxy capacitor
C21, C22,
C23, C24
-
22
-
nF
25 V
SFx capacitor
C25, C26,
C27, C28
-
22
-
nF
25 V
SRx capacitor
C29, C30,
C31, C32
-
22
-
nF
25 V
DCSx capacitor
D1
-
2
-
A
-
Reverse battery protection
D2
-
1
-
A
-
ER Boost diode
D3
-
1
-
A
-
WAKEUP diode
D4
-
1
-
A
-
ISO9141 pull-up diode
D5
-
12
-
V
-
Safing FET Zener diode
D6, D7
-
1
-
A
-
SSxy diode
L1
-
10
-
μH
1A
ER Boost inductor
R1
-
0.43
-
Ω
1W
Current limit resistor
R2
-
1
-
kΩ
100 mW
168/210
DS11626 Rev 5
Note
VBATMON current limit resistor
L9678P, L9678P-S
Applications
Table 12. (continued)Bill Of Materials
Component
Min
Typ
Max
Unit
Requirement
R3
-
3
-
kΩ
250 mW
VDD5 pull-up resistor
R4
-
3
-
kΩ
250 mW
VSUP pull-up resistor
R5
-
510
-
Ω
125 mW
ISO9141 pull-up resistor
R6
-
360
Ω
125 mW
Diagnostic resistor
R7
-
1.5
kΩ
100 mW
Safing FET passive pull-up resistor
R8
-
1
kΩ
100 mW
External Safing FET enable resistor
Q1
-
1
-
A
-
VDD5 external pnp transistor
Q2
-
1
-
A
-
VSUP external pnp transistor
Q3
-
60
-
A
60 V
U1
-
-
-
-
PUMD15
DS11626 Rev 5
Note
External Safing FET (N-channel)
External Safing FET enable
169/210
209
Electrical characteristics
16
L9678P, L9678P-S
Electrical characteristics
Every parameter in this chapter is fulfilled down to VINGOOD(max).
No device damage is granted to occur down to VINBAD(min).
GNDA pin is used as ground reference for the voltage measurements performed within the
device, unless otherwise stated.
All table or parameter declared "Design Info" are not tested during production testing
16.1
Configuration and control
All electrical characteristics are valid for the following conditions unless otherwise noted.
-40 °C Ta +95 °C, VINGOOD(max) VIN 35 V.
Table 13. Configuration and control DC specifications
N°
Symbol
Min
Typ
Max
Unit
1
VNOV
Normal operating
voltage
Design Info
Depending on power supply
configuration
6
13
18
V
2
VJSV
Jump start voltage
Design Info -40 °C ≤ Ta ≤ 50 °C
18.00
-
26.50
V
3
VLDV
Load dump voltage
Transient
Design Info
26.50
-
40
V
4
WU_mon
WAKEUP monitor
threshold
-
-
-
1.5
V
5
WU_off
WAKEUP Off threshold -
2
2.5
3
V
6
WU_on
WAKEUP On threshold -
4
4.5
5
V
7
WURPD
WAKEUP pull-down
resistor
-
120
300
480
kΩ
8
VBGOOD1
SYS_CTL(VBATMON_TH_SEL)=0
0
5.5
-
6
V
9
VBBAD1
SYS_CTL(VBATMON_TH_SEL)=0
0
5
-
5.5
V
10
VBGOOD2
SYS_CTL(VBATMON_TH_SEL)=0
1
6.3
-
6.8
V
11
VBBAD2
SYS_CTL(VBATMON_TH_SEL)=0
1
5.8
-
6.3
V
12
VBGOOD3
SYS_CTL(VBATMON_TH_SEL)=1
0
7.5
-
8
V
13
VBBAD3
SYS_CTL(VBATMON_TH_SEL)=1
0
7
-
7.5
V
14
VBGOOD4
SYS_CTL(VBATMON_TH_SEL)=11
8.3
-
8.8
V
15
VBBAD4
SYS_CTL(VBATMON_TH_SEL)=11
7.8
-
8.3
V
170/210
Parameter
VBATMON input
voltage thresholds
Condition
DS11626 Rev 5
L9678P, L9678P-S
Electrical characteristics
Table 13. Configuration and control DC specifications (continued)
N°
Symbol
16 ILKG_VBATMON_OFF
17 ILKG_VBATMON_ON
Parameter
VBATMON input
leakage
Condition
Min
Typ
Max
Unit
5
µA
Device OFF
-5
Device ON
Design Info
20
24
30
µA
18 RPD_VBATMON
VBATMON pull-down
resistance
Device ON
VBATMON < 10V
Design Info
125
250
375
kΩ
19 ILKG_VBATMON_TOT
VBATMON total input
leakage
ILKG_VBATMON_ON + RPD_VBATMO
VBATMON = 18V
35
70
105
µA
SYS_CTL(VIN_TH_SEL)=0
5
-
5.5
V
SYS_CTL(VIN_TH_SEL)=0
4.5
-
5
V
SYS_CTL(VIN_TH_SEL)=1
7
-
7.5
V
SYS_CTL(VIN_TH_SEL)=1
6.5
-
7
V
VIN Thresholds used to
25 VINFASTSLOPE_L change boost regulator transition time
26 VINFASTSLOPE_HYS
9.3
9.8
10.3
V
9
9.5
10
V
0.2
0.3
0.4
V
27
ILKG_VIN_OFF
Device OFF, VIN = 40V
-10
-
10
µA
28
ILKG_VIN_ON
Device ON, VIN = 12V
-
-
30
mA
29
CVIN
-
1
-
-
-
30
ILKG_VER_OFF
Device OFF, VER = 40 V
-5
-
5
µA
31
ILKG_VER_ON_L
Device ON
ERBOOST > VER
-5
-
5
µA
32
ILKG_VER_ON_H
Device ON
ERBOOST < VER
-
-
200
µA
33
VWD_OVERRIDE_th
WDT/TM threshold
-
10
12
14
V
34
VWDTDIS_HYST
WDT/TM hysteresis
-
0.2
0.4
0.5
V
35
IPD_WDTDIS
WDT/TM pull-down
Current
VWDTDIS ≤ 5 V
20
45
70
µA
Battery line Input
Leakage
Total leakage at RT from VIN,
VBATMON, ERBSTSW, ERBOOST,
BVDD5, VDD5, VDDQ, BVSUP,
VSUP
VBAT = 12 V
Guaranteed by design
-
-
100
µA
Junction temperature
Design Info
-
-
150
°C
20
VINGOOD1
21
VINBAD1
22
VINGOOD2
23
VINBAD2
24
VINFASTSLOPE_H
VIN input voltage
thresholds
VIN input leakage
36
ILKG_BAT
37
Tj
External VIN capacitor
VER input leakage
DS11626 Rev 5
171/210
209
Electrical characteristics
L9678P, L9678P-S
Table 14. Configuration and control AC specifications
No
Symbol
1
TFLT_VBATMONTH
2
TFLT_VINTH
3
TFLT_WAKEUP
4
TLATCH_WAKEUP
5
tdon
Parameter
Condition
Min
Typ
Max
Units
VBATMON thresholds
deglitch filter time
-
26
30
34
µs
VIN thresholds deglitch filter
time
-
3
3.5
4
µs
Wakeup deglitch filter time
-
0.95
1.05
1.15
ms
Wakeup latch time
-
9.7
10.8
11.9
ms
-
-
10
ms
Min
Typ
Max
Unit
Power-up delay time –
Wake-up to RESET released
Table 15. Open ground detection DC specifications
N°
Symbol
Parameter
Condition
1
GNDAOPEN
GNDA threshold
GNDSUBx=0
100
200
300
mV
2
GNDDOPEN
GNDD threshold
GNDSUBx=0
100
200
300
mV
3
BSTGNDOPEN
BSTGND threshold
GNDSUBx=0
100
200
300
mV
4
IPU_BSTGND
BSTGND pull-up
current
-
80
120
160
µA
Min
Typ
Max
Unit
-
7
11
16
µs
-
1.9
2.3
2.7
µs
Table 16. Open ground detection AC specifications
N°
Symbol
Parameter
1
GNDA and GNDD
TFLT_GNDREFOPEN Open Deglitch Filter
Time
2
TFLT_BSTGNDOPEN
16.2
Condition
BSTGND Latch Filter
Time
Internal analog reference
All electrical characteristics are valid for the following conditions unless otherwise noted.
-40 °C Ta +95 °C, VINGOOD1(max) VIN 35 V.
Table 17. Internal analog reference
N°
Symbol
1
VBG1
Bandgap reference
2
VBG2
3
VADC_GROUND
4
Parameter
Condition
Min
Typ
Max
Unit
-
-1%
1.2
+1%
V
Bandgap monitor
-
-1%
1.2
+1%
V
ADC Ground reference
-
-3%
103
+3%
mV
-1.5%
2.5
+1.5%
V
VADC_FULLSCALE ADC Full scale reference -
172/210
DS11626 Rev 5
L9678P, L9678P-S
16.3
Electrical characteristics
Internal regulators
All electrical characteristics are valid for the following conditions unless otherwise noted:
-40 °C Ta +95 °C, VINGOOD1(max) VIN 35 V.
Table 18. Internal regulators DC specifications
N°
Symbol
Parameter
Condition
Min
Typ
Max
Unit
1
VOUT_VINT3V3
VINT3V3 output voltage
-
3.14
3.3
3.46
V
2
VOV_VINT3V3
VINT3V3 over voltage
-
3.47
-
3.7
V
3
VUV_VINT3V3
VINT3V3 under voltage
-
2.97
-
3.13
V
4
VOUT_VDD
VDD output voltage
-
3.14
3.3
3.46
V
5
IOUT_VDD
VDD current capability
External Load is not allowed
-
-
50
mA
6
ILIM_VDD
VDD current limit
-
80
-
-
mA
7
VOV_VDD
VDD over voltage
-
3.47
-
3.7
V
8
VUV_VDD
VDD under voltage
-
2.7
-
2.9
V
9
CVDD
VDD output capacitance
Design Info
60
100
140
nF
Table 19. Internal regulators AC specifications
N°
Symbol
1
TFLT_ VINT_VDD_OV
Internal regulator OV
Deglitch filter time
2
TFLT_ VINT_VDD_UV
Internal regulator UV
Deglitch filter time
16.4
Parameter
Condition
Min
Typ.
Max
Unit
-
7
11
16
µs
-
7
11
16
V
Oscillators
All electrical characteristics are valid for the following conditions unless otherwise noted.
-40 °C Ta +95 °C, 3.14 CVDD 3.46.
Table 20. Oscillators AC specifications
No
Symbol
Parameter
Conditions / Comments
Min
Typ
1
fOSC
Main oscillator average
frequency
-
2
fMOD_OSC
Main oscillator
modulation frequency
3
IMOD_OSC
4
5
15.2
16
SPI_CLK_CNF(MAIN_SS_DIS=0)
Design Info
-
ƒ OSC
--------------128
-
MHz
Main oscillator
modulation index
SPI_CLK_CNF(MAIN_SS_DIS=0)
3
4
5
%
fAUX
Aux oscillator average
frequency
-
7.125
7.5
fMOD_AUX
Aux oscillator
modulation frequency
SPI_CLK_CNF(AUX_SS_DIS=0)
Design Info
-
ƒ OSC_AUX
---------------------------128
DS11626 Rev 5
Max
Unit
16.8 MHz
7.87
MHz
5
-
MHz
173/210
209
Electrical characteristics
L9678P, L9678P-S
Table 20. Oscillators AC specifications (continued)
No
Symbol
6
IMOD_AUX
7
Parameter
Aux oscillator
modulation index
Main oscillator Low
fOSC_LOW_TH Frequency Detection
Threshold
16.5
Conditions / Comments
Min
Typ
Max
Unit
SPI_CLK_CNF(AUX_SS_DIS=0)
3
4
5
%
-
-
128
---------- ƒ AUX
174
-
MHz
Watchdog
All electrical characteristics are valid for the following conditions unless otherwise noted:
-40 °C Ta +95 °C,VINGOOD1(max) VIN 35 V
Table 21. Temporal watchdog timer AC specifications
N°
Symbol
1
TWDT1_TIMEOUT
Temporal watchdog
timeout
-
2
TWDT1_RST
Temporal Watchdog
Reset Time
-
16.6
Parameter
Condition
Min
Typ
Max
Unit
-
-
2.00
ms
-
-
16.3
ms
0.9
-
1.1
ms
Reset
All electrical characteristics are valid for the following conditions unless otherwise noted:
-40 °C Ta +95 °C; VINGOOD1(max) VIN 35 V, VDDx(min) VDDx VDDx(max),
VDDQ = VDD5 or VDD3V3
Table 22. Reset DC specifications
N°
Symbol
1
VOH_RESET
2
VOL_RESET
3
RPD_RESET
Parameter
RESET output voltage
RESET pull down
resistance
Condition
Min
Typ
Max
Unit
ILOAD = -0.5 mA
VDDQ
-0.6
-
VDDQ
V
ILOAD = 2.0 mA
0
-
0.4
V
RESET=VDDQ, Device OFF
65
100
135
kΩ
Table 23. Reset AC specifications
N°
Symbol
1
TRISE_RESET
Rise Time
2
TFALL_RESET
3
THOLD_RESET
174/210
Parameter
Condition
Min
Typ
Max
Unit
80pF load, 20%-80%
-
-
1.00
µs
Fall Time
80pF load, 20%-80%
-
-
1.00
µs
Reset Hold Time
-
0.45
0.5
0.55
ms
DS11626 Rev 5
L9678P, L9678P-S
16.7
Electrical characteristics
SPI interface
All electrical characteristics are valid for the following conditions unless otherwise noted.
-40 °C Ta +95 °C, VINGOOD1(max) VIN 35 V, VDDx(min) VDDx VDDx(max)
VDDQ = VDD5 or VDD3V3.
Table 24. SPI DC specifications
N°
Symbol
Parameter
1
VIH_CS
SPI_CS high level input
voltage
2
VIL_CS
3
IPU_CS
4
Condition
Min
Typ
Max
Unit
-
2
-
-
V
SPI_CS low level input
voltage
-
-
-
0.8
V
SPI_CS pull up current
SPI_CS = 0 V
-70
-45
-20
µA
VIH_MOSI
MOSI high level input
voltage
-
2
-
-
V
5
VIL_MOSI
MOSI low level input
voltage
-
-
-
0.8
V
6
IPD_MOSI
SPI_MOSI pull down
current
SPI_MOSI = VDDQ
20
45
70
µA
7
VIH_SCK
SCK high level input
voltage
-
2
-
-
V
8
VIL_SCK
SCK low level input
voltage
-
-
-
0.8
V
9
IPD_SCK
SPI_SCK pull down
current
SPI_SCK = VDDQ
20
45
70
µA
10
VOH_MISO
SPI_MISO high level
output voltage
ILOAD = -800 µA
VDDQ
-0.5
-
VDDQ
V
11
VOL_MISO
SPI_MISO low level
output voltage
ILOAD = 2.0 mA
-
-
0.4
V
12
VIH_MISO
SPI_MISO high level
input voltage
-
2
-
-
V
13
VIL_MISO
SPI_MISO low level
input voltage
-
-
-
0.8
V
14
ILKG_MISO
SPI_MISO tri-state
leakage
SPI_MISO= VDDQ or 0 V
-10
-
10
µA
DS11626 Rev 5
175/210
209
Electrical characteristics
L9678P, L9678P-S
Table 25. SPI AC specifications
N°
Symbol
1
FSCLK
2
Parameter
SPI Transfer Frequency
(1)
SCLK_x Period (2)
TSCLK
(1)
3
TLEAD
Enable Lead Time (3)
4
TLAG
Enable Lag Time (4)(1)
5
6
Condition
THIGH_SCLK
TLOW_SCLK
SCLK_x High Time (5)
SCLK_x Low Time (6)
(1)
(1)
(1)
7
TSETUP_MOSI
MOSI_x Input Setup Time (7)
8
THOLD_MOSI
MOSI_x Input Hold Time (8)(1)
9
10
TACC_MISO
TDIS_MISO
MISO_x Access Time
(9)(1)
MISO_x Disable Time
(10)(1)
(11)(1)
11
TVALID_MISO
MISO_x Output Valid Time
12
THOLD_MISO
MISO_x Output Hold Time (12)(1)
Typ
Max
Unit
-
-
8
8.08
MHz
-
123.8
-
-
ns
-
250
-
-
ns
-
50
-
-
ns
-
50
-
-
ns
-
50
-
-
ns
-
20
-
-
ns
-
20
-
-
ns
80 pF load
-
-
60
ns
80 pF load
-
-
100
ns
80 pF load
-
-
30
ns
-
0
-
-
ns
-
20
13
THOLD_SCLK
14
TFLT_CS
CS_x noise glitch rejection time
-
50
15
TNODATA
SPI Interframe Time (15)(1)
-
400
-
16
17
TSETUP_MISO
THOLD_MISO
SCLK_x Hold Time
(13)(1)
Min
MISO Input Setup TIme
MISO Input Hold TIme
(7)(1)
(8)(1)
ns
300
ns
-
-
ns
20
-
-
ns
20
-
-
ns
1. Refer to the Figure 59 for details.
Note:
All timing is shown with respect to 10% and 90% of the actual delivered VDDQ voltage.
Figure 59. SPI timing diagram
4
CS_x
15
3
5
2
6
SCLK_x
13
7
MOSI_x
8
MSB IN
DATA
MISO_x
176/210
12
11
9
MSB OUT
LSB IN
DATA
DS11626 Rev 5
10
LSB OUT
DON’T
CARE
L9678P, L9678P-S
16.8
Electrical characteristics
ER boost
All electrical characteristics are valid for the following conditions unless otherwise noted.
-40 °C Ta +95 °C, VINGOOD1(max) VIN 18 V.
Table 26. ER Boost converter DC specifications
N°
Symbol
Parameter
1
VO_ERBST
Boost output voltage
2
3
Condition
Min
Typ
Max
Unit
Across all line and IO_BST load
(steady state)
ERBST33V=0
Test conditions: IO_BST = 0.1 &
40mA
22.4
23.8
25
V
Across all line and IO_BST load
(steady state)
ERBST33V=1
Test conditions: IO_BST = 0.1 &
20mA
31.4
33
35
V
BST33V = 0
0.1
-
60
mA
BST33V = 1
0.1
-
40
mA
IO_ERBST
Boost output current
dVSR_ac
Line transient response
All line, load; dt=100us;
BST33V = 0/1
Design Info
-8%
-
8%
%
6
dVLR_ac
All line, load; dt=100us;
Load transient response BST33V = 0/1
Design Info
-8%
-
8%
%
7
RDSON_ERBST
-
-
1
Ω
8
IOC_ERBST
Over current detection
-
550
-
800
mA
9
ILKG_ERBST
ERBOOST leakage
current
ERBOOST=40V
Device off
-
-
5
µA
VERBST_OK
ERBOOST voltage
threshold
BST33V = 0
18
20
22
V
BST33V = 1
26
28
30
V
VERBST_OV
ERBOOST Over Voltage BST33V = 0
threshold
BST33V = 1
22.6
25
V
31.65
35
V
4
5
10
11
12
13
Power switch resistance -
14
Voltage difference
between VIN and
VERBST_DIS_TH
VIN – ERBOOST
ERBOOST to deactivate
the ER Boost regulator
1.6
2.2
2.5
V
15
Voltage difference
between ERBSTSW and
VCLAMP_EN_TH
ERBSTSW – ERBOOST
ERBOOST to activate
the ER Boost CLAMP
1.6
2.2
2.5
V
-
150
175
190
°C
-
5
10
15
°C
16
TJSD_ERBST
17 THYS_TSDERBST
Thermal shutdown
DS11626 Rev 5
177/210
209
Electrical characteristics
L9678P, L9678P-S
Table 27. ER boost converter AC specifications
N°
Symbol
1
FSW_ERBST
Min
Typ
Max
Unit
-
1.8
1.882
2.0
MHz
10% to 90% voltage on
ERBSTSW
VIN ≥ VINFASTSLOPE_L =
10.3 V
Iload = 60mA
ERboost settings 23 V
Guaranteed by design
10
15
-
25
35
ns
TRISE_ERBSTSW_FAST
TFALL_ERBSTSW_FAST
10% to 90% voltage on
ERBSTSW
VIN ≤ VINFASTSLOPE_H=
9V
Iload=60mA
ERboost settings 23 V
Guaranteed by design
10
-
25
ns
4
TON_ERBST
CERBOOST = 2.2µF,
Vin =12V, IO_ERBST=
5mA
BST33V = 1
Measured from CS edge
to VO_ERBST(min)
-
-
5
ms
5
TFLT_TSD_ERBST
-
10
µs
Min
Typ
Max
Unit
2
Parameter
Condition
ERBOOST switching
frequency
TRISE_ERBSTSW_SLOW
TFALL_ERBSTSW_SLOW
ERBSTSW transition time
3
ERBOOST charge-up time
Thermal shutdown filter time -
Table 28. ER boost converter external components (Design Info)
N°
Symbol
1
LERBST
2
ESLERBST
3
CBLK_ERBST
4
Parameter
Condition
Inductance
-
8
10
-
µH
Inductance resistance
-
-
-
0.1
Ω
Output bulk capacitance
to ensure regulator
stability
Min capacitance value including
derating factors
1
2.2
-
-
-
0.1
ESRCBLK_ERBST Bulk capacitor ESR
µF
5
VFSTR_ERBST
Steering diode forward
voltage
IF=100 mA
-
-
0.85
V
6
ILKGSTR_ERBST
Steering diode reverse
leakage
Ta = 95 °C
-
-
100
µA
178/210
DS11626 Rev 5
L9678P, L9678P-S
16.9
Electrical characteristics
ER charge
All electrical characteristics are valid for the following conditions unless otherwise noted.
-40 °C Ta +95 °C, VINGOOD1(max) VIN 35 V, 8 V ERBOOST.
Table 29. ER current generator DC specifications
N°
Symbol
Parameter
Condition
1
IER_CHARGE
ER charge current
ERBOOST – VER 3 V
2
RDSON_ERCHARGE
ER charge power
resistance
(VERBOOST - VVER) / IVER
IVER = 10mA
Min
Typ
Max
Unit
-33
-30
-27
mA
-
-
22
Ω
Min
Typ
Max
Unit
-
-
6
s
Table 30. ER current generator AC specifications
N°
Symbol
1
TON_ERCAP
16.10
Parameter
Condition
CVER 4.7mF nominal,
BST33V = 0; Design Info
Energy reserve capacitor
charge-up time
ER switch
All electrical characteristics are valid for the following conditions unless otherwise noted.
-40 °C Ta +95 °C, VINGOOD1(max) VIN 35 V.
Table 31. ER switch DC specifications
N°
Symbol
1
RDSON ERSW
2
ILIM,ERSW
3
TJSD_ERSW
4
THYS_TSDERSW
Parameter
Condition
Min
Typ
Max
Unit
Power switch resistance
ILIM,ERSW(min)
0.5
-
3
Ω
ER switch current limit
-
400
-
600
mA
-
150
175
190
°C
-
5
10
15
°C
Min
Typ
Max
Unit
CVIN = 10µF
-
-
5
µs
-
-
-
10
µs
ER switch activation blanking
time after thermal shutdown
-
1
-
ms
Thermal shutdown
Table 32. ER switch AC specifications
N°
Symbol
Parameter
1
TON_ERSW
ER turn-on time (time to
reach either RDSON_ERSW or
ILIM_ERSW)
2
3
Condition
TFLT_TSD_ERSW Thermal shutdown filter time
TBLK_ERSW
DS11626 Rev 5
179/210
209
Electrical characteristics
16.11
L9678P, L9678P-S
COVRACT
All electrical characteristics are valid for the following conditions unless otherwise noted:
-40 °C Ta +95 °C, VINGOOD1(max) VIN 35 V, VDDx(min) VDDx VDDx(max),
VDDQ = VDD5 or VDD3V3
Table 33. COVRACT DC Specifications
N°
Symbol
1
VOH_COVRACT
2
VOL_COVRACT
Parameter
Condition
COVRACT output voltage
Min
Typ
Max
Unit
ILOAD = -0.5 mA
VDDQ
-0.6
-
VDDQ
V
ILOAD = 2.0 mA
0
-
0.4
V
Table 34. COVRACT AC specifications
N°
Symbol
1
TRISE_COVRACT
Rise time
2
TFALL_COVRACT
Fall time
16.12
Parameter
Condition
Min
Typ
Max
Unit
80pF load, 20%-80%
-
-
0.5
µs
80pF load, 20%-80%
-
-
0.5
µs
VDD5 regulator
All electrical characteristics are valid for the following conditions unless otherwise noted.
-40 °C Ta +95 °C, VINGOOD1(max) VIN 35 V.
Table 35. VDD5 regulator DC specifications
N°
Symbol
Parameter
Condition
Min
Typ
Max
Unit
1
VO_VDD5
Output voltage
Across all line and load,
steady state
4.85
5
5.15
V
2
IO_BVDD5
Base driver current limit
VDD5 > VDD5UVL
4
7
10
mA
3
IO_BVDD5_LOW
Base driver current limit
Low level
VDD5 < VDD5UVL
2
-
5
mA
4
IO_VDD5
Output load current
-
0.5
-
200
mA
5
dVSR_ac
Line transient response
All load IO_VDD5;
VIN=6V to 18V @ dt = 1 µs;
Design Info
4.5
-
5.5
V
4.5
-
5.5
V
6
dVLR_ac
Load transient response
All line;
IO_VDD5= 1mA to 100mA
@dt = 1 µs;
Design Info
7
IOF_VDD5
Open feedback current on
VDD5
Active only during
VDD5_rampup state
55
80
105
µA
8
VDD5OV
Over voltage detection
-
5.2
-
5.50
V
180/210
DS11626 Rev 5
L9678P, L9678P-S
Electrical characteristics
Table 35. VDD5 regulator DC specifications (continued)
N°
Symbol
Parameter
9
VDD5UV
Under voltage detection
10
VDD5UVL
Condition
Min
Typ
Max
Unit
-
4.5
-
4.8
V
Under voltage detection low
level
1.8
2
2.2
V
Min
Typ
Max
Unit
Table 36. VDD5 regulator AC specifications
N°
Symbol
1
TSOFTST_VDD5
2
Parameter
Condition
Soft start time
From 10% to 90%
1
2
3
ms
TFLT_VDD5OV
Over voltage
detection deglitch filter time
-
27
30
33
µs
3
TFLT_VDD5UV
Under voltage
detection deglitch filter time
-
27
30
33
µs
4
TFLT_VDD5UVL
Under voltage low
detection deglitch filter time
-
1.5
2
2.5
µs
Min
Typ
Max
Unit
Table 37. VDD5 regulator external components (Design Info)
N°
Symbol
1
hFE_PNP
2
Parameter
Condition
Output transistor gain
-
50
250
500
A/A
Ft_PNP
Output transistor transit
frequency
-
30
-
-
MHz
3
RVDD5BE
Output transistor baseemitter
Pull-up resistance
-
-
3
-
k
4
CBLK_VDD5
Output bulk capacitance
Min 4.7µF nominal
3
-
30
µF
-
-
-
50
mΩ
5
ESRCBLK_VDD5 Bulk capacitor ESR
DS11626 Rev 5
181/210
209
Electrical characteristics
16.13
L9678P, L9678P-S
VDD3V3 regulator
All electrical characteristics are valid for the following conditions unless otherwise noted.
-40 °C Ta +95 °C, VDD5(min) VDD5.
Table 38. VDD3V3 regulator DC specifications
N°
Symbol
1
VO_VDD3V3
2
IO_VDD3V3
3
Parameter
Condition
Min
Typ
Max
Unit
Output voltage
Across all line and load, steady
state
3.2
3.3
3.4
V
Output load current
capability
-
0.5
-
125
mA
-
150
-
-
mA
3
-
3.6
V
3
-
3.6
V
IO_LIM_VDD3V3 Output load current limit
All load IO_VDD3V3;
VIN = 6 V to 18 V @ dt = 1 µs;
Guaranteed by design
dVSR_ac
Line transient response
7
dVLR_ac
All line; IO_VDD3V3= 1mA to
100mA
Load transient response
@dt = 1 µs;
Guaranteed by design
4
VDD3V3OV
Over-voltage threshold
-
3.43
-
3.6
V
5
VDD3V3UV
Under voltage reset
threshold
-
3
-
3.17
V
Min
Typ
Max
Unit
6
Table 39. VDD3V3 regulator AC specifications
N°
Symbol
Parameter
1
TSOFTST_VDD3
2
3
Condition
Soft start time
From 10% to 90%
1
2
3
ms
TFLT_VDD3OV
Over voltage
detection deglitch filter time
-
27
30
33
µs
TFLT_VDD3UV
Under voltage
detection deglitch filter time
-
27
30
33
µs
Min
Typ
Max
Unit
Min 4.7µF nominal
3
-
30
µF
-
-
-
50
mΩ
Table 40. VDD3V3 regulator external components (design info)
N°
Symbol
1
CBLK_VDD3
2
Parameter
Output bulk capacitance
ESRCBLK_VDD3 Bulk capacitor ESR
182/210
Condition
DS11626 Rev 5
L9678P, L9678P-S
16.14
Electrical characteristics
VSUP regulator
All electrical characteristics are valid for the following conditions unless otherwise noted.
-40 °C Ta +95 °C, VINGOOD2(max) VIN 35 V.
Table 41. VSUP regulator DC specifications
N°
Symbol
1
VO_VSUP
2
Parameter
Condition
Min
Typ
Max
Unit
Output voltage
Across all line and load,
steady state
6.5
6.8
7.1
V
IO_BVSUP
Base driver current limit
-
4
7
10
mA
3
IO_VSUP
Output load current
-
0.5
200
mA
4
dVSR_ac
Line transient response
All load IO_VDD5;
VIN = 6 V to 18 V @ dt = 1 µs;
Design Info
6.2
7.4
V
6.2
7.4
V
8
V
5
dVLR_ac
Load transient response
All line;
IO_VDD5= 1mA to 100mA @dt = 1µs;
Design Info
6
VSUPOV
Over voltage detection
-
7.6
7
VSUPUV
Under voltage detection
-
1.8
2
2.2
V
Min
Typ
Max
Unit
From 10% to 90%
1
2
3
ms
Table 42. VSUP AC specifications
N°
1
Symbol
Parameter
TSOFTST_VSUP Soft start time
Condition
2
TFLT_VSUPOV
Over voltage
deglitch filter time
-
27
30
33
µs
3
TFLT_VSUPUV
Under voltage
deglitch filter time
-
27
30
33
µs
Min
Typ
Max
Unit
Table 43. VSUP regulator external components (Design Info)
N°
Symbol
1
hFE_PNP
2
Ft_PNP
3
RVSUPBE
4
CBLK_VSUP
5
Component
Conditions
Output transistor gain
-
50
250
500
A/A
Output transistor
transit frequency
-
30
-
-
MHz
Output transistor BaseEmitter
Pull-up Resistance
-
-
3
-
kΩ
Output Bulk Capacitance
Min 4.7µF nominal
3
-
30
µF
-
-
-
50
mΩ
ESRCBLK_VSUP Bulk Capacitor ESR
DS11626 Rev 5
183/210
209
Electrical characteristics
16.15
L9678P, L9678P-S
VSF regulator
All electrical characteristics are valid for the following conditions unless otherwise noted.
-40 °C Ta +95 °C, VINGOOD1(max) VIN 35 V, VSF + 2V ERBOOST
Table 44. VSF regulator DC specifications
N°
Symbol
Parameter
1
VSF
Output voltage
2
Condition
Min
Typ
Max
Unit
All line, load, IO_VSF up to 6 mA
SYS_CFG(VSF_V)= 0
18
20
22
V
All line, load, IO_VSF up to 6 mA
BST33V = 1, SYS_CFG(VSF_V)= 1
23
25
27
V
3
ILIM_VSF
Output load current limit
Test conditions: VSF = 0
7
10
13
mA
4
VDO_VSF
Drop-out voltage
V(ERBOOST-VSF)
-
-
2
V
5
CVSF
Output capacitance
Design Info.
2.9
-
14
nF
Device OFF
-5
5
µA
60
125
188
kΩ
6
ILKG_VSF_OFF VSF input leakage
7
RPD_VSF
VSF pull-down resistance
Device ON
VSF regulator OFF or ON
1.5V
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