L9733
Automotive octal self configuring low/high side driver
Datasheet - production data
Controlled SR for reduced EMC
Description
3RZHU662
*$3*36
The L9733 is a highly flexible monolithic, medium
current, output driver that incorporates 8 outputs
that can be used as either internal low or high-side
drives in any combination.
Outputs 1-8 are self-configuring as high or lowside drives. Self-configuration allows a user to
connect a high or low-side load to any of these
outputs and the L9733 will drive them correctly as
well as provide proper fault mode operation with
no other needed inputs. In addition, outputs 6, 7 and
8 can be PWM controlled via a external pins (IN6-8).
Features
AEC-Q100 (Rev. F) qualified
Eight independently self configuring low/high
drivers
Supply voltage from 4.5 V to 5.5 V
RON(max) = 0.7 Ω @ Tj = 25 °C,
RON(max) = 1.2 Ω @Tj = 125 °C
Minimum current limit of each output 1 A
Output voltage clamping min. 40 V in low-side
configuration
Output voltage clamping max. -14 V in high-side
configuration
SPI interface for outputs control and for
diagnosis data communication
Additional PWM inputs for 3 outputs
Independent thermal shutdown for all outputs
open load, short to GND, short to Vb,
overcurrent diagnostics in latched or unlatched
mode for each channel
Internal charge pump without need of external
capacitor
This device is capable of switching variable load
currents over the ambient range of -40 °C to
+125 °C. The outputs are MOSFET drivers to
minimize Vdd current requirements. For low-side
configured outputs an internal zener clamp from
the drain to gate with a breakdown of 50 V
minimum will provide fast turn off of inductive
loads. When a high-side configured output is
commanded Off after having been commanded
On, the source voltage will go to (VGND - 15 V).
An 16 bit SPI input is used to command the 8
output drivers either "On" or "Off", reducing the
I/O port requirement of the microcontroller.
Multiple L9733 can be daisy-chained. In addition
the SPI output indicates latched fault conditions
that may have occurred.
Table 1. Device summary
Order code
Package
Packing
L9733XP
PowerSSO-28 (Exposed pad)
Tube
L9733XPTR
PowerSSO-28 (Exposed pad)
Tape and reel
L9733CN
PowerSSO-28 (Exposed pad)
Tube
L9733CNTR
PowerSSO-28 (Exposed pad)
Tape and reel
May 2016
This is information on a product in full production.
DocID11319 Rev 12
1/35
www.st.com
Contents
L9733
Contents
1
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2
Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.1
3
4
Functional operative range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.1.2
Jump start conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.1.3
Operation at low battery condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.1.4
Operation at load dump condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.1.5
Loss of protection against short to battery . . . . . . . . . . . . . . . . . . . . . . . . 9
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.3
Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Electrical performance characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 11
3.1
DC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
3.2
AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
3.3
SPI characteristics and timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Configurations for outputs 1-8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
4.1.1
Low-side drivers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
4.1.2
High-side drivers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
4.2
Outputs 1-5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
4.3
Outputs 6-8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
4.4
Drn1-8 susceptibility to negative voltage transients . . . . . . . . . . . . . . . . . 19
4.5
Supply pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
4.6
2/35
2.1.1
2.2
4.1
5
Operating range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
4.5.1
Main power input (Vdd) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
4.5.2
Battery supply (Vbat) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
4.5.3
Discrete inputs voltage supply (VDO) . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Discrete inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
4.6.1
Output 6-8 enable input (In6, ln7, ln8) . . . . . . . . . . . . . . . . . . . . . . . . . . 20
4.6.2
Reset input (RES) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Serial peripheral interface (SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
DocID11319 Rev 12
L9733
6
7
Contents
5.1
Serial data output (DO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
5.2
Serial data input (DI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
5.3
Chip select (CS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
5.4
Serial clock (SCLK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
5.5
Initial input command register and fault register SPI cycle . . . . . . . . . . . . 22
5.6
Input command register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Other L9733 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
6.1
Charge pump usage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
6.2
Waveshaping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
6.3
POR register initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
6.4
Thermal shutdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Fault operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
7.1
7.2
Low-side configured output fault operation . . . . . . . . . . . . . . . . . . . . . . . 25
7.1.1
No latch mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
7.1.2
Latch mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
High-side configured output fault operation . . . . . . . . . . . . . . . . . . . . . . . 27
7.2.1
No latch mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
7.2.2
Latch mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
8
Application circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
9
Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
9.1
10
PowerSSO-28 (exposed pad) package information . . . . . . . . . . . . . . . . . 32
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
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3
List of tables
L9733
List of tables
Table 1.
Table 2.
Table 3.
Table 4.
Table 5.
Table 6.
Table 7.
Table 8.
Table 9.
Table 10.
Table 11.
Table 12.
Table 13.
Table 14.
4/35
Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Operating range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Thermal data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
DC characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
SPI characteristics and timings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Bit command register definition. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Command register logic definition. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Fault register definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Fault logic definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
PowerSSO-28 (exposed pad) package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Document revision history. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
DocID11319 Rev 12
L9733
List of figures
List of figures
Figure 1.
Figure 2.
Figure 3.
Figure 4.
Figure 5.
Figure 6.
Figure 7.
Figure 8.
Figure 9.
Figure 10.
Figure 11.
Pin connection (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Output turn on/off delays and slew rates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
DO loading for disable time measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Output loading for slew rate measurements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
SPI input/output timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
SPI timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Application schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
HVAC applicative examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Powertrain applicative examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Optimized circuit layout to achieve proper EMI/ESD capability . . . . . . . . . . . . . . . . . . . . . 31
PowerSSO-28 (exposed pad) package outline. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
DocID11319 Rev 12
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5
Pin description
1
L9733
Pin description
Figure 1. Pin connection (top view)
9''
9'2
6&/.
'
&6
'
65&
65&
'51
'51
'51
'51
65&
65&
65&
65&
'51
'51
'51
'51
65&
65&
,1
5(6
,1
,1
9EDW
*1'
*$3*36
Table 2. Pin description
6/35
N°
Pin
Function
1
VDD
5 Volt supply input
2
SCLK
SPI serial clock input
3
CS
4
SRC1
Source pin of configurable driver #1 (0.7 Ω Rdson @ +25 °C)
5
DRN1
Drain pin of configurable driver #1(0.7 Ω Rdson @ +25 °C)
6
DRN2
Drain pin of configurable driver #2 (0.7 Ω Rdson @ +25 °C)
7
SRC2
Source pin of configurable driver #2 (0.7 Ω Rdson @ +25 °C)
8
SRC3
Source pin of configurable driver #3 (0.7 Ω Rdson @ +25 °C)
9
DRN3
Drain pin of configurable driver #3 (0.7 Ω Rdson @ +25 °C)
10
DRN4
Drain pin of configurable driver #4 (0.7 Ω Rdson @ +25 °C)
11
SRC4
Source pin of configurable driver #4 (0.7 Ω Rdson @ +25 °C)
12
IN6
Discrete input used to PWM output driver #6
13
IN7
Discrete input used to PWM output driver #7
14
Vbat
Battery supply voltage
15
GND
Analog ground
16
IN8
Discrete input used to PWM output driver #8
17
RES
Reset input (active low)
18
SRC5
SPI chip select (active low)
Source pin of configurable driver #5 (0.7 Ω Rdson @ +25 °C)
DocID11319 Rev 12
L9733
Pin description
Table 2. Pin description (continued)
Note:
N°
Pin
Function
19
DRN5
Drain pin of configurable driver #5 (0.7 Ω Rdson @ +25 °C)
20
DRN6
Drain pin of configurable driver #6 (0.7 Ω Rdson @ +25 °C)
21
SRC6
Source pin of configurable driver #6 (0.7 Ω Rdson @ +25 °C)
22
SRC7
Source pin of configurable driver #7 (0.7 Ω Rdson @ +25 °C)
23
DRN7
Drain pin of low-side driver #7 (0.7 Ω Rdson @ +25 °C)
24
DRN8
Drain pin of low-side driver #8 (0.7 Ω Rdson @ +25 °C)
25
SRC8
Source pin of configurable driver #8 (0.7 Ω Rdson @ +25 °C)
26
DI
SPI data in
27
DO
SPI data out
28
VDO
Microcontroller logic interface voltage
The exposed slug must be soldered on the PCB and connected to GND.
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34
Operating conditions
L9733
2
Operating conditions
2.1
Operating range
This part may not operate if taken outside the operating range. Once the condition is
returned within the specified maximum rating or the power is recycled, the part will recover
with no damage or degradation.
Table 3. Operating range
Symbol
Vdd
Parameter
Supply voltage
Unit
4.5 to 5.5
V
Vbat (operative
range)
4.5V to 18
Vbat @ JSC
18 to 27
Vbat @ low
battery
Battery supply voltage
Vbat @ load
dump
Tj
3.5 to 4.5
V
27 to 40
Thermal junction temperature range
Snubbing voltage of DRN1-8
2.1.1
Value
IOx
Output current 1-8
Eso
Maximum clamping energy at switch-off
-40 to 150
°C
min 50
VDC
max 800
mA
20
mJ
Functional operative range
4.5 V ≤ Vbat ≤ 18 V (-40 °C ≤ Tj ≤ 150 °C);
All the electrical capabilities are guaranteed by characterization as reported in Section 3:
Electrical performance characteristics.
2.1.2
Jump start conditions
18 V ≤ Vbat ≤ 27 V (-40 °C ≤ Tj ≤ 150 °C);
Operation at Jump start condition for a maximum duration of 1 minute.
All ouputs are switched according to the commands on the SPI bus or the PWM inputs. The
SPI bus and the inputs are functional during the Jump-Start condition.
The over-temperature shutdown and over current protection of the device are not
guaranteed to stay functional for Vbat between 18 V and 27 V.
The reliability and the functionality of the L9733XP are not compromised when the JumpStart condition is not repeated for more than five times.
8/35
DocID11319 Rev 12
L9733
2.1.3
Operating conditions
Operation at low battery condition
3.5 V ≤ Vbat 4.5 V (-40 °C Tj 150 °C);
All outputs are able to keep the status according to the commands on the SPI bus or the
PWM inputs. Switching commands entered via the SPI bus might not be executed by the
L9733 at low-battery condition. The SPI bus and the inputs are functional during the LowBattery condition.
2.1.4
Operation at load dump condition
27 V ≤ Vbat ≤ 40 V (-40 °C ≤ Tj ≤ 150 °C)
There is not an internal circuit that switches OFF the drivers during load dump condition.
The over-temperature shutdown and over current protection of the device are not
guaranteed to stay functional during load dump condition.
2.1.5
Loss of protection against short to battery
When the battery supply voltage, Vbat (pin 14) is switched off during a short-to-battery
condition at an output in high-side configuration, the protection circuits are no longer
functional, and the L9733 may fail with EOS.
2.2
Absolute maximum ratings
This part may be irreparably damaged if taken outside the specified absolute maximum
ratings. Operation outside the absolute maximum ratings may also cause a decrease in
reliability.
Table 4. Absolute maximum ratings
Symbol
Parameter
Value
Unit
VDD
Supply voltage
-0.3 to 7
V
Vbat
Supply voltage
-0.3 to 40
V
-
CS,DI,DO,SCLK,EN,IN6,IN7,IN8,VDO
-0.3 to 7.0
V
-
SRCx pin
min. -24
VDC
-
Max. value of VSRCx = Minimum of {Vbat +1V ||| VDRNx+0,3 V ||| +40 V}
-
DRN1-8(1)
-
-0.3 to 60
VDC
2.5
A
IOL
Current limit of output 1-8 (-40 °C)
IOP
Over current protection at output 1-8 (-40 °C)
3
A
Maximum clamping energy
20
mj
±2 (2)
kV
(2)
kV
ESD
Human body model - All pins
Human body model - Driver outputs
±4
1. For the DRNx the MAX ASB value is the Max Clamp Voltage (see Table 6 on page 13 - DRNx Clamp
voltage).
2. Device is only protected vs. GND.
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34
Operating conditions
2.3
L9733
Thermal data
Table 5. Thermal data
Symbol
Parameter
Typ
Max
Unit
Tamb
Operating ambient temperature
-40
-
125
°C
Tstg
Storage temperature
-50
-
150
°C
-
-
150
°C
151
175
200
°C
Tj
Maximum operating junction temperature
Rth
Thermal shutdown temperature
Rth-hys
Thermal shutdown temperature hysteresis
7
10
25
°C
RTh j-amb
Thermal resistance junction-to-ambient (1)
-
-
24
°C/W
-
-
3
°C/W
RTh j-case Thermal resistance junction-to-case
1. With 2s2p PCB thermally enhanced.
10/35
Min
DocID11319 Rev 12
L9733
3
Electrical performance characteristics
Electrical performance characteristics
These are the electrical capabilities this part was designed to meet. It is required that every
part meets these characteristics.
3.1
DC characteristics
Tamb = -40 to 125 °C, Vdd = 4.5 to 5.5 Vdc, Vbat = 4.5 to 18 Vdc (high-side configuration),
unless otherwise specified.
Table 6. DC characteristics
Symbol
IN6vih
IN6vil
IIN6il
IIN6ih
IN7vih
IN7vil
IIN7il
IIN7ih
IN8vih
IN8vil
IIN8il
IIN8ih
CSih
CSil
ICSih
ICSil
SCLKih
SCLKil
ISCLKih
ISCLKil
DIih
DIil
IDIih
IDIil
DOol
DOoh
Parameter
IN6 input voltage
IN6 input current
IN7 input voltage
IN7 input current
IN8 input voltage
IN8 input current
CS input voltage
CS input current
SCLK input voltage
SCLK input current
DI input voltage
DI input current
DO output voltages
Conditions
Min
Typ
Max
Units
-
-
-
0.7vdo
V
-
0.3vdo
-
-
V
-
-
|10|
μA
10
-
100
μA
-
-
-
0.7vdo
V
-
0.3vdo
-
-
V
-
-
|10|
μA
10
-
100
μA
-
-
-
0.7vdo
V
-
0.3vdo
-
-
V
-
-
|10|
μA
10
-
100
μA
-
-
-
0.7vdo
V
-
0.3vdo
-
-
V
-
-
|10|
μA
10
-
100
μA
-
-
-
0.7vdo
V
-
0.3vdo
-
-
V
-
-
|10|
μA
10
-
100
μA
-
-
-
0.7vdo
V
-
0.3vdo
-
-
V
-
-
|10|
μA
10
-
100
μA
IDO = 2.5 mA
-
-
0.4
V
IDO = -2.5 mA
vdo-0.6
-
-
V
In6 = 0 VDC
In6 = VDO
In7 = 0 VDC
In7 = VDO
In8 = 0 VDC
In8 = VDO
CS = VDO
CS = 0 VDC
SCLK = VDO
SCLK = 0 VDC
DI = VDO
DI = 0 VDC
DocID11319 Rev 12
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34
Electrical performance characteristics
L9733
Table 6. DC characteristics (continued)
Symbol
IDOzol
IDOzoh
RESih
RESil
IRESil
IRESih
PORth
Parameter
DO Tri-state currents
RES input voltage
RES input current
Power on reset threshold
Conditions
Min
Typ
Max
Units
DO = 0 VDC
-
-
|10|
μA
DO = VDO
-
-
|10|
μA
-
-
-
0.7vdo
V
-
0.3vdo
-
-
V
10
-
100
A
-
-
|10|
A
@ -40 °C
2.8
-
4.2
@ 25 °C
2.8
-
3.7
@ 125 °C
2
-
3.4
-
-
RES = 0 VDC
RES = VDO
Islp
Vbat sleep current
VDD = SRC1-8 = 0VDC
DRN1-DRN8=18VDC, Vb. Sum
currents (Tamb > 0 °C)
(Tamb @ -40 °C)
Ivbat
Vbat current
VDD = 5 V
All Outputs Commanded On
-
IVDD
Max. VDD current
All Outputs Commanded On
IVDD
Min. VDD current
All Outputs Commanded Off
IDRN1lk IDRN8lk
DRN1 - DRN8
leakage currents
(low-side)
ISRC1lk ISRC8lk.
SRC1 – SRC8
Leakage currents
(high-side)
IDrn1-8sink
SRC1-8 = GND DI = AC00h
DRN1 – DRN8 sink current
Rload≤ 11 kΩ
(low-side)
Rload≤ 200 kΩ
RDRN1-8
IDrn1-8source
Isrc1-8sink
Isrc1-8source
VDrn1-8open
12/35
V
10
3
μA
μA
-
15
mA
-
-
8.5
mA
0.5
-
VDD = 0 VDC: SRC1-8 = 0 VDC
DRN1- DRN8 = 16 VDC
DRN1- DRN8 = 40 VDC
-
-
5
10
μA
μA
VDD = 0 VDC: SRC1-8 = 0 VDC
DRN1- 8 = 16 V
DRN1- 8 = 40 VDC
-
-
-5
-10
μA
μA
10
120
-
100
280
μA
μA
mA
Open load detection
resistance
VBAT ≥ 9 V
11
-
200
KΩ
Source current
DRN1-DRN8 = GND
-10
-
-100
μA
SRC1 – SRC8
sink/source current
(high-side)
DRN1- 8 = Vb, DI = AC00h
SCR1- 8 = Vb
10
100
μA
SCR1- 8 = GND
-18
-
-100
μA
SRC1- 8 = GND, DI = AC00h
DRN1- DRN8 = Open
VDD=4.9 to 5.1 VDC
2.7
-
3.1
V
SRC1- 8 = GND, DI = AC00h
DRN1- DRN8 = Open
VDD = 4.5 to 5.5 V
2.5
-
3.5
V
DRN1 – DRN8
open load voltage
(low-side)
DocID11319 Rev 12
-
L9733
Electrical performance characteristics
Table 6. DC characteristics (continued)
Symbol
Parameter
Conditions
Min
Typ
Max
Units
2.0
-
2.8
V
2.2
2.5
A
A
2.7
3
A
A
2.2
2.5
A
A
2.7
3
A
A
SRC1 – SRC8 open load
voltage (High-side)
DRN1 - DRN8
DRN1-8 = Vb, DI = AC00h
SCR1-8 = open
IDRN1limit IDRN8limit
DRN1 - DRN8
current limits
(low-side)
DI = ACFFh, DI = AAFFh
SRC1 – SRC8 = 0 VDC
DRN1 - DRN8 = 4.5 - 16 VDC
(Tamb > 0 °C)
(Tamb @ -40 °C)
1
1
IDRN1OVCIDRN8OVC
DRN1 - DRN8
overcurrent threshold
(low-side)
DI = AC00h, DI = AA00h SRC1 –
SRC8 = 0 VDC
DRN1 - DRN8 = 4.5 - 16 VDC
(Tamb > 0 °C)
(Tamb - 40 °C)
1
1
ISRC1limitISRC8limit
SRC1 – SRC8
current limits
(high-side)
DI = ACFFh, DI = AAFFh
DRN1 - DRN8 = Vb
SRC1 – SRC8 = GND
(Tamb > 0 °C)
(Tamb - 40 °C)
1
1
ISRC1OVCISRC8OVC
Overcurrent threshold
(high-side)
DRN1 - DRN8 = Vbat
SRC1 – SRC8 = GND
(Tamb > 0 °C)
(Tamb - 40 °C)
1
1
DRN1Cl+ DRN8Cl+
DRN1 - DRN8
Clamp voltages (low-side)
DI = AC00h
SRC1-8 = GND, IDRN1-8 = 350 mA
50
-
60
V
SRC1Cl+SRC8Cl+
SRC1 – SRC8
DI = AC00h
Clamp voltages (High-side) DRN1-8 = Vbat, ISRC1-8 = -350 mA
-24
-
-14
V
Vsrc1-8open
-
-
-
-
VDrn1-8open
- DRN18VthGND
Short to GND threshold
distance from open load
voltage (low-side)
SRC1 – SRC8 = GND:
Decrease Drn1 - Drn8 until Faults
are ”Set”
0.3
-
0.7
V
DRN18VthVbatVDrn1-8open
DRN1 - DRN8
Short to Vbat threshold
distance from open load
voltage (low-side)
DI = AC00h
SRC1 – SRC8 = GND: Increase
Drn1 - Drn8 until Faults are ”Not
Set”
0.3
-
0.7
V
VDrn1-8open
- SRC18VthGND
SRC1 - SRC8
Short to GND threshold
distance from open load
voltage (High-side)
DI = AC00h
Drn1 – Drn8 = Vb: Decrease SRC1
- SRC8 until Faults are ”Not Set”
0.2
-
0.6
V
SRC18VthVbatVDrn1-8open
SRC1 – SRC8
Short to Vbat threshold
distance from open load
voltage (High-side)
DI = AC00h
Drn1 – Drn8 = Vbat: Increase
SCR1 - SCR8 until Faults are ”
Set”
0.2
-
0.6
V
DocID11319 Rev 12
13/35
34
Electrical performance characteristics
L9733
Table 6. DC characteristics (continued)
Symbol
Parameter
Conditions
On resistance
RdsonDrn1-8(1)
(Drn to SRC1-8)
Min
Typ
Max
Units
@ +125 °C @ IDRN = 350 mA
-
-
1.2
Ω
@ +25 °C @ IDRN = 350 mA
-
-
0.7
Ω
@ -40 °C @ IDRN = 350 mA
-
-
0.5
Ω
151
-
200
°C
5
-
15
°C
Drn1-8ther(2)
Thermal shutdown
temperature
DI = ACFFh, IDrn1-8 = 1 mA,
SRC1 – SRC8 = GND, Increase
temperature until Drn1 - Drn8 > 2
VDC, Verify DO Bits 0-15 are ”Set”
Drn1-8hyst(2)
Hysteresis
Drn1 - Drn8 < 2 VDC
1. RdsonDrn1-8 1.2 Ω; at Vbat between 3.5 V and 27 V and T between -40 °C and 150 °C
2. Design Information, not tested.
3.2
AC characteristics
Tamb = -40 to 125 °C, Vdd = 4.5 to 5.5 Vdc, Vbat = 4.5 to 18 Vdc, unless otherwise specified
Table 7. AC characteristics
Symbol
Min
Typ
Max
Units
TfiltDRN1-8
DRN1 - DRN8
DI = AC00h, DI = A3FFh
Open load & short to
GND filter time (low-side) SRC1 – SRC8 = GND
(Latch mode)
300
-
900
μs
TfiltSRC1-8
SRC1 - SRC8
Open load & short to
Vbat filter time
(high-side)
(Latch mode)
DI = AC00h, DI = A3FFh
DRN1 – DRN8 = Vb
300
-
900
μs
TdelDRN1-8
DRN1 - DRN8
Overcurrent switch off
delay
(low-side)
DI = ACFFh, DI = AA00h
SRC1 – SRC8 = GND
10
-
75
μs
TdelSRC1-8
SRC1 - SRC8
Overcurrent switch off
delay
(high-side)
DI = ACFFh, DI = AA00h
DRN1 – DRN8 = Vb
10
-
75
μs
Tres
Restart time after
overcurrent switch off
time (Int)
DI = ACFFh, DI = AA00h
120
-
450
ms
Drn1-8htol
Slew rate
turn on
Outputs loaded as Figure 4
See Figure 2
0.65
1.95
V/μs
Drn1-8ltoh
Turn off (low-side)
See Figure 2
0.5
1.5
V/μs
14/35
Parameter
Conditions
DocID11319 Rev 12
-
L9733
Electrical performance characteristics
Table 7. AC characteristics (continued)
Symbol
Parameter
Conditions
Min
Outputs loaded as Figure 4
See Figure 2
Typ
Max
Units
1.95
V/μs
1.5
V/μs
20
μs
100
μs
20
μs
SRC1-8htol
Slew rate
turn on
SRC1-8ltoh
Turn off (High-side)
Drn1-8tondly
Delay time
Turn on
Outputs loaded as Figure 4
See Figure 2
2
Drn1-8toffdly
Turn off (low-side)
See Figure 2
10
SRC1-8tondly
Delay time
Turn on
Outputs loaded as Figure 4
See Figure 2
2
See Figure 2
10
-
100
μs
0.5
See Figure 2
SRC1-8toffdly Turn off (high-side)
-
0.65
-
Drn1-8offon
Delay delta
Drn1-8toffdly - Drn1-8tondly
10
-
60
μs
SRC1-8offon
Delay delta
SRC1-8toffdly - SRC1-8tondly
10
-
60
μs
Figure 2. Output turn on/off delays and slew rates
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DocID11319 Rev 12
15/35
34
Electrical performance characteristics
3.3
L9733
SPI characteristics and timings
Tamb= -40 to 125 °C, Vdd = 4.5 to 5.5 Vdc, Vbat = 4.5 to 18 Vdc, unless otherwise specified
Table 8. SPI characteristics and timings
Symbol
DINCin
Parameter
Conditions
Min
Typ
Max
Units
-
-
20
pF
-
-
20
pF
Input capacitance
-
DOrise
Output data (do)
rise time
50 pF from DO to Ground
See Figure 5
-
-
70
ns
DOfall
Output data (do)
fall time
See Figure 5
-
-
70
ns
DOa
Access time
See Figure 6
-
-
350
ns
DOsum
Set up time
See Figure 6
20
-
-
ns
DOhm
Hold time
See Figure 6
10
-
-
ns
DOdis
Output data (DO)
disable time
No Capacitor on DO, See Figure 5
-
-
400
ns
tthFilt
Filter time
All Fault bits are “Set”
SCLKCin
SCLKwid
SCLK width
5
-
20
s
See Figure 5, @ fSCLK =
5.4MHz(1)
185
-
-
ns
5.4MHz(1)
58
-
-
ns
SCLKlm
SCLK low time
See Figure 5, @ fSCLK =
SCLKhm
SCLK high time
See Figure 5, @ fSCLK = 5.4MHz(1)
58
-
-
ns
SCLK rise time
See Figure 5, @ fSCLK =
5.4MHz(1)
-
-
21
ns
SCLK fall time
See Figure 5, @ fSCLK =
5.4MHz(1)
-
-
21
ns
CSrise
Channel select (CS)
rise time
See Figure 5 (1)
-
-
100
ns
CSfall
Channel select (CS)
fall time
See Figure 5 (1)
-
-
100
ns
CSlead
Channel select (CS)
lead time
See Figure 6 (1)
455
-
-
ns
CSlag
Channel select (CS)
lag time
See Figure 6 (1)
50
-
-
ns
DIrise
Input data (DI)
rise time
See Figure 5, @ fSCLK = 5.4MHz(1)
-
-
30
ns
DIfall
Input data (DI)
fall time
See Figure 5 @ fSCLK = 5.4MHz(1)
-
-
30
ns
DIsus
Input data (DI)
set-up time
See Figure 6, @ fSCLK = 5.4MHz(1)
15
-
-
ns
DIhs
Input data (DI)
hold time
See Figure 6, @ fSCLK = 5.4MHz(1)
10
-
-
ns
CS rise to SCLK rise
See Figure 6, @ fSCLK = 5.4MHz(1)
40
-
300
ns
SCLKrise
SCLKfall
CS2SCLK
1. Guaranteed by design.
16/35
DocID11319 Rev 12
L9733
Electrical performance characteristics
Figure 3. DO loading for disable time measurement
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34
Functional description
4
L9733
Functional description
L9733 integrates 8 self-configuring outputs (OUT1-8) which are able to drive either
incandescent lamps, inductive loads (non-pwm'd, in pwm an external diode to reduce
flyback power dissipation is necessary), or resistive loads biased to Vbat (low-side
configuration) or to GND (high-side configuration). These outputs can be enabled and
disabled via the SPI bus. Each of these outputs has a short circuit protection (with
0.8-2.4 Amps threshold) selectable via SPI bus between a filtered switching OFF
overcurrent protection or a linear current limitation (default condition after power ON is
switching OFF protection enabled).
An over-temperature protection as described in Section 2.1 is available for each output.
When a high-side configured output is commanded OFF after having been commanded ON,
the source voltage will go to (VGND - 15 V). This is due to the design of the circuitry and the
transconductance of the MOSFET. When a low-side configured output is commanded OFF
after having been commanded ON, the output voltage will rise to the internal zener clamp
voltage (50 VDC minimum) due to the flyback of the inductive load.
Outputs 1-8 are able to drive any combination of inductive loads or lamps at one time.
Inductive loads for the L9733 can range from 35 mH to a maximum of 325 mH. The
recommended worst-case solenoid loads (at -40 °C) are calculated using a minimum
resistance of 40 Ω for each output. The maximum single pulse inductive load energy the
L9733 output is able to be safely handled is 20 mJ at -40 °C to 125 °C (Worst-case load of
325 mH and 40 Ω).
4.1
Configurations for outputs 1-8
The drain and source pins for each output must be connected in one of the two following
configurations (see Figure 7).
4.1.1
Low-side drivers
When any combination of outputs 1-8 are connected in a low-side drive configuration the
source of the applicable output (Src1-8) shall be connected to ground. The drain of the
applicable output (Drn1-8) shall be connected to the low-side of the load.
4.1.2
High-side drivers
When any combination of outputs 1-8 are connected in a high-side drive configuration the
drain of the applicable output (Drn1-8) shall be connected to Vbat. The source of the
applicable output (Src1-8) shall be connected to the high-side of the load.
4.2
Outputs 1-5
These five outputs can be used as either high or low-side drives. The room temperature
Rdson of these outputs is 0.7 Ω A current limited (100 μA max) voltage generator is
connected to Src 1-5 for open load and short to GND detection when a low-side configured
output is commanded OFF. Another current limited (100 μA max if VDrn 1-5 > 60 %Vbat,
280 μA max if VDrn 1-5 < 60 % Vbat) voltage generator is connected to Drn 1-5 for open
load and short to V bat detection when a high-side configured output is commanded OFF.
18/35
DocID11319 Rev 12
L9733
Functional description
Drain pins of outputs 1-5 (Drn1-5) are connected to the drains of the N channel MOSFET
transistors. Source pins of outputs 1-5 (Src1-5) are connected to the sources of the
N-channel MOSFET transistors.
4.3
Outputs 6-8
These three self-configuring outputs can be used to drive either high or low-side loads. In
addition to being controlled by the SPI BUS these outputs can also be enabled and disabled
via the IN6 & IN7& IN8 inputs. The IN6, IN7 and IN8 inputs are logically OR'd with the SPI
commands to allow either the IN6 & IN7 & IN8 inputs or the SPI commands to activate these
outputs. The use of the IN6 & IN7 & IN8 pins for PWM control on these outputs should only
be done with non-inductive loads if an external flyback diode is not present. The room
temperature Rdson of these four outputs is 0.7 Ω. A current limited (100 μA max) voltage
generator is connected to Src 6-8 for open load and short to GND detection when a low-side
configured output is commanded OFF. Another current limited (100 μA max if VDrn 6-8 >
60%Vbat, 280 μA max if VDrn 6-8 < 60 %Vbat) voltage generator is connected to Drn 6-8
for open load and short to Vbat detection when a high-side configured output is commanded
OFF.
Drain pins of Outputs 6-8 (Drn6-8) are connected to the drains of the N channel MOSFET
transistors. Source pins of Outputs 6-8 (Src6-8) are connected to the sources of the N
channel MOSFET transistors.
4.4
Drn1-8 susceptibility to negative voltage transients
All outputs connected in the low-side configuration must have a ceramic chip capacitor of
0.01 μF to 0.1 μF connected from drain to ground. This is needed to prevent potential
problems with the device operation due to the presence of fast negative transient(s) on the
drain(s) of the device. Adequate de-coupling capacitors from the Drain (VBAT) to ground
shall be provided for high-side configured outputs.
4.5
Supply pins
4.5.1
Main power input (Vdd)
An external +5.0 ±0.5 VDC supply provided from an external source is the primary power
source to the L9733. This supply is used as the power source for all of its internal logic
circuitry and other miscellaneous functions.
4.5.2
Battery supply (Vbat)
This input is the supply for the on board charge pump. This input shall be connected directly
to battery. If this input is not connected to the same supply, without additional voltage drops,
of the drains of any high-side connected outputs, then the Rdson of that given output will be
higher than the specified maximum.
4.5.3
Discrete inputs voltage supply (VDO)
This pin is used to supply the discrete input stages of L9733 and must be connected to the
same voltage used to supply the peripherals of the processor interfaced to L9733.
DocID11319 Rev 12
19/35
34
Functional description
L9733
4.6
Discrete inputs
4.6.1
Output 6-8 enable input (In6, ln7, ln8)
This input allows Output 6 (or Output 7, or Output 8) to be enabled via this external pin
without the use of the SPI. The SPI command and the In6-7 input are logically OR'd
together. A logic "1" on this input (In6, ln7 or ln8) is enable the corresponding output no
matter what the status of the SPI command register is. A logic "0" on this input will disable
this output if the SPI command register is not commanding this output on. This pins (In6, ln7
or ln8) can be left "open" if the internal output device is being controlled only via the SPI.
This input has a nominal 100 kΩ resistor connected from this pin to ground, which will pull
this pin to ground if an open circuit condition occurs. This input is ideally suited for noninductive loads that are pulse width modulated (PWM'd). This allows PWM control without
the use of the SPI inputs.
4.6.2
Reset input (RES)
When this input goes low it resets all the internal registers and switches off all the output
stages. This input has a nominal 100 kΩ resistor connected from this pin to VDD, which will
pull this pin to VDD if an open circuit condition occurs.
20/35
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L9733
5
Serial peripheral interface (SPI)
Serial peripheral interface (SPI)
The L9733 has a serial peripheral interface consisting of Serial Clock (SCLK), Data Out
(DO), Data In (DI), and Chip Select (CS). All outputs will be controlled via the SPI. The input
pins CS, SCLK, and DI, thanks to VDO pin, have level input voltages allowing proper
operation from microcontrollers that are using 5.0 or 3.3 volts for their Vdd supply. The
design of the L9733 allows a "daisy-chaining" of multiple L9733's to further reduce the need
for controller pins.
5.1
Serial data output (DO)
This output pin is in a tri-state condition when CS is a logic '1'. When CS is a logic '0', this pin
transmits 16 bits of data from the fault register to the digital controller. After the first 16 bits of
DO fault data are transmitted (after a CS transition from a logic '1' to a logic '0'), then the DO
output sequentially transmits the digital data that was just received (16 SCLK cycles earlier)
on the DI pin. The DO output continues to transmit the 16 SCLK delayed bit data from the DI
input until CS eventually transitions from a logic '0' to a logic '1'. DO data changes state 10
nsec or later, after the falling edge of SCLK. The LSB is the first bit of the byte transmitted
on DO and the MSB is the last bit of the byte transmitted on DO, once CS transitions from a
logic '1' to a logic '0'.
5.2
Serial data input (DI)
This input takes data from the digital controller while CS is low. The L9733 accepts a 16 bit
byte to command the outputs on or off. The L9733 also serially wraps around the DI input
bits to the DO output after the DO output transmits its 16 fault flag bits. The LSB is the first
bit of each byte received on DI and the MSB is the last bit of each byte received on DI, once
CS transitions from a logic '1' to a logic '0'. The last 4 bits (b15-b12) of the first 16 bit byte
are used as key-word. The 4 bits (b11-b8) of the first 16 bits byte are used to select writing
mode between OUT8-1 status and diagnosis operating mode . The DI input has a nominal
100 kΩ resistor connected from this pin to the VDO pin, which pulls this pin to VDO if an
open circuit condition occurs.
5.3
Chip select (CS)
This is the chip select input pin. On the falling edge of CS, the DO pin is released from tristate mode. While CS is low, register data are shifted in and shifted out the DI pin and DO
pin, respectively, on each subsequent SCLK. On the rising edge of CS, the DO pin is tristated and the fault register is "Cleared" if a valid DI byte has been received. A valid DI byte
is defined as such:
–
a multiple of 16 bits was received;
–
a valid key-word was received.
The fault data is not cleared unless all of the 2 previous conditions have been met. The CS
input has a nominal 100 kΩ resistor connected from this pin to the VDO pin, which pulls this
pin to VDO if an open circuit condition occurs.
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34
Serial peripheral interface (SPI)
5.4
L9733
Serial clock (SCLK)
This is the clock signal input for synchronization of serial data transfer. DI data is shifted into
the DI input on the rising edge of SCLK and DO data changes on the falling edge of SCLK.
The SCLK input has a nominal 100 kΩ resistor connected from this pin to the VDO pin,
which pulls this pin to VDO if an open circuit condition occurs.
5.5
Initial input command register and fault register SPI cycle
After initial application of Vdd to the L9733, the input command register and the fault register
are "Cleared" by the POR circuitry and that means that the default condition for the output
status is Off, the default diagnostic mode is No Latch and the switching OFF overcurrent
protection is enable. During the initial SPI cycle, and all subsequent cycles, valid fault data
will be clocked out of DO (fault bits).
5.6
Input command register
An input byte (16 bits) is routed to the Command Register. The content of this Command
Register is given in Table 10. Additional DI data will continue to be wrapped around the DO
pin. If CS should happen to go high before complete reception of the current byte, this just
transmitted byte shall be ignored (invalid).
Table 9. Bit command register definition
Key word
Writing mode: output
Output status
MSB
LSB
1
0
1
0
1
1
0
0
b15
b14
b13
b12
b11
b10
b9
b8
Key word
OUT 8 OUT 7 OUT 6 OUT 5 OUT 4 OUT 3 OUT 2 OUT 1
b7
b6
b5
Writing mode: diag
b4
b3
b2
b1
Driver diag mode
MSB
LSB
1
0
1
0
0
0
1
1
b15
b14
b13
b12
b11
b10
b9
b8
Key word
Diag 8 Diag 7 Diag 6 Diag 5 Diag 4 Diag 3 Diag 2 Diag 1
b7
b6
Writing mode: protect
b5
b4
b3
b2
b1
b0
Driver overcurrent protection
MSB
LSB
1
0
1
0
1
0
1
0
b15
b14
b13
b12
b11
b10
b9
b8
22/35
b0
Ilim 8 Ilim 7 Ilim 6 Ilim 5 Ilim 4 Ilim 3 Ilim 2
b7
b6
DocID11319 Rev 12
b5
b4
b3
b2
b1
Ilim 1
b0
L9733
Serial peripheral interface (SPI)
Table 10. Command register logic definition
Bit
State
Status
b0-b7
0
OUT1 - OUT8 are commanded off
Output
b0-b7
1
OUT1 - OUT8 are commanded on
Output
b0-b7
0
OUT1 - OUT8 diagnostic is No Latch Mode
Diag
b0-b7
1
OUT1 - OUT8 diagnostic is Latch Mode
Diag
b0-b7
0
OUT1 - OUT8 switching OFF overcurrent protection
Protection
b0-b7
1
OUT1 - OUT8 linear overcurrent protection
Protection
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Writing mode
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Other L9733 features
L9733
6
Other L9733 features
6.1
Charge pump usage
In order to provide low Rdson values when connected in a high-side configuration, a charge
pump to drive the internal gate voltage(s) above Vbat is implemented. The charge pump
used on the L9733 doesn't need external capacitor. The L9733 uses a common charge
pump and oscillator for all the 8 configurable output channels. The charge pump uses the
Vbat supply connected directly to the Vb pin. The normal range of the Vbat voltage is 10 to
18V18V. However, the L9733 is functional with Vbat voltages as low as 4.5 V DC with
eventually a degradation of Rdson.
The frequency range of this charge pump is from 3.6 to 7.6 MHz. The frequency is above
1.8 MHz in order to be above the AM radio band and below 8.0 MHz so that harmonics do
not get within the FM radio band.
6.2
Waveshaping
Both the turn on and the turn off slew rates on all outputs (OUT1-8) are limited to between
10 μs and 100 μs for both rise and fall times (10 to 90 %, and vice versa), to reduce
conducted EMC energy in the vehicle's wiring harness. The characteristics of the turn-on
and turn-off voltage is linear, with no discontinuities, during the output driver state transition.
6.3
POR register initialization
When the L9733 wakes up, the Vdd supply to the L9733 is allowed from 0 to 5 VDC in 0.3 to
3ms. The L9733 has a POR circuit, which monitors the Vdd voltage. When the Vdd voltage
reaches an internal threshold, and remains above this trip level for at least 5 to 20 μs, the
Command and Fault registers are "cleared". Before Vdd reaches this trip level, none of the
eight outputs are allowed to momentarily glitch on.
6.4
Thermal shutdown
Each of the eight outputs has independent thermal protection circuitry that disables each
output driver once the local N-Channel MOSFET's device temperature reaches between
+151 and +200 °C. A filter is present to validate the thermal fault (5 μs to 20 μs). There is a
5 to 15 °C hysteresis between the enable and disable temperature levels. The faulted
channel will periodically turn off and on until the fault condition is cleared, the ambient
temperature is decreased sufficiently or the output is commanded off. If a thermal shutdown,
of one or more output drivers, is active during the falling edge of the chip select (CS) signal
all the bits of the Fault Register are "set" to "1" (thermal shutdown is not latched and could
be read only in the moment it is present). The thermal fault is cleared on the rising edge of
Chip Select if a valid DI byte is received.
Note:
24/35
Due to the design of the L9733 each output's thermal limit "may not" be truly independent to
the extent that if one output is shorted, it may impact the operation of other outputs (due to
lateral heating in the die).
DocID11319 Rev 12
L9733
Fault operation
7
Fault operation
The fault diagnostic capability consists of one internal 16 bits shift register and 2 bits are
used for each output. The diagnostic information is: no fault present, overcurrent, open load
and short circuit.
For L9733XP all of the faults will be cleared on the rising edge of chip select if a valid DI byte
is received.
For L9733CN the OVC register are cleared when the end of the diagnosis restart time Tres is
reached or by the input signal (IN) in low state. The other faults are cleared on the rising
edge of chip select if a valid DI byte is received.
Table 11. Fault register definition
OUT 8
OUT 7
OUT6
OUT5
OUT4
OUT3
OUT2
OUT1
MSB
LSB
D1
D0
D1
D0
D1
D0
D1
D0
D1
D0
D1
D0
D1
D0
D1
D0
b15
b14
b13
b12
b11
b10
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
Table 12. Fault logic definition
D1
D0
Fault status
0
0
No fault is present
0
1
Open load
1
0
Short circuit to GND (low-side) or short circuit to Vbat (high-side)
1
1
Overcurrent
If all the bits b0-b15 of the fault register have value '1' it means that a thermal fault, at least
on one of the eight independent Outputs, occurred.
7.1
Low-side configured output fault operation
The diagnostic circuitry verifies for the low-side configured output the following condition:
Normal operation, open load, short circuit to GND and overcurrent (only if the switching OFF
protection, selectable for each channel via SPI bus, is active).
The diagnostic circuitry operates in two different modes, selected for each channel by SPI:
no latch mode and latch mode. The fault priority is overcurrent and then open load or short
circuit to GND, this means that if an overcurrent occurs the fault register is always
overwritten and following open load or short to GND faults that happen before that the
register is cleared will be ignored.
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34
Fault operation
7.1.1
L9733
No latch mode
This diagnostic operating mode doesn't latch open load and short to GND faults.
1. Open load
The diagnostic of open load is detected only in OFF condition sensing the Drn1-8
output voltage. This fault is detected on the falling edge of the CS input if the power
drain voltage is inside the voltage range limited by the two thresholds Vth_Vbat and
Vth_GND. An internal current limited voltage regulator fixes the drain voltage inside the
described range when no load is connected.
2. Short circuit to GND
The diagnostic of short circuit to GND is detected only in OFF condition sensing the
Drn1-8 output voltage. This fault is detected on the falling edge of the CS input if the
power drain voltage is lower than the Vth_GND threshold.
3. Overcurrent
The diagnostic of overcurrent is detected only in ON condition, if the switching OFF
protection of the channel is enabled (default), sensing the current level of the output
power transistor. If the output current has been above the short threshold Iovc for the
filtering time Tdel the output power is switched off and at the same time an overcurrent
fault is written in the fault register.
There are three possibilities to restart one output after the fault has occurred:
–
Automatically after a time Tres
–
On the rising edge of CS if two valid DI bytes have been received and first the
Output Status in the command register is written with logic '0' and then with a logic
“1” in the following SPI cycle
–
On the rising edge (low to high transition) at the corresponding parallel input pin
(only for Outputs 6-8).
–
If the switching OFF protection is not active the On phase overcurrent protection is
a linear current limitation and no diagnosis is available.
The use of the IN6-8 pins for PWM control on the outputs 6-8 could generate bad diagnostic
behavior when the falling edge of CS happens a short time after the falling edge of IN6-8
during the power MOS transient. Software filtering may be needed to ignore fault signals
during Drn6-8 transient after falling edge of IN6-8.
7.1.2
Latch mode
This diagnostic operating mode latches all faults when they happen.
1. Open load
The diagnostic of open load is detected only in OFF condition sensing the Drn1-8
output voltage. This fault is detected if the power drain voltage is inside the voltage
range limited by the two thresholds Vth_Vbat and Vth_GND for the filtering time Tfilt.
An internal current limited voltage regulator fixes the drain voltage inside the described
range when no load is connected.
2. Short circuit to GND
The diagnostic of short circuit to GND is detected only in OFF condition sensing the
Drn1-8 output voltage. This fault is detected if the power drain voltage is lower than the
Vth_GND threshold for the filtering time Tfilt.
3. Overcurrent
The diagnostic of overcurrent is detected only in ON condition, if the switching OFF
protection of the channel is enabled (default), sensing the current level of the output
power transistor. If the output current has been above the short threshold Iovc for the
26/35
DocID11319 Rev 12
L9733
Fault operation
filtering time Tdel the output power is switched off and at the same time an overcurrent
fault is written in the fault register. If the switching OFF protection is not active the On
phase overcurrent protection is a linear current limitation and no diagnosis is available.
There are three possibilities to restart one output after the fault has occurred:
–
Automatically after a time Tres
–
On the rising edge of CS if two valid DI bytes have been received and first the
Output Status in the command register is written with logic '0' and then with a logic
“1” in the following SPI cycle
–
On the rising edge (low to high transition) at the corresponding parallel input pin
(only for Outputs 6-8).
If the power MOS transient, after a switching-off command, is longer than Tdel
filtering time, a bad diagnostic behavior happens and software filtering may be
needed.
7.2
High-side configured output fault operation
The diagnostic circuitry verifies for the high-side configured output the following condition:
Normal operation, open load, short circuit to Vbat and overcurrent (only if the switching OFF
protection, selectable for each channel via SPI bus, is active).
The diagnostic circuitry operates in two different modes, selected for each channel by SPI:
no latch mode and latch mode. The fault priority is overcurrent and then open load or short
circuit to Vb, this means that if an overcurrent occurs the fault register is always overwritten
and following open load or short to Vbat faults that happen before that the register is cleared
will be ignored.
7.2.1
No latch mode
This diagnostic operating mode doesn't latch open load and short to Vbat faults.
1. Open load
The diagnostic of open load is detected only in OFF condition sensing the Src1-8
output voltage. This fault is detected on the falling edge of the CS input if the power
drain voltage is inside the voltage range limited by the two thresholds Vth_Vbat and
Vth_GND. An internal current limited voltage regulator fixes the drain voltage inside the
described range when no load is connected.
2. Short Circuit to Vb
The diagnostic of short circuit to Vbat is detected only in OFF condition sensing the
Src1-8 output voltage. This fault is detected on the falling edge of the CS input if the
power drain voltage is higher than the Vth_Vbat threshold.
3. Overcurrent
The diagnostic of overcurrent is detected only in ON condition, if the switching OFF
protection of the channel is enabled (default), sensing the current level of the output
power transistor. If the output current has been above the short threshold Iovc for the
filtering time Tdel the output power is switched off and at the same time an overcurrent
fault is written in the fault register.
There are three possibilities to restart one output after the fault has occurred:
–
Automatically after a time Tres
–
On the rising edge of CS if two valid DI bytes have been received and first the
Output Status in the command register is written with logic '0' and then with a logic
“1” in the following SPI cycle
DocID11319 Rev 12
27/35
34
Fault operation
L9733
–
–
7.2.2
On the rising edge (low to high transition) at the corresponding parallel input pin
(only for Outputs 6-8).
If the switching OFF protection is not active the On phase overcurrent protection is
a linear current limitation and no diagnosis is available.
The use of the IN6-8 pins for PWM control on the outputs 6-8 could generates bad
diagnostic behavior when the falling edge of CS happens a short time after the
falling edge of IN6-8 during the power MOS transient. Software filtering may be
needed to ignore fault signals during Drn6-8 transient after falling edge of IN6-8.
Latch mode
This diagnostic operating mode latches all faults when they happen.
1. Open load
The diagnostic of open load is detected only in OFF condition sensing the Src1-8
output voltage. This fault is detected if the power drain voltage is inside the voltage
range limited by the two thresholds Vth_Vbat and Vth_GND for the filtering time Tfilt.
An internal current limited voltage regulator fixes the drain voltage inside the described
range when no load is connected.
2. Short Circuit to Vb
The diagnostic of short circuit to Vbat is detected only in OFF condition sensing the
Src1-8 output voltage. This fault is detected if the power drain voltage is higher than the
Vth_Vbat threshold for the filtering time Tfilt.
3. Overcurrent
The diagnostic of overcurrent is detected only in ON condition, if the switching OFF
protection of the channel is enabled (default), sensing the current level of the output
power transistor. If the output current has been above the short threshold Iovc for the
filtering time Tdel the output power is switched off and at the same time an overcurrent
fault is written in the fault register.
There are three possibilities to restart one output after the fault has occurred:
–
Automatically after a time Tres
–
On the rising edge of CS if two valid DI bytes have been received and first the
Output Status in the command register is written with logic '0' and then with a logic
“1” in the following SPI cycle
–
On the rising edge (low to high transition) at the corresponding parallel input pin
(only for Outputs 6-8).
If the switching OFF protection is not active the On phase overcurrent protection is
a linear current limitation and no diagnosis is available.
If the power MOS transient, after a switching-off command, is longer than Tdel filtering time,
a bad diagnostic behavior happens and software filtering may be needed.
28/35
DocID11319 Rev 12
L9733
Fault operation
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DocID11319 Rev 12
29/35
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Fault operation
L9733
Figure 9. Powertrain applicative examples
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30/35
DocID11319 Rev 12
L9733
8
Application circuit
Application circuit
Figure 10. Optimized circuit layout to achieve proper EMI/ESD capability
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DocID11319 Rev 12
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34
Package information
9
L9733
Package information
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK® packages, depending on their level of environmental compliance. ECOPACK®
specifications, grade definitions and product status are available at: www.st.com.
ECOPACK® is an ST trademark.
9.1
PowerSSO-28 (exposed pad) package information
Figure 11. PowerSSO-28 (exposed pad) package outline
*$3*36
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32/35
DocID11319 Rev 12
L9733
Package information
Table 13. PowerSSO-28 (exposed pad) package mechanical data
Dimensions
Ref
Inches(1)
Millimeters
Min.
Typ.
Max.
Min.
Typ.
Max.
A
2.15
-
2.45
0.0846
-
0.0965
A2
2.15
-
2.35
0.0846
-
0.0925
a1
-
-
0.1
-
-
0.0039
b
0.18
-
0.36
0.0071
-
0.0142
c
0.23
-
0.32
0.0091
-
0.0126
D (2)
10.1
-
10.50
0.3976
-
0.4134
7.4
-
7.6
0.2913
-
0.2992
e
-
0.65
-
-
0.0256
-
e3
-
8.45
-
-
0.3327
-
F
-
2.3
-
-
0.0906
-
G
-
-
0.1
-
-
0.0039
G1
-
-
0.06
-
-
0.0024
H
10.1
-
10.5
0.3976
-
0.4134
h
-
-
0.4
-
-
0.0157
E
(2)
k
5° (Typ.)
L
0.6
-
1
0.0236
-
0.0394
M
-
4.3
-
-
0.1693
-
N
10° (Max.)
O
-
1.2
-
-
0.0472
-
Q
-
0.8
-
-
0.0315
-
S
-
2.9
-
-
0.1142
-
T
-
3.65
-
-
0.1437
-
U
-
1
-
-
0.0394
-
X
4.2
-
4.8
0.1654
-
0.1890
Y
6.6
-
7.2
0.2598
-
0.2835
1. Values in inches are converted from mm and rounded to 4 decimal digits.
2. "D” and “E" do not include mold flash or protrusions Mold flash or protrusions shall not exceed 0.15 mm per
side (0.006”).
DocID11319 Rev 12
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34
Revision history
10
L9733
Revision history
Table 14. Document revision history
Date
Revision
13-Apr-2005
1
Initial release.
15-Jun-2006
2
Changed only look and feel.
08-Aug-2006
3
Modified Table 9: Bit command register definition on page 22.
28-May-2007
4
Changed the min. value of the CSlead parameter on the Table 8.
17-Jul-2007
5
Updated Table 6 and Table 7. Added new Figure 4.
Changed the status from Preliminary data to Datasheet.
03-Aug-2007
6
Updated in Table 4 the ESD parameter.
7
Added order codes in Table 1: Device summary on page 1.
Added “CS2SCLK” parameter in Table 8: SPI characteristics and
timings.
Updated Figure 6: SPI timing diagram.
02-Dec-2008
8
Updated Table 1: Device summary on page 1.
Removed all references to the SO-28 package.
Updated Section 2.1: Operating range and Section 2.2: Absolute
maximum ratings.
Added Section 2.1.1: Functional operative range, Section 2.1.2:
Jump start conditions, Section 2.1.3: Operation at low battery
condition and Section 2.1.4: Operation at load dump condition.
Added Section 8: Application circuit.
Added “PORth” parameter in Table 6: DC characteristics.
13-May-2009
9
Updated Table 1: Device summary on page 1.
Updated Figure 11: PowerSSO28 mechanical data and package
dimensions.
27-Jul-2010
10
Updated Table 1: Device summary on page 1.
Updated Section 7: Fault operation on page 25.
19-Sep-2013
11
Updated Disclaimer.
02-May-2016
12
qualified” in Features bullet.
12-Jun-2008
Changes
Modified in cover page the title and added “AEC-Q100 (Rev. F)
Updated Section 9: Package information.
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IMPORTANT NOTICE – PLEASE READ CAREFULLY
STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and
improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on
ST products before placing orders. ST products are sold pursuant to ST’s terms and conditions of sale in place at the time of order
acknowledgement.
Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or
the design of Purchasers’ products.
No license, express or implied, to any intellectual property right is granted by ST herein.
Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product.
ST and the ST logo are trademarks of ST. All other product or service names are the property of their respective owners.
Information in this document supersedes and replaces information previously supplied in any prior versions of this document.
© 2016 STMicroelectronics – All rights reserved
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