L9779WD

L9779WD Multifunction IC for engine management system Datasheet - production data  Protected low-side (low current) – OUT19, 20  IGBT pre-drivers (IGN1 to 4)  External MOS pre-drivers (OUT8 to 9)  Configurable power stages CPS – Stepper motor driver/ high-side - low-side (OUT21 to 28) *$3*36 HiQUAD-64  Thermal warning and shutdown  Serial interface – Micro Second Channel interface (MSC) – ISO9141 interface (K-Line) Features  High speed CAN transceiver  5 V logic regulator  5 V tracking sensor supply  Dedicated pin VDDIO to select the voltage level of digital output used for serial communication  Smart reset function  VDA 2.0 compliance with 3 level Watchdog  Power latch with Secure Engine Off (SEO) functionality, to safely complete driver switch off procedure  Package: HiQUAD-64  3.3 V logic regulator  Flying wheel interface function (VRS) with adaptive time and amplitude control  Protected low-side relay driver – OUT13 to 18, MRD  Protected low-side (injector drivers) – OUT1 to 4  Protected low-side (high current) – OUT5, 6, 7 Description The L9779WD is an integrated circuit designed for automotive environment and implemented in BCD6S technology. It is conceived to provide all basic functions for standard engine management control units. It is assembled in the HiQUAD-64 power package. Table 1. Device summary Order code Package Packing L9779WD HiQUAD-64 Tray L9779WD-TR HiQUAD-64 Tape and Reel September 2015 This is information on a product in full production. DocID027452 Rev 5 1/170 www.st.com Contents L9779WD Contents 1 Detailed features description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 3 Pins description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 4 Application schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 5 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 6 5.1 ESD protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 5.2 Latch-up test . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 5.3 Temperature ranges and thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 5.4 Operating range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 5.4.1 Low battery . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 5.4.2 Normal battery . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 5.4.3 High battery . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 5.4.4 Load dump . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 6.1 Ignition switch, main relay, battery pin . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 6.2 Power-up/down management unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 6.3 6.2.1 Power-up sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 6.2.2 Power-down sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 VDD_IO function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 6.3.1 6.4 Smart reset circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 6.4.1 Smart reset circuit functionality description . . . . . . . . . . . . . . . . . . . . . . 32 6.4.2 VDD5_UV detection modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 6.5 Thermal shut down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 6.6 Voltage regulators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 6.7 Charge pump . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 6.8 Main relay driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 6.8.1 2/170 Description of VDD_IO function and IC pin . . . . . . . . . . . . . . . . . . . . . . 31 Main relay driver functionality description . . . . . . . . . . . . . . . . . . . . . . . 49 DocID027452 Rev 5 L9779WD Contents 6.8.2 6.9 MRD scenarios . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 Low-side switch function (LSa, LSb, LSd) . . . . . . . . . . . . . . . . . . . . . . . . 55 6.9.1 LSa function OUT 1 to 5 (Injectors) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 6.9.2 LSb function OUT6, 7 (O2 heater) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 6.9.3 LSc function OUT19, 20 (low current drivers) . . . . . . . . . . . . . . . . . . . . 60 6.9.4 LSd function OUT13 to 18 (relay drivers) . . . . . . . . . . . . . . . . . . . . . . . 62 6.10 LSa, LSb, LSc, LSd diagnosis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 6.11 Ignition pre-drivers (IGN1 to 4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 6.12 6.11.1 Ignition pre-drivers functionality description . . . . . . . . . . . . . . . . . . . . . . 70 6.11.2 Ignition pre-driver diagnosis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 External MOSFET gate pre-drivers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 6.12.1 6.13 6.14 Configurable power stages (CPS) (OUT21 to 28) . . . . . . . . . . . . . . . . . . 76 6.13.1 Configurable power stages functionality description . . . . . . . . . . . . . . . 76 6.13.2 Diagnosis of configurable power stages (CPS) . . . . . . . . . . . . . . . . . . . 80 6.13.3 Diagnosis of CPS [OUT21 to OUT28] when configured as H-bridges . . 81 6.13.4 Diagnosis of CPS [OUT21 to OUT28] when configured as single power stages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 ISO serial line (K-LINE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 6.14.1 6.15 6.17 ISO serial line (K-LINE) functionality description . . . . . . . . . . . . . . . . . . 92 CAN transceiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 6.15.1 6.16 External MOSFET gate pre-drivers diagnosis . . . . . . . . . . . . . . . . . . . . 75 CAN transceiver functionality description . . . . . . . . . . . . . . . . . . . . . . . 95 Flying wheel interface function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 6.16.1 Flying wheel interface functionality description . . . . . . . . . . . . . . . . . . 100 6.16.2 Auto-adaptative sensor filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 6.16.3 Application circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 6.16.4 Diagnosis test . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 Monitoring module (watchdog) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .110 6.17.1 WDA - Watchdog (algorithmic) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 6.17.2 Monitoring module - WDA Functionality . . . . . . . . . . . . . . . . . . . . . . . 111 6.17.3 Watchdog related MSC commands . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 6.17.4 Watchdog related MSC registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 MSC_RESPTIME . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 WDA_RESPTIME . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 REQULO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 REQUHI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123 RST_AB1_CNT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 DocID027452 Rev 5 3/170 4 Contents L9779WD 6.17.5 6.18 MicroSecond Channel activity watchdog . . . . . . . . . . . . . . . . . . . . . . . 125 Serial interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127 6.18.1 MSC interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127 6.18.2 Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135 6.18.3 Registers (Upstream blocks) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142 STEP_CNT_H . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143 STEP_CNT_L . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144 IDENT_REG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144 CONFIG_REG1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145 CONFIG_REG2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146 CONFIG_REG3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147 CONFIG_REG4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148 CONFIG_REG5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149 CONFIG_REG6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150 CONFIG_REG7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152 CONFIG_REG10 (CPS Configuration register) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153 DIA_REG[1:5] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153 DIA_REG6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156 DIA_REG7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157 DIA_REG8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158 DIA_REG9 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159 DIA_REG10 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160 DIA_REG11 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161 DIA_REG12 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162 CONTR_REG1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163 CONTR_REG2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164 CONTR_REG3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165 CONTR_REG4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166 7 Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167 7.1 8 4/170 HiQUAD-64 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169 DocID027452 Rev 5 L9779WD List of tables List of tables Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 11. Table 12. Table 13. Table 14. Table 15. Table 16. Table 17. Table 18. Table 19. Table 20. Table 21. Table 22. Table 23. Table 24. Table 25. Table 26. Table 27. Table 28. Table 29. Table 30. Table 31. Table 32. Table 33. Table 34. Table 35. Table 36. Table 37. Table 38. Table 39. Table 40. Table 41. Table 42. Table 43. Table 44. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Pins description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 ESD protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Temperature ranges and thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Operating range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 KEY_ON pin electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 VDD_IO electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Internal reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 RST pin external components required . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 RST pin electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Temperature information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Voltage regulators external components required . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 VB Power supply electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 Linear 5 V regulator electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 Linear 3.3 V regulator electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 5V tracking sensor supply electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 Main relay driver electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 LSa electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 LSa diagnosis electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 LSa diagnosis electrical characteristics (OUT 5) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 LSb electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 LSb diagnosis electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 LSc electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 LSc diagnosis electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 LSd electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 LSd diagnosis electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 Fault encoding condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 Ignition pre-drivers electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 External MOSFET gate pre-drivers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 Configuration of the stepper motor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 H-bridge1 configurable power stages OUT [21 to 24] . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 H-bridge2 configurable power stages OUT [25 to 28] . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 Stepper configuration electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 Electrical and diagnosis characteristics of [OUT22], [OUT24], [OUT27], [OUT28] when configured as single power stages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 Electrical characteristics of [OUT22], [OUT24], [OUT27], [OUT28] when configured as single power stages connected in parallel (For information only) . . . . . . . . . . . . . . . . . 88 Electrical characteristics of [OUT21], [OUT23], [OUT25], [OUT26] when configured as single power stages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 Diagnosis characteristic of [OUT21], [OUT23], [OUT25], [OUT26] when configured as single power stages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 CPS table single mode parallelism . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 CPS table combined mode parallelism . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 ISO serial line (K-LINE) functionality electrical characteristics . . . . . . . . . . . . . . . . . . . . . . 92 CAN transceiver electrical characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 CAN transceiver timing characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 Pick voltage detector precision . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 DocID027452 Rev 5 5/170 6 List of tables Table 45. Table 46. Table 47. Table 48. Table 49. Table 50. Table 51. Table 52. Table 53. Table 54. Table 55. Table 56. Table 57. Table 58. Table 59. Table 60. Table 61. Table 62. Table 63. Table 64. Table 65. Table 66. Table 67. Table 68. Table 69. Table 70. Table 71. Table 72. Table 73. Table 74. Table 75. Table 76. 6/170 L9779WD Hysteresis threshold precision . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 MSC command possible configuration of different option of VRS function. . . . . . . . . . . . 104 VRs typical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 Diagnosis test electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 WDA_INT electrical characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 Error counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 State for = 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 Reset-behaviour of , AB1 and . . . . . . . . . . . . . . . . . . . . . . . . . 116 Expected responses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 Reset behaviour . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 RD_DATA8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 WR_RESP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 WR_RESPTIME . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 MicroSecond Channel activity watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 Content of a command frame (transmitted LSB first) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129 Content of a data frame (transmitted LSB first) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130 Timing characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132 Time electrical characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133 Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135 RD_DATA1, 2, 3, 4, 5, 6, 7 and 8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136 WR_CONFIG1, 2, 3, 4, 5, 6, 7, WR_RESP, WR_RESPTIME . . . . . . . . . . . . . . . . . . . . . 137 Lock, unlock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137 SW_RST . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138 Start, Stop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138 MRD_REACT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139 RD_SINGLE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139 Register through the command data field . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139 Association between the registers and the "4 bit address field. . . . . . . . . . . . . . . . . . . . . 140 Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142 CONFIG_REG6 power off source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151 HiQUAD-64 package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168 Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169 DocID027452 Rev 5 L9779WD List of figures List of figures Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Figure 10. Figure 11. Figure 12. Figure 13. Figure 14. Figure 15. Figure 16. Figure 17. Figure 18. Figure 19. Figure 20. Figure 21. Figure 22. Figure 23. Figure 24. Figure 25. Figure 26. Figure 27. Figure 28. Figure 29. Figure 30. Figure 31. Figure 32. Figure 33. Figure 34. Figure 35. Figure 36. Figure 37. Figure 38. Figure 39. Figure 40. Figure 41. Figure 42. Figure 43. Figure 44. Figure 45. Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Pins connection diagram (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Application schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Configuration supplied by VB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Power-up/down management unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Non-permanent supply power-up sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Permanent supply power-up sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Power-down sequence without power latch mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Power-down sequence without power latch mode and PSOFF = 1 . . . . . . . . . . . . . . . . . . 27 Power-down sequence with power latch mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Power-down sequence with power latch mode and KEY_ON toggle . . . . . . . . . . . . . . . . . 29 KEY_ON voltage vs. status diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Smart reset circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 RST pin as a function of VDD5 (if CONFIG_REG6 bit3 = Low) . . . . . . . . . . . . . . . . . . . . . 36 Structure regulators diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Graphic representation of the calculation method . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 Circuit and PCB layout suggested . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 VB overvoltage diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 VDD5 overvoltage diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 VDD5 vs battery: ramp-up diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 VDD5 vs battery (ramp-down diagram) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 Main relay driver controlled by L9779WD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 Scenario 1a: Standard on/off MRD driver with NO power latch mode bit PSOFF = 0 . . . . 50 Scenario 1b: Standard on/off MRD driver with NO power latch mode bit PSOFF = 1 . . . . 51 Scenario 2: Standard on/off MRD driver with power latch mode bit PSOFF = 0 . . . . . . . . 51 Scenario 3a: Deglitch concept on KEY_ON at start-up . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 Scenario 3b: Deglitch concept on KEY_ON during ON phase . . . . . . . . . . . . . . . . . . . . . . 52 Scenario 4: Non standard on, KEY_ON removed before VB present . . . . . . . . . . . . . . . . 52 Scenario 5: MRD overcurrent without VB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 Scenario 6: permanent MRD overcurrent with VBPOR restart . . . . . . . . . . . . . . . . . . . . . . 53 Scenario 7 (temporary MRD overcurrent with VB POR restart) . . . . . . . . . . . . . . . . . . . . . 53 Scenario 8 (temporary MRD overcurrent with VB µC commands restart) . . . . . . . . . . . . . 54 LSa function OUT 1 to 5 (Injectors) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 LSb function OUT6, 7 (O2 heater) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 LSc function OUT19, 20 (low current drivers). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 LSd function OUT13 to 18 (relay drivers) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 Behavior of OUT13, 14, 21, 25 with VB = VB_LV for a time shorter than Thold and with a valid ON condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 Behavior of OUT13, 14, 21, 25 with VB = VB_LV for a time longer than Thold and with a valid ON condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 Behavior of OUT13, 14, 21, 25 with VB that drops lower than POR threshold during cranking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 LSx diagnosis circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 Fault encoding condition diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 LSx ON/OFF slew rate control diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 Ignition-pre drivers (IGN1 to 4) circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 Ignition-pre drivers (IGN1 to 4) diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 External MOSFET gate pre-drivers circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 DocID027452 Rev 5 7/170 8 List of figures Figure 46. Figure 47. Figure 48. Figure 49. Figure 50. Figure 51. Figure 52. Figure 53. Figure 54. Figure 55. Figure 56. Figure 57. Figure 58. Figure 59. Figure 60. Figure 61. Figure 62. Figure 63. Figure 64. Figure 65. Figure 66. Figure 67. Figure 68. Figure 69. Figure 70. Figure 71. Figure 72. Figure 73. Figure 74. Figure 75. Figure 76. Figure 77. Figure 78. Figure 79. Figure 80. Figure 81. Figure 82. Figure 83. Figure 84. 8/170 L9779WD Stepper motor operation diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 Configurable power stages OUT [21 to 24] can be configured to create the H-bridge1 . . . 79 Configurable power stages OUT [25 to 28] can be configured to create the H-bridge2 . . . 79 Stepper counter diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 Stepper motor driver “off” diagnosis time diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 Stepper motor driver diagnosis I-V relationship diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 82 Open load detection during “on” phase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 Open load detection during “on” phase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 Short to GND detection during “on” phase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 Short to VB & open load diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 ISO serial line (K-LINE) circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 ISO serial line switching waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 ISO serial line: short circuit protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 CAN transceiver diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 CAN transceiver switching waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 CAN transceiver test circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 Flying wheel interface circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 Auto adaptative hysteresis diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 VRS interface block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 Auto-adaptive time filter (rising edge) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 Adaptive filter function when the MSC bit are 00 or 01. . . . . . . . . . . . . . . . . . . . . . . . . . . 104 Adaptive Filter Function when the MSC bit is 10 or 11 . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 Variable reluctance sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 VRs typical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 Hall effect sensor configuration 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 Hall effect sensor configuration 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 Diagnosis test diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 WDA block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 Monitoring cycle diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 4-bit Markov chain diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 MicroSecond Channel activity watch dog diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126 Communication diagram between µC and L9779WD. . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 Command frame diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129 Data frame diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130 Upstream communication diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131 Timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131 Time circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132 Cycle time diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133 HiQUAD-64 package outline. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167 DocID027452 Rev 5 L9779WD 1 Detailed features description Detailed features description  Package –     5 V logic regulator – 5 V precision voltage regulator (± 2%) with external NMOS – Max current regulated: 400 mA – Charge pump capacitor at pin CP is used to drive the gate of the external NMOS transistor 3.3 V logic regulator – 3.3 V precision voltage regulator (± 2%) with over-current protection – Max current regulated: 100 mA 5 V tracking sensor supply – 2 x 5 V tracking sensor supply with protection and diagnosis on MSC – Short-circuit to Vbat/GND fully protected – Max current regulated: 2 x 100 mA VDD_IO supply –     Main Reset monitoring VB_UV Logic voltage management and safety control Watch dog – Main reset management 5 V voltage monitoring safety output disable – MicroSecond Channel activity watch dog – MSC controllable query and answer watch dog compliant with VDA2.0 level 3 (enabled by default) Power latch –  All the digital output is supplied by external VDD_IO through VDD_IO pin Smart reset –  HiQUAD-64 L9779WD is switched on by KEY_ON signal and switched off by logic OR of KEY_ON signal and MicroSecond Channel bit Secure engine off mode (default) switches off the drivers in the following order: – OUT1 through to OUT4 in 225 ms (typical) – OUT13 and OUT14 in 600 ms (typical) Flying wheel interface function (VRS) – The VRS is the interface between the microprocessor and the magnetic pick-up or variable reluctance sensor that collects the information coming from the flying wheel – Adaptive filtering on amplitude and timing adapts better the device response to VRS input switching Protected low-side driver – LSa (OUT1 to 5) 4 Ch. serial IN via MicroSecond Channel, Rdson = 0.72 Ohm @150 °C, Vcl = 58 V ±5, Imax = 2.2 A; 1 Ch. serial IN via MicroSecond Channel, Rdson = 0.72 Ohm @150 °C, Vcl = 58 V ±5, Imax = 3 A; DocID027452 Rev 5 9/170 169 Detailed features description – L9779WD LSb (OUT6, 7) 2 Ch. serial IN via MicroSecond Channel, Rdson = 0.47 Ohm @150°C, Vcl = 45 V ±5, Imax = 5 A – LSc (OUT19, 20) 2 Ch serial IN via MicroSecond Channel, Imax = 50 mA Full diagnosis on MicroSecond Channel (2 bit for each channel) and voltage slew rate control. When an over current fault occurs, the driver switch off with faster slew rate in order to reduce the power dissipation.  Protected low side relay driver (OUT13 to 18, MRD) – LSD 6 Ch. serial IN via MicroSecond Channel, Rdson = 1.5 Ohm @150 °C, Vcl = 48 V, Imax = 600 mA (2 of them with low battery voltage function); 1 main relay driver Rdson = 2.4 Ohm @150 °C, Vcl = 48 V, Imax = 600 mA With full diagnosis on MicroSecond Channel (2 bit for each channel) and voltage slewrate control. When an over current fault occurs, the driver switch off with faster slew rate in order to reduce the power dissipation.  Ignition pre-drivers (IGN1 to 4) –  4 x ignition pre-drivers with full diagnostic. External MOS pre-drivers (OUT8 to 9) – 2 x MOS pre-drivers with sense of the external drain voltage to perform the diagnostic: Open load in OFF state Shorted load in ON state with programmable threshold voltage and programmable filter time via MSC  Configurable power stages CPS: stepper motor driver/ high-side - low-side (OUT21 to 28) 1 x Stepper motor driver designed for a double winding coil motor, used for engine idle speed control. The bridge driver is made by 4 independent high-side drivers and 4 independent lowside drivers: – 4 high-side driver, Rdson =1.5 Ohm, Imax = 600 mA – 4 low-side driver, Rdson = 1.5 Ohm, Imax = 600mA The 4 high-side drivers and the 4 low-side drivers can be controlled independently The low-side drivers could be connected in parallel (in pairs): OUT22 with OUT24 and OUT27 with OUT28. Low-side and high-side drivers implement voltage SR control to minimize emission. Two high-side drivers have the low battery voltage function.  10/170 Thermal shutdown – 1 x Thermal shutdown (Tj > 175 °C = Tsd) if Tj > Tsd: VTRK1, 2 are turned off. – 1 x Thermal shutdown (Tj > 175 °C = Tsd) if Tj > Tsd: OUT1 to 10, OUT13 to 20, OUT21 to 28, IGN1 to 4 are turned off. – 1 x Thermal shutdown (Tj > 175 °C = Tsd) if Tj > Tsd: MRD is turned off (if battery present). DocID027452 Rev 5 L9779WD Detailed features description – 1 x Thermal Shutdown (Tj > 175 °C = Tsd) if Tj > Tsd: V3V3 is turned off. There are 5 temperature sensors for OT2 (OUT1..10, OUT13…20, OUT21…28, IGN1…4 are turned off) in different Layout position, they are logically “AND” in case of thermal shutdown.  ISO9141 interface –  ISO9141 serial interface (K-Line) CAN transceiver The CAN bus transceiver allows the connection of the microcontroller, with CAN controller unit, to a high speed CAN bus with transmission rates up to 1Mbit/s for exchange of data with other ECUs. DocID027452 Rev 5 11/170 169 Block diagram 2 L9779WD Block diagram Figure 1. Block diagram /:' 9% %DQGJDS 9UHJXODWRUOLQHDU 9EJ 9% FRQWUROOHU FSBRXW 9 9 9LQWHUQDOVXSSO\ P$ 9'' 9EJ 9'' 9% 9'' .H\RQGHWHFWLRQDQG ILOWHULQJ .( TD_Start_V3V VDD_UV_high and 3 V3V3 switch on DocID027452 Rev 5 47/170 169 Functional description L9779WD Table 17. 5V tracking sensor supply electrical characteristics Pin Symbol Parameter Test condition Typ Max Unit VDD5 -20 - VDD5 +20 mV 160 - 400 mA Output voltage tracking error VB = 6-18 V 1 mA < IVTRK < 100 mA Output current limitation VTRK1,2 VTRK = -1V VLINE_trk Line regulation voltage VTRK VB = 6-18 V 1 mA < IVTRK < 100 mA Ctrk = 1 µF - - 20 mV Vload_ trk Load regulation voltage VTRK VB = 6-18 V 1 mA < IVTRK < 100 mA Ctrk = 1 µF - - 20 mV Isink_VTRK Short circuit reverse current Output shorted to Vbat +2 V - - 4 mA Over current threshold VTRK VB = 6-18 V 101 - 5.3 - - V 40 - - dB VB = 4.8 V; IVTRK1,2 = 100 mA - - 3600 mΩ Cload  470 nF tested with 1 µF - - 5.5 V Cload < 470 nF tested with 100 nF - - 6 V 48 64 80 µs VTRK IVTRK_MAX VTRK_1 VTRK_2 ITH_UVTRK VTH_OVTRK V threshold over voltage VTRK Ramp on tracking output Cout = 4.7 µF; VDD5 = 5 V 4 Vpp, VB mean 9 V, f = 20 kHz Supply voltage tracking SVR_VTRK rejection Rdson Vos Vov_filter 48/170 Min - Over shoot during power up Over voltage filter time Test by scan DocID027452 Rev 5 IVTRK_MAX mA L9779WD 6.8 Functional description Main relay driver Figure 22. Main relay driver controlled by L9779WD 6BAT ,OAD RELAY 07,?%. +%9 6" $RIVER  PROTECTION -2$ '!0'03 6.8.1 Main relay driver functionality description Main relay driver MRD is controlled by L9779WD depending on the voltage levels at pins KEY_ON, VB and the power latch mode set by the µC as described in the previous sections. The output stage MRD for main-relay-control is realized with a low-side-switch with integrated clamping at VCL voltage realized with a zener diode. When VB is present (VB>VB_LV) the MRD driver is protected, in ON condition, against the over temperature fault. When the temperature is above junction the MRD is switched off. After HYSTERESIS the MRD returns to normal operation automatically. In case of MRD short to battery without VB present i.e. during start-up sequence, when the current exceeds the IOVC value, this pin will be switched off after a certain filter time TFILTEROVC; to turn on MRD again it is necessary a high to low transition on KEY_ON pin. Refer to scenario 5 (Figure 29). In case of MRD short to battery with VB present i.e. during normal mode, when the current exceeds the IOVC value, this pin will be switched off after a certain filter time TFILTEROVC; the uC can try to turn on the MRD using the command MRD_REACT until the VB voltage is above VB_UV. Below this threshold the MRD retries to switch on, then if the fault is still present the MRD switches off and to turn it on again it is necessary a high to low transition on KEY_ON pin. Refer to scenario 6-7-8 (Figure 30, 31 and 32). In every condition the bit MRD_OVC reports that the MRD is currently off due to a previous over current event. Diagnosis of MRD short to ground may be done as described in the power up/down management unit, switching off the MRD keeping alive all other regulators. DocID027452 Rev 5 49/170 169 Functional description L9779WD Table 18. Main relay driver electrical characteristics Pin Symbol Min Typ Max Unit Iload = 0.4 A; Vbat = 0 & 13.5 V - - 2.4 Ω Output leakage current Vpin = 13.5 V; Vbat = 0 & 13.5 V - - 10 µA Voltage S/R on/off R = 21 , C = 10 nF; Vbat = 0 & 13.5 V 1 - 10 V/µs Output clamping voltage Vbat = 0 & 13.5 V 42 - 55 V Imax Output current Design info - 0.6 A IOVC Over current threshold Vbat = 0 & 13.5 V 0.7 - 1.4 A Over current filtering time Test by SCAN 5.25 7 8.75 us VB threshold for MRD active Vbat = 0 & 13.5 V - - 4.15 V PWclampSP Clamp single pulse ATE test Iload = 0.5 A; single pulse - - 15 mJ PWclampRP Clamp repetitive pulses reliability test Iload = 0.25 A Freq =1 Hz; 1 Mpulse - - 4 mJ IOUTlk MRD VS/R Vcl TFILTEROVC VB_UV 6.8.2 Test condition Drain –source resistance RDS-on MRD Parameter MRD scenarios Figure 23. Scenario 1a: Standard on/off MRD driver with NO power latch mode bit PSOFF = 0 +%9?/. T+%9 T+%9  -2$ 6" 0/2( 6"6"?56?( 0/2 6$$ 234 T '!0'03 50/170 DocID027452 Rev 5 L9779WD Functional description Figure 24. Scenario 1b: Standard on/off MRD driver with NO power latch mode bit PSOFF = 1 +%9?/. T+%9 T+%9 -2$ 6"?56?, 6" 0/2( 6"6"?56?( 0/2 6$$?56?, 6$$ 234 T '!0'03 Figure 25. Scenario 2: Standard on/off MRD driver with power latch mode bit PSOFF = 0 T+%9 T+%9 3WITCHEDOFFBY U#BIT07,?%. -2$ 6" 0/2 6$$ 234 T '!0'03 Figure 26. Scenario 3a: Deglitch concept on KEY_ON at start-up +%9?/. T+%9 -2$ 6" 0/2 T 6$$ '!0'03 DocID027452 Rev 5 51/170 169 Functional description L9779WD Figure 27. Scenario 3b: Deglitch concept on KEY_ON during ON phase +%9?/. T+%9 T+%9 -2$ 6" 0/2 6$$ T '!0'03 Figure 28. Scenario 4: Non standard on, KEY_ON removed before VB present +%9?/. T+%9 T+%9 -2$ 6" 0/2 6$$ T '!0'03 Figure 29. Scenario 5: MRD overcurrent without VB +%9?/. T+%9 4&),4%26# T+%9 -2$ 4HISSIGNALKEEPS THE-2$OFFUNTIL +%9?/.LOW )NTERNAL /VER#URR?-2$ LATCH 3HORTTO6"ON -2$ &!5,4 02%3%.4 6" 0/2 6$$ T '!0'03 52/170 DocID027452 Rev 5 L9779WD Functional description Figure 30. Scenario 6: permanent MRD overcurrent with VBPOR restart +%9?/. T+%9 .ORESETFOR-2$?/6# AFTERREADING -2$ T+%9 )NTERNAL /VER#URR?-2$ LATCH 4&,)4%26# -2$?/6# &!5,4 02%3%.4 3HORTTO6"ON -2$ 6" 0/2 6$$ T '!0'03 Figure 31. Scenario 7 (temporary MRD overcurrent with VB POR restart) +%9?/. T+%9 -2$ 4&),4%26# -2$?/6# 3HORTTO6"ON -2$ &!5,4 02%3%.4 6" 0/2 6$$ T '!0'03 DocID027452 Rev 5 53/170 169 Functional description L9779WD Figure 32. Scenario 8 (temporary MRD overcurrent with VB µC commands restart) —#READSTHE -2$?/6#FLAG +%9?/. —#SWITCHONTHE -2$BY -2$?2%!#4BIT T+%9 -2$ T+%9 -2$?/6# 3HORTTO6"ON -2$ &!5,4 02%3%.4 6" 0/2 6$$ T '!0'03 54/170 DocID027452 Rev 5 L9779WD Functional description 6.9 Low-side switch function (LSa, LSb, LSd) 6.9.1 LSa function OUT 1 to 5 (Injectors) Figure 33. LSa function OUT 1 to 5 (Injectors) 6BAT -3#?$IAG?REG 0ROTECTION $IAGNOSIS 2ESET? , -3#?#MD?,3A ,OAD ).* /UT?,3A $RIVER /%INT '!0'03 LSa functionality description LSa are 5 protected low-side drivers with diagnosis and over current protection circuit. They are driven via MicroSecond Channel interface. The maximum current for OUT1 to 4 is 2.2 A while for OUT5 is 3 A. When Reset_L9779 signal or OUT_DIS bit is asserted OUT_LSa is switched off. When an over current fault occurs, the driver switches off with faster slew rate in order to reduce the power dissipation. The turn on/off time is fixed and the slew-rate is controlled. Max Cload = 20 nF. Table 19. LSa electrical characteristics Pin Symbol Test condition Min Typ Max Unit RDS-on LSa Drain source resistance Iload = 1.25 A - - 0.72 Ω IOUTlk Output leakage current Vpin = 13.5 V - - 10 µA Voltage S/R on/off Load: 8 Ω, 10 nF From 80% to 30% of VOUT 2 - 6 V/µs FAST VR/S off when an OVC fault happens Load: 8 Ω, 10 nF From 80% to 30% of VOUT 5 - 20 V/µs TTurn-on_ LSa Turn-on delay time From command to 80% VOUT, Load: 8 Ω, 10 nF - - 6 µs TTurn-off_ LSa Turn-off delay time From command to 30% VOUT, Load: 8 Ω, 10 nF - - 6 µs Output clamping voltage Iload = 1.25 A 53 58 63 V - - 25 mJ VS/R OUT 1 to 5 Parameter VS/R GateKill Vcl PWclampSP Clamp single pulse ATE test Iload = 1.25 A single pulse DocID027452 Rev 5 55/170 169 Functional description L9779WD Table 19. LSa electrical characteristics (continued) Pin Symbol PWclampRP OUT 1 to 4 Reverse voltage PWclampSP OUT5 56/170 PWclampRP Parameter Test condition Min Typ Max Tc ≤ 30°C; I_OUT_n ≤ 1.8 A 13 Mio cycles - - 7.5 Tc ≤ 65°C; I_OUT_n ≤ 1.4 A 130 Mio cycles - - 4 Tc ≤ 80°C; I_OUT_n ≤ 1.4 A 214 Mio cycles - - 4 Clamp repetitive pulses Tc ≤ 100°C; I_OUT_n ≤ 1.4 A Freq = 50 Hz (to be verified) 175 Mio cycle - - 4 Tc ≤ 115°C; I_OUT_n ≤ 1.4 A 45 Mio cycle - - 4 Tc ≤ 130°C; I_OUT_n ≤ 1.0 A 65 Mio cycle - - 3 Tc ≤ 145°C; I_OUT_n ≤ 1.0 A 6 Mio cycle - - 3 -0.5 - -1.2 Iload = 1.25 A single pulse - - 25 Tc < 30°C; I_OUT5 < 0.7 A 21 Mio cycles - - 17 Tc < 65°C; I_OUT5 < 0.7 A 70 Mio cycles - - 14 Tc < 80°C; I_OUT5 < 0.7 A 115.5 Mio cycles - - 14 Tc < 90°C; I_OUT5 < 0.7 A 63 Mio cycles - - 14 Tc < 100°C; I_OUT5 < 0.7 A 31.5 Mio cycles - - 14 Tc < 105°C; I_OUT5 < 0.7 A 10.5 Mio cycles - - 14 Tc < 110°C; I_OUT5 < 0.7 A 7 Mio cycles - - 14 Tc < 115°C; I_OUT5 < 0.7 A 5.95 Mio cycles - - 14 Tc < 120°C; I_OUT5 < 0.7 A 5.25 Mio cycles - - 12 Tc < 125°C; I_OUT5 < 0.7 A 4.9 Mio cycles - - 12 Tc < 130°C; I_OUT5 < 0.7 A 4.55 Mio cycles - - 12 Body diode reverse current voltage drop (valid for OUT5 I = -2.2 A also) Clamp single pulse Clamp repetitive pulses Freq = 30 Hz DocID027452 Rev 5 Unit mJ V mJ L9779WD Functional description Table 19. LSa electrical characteristics (continued) Pin OUT5 Symbol PWclampRP Parameter Clamp repetitive pulses Freq = 30 Hz Test condition Min Typ Max Tc < 135°C; I_OUT5 < 0.7 A 4.55 Mio cycles - - 12 Tc < 140°C; I_OUT5 < 0.7 A 3.5 Mio cycles - - 12 Tc < 145°C; I_OUT5 < 0.7 A 3.5 Mio cycles - - 12 Unit mJ Table 20. LSa diagnosis electrical characteristics Pin Symbol Ropen load Min resistor value open Not tested load detection Min Typ Max Unit 500 - - k Output current Not tested - 2.2 - A IOVC Over current threshold - 3 - 6 A Over current filtering time Tested by scan 2 3 4 µs Filtering open load and Tested by scan short to gnd diag. off 35 50 65 µs Td_mask Diagnosis Mask time after switch-off Tested by scan 300 - 500 µs VHVT Open load threshold voltage - VOutopen +120mV - 3 V Open load output voltage Open load condition 2.3 - 2.7 V VLVT Output short-circuit to GND voltage range threshold - 1.9 - VOutopen -200mV V IOUT_PD Output diagnostic pull down current Off state Vpin = 5 V 50 - 110 µA IOUT_PU Output diagnostic pull up current Off state Vpin = 1.5 V 110 160 210 µA Open load threshold current - 30 - 90 µA TFILTERdiaggoff VOutopen OUT 1 to 5 Test condition Imax TFILTEROVC OUT 1 to 5 Parameter Itopen For OUT 5 only the following parameters are different with respect to OUT1 to 4. Table 21. LSa diagnosis electrical characteristics (OUT 5) Pin OUT 5 Symbol Parameter Test condition Imax Output current Not tested IOVC Over current threshold - DocID027452 Rev 5 Min Typ Max Unit - 3 - A 3.7 - 6.9 A 57/170 169 Functional description 6.9.2 L9779WD LSb function OUT6, 7 (O2 heater) Figure 34. LSb function OUT6, 7 (O2 heater) 6BAT -3#?$IAG?REG  0ROTECTION $IAGNOSIS ,OAD 2ESET? , -3#?#MD?,3B %.?,OW2ES /UT?,3B $RIVER '!0'03 LSb functionality description LSb are 2 protected low-side drivers with diagnosis and over current protection circuit. They are driven via MicroSecond Channel interface. The turn on/off time is fixed and the slew-rate is controlled. When an over current fault occurs, the driver switches off with faster slew rate in order to reduce the power dissipation. The turn on/off time is fixed and the slew-rate is controlled. Max Cload = 20 nF. Table 22. LSb electrical characteristics Pin Symbol Parameter Test condition T = -40°C, Iload = 3 A RDS-on LSb Drain source resistance T = 25°C, Iload = 3 A T = 130°C, Iload = 3 A OUT 6, 7 IOUTlk Output leakage current - VS/R Voltage S/R on/off R = 4.5 Ω, C = 10 nF From 80% to 30% of VOUT VS/R GateKill Typ Max Unit 0.05 - 0.16 Ω 0.13 - 0.23 Ω 0.21 - 0.47 Ω - - 10 µA 0.5 - 2.5 V/µs 5 - 20 V/µs TTurn-on_ LSb Turn-on delay time From command to 80% VOUT Load: 4.5 Ω, 10 nF - - 7.5 µs TTurn-off_ LSb Turn-off delay time From command to 20% VOUT Load: 4.5 Ω, 10 nF - - 7.5 µs 41 45 49 V - - 25 mJ Vcl PWclampSP 58/170 FAST VR/S off when an Load: 8 Ω, 10 nF OVC fault happens From 80% to 30% of VOUT Min Output clamping voltage Iload = 1.5 A Clamp single pulse ATE Iload = 1.5 A; single pulse test DocID027452 Rev 5 L9779WD Functional description Table 22. LSb electrical characteristics (continued) Pin Symbol Parameter Clamp repetitive pulses Freq = 5 Hz Reliability Test PWclampRP OUT 6, 7 Reverse voltage Body diode reverse current voltage drop Test condition Min Typ Max Tc ≤ 30 °C; I_OUT_n ≤ 1.8 A 13 Mio cycles - - 7.5 Tc ≤ 65°C; I_OUT_n ≤ 1.4 A 130 Mio cycles - - 4 Tc ≤ 80°C; I_OUT_n ≤ 1.4 A 214 Mio cycles - - 4 Tc ≤ 100°C; I_OUT_n ≤ 1.4 A 175 Mio cycle - - 4 Tc≤ 115°C; I_OUT_n ≤ 1.4 A 45 Mio cycle - - 4 Tc ≤ 130°C; I_OUT_n ≤ 1.0 A 65 Mio cycle - - 3 Tc ≤ 145°C; I_OUT_n ≤ 1.0 A 6 Mio cycle - - 3 -1.3 -1 -0.5 I = -5 A Unit mJ V Table 23. LSb diagnosis electrical characteristics Pin Symbol Imax IOVC TFILTEROVC Parameter Test condition Output current Over current threshold Over current filtering time Min Typ Max Unit Not tested - 5 - A T = -40°C 8.6 - 12.4 A T = 25°C 8 - 11.2 A T = 130°C 7.8 - 9.9 A Tested by scan 1.5 - 2.5 µs 7 - 13 µs 300 - 500 µs VOutopen +120mV - 3 V TFILTERdiaggof Filtering open load and short Tested by scan to GND diag. off f Td_mask Diagnosis mask delay after switch-off Tested by scan OUT6, 7 VHVT Open load threshold voltage Open load output voltage Open load condition 2.3 - 2.7 V VLVT Output short-circuit to GND threshold voltage - 1.9 - VOutopen -200mV V IOUT_PD Output diagnostic pull down current OFF STATE Vpin = 5 V 50 - 110 µA IOUT_PU Output diagnostic pull up current OFF STATE Vpin = 1.5 V -210 - -108 µA Open load threshold current - 30 - 90 µA VOutopen Itopen DocID027452 Rev 5 59/170 169 Functional description 6.9.3 L9779WD LSc function OUT19, 20 (low current drivers) Figure 35. LSc function OUT19, 20 (low current drivers) 6BAT -3#?$IAG?REG  0ROTECTION $IAGNOSIS ,OAD 2ESET? , -3#?#MD?,3C %.?,OW2ES /UT?,3C $RIVER '!0'03 LSc functionality description LSc are 2 protected Low-Side drivers with diagnosis and over current protection circuit. The off state diagnosis (open load and short to GND) detection can be switched off by OFF_LCDR bit. They are driven via MicroSecond Channel. When Reset_L9779 signal or OUT_DIS bit is asserted OUT_LSc is switched off. When an over current fault occurs, the driver switches off with faster slew rate in order to reduce the power dissipation. The turn on/off time is fixed. During turn-off the slope is fixed by external RC load. Max Cload = 20 nF. Table 24. LSc electrical characteristics Pin OUT 19, 20 Symbol Test condition Min Typ Max Unit RDS-on LSc Drain source resistance Iload = 50 mA - - 20 Ω IOUTlk Output leakage current Vpin = 13.5 V @hot - - 10 µA TTurn-on_ LSb Turn-on delay time From command to 80% VOUT; Load: 250 Ω, 10 nF - - 5 µs TTurn-off_ LSb Turn-off delay time From command to 30% VOUT; Load: 250 Ω, 10 nF - - 5 µs Vcl Output clamping voltage Iload = 50 mA 40 45 50 V PWclampSP Clamp single pulse ATE test - - - 3.5 mJ PWclampRP Clamp repetitive pulses Reliability Test Tc ≤ 145 °C; I_OUT_n < 0.03 A 0.5 Mio cycles - - 0.2 mJ Body diode reverse current voltage drop I = -50 mA -0.5 -1 -1.1 V Reverse current 60/170 Parameter DocID027452 Rev 5 L9779WD Functional description Table 25. LSc diagnosis electrical characteristics Pin Symbol IOVC TFILTEROVC TFILTERdiagoff Td_mask Test condition Min Typ Max Unit Over current threshold - 70 - 130 mA Over current filtering time Tested by scan 2 4 5 µs Filtering open load and short to GND diag. off Tested by scan 35 50 65 µs Diagnosis mask delay after Tested by scan switch-off 300 - 500 µs Open load threshold voltage - VOutopen +160mV - 3 V Output open load voltage - 2.3 - 2.7 V Output short-circuit to GND threshold voltage 1.9 - VOutopen -200mV V IOUT_PD Output diagnostic pull down Vpin = 5 V current Off state 50 - 110 µA IOUT_PU Output diagnostic pull up current Off state 110 160 210 µA Open load threshold current - 30 - 110 µA VS/R ON Voltage R On 2 - 6 V/µs VS/R OFF Voltage R Off 5 - 14 V/µs VHVT VOutopen OUT19,20 Parameter VLVT Itopen Vpin = 1.5 V R = 270 Ω Cload = 10 F From 80% to 30% of VOUT DocID027452 Rev 5 61/170 169 Functional description 6.9.4 L9779WD LSd function OUT13 to 18 (relay drivers) Figure 36. LSd function OUT13 to 18 (relay drivers) 6BAT -3#?$IA ?REG 0ROTECTION $IAGNOSIS 2ESET? , -3#?#MD?,3D %.?,OW2ES ,OAD 2ELAY /UT?,3D $RIVER '!0'03 LSd functionality description LSd are 6 protected Low-Side drivers with diagnosis, and over current protection circuit. They are driven via MicroSecond Channel interface. When Reset_L9779 signal or OUT_DIS bit is asserted OUT_LSd is switched off. The turn on/off time is fixed and the slew-rate is controlled. OUT13 and OUT14 are able to remain active also during crank pulse when the battery voltage on the VB pin goes below the level VB_LV for a period of time THOLD, this time lapse calculation is triggered by the falling edge of RST. In this situation VDD5 is below undervoltage threshold (VDD_UV) and the micro controller is in reset condition. During the THOLD time the VDD5 supply and the micro controller have to recover and take over control of the output. Otherwise the output is switched OFF after the THOLD time. The low battery functionality can be enabled/disabled through bit OUT13_EN_LB and OUT14_EN_LB of CONF_REG7. Table 26. LSd electrical characteristics Pin Symbol Test condition Min Typ Max Unit RDS-on LSd Drain source resistance Iload = 0.6 A - - 1.5 Ω IOUTlk Output leakage current Vpin = 13.5 V - - 10 µA Voltage S/R on/off R = 21 Ω, C = 10 nF From 80% to 30% of VOUT 2 - 6 V/µs FAST VR/S off when an OVC fault happens Load: 8 Ω, 10 nF; From 80% to 30% VOUT; 5 - 30 V/µs TTurn-on_ LSd Turn-on delay time From command to 80% VOUT Load: 21 Ω, 10nF - - 6 µs TTurn-off_ LSd Turn-off delay time From command to 30% VOUT Load: 21 Ω, 10 nF - - 6 µs 40 45 50 V VS/R VS/R GateKill OUT 13 to 18 Vcl 62/170 Parameter Output clamping voltage Iload = 0.6 A DocID027452 Rev 5 L9779WD Functional description Table 26. LSd electrical characteristics (continued) Pin Symbol Parameter Clamp single pulse ATE test PWclampSP OUT 13 to 18 Test condition Min Typ Max Unit Iload = 0.6 A; single pulse - - 15 mJ Tc ≤ 30 °C; I_OUT_n < 0.45 A 1 Mio cycles - - 6.5 Tc ≤ 80 °C; I_OUT_n  0.3 A 25 Mio cycle - - 6.5 Clamp repetitive pulses Freq = 1 Hz (to be verified) Tc ≤ 100°C; Reliability Test I_OUT_n < 0.3A 20 Mio cycle PWclampRP mJ Tc ≤ 130°C; I_OUT_n < 0.3 A 5 Mio cycle Reverse current Body diode reverse current I = -0.6 A voltage drop - - 6.5 - - 5.5 -0.5 -1 -1.1 V Min/Max of Reverse Current will be add after BA characterization. Table 27. LSd diagnosis electrical characteristics Pin Symbol Ropen load Test condition Min resistor value open Not tested load detection Min Typ Max Unit 500 - - kΩ Imax Output current Not tested - 0.6 - A IOVC Over current threshold - 1 - 2 A Over current filtering time Tested by scan 2 4 5 µs TFILTERdiagoff Filtering open load and short to GND diag. off Tested by scan 35 50 65 µs Td_mask Diagnosis mask delay after switch-off Tested by scan 300 - 500 µs VHVT Output voltage ok range threshold - VOutopen +120mV - 3 µs VOUTOPEN Output open load voltage Open load condition 2.3 - 2.7 V VLVT Output short-circuit to GND threshold voltage - 1.9 - VOutopen -200mV V IOUT_PD Output diagnostic pull down current off state Vpin = 5 V 50 - 110 µA IOUT_PU Output diagnostic pull up current off state Vpin = 1.5 V -210 - -108 µA TFILTEROVC OUT 13 to 18 Parameter DocID027452 Rev 5 63/170 169 Functional description L9779WD Table 27. LSd diagnosis electrical characteristics (continued) Pin Symbol OUT 13 to 18 Itopen Open load threshold current THOLD VB_UV OUT13, 14 Parameter Test condition Min Typ Max Unit - 30 - 90 µA Switch on to off delay during low battery voltage operation Tested by scan 400 - 800 ms VB voltage threshold for low battery function - - - 4.15 V Figure 37. Behavior of OUT13, 14, 21, 25 with VB = VB_LV for a time shorter than Thold and with a valid ON condition +%9?/. 6" 6"?,6 /54 ,3 /54 (3 /. /. /. /. /. /. 4?(/,$ 0/2 6$$ 6$$?56 234 '!0'03 64/170 DocID027452 Rev 5 L9779WD Functional description Figure 38. Behavior of OUT13, 14, 21, 25 with VB = VB_LV for a time longer than Thold and with a valid ON condition +%9?/. 6" 6"?,6 /54 ,3 /54 (3 /. /. /&& /. /. /&& 4?(/,$ 0/2 6$$ 6$$?56 234 '!0'03 DocID027452 Rev 5 65/170 169 Functional description L9779WD Figure 39. Behavior of OUT13, 14, 21, 25 with VB that drops lower than POR threshold during cranking +%9?/. 6" 6"?,6 /54 ,3 /54 (3 /. /. /&& /. /. /&& 4?(/,$ 0/2 4HEDEVICE SWITCHESOFFALL FUNCTION 6$$ 6$$?56 234 '!0'03 66/170 DocID027452 Rev 5 L9779WD 6.10 Functional description LSa, LSb, LSc, LSd diagnosis Each channel locally detects and writes its own fault or no-fault condition (codified on 2 bit according to the table FAULT ENCODING CONDITION).  short circuit to battery or overcurrent for all the outputs during ON condition.  open load or short to GND during OFF condition. The faults are latched and reset every Read Diag operation. In OFF condition the first fault detected is latched and can be overwritten only by the ON condition fault. Channel “on” Short to Vb: Current diagnosis is the result of a comparison between driver load current and internal IOVC thresholds. If: ILOAD > IOVC for t > TFILTEROVC the driver is switched off and the fault is set, latched and reset every Read Diag operation. When the fault occurs the driver is switched off with a controlled slew-rate. The driver switches on AGAIN in the following conditions: – If command goes LOW and then HIGH again – If command remains active the driver is switched automatically on at every Read Diag operation. Short to GND: Not available. Open Load: Not available. Channel “off” Short to Vb: Not available. Short to GND & open load: In open load condition an internal circuit drives the OUTx voltage to VOUTOPEN with a maximum pull-up/down current of IOUT_PU and IOUT_PD. Diagnosis is done comparing driver output voltage with internal voltage thresholds VHVT and VLVT: if the voltage is below VLVT a short to GND is detected, if the voltage is above VLVT and below VHVT an open load is detected and if the voltage is above VHVT no fault is present. Diagnosis status is masked for Td_mask time after the off event occurs to allow the output voltage to reach the proper value. Short to GND and open load are filtered with TFILTERdiagoff time. Diag status is latched and reset at every Read Diag operation. DocID027452 Rev 5 67/170 169 Functional description L9779WD For LSc(OUT19,20) the IOUT_PD/IOUT_PU can be switched off by OFF_LCDR bit and therefore the Open Load and Short To GND detections are not available. Figure 40. LSx diagnosis circuit 6BAT ,OAD 6DD )/54?05 &ILTER $IAGNOSIS  PROTECTION 2 ESET ? /UT?,3X )/54?0$ &ILTER , $RIVER - 3#?# MD?,3X %. ? ,OW2 ES  /%?INT '!0'03 Table 28. Fault encoding condition Bit n Bit n+1 Description 1 1 Power stage OK no Fail 0 1 Open Load OL 1 0 Short circuit to VB/over current SGB 0 0 Short circuit to GND SCG Figure 41. Fault encoding condition diagram 6?/54X LOW SIDE .ORMAL .ORMAL FUNCTION 6 6(64MIN 6/54/0%. MAX 6/54/0%. 6/54/0%.MIN /PEN ,OAD /PEN,OAD 6,64MAX 6 3HORT TO 3HORTTO '.$ '!0'03 68/170 DocID027452 Rev 5 L9779WD Functional description Figure 42. LSx ON/OFF slew rate control diagram 4ON ;6=; 6= 4OFF ,OW3IDE 6OUT 32ON 32OFF 6OUT,OW3IDE ,OGICCONTROLL ,OGICCONTROLL ;MS= ;!=; 6= )GATE )ON )SRON 6GATE 6GATE ;MS= )SROFF )GATE )OFF '!0'03 6.11 Ignition pre-drivers (IGN1 to 4) Figure 43. Ignition-pre drivers (IGN1 to 4) circuit 6" 6$$ )'.X ,/')# /6%2 4%-0 $%4%#4)/. /0%.,/!$ #,+ $/ $) %. -3# &),4%2 3(/244/6" 3(/244/'.$ $%4%#4)/. '!0'03 DocID027452 Rev 5 69/170 169 Functional description 6.11.1 L9779WD Ignition pre-drivers functionality description The 4 ignition pre-drivers are push-pull output with diagnosis and over current protection circuit. They can drive IGBT Darlington transistors. The load is switched on with a current and switched off with I_LS_cont current. They are driven via MicroSecond Channel. When Reset_L9779 signal or OUT_DIS bit is asserted, output IGNx becomes high impedance. By MSC command it is possible to have the low-side stage always off, in this case there is an external pull down resistor that discharges. The IGNx output in Off phase. This Bit is present in config2(0) and its name is LS_IGN_OFF. Table 29. Ignition pre-drivers electrical characteristics Pin Symbol VDD5 Parameter Test condition Typ Max Unit 5.1 V Supply voltage range Info only 4.9 - Output voltage high level I_cont = 15 mA 4.35 - Leakage current - -10 - 10 µA -I_lim High-side current limitation - 19 - 33 mA I_LS_cont LS path continuous current capability Add also the RDSON Test - - 30 mA - 3 - 14 Ω Vign Ileak_out I_LS_RD LS RDSON S on V IOVC High side over current detection - 7 - 14 mA VLVT Output short-circuit to Gnd threshold voltage - 1.6 1.8 2 V - VDD5 +0.1V - VDD5 +2V - 100 - 850 µA - - 10 µs 50 - 100 µs IGN1 to 4 Vign_scb SCB detection voltage Iol OL detection current - Tdon Output on delay time CIgn = 10 nF OVC/Open load diagnosis filter time, Test by scan - Output on rise time CIgn = 10 nF - - 10 µs Output off delay time CIgn = 10 nF - - 10 µs Output off fall time CIgn = 10 nF - - 10 µs Rload Resistive load For info only 1 - 10 k Cout Output capacitance loads For info only 4 - 15 nF Tign_filt Tr Tdoff Tf 70/170 Min DocID027452 Rev 5 L9779WD Functional description Figure 44. Ignition-pre drivers (IGN1 to 4) diagram 6A LID-3#DATAF RAME TIME TR TDON TDOFF TF 6) '.X 6) '. 6) '. TIME 6) '. 6.11.2 '!0'03 Ignition pre-driver diagnosis Each channel locally detects and writes its own fault or no-fault condition (codified on 2 bit according to Table 28: Fault encoding condition). The detected faults are:  IGNx short circuit to battery (SCB)  IGNx open load (OL)  IGNx short to GND (SCG) Short to GND This diagnosis is made in two different ways based on the status of IGN_DIA_SGEN. If IGN_DIA_SGEN = 1 When the IGNx is on, if for a time longer than Tign_filt, the current is bigger than IOVC, the short to GND fault is detected and the IGNx output becomes high impedance, the fault is latched and is reset at every Read Diag operation. If IGN_DIA_SGEN = 0 When the IGNx is on, if for a time longer than Tign_filt, the voltage of IGNx is lower than VLVT, the short to GND fault is detected and the IGNx output becomes high impedance, the fault is latched and is reset at every Read Diag operation. The high impedance is removed and IGNx is driven by the command: – after a Read Diag operation – if command is switched OFF and ON again. Open load When IGNt is on, if for a time longer than Tign_filt, the current is below Iol the open-load fault is detected, latched and it is reset at every Read Diag operation. IGNx remains always driven. DocID027452 Rev 5 71/170 169 Functional description L9779WD Short circuit to battery When the load is on, if the voltage of IGNx is bigger than the Vign_scb threshold for a time longer than Tign_filt the SCB fault is detected and the output IGNx becomes high impedance. When the load is off, if the voltage of IGNx is bigger than the Vign_scb threshold for a time longer than Tign_filt the SCB fault is detected and the output IGNx becomes high impedance. The SCB fault has a higher priority with respect to the OL fault. According to the IGN_DIA_MODE bit, two behaviors are possible: 1. Latch mode The fault is latched and is reset at every Read Diag operation. The high impedance is removed and IGNx is driven by the command: 2. – after a Read Diag operation – if the command is switched OFF and ON again. No latch mode The fault is not latched and if the voltage of IGNx is lower than the Vign_scb threshold for a time longer than Tign_filt the fault state disappears and the high impedance is removed. 72/170 DocID027452 Rev 5 L9779WD 6.12 Functional description External MOSFET gate pre-drivers 2x external N-MOS gate drivers are available. Figure 45. External MOSFET gate pre-drivers circuit 6" 6$$ ,/!$ $2!).X /54X %84%2.!, . -/3 ,/')# /0%.,/!$ 6 #,+ $/ $) %. -3# &),4%2 3(/24%$ ,/!$ $%4%#4)/. '!0'03 The pre-drivers are designed with the following diagnostic features:  Open load detection during off state  Short circuit detection during on state  Programmable drain threshold and filter time for short fault detection. By monitoring the drain voltage of the external MOS each pre-driver is able to detect an open load and short to GND in the off state and a shorted load to VB in the on state. All faults are reported through MSC communication. An open load fault is detected when the drain voltage is less than the Vopen threshold. A shorted load fault is reported when the drain voltage is greater than the programmed threshold voltage for a time longer than the tshort programmed time. The output is switched off and the fault bit is set. The filter time and threshold voltage are programmed through MSC. A suitable clamping device must be put external in order to protect the device. DocID027452 Rev 5 73/170 169 Functional description L9779WD Table 30. External MOSFET gate pre-drivers Pin Symbol Min Typ Max Uni t - VDD5 -0.5V - VDD5 - Ileak_L Leakage current of push-pull low-side - - - 1 µA Ileak_H Leakage current of push-pull high-side - - - 1 µA Idrive Turn-on current - 22 - 12 mA Idrive Turn-off current - 12 - 22 mA Rgate External resistive pull-down Application note - 200 - kΩ VHVT Output voltage ok range threshold - VOutopen +120mV - 3 - VOUTOPEN Output open load voltage Open load condition 2.3 - 2.7 V VLVT Output Short-circuit to Gnd threshold voltage - 1.9 - VOutopen -200mV V IDRAIN_PD Output diagnostic pull down current off state Vpin = 5 V 50 - 110 µA IDRAIN_PU Output diagnostic pull up current off state Vpin = 1.5 V 110 160 210 µA Open load threshold current - 30 - 90 µA TFILTERdiago Filtering open load and short to gnd diag. off, Test by scan ff 37 50 63 µs 300 - 500 µs - - 2.2 µs -20% 0.15(1) +20% -20% 0.3 +20% -20% 0.45 +20% -15% 0.5 (defaul t) +15% -15% 1 +15% -15% 1.5 +15% -15% 2 +15% -15% 2.5 +15% Itopen Td_mask Tdelay Vshort 74/170 Test condition Output voltage high level VON DRAIN8_9, OUT8_9 Parameter Diagnosis Mask Delay after switch-off, Test by scan - Output on-off delay time Cout = 10 nF From command to 10% of transition Short to VB fault detection voltage threshold. Programmable from 0.15 V to 2.5 V - DocID027452 Rev 5 V L9779WD Functional description Table 30. External MOSFET gate pre-drivers (continued) Pin Symbol Parameter Test condition Min Typ Max Uni t +25% µs 1.3 2.6 DRAIN8_9, OUT8_9 Short to VB fault filter time. Programmable from 1.3 µs to 170 µs, Test by scan Tshort 5.2 (defaul t) - -25% 10 21 42 84 170 1. 0.172 for OUT8. 6.12.1 External MOSFET gate pre-drivers diagnosis Each channel locally detects and writes its own fault or no-fault condition (codified on 2 bit according to the Table 28: Fault encoding condition).  Short circuit to battery or overcurrent for all the outputs during ON condition.  Open load or short to GND during OFF condition. The faults are latched and reset at every Read Diag operation. In “off” conditions the first fault detected is latched and can be overwritten only by the ON condition fault. Channel “on” Short to Vb: Current diagnosis is the result of a comparison between Drain pin voltage and the internal Vshort threshold selected by MSC. If: Vdrain> Vshort for t > TSHORT the driver is switched off and the fault is set, latched and reset at every Read Diag operation. When the fault occurs the driver is switched off with a controlled slew-rate. The drivers switches on AGAIN in the following conditions: – If command goes LOW and than HIGH again – If command remains active driver is switched automatically on at every Read Diag operation. Short to GND: Not available. Open load: Not available. DocID027452 Rev 5 75/170 169 Functional description L9779WD Channel “off” Short to Vb: Not available. Short to GND and open load: In open load conditions an internal circuit drives the DRAINx voltage to VOUTOPEN with a maximum pull-up/down current of IOUT_PU and IOUT_PD. Diagnosis is done comparing driver output voltage with internal voltage thresholds VHVT and VLVT: if the voltage is below VLVT a short to GND is detected, if the voltage is above VLVT and below VHVT an open load is detected and if the voltage is above VHVT no fault is present. Diagnosis status is masked for Td_mask time after the off event occurs to allow the output voltage to reach the proper value. Short to GND and Open load are filtered with TFILTERdiagoff time. Diag status is latched and reset every Read Diag operation. 6.13 Configurable power stages (CPS) (OUT21 to 28) 6.13.1 Configurable power stages functionality description L9779 has 4 low-side N-channel power stages and 4 high-side P-channel power stages [OUT21 to OUT28] that can be arranged as follows using the CPS_CONF1,2 bit (default Hbridge):  Eight individual power stages (four low-side and four high-side power stages). Low side can be connected in parallel (in pair) to obtain a low side driver with about 0.75 Ω Rdson resistance: OUT22 with OUT24 and OUT27 with OUT28. For three reasons outputs are switched in parallel: a) to increase current capability (please see electrical characteristic) b) to reduce power dissipation (please see electrical characteristic) c) to increase clamp energy capability (please see electrical characteristic) The max. clamping energy is probably less than the sum of the corresponding max. clamping energies. Parallel connection of Low-side power stages is possible as the control bit to turn-on and off the power stages is allocated in the same register. Unlike the H-bridge configuration, no coherency check is done. OUT21 and OUT25 are able to remain active also during crank pulse during which the battery voltage on the VB pin goes below the level VB_LV for a period of time THOLD, this time lapse calculation is triggered by the falling edge of RST In this situation VDD5 is below undervoltage threshold (VDD_UV) and the micro controller is in reset condition. During the THOLD time the VDD5 supply and the micro controller have to recover and take over control of the output. Otherwise the output is switching to OFF condition after the THOLD time. The low battery functionality can be enabled/disabled through bit OUT21_EN_LB and OUT25_EN_LB of CONF_REG7. For the behavior of OUT21, 25 during cranking refer to behavior of OUT13, 14. 76/170 DocID027452 Rev 5 L9779WD Note: Functional description The bit OUT21,25_EN_LB has priority over CPS_CONFx bit, this means that if one of OUT21,25_EN_LB is set to 1 the OUT21…28 become independent power stages.  Two H-Bridge for stepper motor driving (no half-bridge arrangement is possible). The over current threshold is the same as the single power stages. When configured for stepper motor driving the motor movement is controlled through bit EN, DIR and PWM (see Table 31). In stepper motor configuration HS and LS power stages (OUT21...OUT28) can be used as single power stages, and any of them can be connected in parallel to each other (same type). If the bit EN=1, the writing of bit PWM from 0 to 1 lead to the next step of the turn on sequence. The writing of bit PWM to 0 left unchanged the MOS of the bridge that is ON. The step is done only if the PWM bit goes from 0 to 1. The order of the turn-on sequence is defined by the bit DIR. Table 31. Configuration of the stepper motor PWM EN DIR H-bridge 1 Power on H-bridge 2 Power on X 0 X None None 1 1 1 OUT21, OUT24 OUT26, OUT27 1 1 1 OUT21, OUT24 OUT25, OUT28 1 1 1 OUT23, OUT22 OUT25, OUT28 1 1 1 OUT23, OUT22 OUT26, OUT27 1 1 0 OUT21, OUT24 OUT26, OUT27 1 1 0 OUT23, OUT22 OUT26, OUT27 1 1 0 OUT23, OUT22 OUT25,OUT28 1 1 0 OUT21, OUT24 OUT25,OUT28 The initial stepper position, after power-on, is the one with OUT21 and OUT24 ON in Hbridge1 and with OUT26 and OUT27 ON in Hbridge2. If configured as H-bridges the internal logic prohibits that the low-side and the high-side switch of the same half-bridge will be switched on simultaneously. In the below diagram the stepper motor operation is available. DocID027452 Rev 5 77/170 169 Functional description L9779WD Figure 46. Stepper motor operation diagram 7RITING$)2BIT 7RITING$)2BIT 7RITING%.BIT 7RITING%.BIT 7RITING07-BITFROMTO 7RITING07-BITFROMTO 4SETTLE /54/. /54 /54/. /54/. /54 /54/. /54/. /54 /54/. /54/. /54 /54/. '!0'03 The writing of DIR bit and PWM bit cannot be done in the same time, at least two consecutive MSC frames are necessary.(if done the stepper will move one step in the old direction). The writing of EN bit and PWM bit cannot be done in the same time, at least two consecutive MSC frames are necessary. (If done it is supposed that only the EN bit has been received). Table 32. H-bridge1 configurable power stages OUT [21 to 24] 78/170 H-bridge1 Comment Nominal current Ron max Switch off current (min.) Clamping (typ.) OUT21 High-side P-Ch 0.6 A 1.5 Ω 1A N/A OUT22 Low-side N-Ch 0.6 A 1.5 Ω 1A 45 V DocID027452 Rev 5 L9779WD Functional description Table 32. H-bridge1 configurable power stages OUT [21 to 24] (continued) H-bridge1 Comment Nominal current Ron max Switch off current (min.) Clamping (typ.) OUT23 High-side P-Ch 0.6 A 1.5 Ω 1A N/A OUT24 Low-side N-Ch 0.6 A 1.5 Ω 1A 45 V Table 33. H-bridge2 configurable power stages OUT [25 to 28] H-bridge2 Comment Nominal current Ron max Switch off current (min.) Clamping (typ.) OUT25 High-side P-Ch 0.6 A 1.5 Ω 1A N/A OUT26 High-side P-Ch 0.6 A 1.5 Ω 1A N/A OUT27 Low-side N-Ch 0.6 A 1.5 Ω 1A 45 V OUT28 Low-side N-Ch 0.6 A 1.5 Ω 1A 45 V Figure 47. Configurable power stages OUT [21 to 24] can be configured to create the H-bridge1 6"!4 #-$?/54 #-$?/54 /54 /54 /54 /54 #-$?/54 #-$?/54 '.$ '!0'03 Figure 48. Configurable power stages OUT [25 to 28] can be configured to create the H-bridge2 6"!4 #-$?/54 #-$?/54 /54 /54 /54 /54 #-$?/54 #-$?/54 '.$ '!0'03 DocID027452 Rev 5 79/170 169 Functional description L9779WD Stepper counter In order to keep trace of the stepper movement in L9779WD a 10-bit register is available (5 bits in the STEP_CNT_H and 5 bits in the STEP_CNT_L) The value of this register after the power-up is 512 and:  with DIR=1 the value is increased by one for each step of the motor  with DIR=0 the value is decreased by one for each step of the motor. When the counter reaches the max or min value it remains at that value unless the direction is inverted. In the STEP_CNT_H and STEP_CNT_L registers there are two bits used to check if the content of the register is referred to the same motor step. The stepper counter is reset by power-on reset and software reset. Figure 49. Stepper counter diagram 3TEPPERCOUNTERVALUE  $)2  3TARTINGVALUE $)2  '!0'03 Driver parallel configuration Low side drivers can be connected in parallel to increase the current driving capability. High side drivers behave similarly. Configurations are set by CONFIG_REG7 and CONFIG_REG10. 6.13.2 Diagnosis of configurable power stages (CPS) All CPS have fault diagnostic functions:  Short-circuit to battery voltage: (SCB) can be detected if switches are turned on  Short-circuit to ground: (SCG) can be detected if switches are turned off  Open load: (OL) can be detected if switches are turned off  Over temperature: (OT) will be detected with the general thermal warning(OT2) Diagnosis is different for configuration as full-bridges or as single power stages. The faults are coded in different way and are stored in diagnostic registers. In each configuration the registers can be read via MSC. With the beginning of each read cycle the registers are cleared automatically. 80/170 DocID027452 Rev 5 L9779WD Functional description In each configuration there is one central diagnostic bit F2 for fault occurrence at any output. 6.13.3 Diagnosis of CPS [OUT21 to OUT28] when configured as H-bridges Stepper motor driver OFF diagnosis (output in high impedance state). In OFF condition Short to GND/Short to VB or Open Load condition is continuously detected through a deglitch filter Tdgc_off, after Tmask_step masking time to filter ON/ OFF transition. To avoid false diagnostic due to motor residual movement, the off command (EN bit=0) must be sent Tsettle time after the last valid on command PWM bit written to 1 (one couple of HS and LS switched on). A fault longer than deglitch time is latched. Off state diagnostic fault can be overwritten by on state fault. Off state fault does not prevent the stepper from switching on. The latched fault is cleared by reading the diagnosis data registers via MSC - and so resetting the diagnosis registers. An Off state due to a wrong command sent by MSC interface does not activate the Off diagnosis. Stepper motor driver ON diagnosis (Output driven by MSC CONTR_REG bit) In ON condition when over current fault is detected and validated after digital filtering time Tdgc_ON, the bridge is turned OFF and the fault is latched. The bridge is turned ON again by MSC command. The latched fault is cleared by reading the diagnosis data registers via MSC and so resetting the diagnosis registers. Over current fault has higher priority over OFF condition faults. Each Bridge has dedicated fault diagnosis register DIAG_H1, DIAG_H2. In ON condition if the current in the load current is lower than I_OPEN_LOAD for a time longer than Tdgc_ol_on, an Open load condition is detected It could be necessary two steps of the stepper motor operation to detect the real kind of fault, in this case as first diagnosis the fault is "Fault detection running" and with the next PWM command it is possible to understand if the fault is an OPEN LOAD or an OVERCURRENT/SHORT to GND. The Faults "DETECTION_RUNNING" & "OPEN LOAD" are latched during the during rise & fall edge of low-side driver command, if the fault disappeared during these phases the fault condition is no latched: – The FAULT DETECTION RUNNING is no latched, the fault comes back to 0 if the current becomes higher than open load threshold, before the switch off of low-side driver. – The FAULT OPEN LAOD is no latched, the fault comes back to 0 if the current becomes higher than open load threshold, before the switch off of low-side driver. A diagnostic read will clear the “fault detection running” flag. Anyway the diagnostic will restart. DocID027452 Rev 5 81/170 169 Functional description L9779WD Figure 50. Stepper motor driver “off” diagnosis time diagram /54 6" 6" (64( 6/54./2,64( TIME 4MASKSTEP /54 6" 6/54./2- ,64( ,64( TIME /. /&& /0%.,/!$ !FTERFILTERTIME4DGC?OFF 3(/244/6" !FTERFILTERTIME 3(/244/'.$ !FTERFILTERTIME '!0'03 Figure 51. Stepper motor driver diagnosis I-V relationship diagram ,'66B287BRQ 287 —$ 9% +97+ —$ —$ 9'' 287 ,'66B287BRQ 287 —$ —$ 9% /97+ —$ 287 67* 1250$/ 67% *$3*36 Note: 82/170 this wave shows the I/V relationship of pin current and pin voltage when OUTA(OUTC) short to OUTB(OUTD) and force the pin voltage from 0 V to VB in typical condition. For example, when pin voltage of OUTA = OUTB = 1.5 V, the pull up/down current is about -50 µA for OUTA and about 14 µA for OUTB. When pin voltage of OUTA = OUTB = 5 V, the pull up/down current is about 40 µA for OUTA and about 220 µA for OUTB. DocID027452 Rev 5 L9779WD Functional description Figure 52. Open load detection during “on” phase /54!" /54#$ )?,/!$ )?/0%.?,/!$ 4DGC?OL?ON 4DGC?OL?ON &!5,4$%4%#4)/.25..).' ./&!5,4 ./&!5,4 ,OW3IDE$RIVER#OMMAND   /54!" /54#$ )?,/!$ )?/0%.?,/!$ 4DGC?OL?ON 4DGC?OL?ON &!5,4$%4%#4)/.25..).' /0%.?,/!$ ./&!5,4 '!0'03 Figure 53. Open load detection during “on” phase #HANGESLOW SIDEDRIVERCOMMAND #HANGESLOW SIDEDRIVERCOMMAND /54!" /54#$ \)LOAD\ /PENLOAD/. &AULT(APPENS !NDITISVALIDATED !FTER4DC?OL?ON &!5,4 $%4%#4)/. 25..).' ,!4#(%$ ,ATCHED/PEN ,OAD/N&AULT )?/0%.?,/!$ 4DGC?OL?ON $)!'./3)3 ./&!5,4 &!5,4$%4%#4)/.25..).' /0%.,/!$ /.,!4#(%$ '!0'03 DocID027452 Rev 5 83/170 169 Functional description L9779WD Figure 54. Short to GND detection during “on” phase #HANGESLOWSIDEDRIVERCOMMAND /54!" /54#$ )LOADFROM/54"TO/54! "! /540543(IGH : "! 4DGC?OL?ON 4DGC ?/. \)LOAD\ &AULTAPPEARS ,ATCHED&AULT CLEAREDBY DIAGNOSIS READING )?3# )?/0%.?,/!$ 4DGC?OL?ON &!5,4 $%4%#4)/. 25..).' $)!'./3)3 ./&!5,4 ./ &!5,4 3(/244/'.$ 3(/244/'.$ '!0'03 Table 34. Stepper configuration electrical characteristics Pin Symbol Test condition Min Typ Max Unit OUT(21,22), OUT(23,24), OUT(25,27), OUT(26,28) output voltage OUT(21,22) short to OUT(23,24); OUT(25,27) short to OUT(26,28); 2.3 - 2.7 V HVTH Diagnostic high threshold Driver in OFF condition VOutnorm +120mV - 3 V LVTH Diagnostic low threshold Driver in OFF condition 1.9 - VOutnorm -200mV V IOVC Over current threshold - 1 - 2.1 A Output open load threshold current - 10 - 90 mA Output diagnostic IOUT_PD_A+B pull down current or C+D OFF STATE Vpin = 5 V 200 - 350 µA Output diagnostic IOUT_PU_A+B pull up current OFF or C+D STATE Vpin = 0 V 50 - 150 µA Open load resistor threshold Application note 150 - - kΩ Tdgc_ON Deglitch filter time in ON condition Test by scan -25% 10 +25% µs Tdgc_OFF - Test by scan -25% 125 +25% µs Tdgc_ol_on - Test by scan -25% 20 +25% µs VOutnorm OUT 21 to 28 I_OPEN_LOAD Ropenl 84/170 Parameter DocID027452 Rev 5 L9779WD Functional description Table 34. Stepper configuration electrical characteristics (continued) Pin Symbol OUT21…28 Test condition Min Typ Max Unit -25% 1 +25% ms Tmask_step - Test by scan Tsettle - For information only; No tested 100 - - ms Operating frequency For information only; No tested 50 - - µs T_PWM 6.13.4 Parameter Diagnosis of CPS [OUT21 to OUT28] when configured as single power stages For the low side the diagnosis is the same as LSd. For the high side the diagnosis is described below. Each channel locally detects and writes its own fault or no-fault condition (codified on 2 bit according to Table 28: Fault encoding condition).  Short circuit to battery or overcurrent for all the outputs during ON condition.  Open load or short to GND during OFF condition. The faults are latched and reset at every Read Diag operation. In OFF condition the first fault detected is latched and can be overwritten only by the ON condition fault. Channel “on” Short to GND: Current diagnosis is the result of a comparison between driver load current and internal Ilimit thresholds. If: ILOAD > IOVC for t > TFILTEROVC the driver is switched off and the fault is set, latched and reset at every Read Diag operation. When the fault occurs the driver is switched off with a controlled slew-rate. The Drivers switches on AGAIN in the following conditions: – If command goes inactive and then active again – If command remains active driver is switched automatically on at every Read Diag operation. Short to VB: Not available. Open load: Not available. DocID027452 Rev 5 85/170 169 Functional description L9779WD Channel “off” Short to GND: Not available. Short to VB & open load: In open load condition an internal circuit drives the OUTx voltage to VOUTOPEN with a maximum pull-up/down current of IOUT_PU and IOUT_PD. Diagnosis is done comparing driver output voltage with internal voltage thresholds VHVT and VLVT: if the voltage is above VHVT a short to VB is detected, if the voltage is above VLVT and below VHVT an open load is detected and if the voltage is below VLVT no fault is present. Diagnosis status is masked for Td_mask time after the off event occurs to allow the output voltage to reach the proper value. Short to GND and Open load are filtered with TFILTERdiagoff time. Diag status is latched and reset at every Read Diag operation. Figure 55. Short to VB & open load diagram 6?/54X HIGH SIDE 3HORTTO 6" 6 6(64MIN 6/54/0%. MAX 6/54/0%. 6/54/0%.MIN /PEN,OAD /PEN ,OAD 6,64MAX 6 .ORMAL FUNCTION '!0'03 86/170 DocID027452 Rev 5 L9779WD Functional description Electrical and diagnosis characteristics of [OUT22], [OUT24], [OUT27], [OUT28] when configured as single power stages Same parameter and diagnosis function as LSd. Table 35. Electrical and diagnosis characteristics of [OUT22], [OUT24], [OUT27], [OUT28] when configured as single power stages Pin Symbol Parameter Min Typ Max Unit RDS-on LSd Drain source resistance Iload = 0.6 A - - 1.5 Ω IOUTlk Output leakage current Vpin = 13.5 V - - 10 µA Voltage S/R On/off R = 21 Ω, C = 10nF From 80% to 30% of VOUT 2 - 6 V/us Fast VR/S off when an OVC fault happens Load: 8 Ω, 10nF - from 80% to 30% of VOUT 5 - 30 V/µs TTurn-On_ LSd Turn-on delay time From command to 80% VOUT Load: 21 Ω, 10nF - - 6 µs TTurn-Off_ LSd Turn-off delay time From command to 30% VOUT Load: 21 Ω, 10nF - - 6 µs Over current filtering time Tested by scan 2 3 4 µs TFILTERdiagoff Filtering open load and short to GND diag. off Tested by scan 8 10 12 µs Td_mask Diagnosis mask delay after switch-off Tested by scan 350 400 450 µs 46 48 50 V Iload = 0.6A; single pulse - - 15 mJ Tc ≤ 30 °C; I_OUT_n ≤ 0.45 A 1 Mio cycles - - 6.5 Tc ≤ 80°C; I_OUT_n ≤ 0.3A 25 Mio cycle - - 6.5 VS/R VS/R GateKill TFILTEROVC OUT22, 24,27,28 1.5 Ω PWclampSP PWclampRP Test condition Output clamping voltage Iload = 0.6A Clamp single pulse ATE test Clamp repetitive pulses Freq = 1 Hz (to be verified) Reliability Tc ≤ 100°C; Test I_OUT_n ≤ 0.3A 20 Mio cycle Tc ≤ 130 °C; I_OUT_n ≤ 0.3 A 5 Mio cycle Reverse voltage Body diode reverse current voltage drop I = -0.6 A DocID027452 Rev 5 mJ - - 6.5 - - 5.5 -0.5 -1 -1.1 V 87/170 169 Functional description L9779WD Electrical characteristics of [OUT22], [OUT24], [OUT27], [OUT28] when configured as single power stages connected in parallel When the low side drivers are connected in parallel (in pair) to obtain a low side driver with a lower resistance, OUT22 with OUT24 and OUT27 with OUT28, the following parameters should be considered: Table 36. Electrical characteristics of [OUT22], [OUT24], [OUT27], [OUT28] when configured as single power stages connected in parallel (For information only) Pin Symbol Imax Test condition Typ Max Unit Not tested - 1.2 - A RDS-on LSd Drain source resistance Iload = 1.2 A - - 0.75 Ω IOUTlk Output leakage current - - 10 µA VS/R Voltage S/R on/off 2 - 6 - TTurn-on Turn-on delay time - - 6 µs TTurn-off Turn-off delay time - - 6 µs - 2 - 4.2 A (1) Over current filtering time Tested by scan 2 3 4 µs TFILTERdiagoff Filtering open load and short to GND diag. off Tested by scan 8 10 12 µs Td_mask Diagnosis mask delay after switch-off Tested by scan 350 400 450 µs Clamp single pulse Iload = 1 A; single pulse(1) - - 25 mJ PWclampRP Clamp repetitive pulses Reliability note: Iload = 0.6 A Freq =10 Hz; 36 Mpulse (1000h) - - 12 mJ IOUT_PD Output diagnostic pull down current off state Vpin = 5 V (1) 50 - 110 µA IOUT_PU Output diagnostic pull up current off state -210 - -108 µA ∆Vclamp Delta clamping voltage between low side to be parallelized -250 - +250 mV TFILTEROVC PWclampSP (1) 1. Not to be tested, already covered by single low side measure and guaranteed by design. 88/170 Min Output current IOVC Out 22_24, 27_28 Parameter DocID027452 Rev 5 L9779WD Functional description Electrical characteristics of [OUT21], [OUT23], [OUT25], [OUT26] when configured as single power stages If necessary an external free-wheeling diode must be used for the High side drivers. Table 37. Electrical characteristics of [OUT21], [OUT23], [OUT25], [OUT26] when configured as single power stages Pin Symbol Parameter Test condition Min Typ Max Unit Output current Not tested - 0.6 RDS-on LSd Drain source resistance Iload = 0.6 A - - 1.5 Ω IOUTlk Output leakage current Vpin = GND, VB = 13.5 V - - 10 µA VS/R voltage S/R on/off R = 21 Ω, C = 10 nF; from 70% to 20% of VOUT 2 - 6 - TTurn-on_ LSd Turn-on delay time From command to 70% VOUT Load: 21 Ω, 10 nF - - 6 µs TTurn-off_ LSd Turn-off delay time From command to 20% VOUT Load: 21 Ω, 10 nF - - 6 µs Imax Out 21,23,25,26 A Diagnosis characteristic of [OUT21], [OUT23], [OUT25], [OUT26] when configured as single power stages Table 38. Diagnosis characteristic of [OUT21], [OUT23], [OUT25], [OUT26] when configured as single power stages Pin Symbol Test condition Ropen load Min resistor value open load detection Not tested IOVC Over current threshold - TFILTEROVC TFILTERdiaggoff Td_mask Out 21, 23, 25, 26 Parameter VOUTOPEN Min Typ Max Unit 500 - - kΩ 2 A 1 Over current filtering time Tested by scan 2 4 5 µs Filtering open load and short to GND diag. off 7 - 13 µs Diagnosis mask time after Tested by scan switch-off 1.2 - 1.6 ms Output open load voltage Open load condition 2.3 - 2.7 V VOUTOPEN +160mV - 3 V Tested by scan VHVT Output short-circuit to VB Voltage range threshold VLVT Open load threshold voltage - 1.9 - VOUTOPEN -200mV V IOUT_PD Output diagnostic pull down current off state Vpin = 5 V 160 240 320 µA IOUT_PU Output diagnostic pull up current off state Vpin = GND 30 50 70 µA Open load threshold current - 100 - 200 - ItOPEN DocID027452 Rev 5 89/170 169 Functional description L9779WD Table 38. Diagnosis characteristic of [OUT21], [OUT23], [OUT25], [OUT26] when configured as single power stages (continued) Pin Symbol OUT21, 25 Note: Parameter Test condition THOLD Switch on to off delay during low battery voltage operation. Tested by SCAN VB_LV VB voltage threshold for low battery function Min Typ Max Unit 400 - 800 ms - - 4.15 V - When power stages are configured in parallel mode, some parameters change depending on CONFIG_REG7 and CONFIG_REG10 registers (refer to register configuration Table 39 & 40). (CPS) CONFIG_REG10 (WR_CPS command 110011) Table 39. CPS table single mode parallelism Register bit 7 3 2 1 0 If not specified Output Drivers are set as single (not in parallel with any other) Over Current mask time increased to 8 µs (bit 6…4 set Low, they can be combined as per next table) Enable Diagn by on 2Low 0 0 0 1 0 OUT22 and OUT24 Low side Parallel OUT24 OUT22 2Low 2Low 0 0 1 0 0 OUT22 and OUT24 Low side Parallel OUT27 and OUT28 Low side Parallel OUT24 OUT22 OUT27 OUT27 4Low 0 1 0 0 0 OUT22 and OUT24 and OUT27 and OUT28 Low side Parallel OUT24 OUT22 2High 0 0 1 1 0 OUT21 and OUT23 High side Parallel OUT23 OUT21 2High 2high 0 1 1 1 0 OUT21 and OUT23 High side Parallel OUT25 and OUT26 High side Parallel OUT23 OUT21 OUT25 OUT25 4High 0 1 0 1 0 OUT21 and OUT23 and OUT25 and OUT26 High side Parallel OUT23 OUT21 3High 1 0 1 0 0 OUT23 and OUT25 and OUT26 High side Parallel OUT23 OUT25 3Low 1 1 1 0 0 OUT24 and OUT27 and OUT28 Low side Parallel OUT24 OUT24 Table 40. CPS table combined mode parallelism Register 7 6 5 4 3 2 1 0 bit Over current mask time increased to 8 µs Enable by Diagn on 2Low 2High 0 0 0 1 0 0 1 0 OUT22 and OUT24 Low side Parallel OUT25 and OUT26 High side Parallel OUT24 OUT22 OUT25 OUT25 2Low 2Low 2High 0 0 0 1 0 1 0 0 OUT27 and OUT28 Low side Parallel OUT22 and OUT24 Low side Parallel OUT25 and OUT26 High side Parallel OUT27 OUT27 OUT24 OUT24 OUT25 OUT25 3Low 3High 1 1 1 1 0 1 0 0 OUT24 and OUT27 and OUT28 Low side Parallel 1 0 1 0 1 1 0 0 OUT23 and OUT25 and OUT26 High side Parallel OUT24 OUT24 OUT23 OUT25 90/170 DocID027452 Rev 5 L9779WD Functional description Table 40. CPS table combined mode parallelism (continued) Register 7 6 5 4 3 2 1 0 bit Over current mask time increased to 8 µs Enable by Diagn on 4Low 4High 0 1 0 0 1 0 0 0 OUT22 and OUT24 and OUT27 and OUT28 Low side Parallel OUT24 OUT22 0 1 0 1 1 0 1 0 OUT21 and OUT23 and OUT25 and OUT26 High side Parallel OUT23 OUT21 2Low 2High 0 0 1 1 0 1 1 0 OUT27 and OUT28 Low side Parallel OUT21 and OUT23 High side Parallel OUT27 OUT27 OUT23 OUT21 2Low 2Low 2High 2High 0 1 1 1 0 1 0 0 OUT22 and OUT24 Low side Parallel 0 0 1 0 1 1 1 0 OUT27 and OUT28 Low side Parallel OUT21 and OUT23 High side Parallel OUT25 and OUT26 High side Parallel OUT24 OUT27 OUT23 OUT25 4Low 2High 0 1 0 1 0 1 1 0 OUT22 and OUT24 and OUT27 and OUT28 Low side Parallel OUT24 OUT22 OUT21 and OUT23 High side Parallel OUT23 OUT21 4Low 2High 0 0 0 1 1 0 0 0 OUT22 and OUT24 and OUT27 and OUT28 Low side Parallel OUT24 OUT22 OUT25 and OUT26 High side Parallel OUT25 OUT25 2Low 4High 0 1 0 0 0 0 1 0 OUT22 and OUT24 Low side Parallel OUT24 OUT22 OUT21 and OUT23 and OUT25 and OUT26 High side Parallel OUT23 OUT25 2Low 4High 0 1 0 0 0 1 0 0 OUT27 and OUT28 Low side Parallel OUT27 OUT27 OUT21 and OUT23 and OUT25 and OUT26 High side Parallel OUT23 OUT25 Half Bridge 2Low 2High 1 0 1 1 0 1 1 0 Note: OUT22 and OUT24 Low side Parallel OUT21 and OUT23 High side Parallel OUT22 OUT27 OUT21 OUT26 OUT24 OUT22 OUT23 OUT21 When those four single Lside and four single Hside are configured as parallel configuration, for example 2 single Lside stage to 1 Lside stage or 4 single Lside stage to 1 Lside stage, the Rdson could be 1/2 or 1/4 as one single stage, the over current threshold could be roughly double or 4 times as single stage, but the over current detected filter time will be increased to 2 times as single stage from 4 µs typical to 8 µs typical by L9779WD itself, because each single stage will switch on its own overcurrent threshold no matter the configuration for off stage diagnostic, all thresholds will be kept as single stage whatever the configuration of those 4 Lside/Hside. DocID027452 Rev 5 91/170 169 Functional description 6.14 L9779WD ISO serial line (K-LINE) Figure 56. ISO serial line (K-LINE) circuit 6" )3/3%2)!, ,).% 6$$?)/ %XTERNAL RESISTOR +?28 TO—# +?,).% 6$$ +?48 FROM—# '!0'03 6.14.1 ISO serial line (K-LINE) functionality description The ISO serial line is an interface containing one bidirectional line for communication between the µP and an external diagnosis tester or anti-theft device. In case of ground loss the outputs K_LINE get in high impedance state and can withstand a negative voltage up to -18 V. Short circuit to Vb protection is provided: if the K_LINE pin is shorted to battery the output is switched off after a delay of tfilter_K_LINE and it is necessary an input change to turn on it again. The negative transition at K_LINE pin can be driven with slew-rate limitation for optimizing the EMI behavior. This slew-rate limitation must be enabled via the ISO_SRC bit. The K_TX signal is ignored (K_LINE pin to high level) until the RST pin is asserted. KLINE can work up to 250 kHz input frequency in typical application condition. Table 41. ISO serial line (K-LINE) functionality electrical characteristics Pin K_TX Symbol Test condition Min Typ Max Unit VKTXL K_TX input low voltage - -0.3 - 1.1 V VKTXH K_TX input high voltage - 2.3 - VDD +0.3 V TX_KLINE pull-up resistor - 50 - 250 kΩ Transmitter input sink current K_LINE = 0, K_TX = High - - 5 µA RTX_KPU ITXsink 92/170 Parameter DocID027452 Rev 5 L9779WD Functional description Table 41. ISO serial line (K-LINE) functionality electrical characteristics (continued) Pin Symbol Parameter Min Typ Max Unit VKOUTL Transmitter output low voltage Isink_K_LINE = 35 mA, K_TX = Low -1 - 1.5 V Transmitter short circuit current K_LINE = VB, K_TX = Low 60 - 165 mA Test by SCAN 7 10 13 µs Reverse battery or GND loss current Key_on = VB = 0 V K_LINE = -18 V - - 10 mA Under voltage current Key_on = High, K_TX = Low, VB = 13.5 V, K_LINE = -1V - - 1 mA Receiver input hysteresis - 0.08*VB - 0.3*VB V VKINH Receiver input high voltage - 0.7* VB - VB V VKINL Receiver input low voltage - -1 - 0.35*VB V From off to on: VB = 13.5 V, Rext = 510 Ω C = 10 nF to GND 5.3 - 8.8 V/µs IKOS Test condition Tfilter_K_LINE Overcurrent filter time IKREV K_LINE VKH VK_SR K_line voltage slew rate From on to off CK_LINE = 10 nF, RK_LINE = 510 Ω - - 10 µs VKRXL K_RX output low voltage VDD_IO = 5 V or 3.3 V Isink = 2 mA - - 0.5 V VKRXH K_RX output high voltage VDD_IO = 5 V or 3.3 V Isource = 2 mA VDD_IO -0.5 - - V T_rK K_RX rise time from 10% to 90% With 20 pF capacitive load - - 2 µs T_fK K_RX fall time from 90% to 10% 20 pF capacitive load - - 2 µs Tp_HLT Transmitter turn-on delay time CK_LINE = 10 nF, RK_LINE = 510 Ω - - 5 µs TpHLK K_RX turn-on delay time Cload = 20 pF - - 4 µs TpLHK K_RX turn-off delay time Cload = 20 pF - - 4 µs K_RX K_LINE, K_RX - Transmitter fall time T_fT K_TX, K_LINE Depends on external RC load DocID027452 Rev 5 93/170 169 Functional description L9779WD Figure 57. ISO serial line switching waveform 6$$( +?48  6 TP(,4 6"  +?,).%    6 TF4 TP(,+ 6$$( TP,(+   +?28    6 TF+  TR+ '!0'03 Figure 58. ISO serial line: short circuit protection 6$$( +?48 6 )3# )?+,).% ! 6" +?,).% 6 3(/24#)2#5)44/6" 94/170 DocID027452 Rev 5 '!0'03 L9779WD 6.15 Functional description CAN transceiver Figure 59. CAN transceiver diagram #!.3%2)!,,).% 6$$ 6 $$ 0/7%2 #/.42/, #!.?48 6$$ #!.?28 #!.(  #!., 28?%#( / '!0'03 6.15.1 CAN transceiver functionality description The CAN bus transceiver allows the connection with a microcontroller through a high speed CAN bus with transmission rates up to 1Mbit/s. The transceiver has one logic input pin (CAN_TX), one logic output pin (CAN_RX) and two input/output pins for the electrical connections to the two bus wires (CANH and CANL). The microcontroller sends data to the CAN_TX pin and it receives data from the CAN_RX pin. In case of power loss (VB pin disconnected) or ground loss (GND pins disconnected), the transceiver doesn't disturb the communication of the remaining transceivers connected to the bus. If CANL is shorted to ground, the transceiver is able to operate with reduced EMI/RFI performances. TX or RX=0 means Dominant state of CANH and CANL; TX or RX=1 means Recessive state compliant to ISO11898-2.  Speed communication up to 1Mbit/s  Function range from +40 V to -18 V DC at CAN pins  GND disconnection fail safe at module level  GND shift operation at system level  ESD: Immunity against automotive transients per ISO7637 specification  Matched output slopes and propagation delay. The CAN_TX signal is ignored (CAN to recessive state) until the RST pin is asserted. DocID027452 Rev 5 95/170 169 Functional description L9779WD CAN error handling The L9779WD provides the following 4 error handling features that are realized in different stand alone CAN transceivers / micro controllers to switch the application back to normal operation mode. If one of the below fault happens the status bit CAN_ERROR is set. The error handling features can be disabled through the CAN_ERR_DIS bit. 1. Dominant CAN_TX time out If CAN_TX is in dominant state (low) for t > tdom (TxD) the transmitter will be disabled, status bit will be latched and can be read and cleared by MSC. The transmitter remains disabled until the status register is cleared. 2. CAN permanent recessive If CAN_TX changes to dominant (low) state but CAN bus (CAN_RX pin) does not follow for 4 times, the transmitter will be disabled, status bit will be latched and can be read and cleared by MSC. The transmitter remains disabled until the status register is cleared. 3. CAN permanent dominant If the CAN bus state is dominant (low) for t > tCAN a permanent dominant status will be detected. The status bit will be latched and can be read and cleared by MSC. The transmitter will not be disabled. 4. CAN_RX permanent recessive If CAN_RX pin is clamped to recessive (high) state, the controller is not able to recognize a bus dominant state and could start messages at any time, which results in disturbing the overall bus communication. Therefore, if RX_ECHO does not follow CAN_TX for 4 times the transmitter will be disabled. The status bit will be latched and can be read and optionally cleared by MSC. The transmitter remains disabled until the status register is cleared. CAN transceiver electrical characteristics Table 42. CAN transceiver electrical characteristics Pin Symbol Test conditions Min Typ Max Unit VTX_CANLOW Input voltage dominant level Active mode -0.3 - 1.1 V VTX_CANHIGH Input voltage recessive level Active mode 2.3 - VDD +0.3 V VTX_CANHYS VTX_CANHIGHVTX_CANLOW Active mode 0.25 0.5 - V RTX_CANPU CAN_TX pull up resistor Active Mode 50 - 250 kΩ - 0.5 V - - V CAN_TX VRX_CANLOW Output voltage dominant level VRX_CANHIGH Output voltage recessive level CAN_RX 96/170 Description Active mode, VDD_IO = 5 V or 3.3 V, 2 mA VDD_IO -0.5 DocID027452 Rev 5 L9779WD Functional description Table 42. CAN transceiver electrical characteristics (continued) Pin Symbol Description Test conditions VCANHdom CANH voltage level in dominant state VCANLdom CANL voltage level in dominant state Differential output voltage in dominant VDIFF,domOUT state: VCANHdomVCANLdom VCM Active mode; VTXCAN = VTXCANLOW; RL = 60 Ω Driver symmetry: RL = 60 Ω; CSPLIT = 4.7 nF; VCANHdom+VCANLdom VCANHrec CANH voltage level in recessive state VCANLrec CANL voltage level in recessive state VDIFF,recOUT Differential output voltage in recessive state: VCANHrecVCANLrec VCANHL,CM Common mode bus voltage IOCANH,dom IOCANL,dom Min Typ Max Unit 2.75 - 4.5 V 0.5 - 2.25 V 1.5 - 3 V 1.1* 0.9* V VCANSUP CANSUP VCANSUP V 2 2.5 3 V 2 2.5 3 V -50 - 50 mV -12 - +12 V Active mode; CANH output current VTX_CAN = VTX_CANLOW; in dominant state VCANH = 0 V -100 -75 -45 mA Active mode; CANL output current VTX_CAN = VTX_CANLOW; in dominant state VCANL = 5 V 45 75 100 mA Input leakage current Unpowered device; VBUS = 5 V 0 - 250 µA Rin Internal resistance Active mode VTX_CAN = VTX_CANHIGH; No load 25 - 45 kΩ Rin,diff Differential internal resistance Active mode & STBY mode; VTX_CAN = VTX_CANHIGH; No load 50 - 85 kΩ Cin Internal capacitance Guaranteed by design - 20 - pF Cin,diff Differential internal capacitance Guaranteed by design - 10 - pF VTHdom Differential receiver threshold voltage recessive to dominant state Active mode - - 0.9 V CAN_H CAN_L ILeakage VTX_CAN = VTX_CANHIGH; No load Application info: Measured with respect to the ground of each CAN node DocID027452 Rev 5 97/170 169 Functional description L9779WD Table 42. CAN transceiver electrical characteristics (continued) Pin CAN_H CAN_L Symbol Description Test conditions Min Typ Max Unit 0.5 - - V VTHrec Differential receiver threshold voltage dominant to recessive state Active mode SRH CANH slew rate between 10% and 90% - 5 - 35 V/µs SRL CANL slew rate between 10% and 90% - 5 - 35 V/µs DIFF_SR Slew rate difference between CANH and CANL - - - 60 % SRVDIFF Slew rate of Vdiff = VCANH-VCANL - 12 - 100 V/µs VTHdom - VTHrec hysteresis - 25 - 50 mV VTHhys Table 43. CAN transceiver timing characteristics Symbol tTXpd,hl tTXpd,lh tdom(TX_CAN) tCAN 98/170 Description Propagation delay TX_CAN to RX_CAN (High to Low) Propagation delay TX_CAN to RX_CAN (Low to High) Test conditions Min Typ Max Unit Active mode; 50% VTX_CAN to 50% VRX_CAN; CL=100 pF; CRX_CAN = 15 pF; RL = 60 Ω; Guaranteed by design. 0 - 255 ns CRX_CAN = 100 pF @Troom and Tcold - - 265 ns CRX_CAN = 100 pF @Thot - - 275 ns Active mode; 50% VTX_CAN to 50% VRX_CAN; CL = 100 pF; CRX_CAN = 15 pF; RL = 60 Ω; Guaranteed by design. 0 - 255 ns CRX_CAN = 100 pF @Troom and Tcold - - 265 ns CRX_CAN = 100 pF @Thot - - 275 ns TX_CAN dominant time-out Tested by scan 525 700 875 µs CAN permanent dominant time-out Tested by scan - 700 - µs DocID027452 Rev 5 L9779WD Functional description Figure 60. CAN transceiver switching waveforms 6 T48PDHL 6 #!.?48   6 T48PDLH 6  6 #!.?28  6 '!0'03 Figure 61. CAN transceiver test circuit #!.?48 6#!.( #!.( #!. : 42!.3#%)6%2 P& : #!.?28 #!., N& 6#!., P& '!0'03 DocID027452 Rev 5 99/170 169 Functional description 6.16 L9779WD Flying wheel interface function Figure 62. Flying wheel interface circuit 6230 %N?, &CK?623 6DD )REF 2ELUCTANCE6ARIABLE (ALLEFFECT 3ENSOR 0ASSIVE &ILTER 623. 3-!24 623 /54?623 3ERIALINTERFACE $IAGNOSIS PROGRAMMING 623VOLTAGE !UTOADAPTATIVE )NT?VRS (YSTERESIS !UTOADAPTATIVE 4IMEFILTERINGBLOCK /UT?VRS '!0'03 6.16.1 Flying wheel interface functionality description The flying wheel interface is an interface between the microprocessor and the flying wheel sensor: it handles signals coming from magnetic pick-up sensor or Hall Effect sensor and feeds the digital signal to Microcontroller that extracts flying wheel rotational position, angular speed and acceleration. This circuit implements an auto adaptative hysteresis and filter time algorithm that can be configured via MSC using VRS_mode bit. If the auto adaptive hysteresis is OFF the hysteresis value can be selected using VRS_Hyst bit. If fault is present (OL / SC GND / SC VB) the functionality is not guaranteed. 100/170 DocID027452 Rev 5 L9779WD 6.16.2 Functional description Auto-adaptative sensor filter Two main VRS configuration sets are available for VRS, by means of CONFIG_REG1 register bit 1: fully adaptive VRS mode and limited adaptive VRS mode (default: 0). For VRS configurations in both limited and fully adaptive mode, CONFIG_REG5 is used. Auto-adaptative hysteresis (fully adaptive mode) When enabled the auto adaptative hysteresis works as described below. Input signals difference is obtained through a full differential amplifier; its output, DV signal, is fed to peak detection circuit and then to A/D converter implemented with 4 voltage comparators (5 levels) (Pvi). Output of A/D is sent to Logic block (Table 45: Hysteresis threshold precision) that implements correlation function between Peak voltage and hysteresis value; hysteresis value is used by square filtering circuit which conditions DV signal. Figure 63. Auto adaptative hysteresis diagram #HANGESLOW SIDEDRIVERCOMMAND #HANGESLOW SIDEDRIVERCOMMAND /54!" /54#$ \)LOAD\ /PENLOAD/. &AULT(APPENS !NDITISVALIDATED !FTER4DC?OL?ON &!5,4 $%4%#4)/. 25..).' ,!4#(%$ ,ATCHED/PEN ,OAD/N&AULT )?/0%.?,/!$ 4DGC?OL?ON $)!'./3)3 ./&!5,4 &!5,4$%4%#4)/.25..).' /0%.,/!$ /.,!4#(%$ '!0'03 DocID027452 Rev 5 101/170 169 Functional description L9779WD Figure 64. VRS interface block diagram .RKP 9563 6:,7&+  .RKP 6(1625 99 &/$03 9&0 ',$* .RKP $GDSWLYH)LOWHU  ILOWHUWLPHRQULVLQJHGJHDQG PDVNLQJWLPHRQIDOOLQJHGJH  ILOWHU WLPHRQERWKULVLQJDQGIDOOLQJHGJH $GDSWLYH)LOWHU &203  .RKP 9561 9 6SLELWV   )$8/7 PX[ 6SLELWV   99 3HDN 'HWHFWRU 7KUHVKROG 6HOHFWRU &XUUHQW *HQHUDWRU 'HFRGHU '!0'03 Table 44. Pick voltage detector precision Pick voltage [PV] Min Typ Max Unit PV1 600 930 1300 mV PV2 1200 1600 1950 mV PV3 1990 2300 2660 mV PV4 2600 3000 3380 mV Table 45. Hysteresis threshold precision Value Hysteresis current [H] Note: 102/170 Unit Correspondent value on 20 kΩ ext. resistor Unit Min Typ Max Typ HI1 3 5 7 µA 100 mV HI2 7 10 13.5 µA 200 mV HI3 12.8 17 23 µA 347 mV HI4 23 32 41 µA 644 mV HI5 35 51 65 µA 1020 mV For a single IC, there is no overlap of parameters PVX (PV1 7 and sequencer-run RST_CNT new 000 .. 111 no = RST_CNT old ‘0’, no monitoring module reset 000 .. 110 yes = RST_CNT old + 1 ‘1’, thus monitoring module reset 111 yes = RST_CNT old =111 ‘0’, no monitoring module reset WD_RST In a factory test-mode the pin [WDA] is always active '0'; the internal signal is not changed by the factory test-modes. DocID027452 Rev 5 115/170 169 Functional description Note: L9779WD There is no impact on internal power stages from active pin [WDA] in factory test-mode. Table 52. Reset-behaviour of , AB1 and Signal Reset source Reset state WDA_INT RST_UV ‘1‘, i.e. pin WDA is active AB1 RST_UV ‘0‘, i.e. inactive WD_RST RST_UV ‘0‘, i.e. inactive Response comparison The 2-bit counter counts the received bytes of the 32-bit response and controls the generation of the expected response. Its default value is "11" (corresponds to "waiting for RESP_BYTE3"). The flag is set '1' when a response byte is incorrect. The flag remains '0' if the 32-bit response is correct. The ERROR COUNTER is updated with the flag. The default state of the flag is '0'. The 2-bit counter and the flag are reset to their corresponding default values at a sequencer-run. The reset condition of the counter and the flag are the corresponding default states. Procedure of the sequential response comparison: = "11": switch the expected response for RESP_BYTE3 to the comparator Write access: RESP_BYTE3 Set to "10", update flag = "10": switch the expected response for RESP_BYTE2 to the comparator Write access: RESP_BYTE2 set to "01", update flag = "01": switch the expected response for RESP_BYTE1 to the comparator Write access: RESP_BYTE1 set to "00", update flag = "00": switch the expected response for RESP_BYTE0 to the comparator Write access: RESP_BYTE0 Start sequencer (SEQU_START signal), set to "11", update flag (update ERROR COUNTER) Sequencer clears flag to '0 SEQU_START = 116/170 (RESP_CNT1) AND RESP_CNT0) AND “response byte write” DocID027452 Rev 5 L9779WD Functional description Expected Responses: RESP_SOLL7 = REQU2 XOR RESP_CNT0 RESP_SOLL6 = REQU0 XOR RESP_CNT0 RESP_SOLL5 = REQU3 XOR RESP_CNT0 RESP_SOLL4 = REQU1 XOR RESP_CNT0 RESP_SOLL3 = ((REQU2 XOR REQU0) XOR REQU3) XOR RESP_CNT1 RESP_SOLL2 = ((REQU0 XOR REQU3) XOR REQU1) XOR RESP_CNT1 RESP_SOLL1 = ((REQU2 XOR REQU0) XOR REQU1) XOR RESP_CNT1 RESP_SOLL0 = (RESP_CNT1 XOR REQU3) XOR REQU0 Table 53. Expected responses question REQU (3-0) RESP_BYTE3 RESP_BYTE2 RESP_BYTE1 RESP_BYTE0 0 FF 0F F0 00 1 B0 40 BF 4F 2 E9 19 E6 16 3 A6 56 A9 59 4 75 85 7A 8A 5 3A CA 35 C5 6 63 93 6C 9C 7 2C DC 23 D3 8 D2 22 DD 2D 9 9D 6D 92 62 A C4 34 CB 3B B 8B 7B 84 74 C 58 A8 57 A7 D 17 E7 18 E8 E 4E BE 41 B1 F 01 F1 0E FE Reset behaviour All monitoring module registers are reset by RST_UV The following monitoring module components are also reset by RST_PRL: Table 54. Reset behaviour Component: Reset Condition: ERROR COUNTER 110b Register for “EC>7” ‚0‘ DocID027452 Rev 5 117/170 169 Functional description L9779WD Table 54. Reset behaviour (continued) Component: Reset Condition: Register RESPTIME Maximum value: 0011 1111b timer state Note: “000...00” The signal RST_PRL (partial reset) is active when RST_UV or SW_RST (Soft reset) is active (straight by RST pin. It could be filtered by THOLD after the falling edge of the RST and filtered by the crank event). Access during a sequencer-run A sequencer-run (which means the same as a monitoring cycle) is initiated by the writing of a response (i.e. all answer bytes ) or a write to or by reaching "end of time window". It must not be interrupted by a new access, i.e. the monitoring module completes the action already started:  A sequencer-run was initiated by a "response write": The sequencer completes its task with the data of the previous access and the new data are ignored.  A sequencer-run was initiated by a "response-time write": The sequencer uses the response-time of the previous access, the error counter is correspondingly incremented by one and the bit (REQUHI register) is set and the new data are ignored. will be reset by reading and by the next start of a sequencer run (not reset by the sequencer run that is started by a "response-time write"!)  A sequencer-run was initiated by "end of time window": The sequencer finishes the started run, the error counter is incremented by one and the new data are ignored. The writing of a response-time during a sequencer-run must not set the bit (REQUHI register). The new response-time value is also not accepted. The writing of a response during a sequencer-run must not set the bit, the new response is also not accepted. Clock and time references The monitoring module must work independently of the micro-controller clock so that it can monitor the timing of the micro-controller. Therefore, a separate oscillator is necessary. This oscillator is integrated in the L9779 and provides a clock CLK1 for the monitoring module. Clocked with CLK1, a divider generates the base time of 101*1/f_clk = 101 * 1/64 kHz = 1.58 ms for the response-time and 8 * 101*1/64kHz =8* 1.58 ms = 12.6 ms for the fixed time window. Accuracy of CLK1 is ±5% (or better). The response-time is adjustable by the controller in the range 0ms to about 100ms (register RESPTIME). The response-time can be calculated with the equation responsetime = (1+101*RESPTIME)*1/f_clk (where f_CLK depends on CONFIG6 bit1 value: if High default- f_clk = 64 kHz, if Low f_clk = 39 kHz). The RESPTIME register is set to '0011 1111'b after a reset. The ERROR COUNTER is incremented by one if the controller changes the response-time. If the response-time is set to 0ms, then the ERROR COUNTER is incremented by one even if a correct response is received within the time window. The maximum error reaction time is given by: maximum response-time, response at the end of a time-window and ERROR COUNTER 0 ' 5 * (100 ms + 12.6 ms) = 563 ms. Note that clock-tolerances have to be taken into account additionally. 118/170 DocID027452 Rev 5 L9779WD Functional description Watchdog influence on power up/down management unit The watchdog AB1 counter is increased every time the watchdog error counter is EC > 7, which means it has an overflow. If the AB1 counter reaches the value of 7 and a further error occurs, the system will be switched off same as it would happen in case of the already existing PWL_EN_TIMEOUTN signal. Watchdog influence on smart power reset WDA has influence on the RST pin only if the WDA error counter is EC > 7 and the resulting reset signal "WD_RST" is enabled by MSC configuration bit "INIT_WDR" in WR_RESPTIME command. Watchdog influence on Lsa functions (Section 6.9.1) For LSa functions OUT1, OUT2, OUT3, OUT4 (not OUT5). In case of an internal WDA event (e.g. the WDA error counter is EC > 4 which results in the signal WDA_INT being set) or in case of the WDA pin being pulled low externally, the output stages OUT1, OUT2, OUT3, OUT4 go to inactive state. Watchdog influence on LSd functions OUT13, OUT14 (starter relay drivers) Section 6.9.4 In case of an internal WDA event (e.g. the WDA error counter is EC > 4 which results in the signal WDA_INT being set) or in case of the WDA pin being pulled low externally, the OUT13 and OUT14 stages go to inactive state after the time delay THOLD if the WDA event is still active. In the case WDA event has switched off OUT13/OUT14 once, Thold becomes 0ms on the next WDA event, unless OUT13/OUT14 are switched off/on or device has been reset. Moreover, if WDA pin is Low and kept Low at power up, OUT13/OUT14 can be switched on by the external micro, even though WDA EC ≥ 4. That is to allow external micro to control the system especially in the case of WDA pin stuck-low. WDA status pin can be checked by bit 3 of DIA3_REG. See also Section 6.2.2. Watchdog influence on Ignition drivers IGN1, IGN2, IGN3, IGN4 In case of an internal WDA event (e.g. the WDA error counter is EC > 4 which results in the signal WDA_INT being set) or in case of the WDA pin is pulled low externally, the output stages go to inactive state. Watchdog influence on CAN transceiver The WDA has influence on the CAN if the MSC configuration bit CAN_TDI is set. Once the CAN_TDI bit is set, in case of an internal WDA event (e.g. the WDA error counter is EC > 4 which results in the signal WDA_INT being set) or in case of the WDA pin is pulled low externally, the CAN goes to receive-only mode (Rx Only). DocID027452 Rev 5 119/170 169 Functional description 6.17.3 L9779WD Watchdog related MSC commands RD_DATA8 (read WDA registers) Table 55. RD_DATA8 Data frame CSB C(5..0) CD(7..0) RD_DATA8 1 101110 XXXXXXXX CSB: command selection bit - always '1' C(5...0): command bits CD(7...0): command data bits Reads data block 8 consists of the registers WDA_RESPTIME, REQULO, REQUHI, RST_AB1_CNT. The command has no relevant data as command data bits - they may be set to '1' or '0'. WR_RESP Table 56. WR_RESP Data frame CSB C(5..0) CD(7..0) WR_RESP 1 100100 RESP(7...0) CSB: command selection bit - always '1' C(5...0): command bits CD(7...0): command data bits Writes RESP(7...0) - the answer of the µC to the monitoring module question of the U-Chip to the U-Chip-internal logic of the monitoring module. WR_RESPTIME Table 57. WR_RESPTIME Data frame CSB C(5..0) CD(7..0) WR_RESPTIME 1 110000 INIT_WDR, CAN_TDI, RESPTIME(5...0), CSB: command selection bit - always '1' C(5...0): command bits CD(7...0): command data bits Writes RESPTIME(5...0) to the register RESPTIME of the monitoring module. The command has CD(5...0) = RESPTIME(5...0) as command data bits; the command data bits CD7 and CD6 configure INIT_WDR (enable WDA reset) and CAN_TDI (disable CAN in case of WDA event). 120/170 DocID027452 Rev 5 L9779WD 6.17.4 Functional description Watchdog related MSC registers MSC registers REQULO, REQUHI, RST_AB1_CNT, RESPTIME are defined as here below: WDA is configured via MSC by writing MSC_RESPTIME register (WR_RESPTIME command), which is read by RD_DATA7 in upstream. WDA_RESPTIME is a read_only register, which is written by MSC_RESPTIME, that is to allow proper internal re-synchronization. MSC_RESPTIME bits 5 down through to 0 are automatically replicated into WDA_RESPTIME bit 5 down through to 0 respectively with less than 200 ns latency. This register is read by RD_DATA8 in upstream. MSC_RESPTIME (upstream data block 7, read command: RD_DATA7) MSC_RESPTIME MSC RESPONSE TIME 7 6 5 4 3 2 1 0 INIT_WDR CAN_TDI RESPTIME5 RESPTIME4 RESPTIME3 RESPTIME2 RESPTIME1 RESPTIME0 RW Address: - Type: RW Reset: 0000 0000b (reset source: Bit 7-0: RST, RST_PRL) [7] INIT_WDR: ‚1': monitoring module reset enabled ‚0': monitoring module reset disabled locked by command LOCK [6] CAN_TDI: '1': disable transmission if WDA_INT active locked by command LOCK [5-0] RESPTIME (5-0): Response-time = (1+ 101*RESPTIME(5-0)) * 1/f_clk with f_clk = 64 kHz if CONFIG6 bit 1 is High, else f_clk=39kHz The error counter is incremented by one on a controller write access to this register! not locked by command LOCK may be written by the command WR_RESPTIME DocID027452 Rev 5 121/170 169 Functional description L9779WD WDA_RESPTIME (upstream data block 8, read command: RD_DATA8) WDA_RESPTIME WDA RESPONSE TIME 7 6 5 4 3 2 1 0 0 0 RESPTIME5 RESPTIME4 RESPTIME3 RESPTIME2 RESPTIME1 RESPTIME0 R Address: - Type: R Reset: 0011 1111 (reset source RST_PRL) Reset: [7] 0 [6] 0 [5-0] effective WDA RESPTIME (after first WR_RESPTIME command till reset WDA_RESPTIME[5:0]==MSC_RESPTIME[5:0]) REQULO (upstream data block 8, read command: RD_DATA8) REQULO REQUEST LO 7 6 5 4 WDA_INT ERR_CNT2 ERR_CNT1 ERR_CNT0 3 2 1 0 REQU3 REQU2 REQU1 REQU0 R Address: - Type: R Reset: 1110 0000b (reset source: Bit 6-4: RST_UV, RST_PRL; Bit 7, 3-0: RST_UV) [7] WDA_INT: '1': ERROR COUNTER > 4 [6-4] ERR_CNT (2-0): value of the ERROR COUNTER [3-0] REQU (3-0): 4-bit question 122/170 DocID027452 Rev 5 L9779WD Functional description REQUHI (upstream data block8, read command: RD_DATA8) REQUHI 7 RESP_CNT1 REQUEST HI 6 RESP_CNT0 5 RESP_ERR 4 3 RESP_Z0 CHRT 2 W_RESP 1 0 NO_RESP RESP_TO_EAR LY R Address: - Type: R Reset: 1100 0000b (reset source: RST_UV, Bit 4 additionally RST_PRL) [7-6] RESP_CNT(1-0): Counter for receiving the 4 response bytes [5] RESP_ERR: '1': 1 byte of the 32-bit response is incorrect (1) [4] RESP_Z0: '1': Controller set response-time to 0ms; a correct response within the time window nevertheless increments the error counter by one '0': Response-time is greater than 0ms [3] CHRT: '1': Controller has changed response-time; reset to zero after a read access and after the next sequencer run [2] W_RESP: '1': in case of incorrect response in value; reset to zero at sequencer-run (1) [1] NO_RESP: '1': in case of no response at all; timer is restarted automatically; reset to zero after a read access [0] RESP_TO_EARLY: '1': Response before time window was opened; reset to zero at sequencer-run (1) 1. Sequencer-run: A sequencer-run is initiated by the writing of a complete response (RESP_BYTE3…RESP_BYTE0) or by writing of a response-time or by reaching the end of a time window. In case WDA reference time base (1/f_clk) has to be changed to f_clk = 39 kHz, CONFIG6 bit1 has to be written to 0 before sequencer-run is started. RESP_TO_EARLY = '1': monitoring module has received a response before beginning of the time window and therefore this was rejected. Reception of a response means "end of reception of RESP_BYTE0" after the other response bytes (i.e. RESP_BYTE3, RESP_BYTE2, RESP_BYTE1 - in this order!) have been received. NO_RESP = '1': monitoring module has received no response at all or a response too late after the time window already closed. However, a response too late might be read as RESP_TO_EARLY, as too late a response is at the same time too early a response concerning the next WDG cycle. This results in the NO_RESP monitoring being overwritten by a RESP_TO_EARLY monitoring. This means that no "end of reception of RESP_BYTE0" was detected before the end of the time window - neither during the time window nor before beginning of the time window. (Remember: RESP_BYTE0 is the last of four response bytes!) DocID027452 Rev 5 123/170 169 Functional description L9779WD W_RESP = '1': an error occurred during the sequencer run before. RESP_ERR = '1': an error occurred during the actual sequencer run. The bit will be set to '1' after receiving any incorrect answer byte and will remain '1' until the end of the actual sequencer run (no matter if the other answer bytes in this sequencer run are correct or not). At the end of a sequencer run the error bit W_RESP will be set to the actual value of RESP_ERR, and thereafter the error bit RESP_ERR will be cleared to '0'. RESP_CNT = '11': waiting for RESP_BYTE3 RESP_CNT = '10': waiting for RESP_BYTE2 (after RESP_BYTE3 was received) RESP_CNT = '01': waiting for RESP_BYTE1 (after RESP_BYTE2 was received) RESP_CNT = '00': waiting for RESP_BYTE0 (after RESP_BYTE1 was received) RST_AB1_CNT (upstream data block 8, read command: RD_DATA8) RST_AB1_CNT AB1 COUNTER 7 6 5 4 0 0 AB1_CNT2 AB1_CNT1 3 2 1 0 AB1_CNT0 RST_CNT2 RST_CNT1 RST_CNT0 R Address: - Type: R Reset: xx00 0000b (reset source: Bit 6…0: only RST_UV; RST_PRL has no effect) [7] 0 [6] 0 [5-3] REQU (3-0): AB1_CNT (2-0) [2-0] RST_CNT (2-0) reset counter RST_CNT 124/170 DocID027452 Rev 5 L9779WD 6.17.5 Functional description MicroSecond Channel activity watchdog MSC data frames are monitored to be sent in intervals shorter than tMSC_mon. If L9779WD receives no valid data frame for longer than tMSC_mon, it will switch off all the drivers and the error flag (TRANS_F) and OUT_DIS will be set. The MRD and OUT13, 14, 21 and 25 (if low battery function is enabled) are not disabled by missing activity on MSC. No reset request is sent to the smart reset function module. To enable the outputs again, the µC has to read the TRANS_F and then send the command START, and then outputs are reactivated with the first correct data frame. If the fault flag is not cleared the START command is ignored. By default the MicroSecond Channel activity watch dog is enabled and the monitoring time will start after writing of the OUT_DIS bit by START command. Each time the L9779WD receives a valid data frame the tMSC_on timer is reset. This means that micro controller can drive the outputs only when the monitoring module is active. To disable the MicroSecond Channel activity watch dog the µC have to set to 0 the bit MSC_ACT_EN. If the MSC frame has a wrong number of bit the flag TRANS_L is set but no action on outputs is taken. The frame with wrong length is ignored. Table 58. MicroSecond Channel activity watchdog Symbol Min Typ Max Unit tMSC_mon 100 142 185 µs -30% 0.9*t2WD +30% ms -30% 0.8*t2WD +30% -30% 0.7*t2WD +30% - 0 - 14 20 26 35 50 65 59 70 91 70 100 130 t1WD t2WD DocID027452 Rev 5 - ms 125/170 169 126/170 DocID027452 Rev 5  75$16B/   75$16B)  287[  287B',6ELW  06&DFWLYLW\ —&ZULWHV&21752/UHJEHIRUHWKHWLPHUUHDFKHVW06&B021 2872)) 1R0RQLWRU —&ZULWHV &21752/ UHJ 28721 IROORZLQJ &21752/UHJ —&VHQGV —&ZULWHV 67$57 &21752/ FRPPDQG UHJ 28721 IROORZLQJ &21752/UHJ XV —&GRHVQRWZULWH&21752/UHJEHIRUHWKHWLPHUUHDFKHVW06&B021 —&ZULWHV &21752/ UHJ —&UHDGV ',$*UHJ 2873872)) 83675($0 1R0RQLWRU —&VHQGV 67$57 FRPPDQG X&VHQGV 67$57 FRPPDQG —&ZULWHV &21752/ UHJ 28721 IROORZLQJ &21752/UHJ —&ZULWHV &21752/ UHJ± :521* %,7 180%(5 —&ZULWHV &21752/ UHJ 28721 IROORZLQJ &21752/UHJ XV —&ZULWHV &21752/ UHJ± :521* %,7 180%(5 —&ZULWHV &21752/ UHJ± :521* %,7 180%(5 287387 2)) Functional description L9779WD Figure 76. MicroSecond Channel activity watch dog diagram '!0'03 L9779WD 6.18 Functional description Serial interface The L9779WD offers the possibility to communicate with a µC using the MicroSecond Channel (MSC). The serial communication is used: 6.18.1  to set the parameter  to read diagnosis  to activate, to deactivate and to use the low side drivers  to activate test mode (ST reserved). MSC interface Communication with the microcontroller is done via MSC i.e.MicroSecond Channel; equivalent to µsec-bus 2nd generation. Downstream communication is data or command sent by µC and received by L9779WD. Upstream communication is data sent by the L9779WD and received by µC. The MicroSecond Channel (MSC) interface provides a serial communication link typically used to connect peripheral devices with a micro controller. The serial communication link is built up by a fast synchronous downstream channel (with differential inputs and differential clock) and a slow synchronous upstream channel. Differential inputs for downstream data are pins [DIP] and [DIN]; the differential input signal [DIP]-[DIN] is referred to as DI. The clock pins are [CLP] and [CLN], the differential clock [CLP]-[CLN] is referred to as CL. There is an internal resistor between pins [DIP] and [DIN] and between [CLP] and [CLN]. There is one input for chip select at pin [EN], and one output for upstream data at pin [DO]. L9779WD always is the slave in this communication link. These pins are single-ended. Multiple power devices with MSC on downstream are possible. Downstream device is selected by EN. MSC uses normal polarity for DI, CLK, and DO: a logic '1' is a 'high level' and a logic '0' is a 'low level'. MSC uses inverted polarity for EN: a logic '1' is a 'low level' and a logic '0' is a 'high level'. By this way it is possible to drive multiple power devices with shared CL and DI lines and individual EN signal. The maximum downstream clock rate is CL = 40MHz. Upstream is done with a lower clock rate fSDO, selectable by the microcontroller; after a reset the upstream clock rate is fSDO = CL/64. The upstream clock is synchronous with CL since it is derived from a clock divider. Therefore the CL signal must always be running independently whether a downstream transmission is running or not. DocID027452 Rev 5 127/170 169 Functional description L9779WD Figure 77. Communication diagram between µC and L9779WD , —# %. #,0 #,. $)0 $OWNSTREAM $IVIDER $). 5PSTREAM $/ '!0'03 Downstream communication Signals The enable input is active with inverted polarity - i.e.‚ low level during the active phases of command or data frames. An active enable signal validates the DI input signal. Outside the active phase (enable line is at high level) invalid data may occur at DI. The active phase of a downstream frame starts with the falling edge of the enable signal and ends with the rising edge of the enable signal. The enable signal changes its state with the rising edge of the clock CL (because CL has normal polarity). DI changes its state on rising edge and it is latched by L9779WD on the falling edge of CL. Downstream frames are synchronous serial frames. They support enable signal and command/data selection bit as part of the frame. Command/data selection bit allows distinguishing frames as command and data frames in the receiver circuit. Command frames and data frames may be sent in any sequence with a passive phase of at least 2 CL-cycles after each frame. Command frame A command frame always starts with a high level bit (command selection bit). The number of the command bit of the active phase of a command frame NCB is fixed to 14. If the number of the command bit is not equal to NCB = 14 the frame will be ignored, the command will not be executed and the error flag (TRANS_L) will be set. The length of the command frame's passive phase tCPP must be a minimum of 2 * tCL. Execution of the command is finished not later than 16*tCL after the end of active phase. 128/170 DocID027452 Rev 5 L9779WD Functional description Figure 78. Command frame diagram #OMMANDFRAME 0ASSIVE PHASE !CTIVEPHASE 3HIFT 3AMPLE T&#, T#00  #LOCK #,+ $ATA $) )NVALID )NVALID #OMMANDBITS ENABLE %. 0ASSIVE !CTIVE #OMMANDSELECTIONBIT  .#"NUMBEROFACTIVEPHASECOMMANDBITS  T#00LENGTHOFDATAFRAMEPASSIVEPHASE '!0'03 Table 59. Content of a command frame (transmitted LSB first) Bit 0 Description =’1’: command selection bit 1-6 Command LSB first! 7-14 Data for the command LSB first! Data frame A data frame always starts with a low level bit (data selection bit). The number of the data bit of the active phase of a data frame NDB is fixed to 30. If the number of the data bit is not equal to NDB = 30 the frame will be ignored and the error flag (TRANS_L) will be set. The length of the data frame's passive phase tDPP must be a minimum of 2 * tCL. Execution of the data frame is finished not later than 16*tCL after the end of active phase. DocID027452 Rev 5 129/170 169 Functional description L9779WD Figure 79. Data frame diagram $ATAFRAME 0ASSIVE PHASE !CTIVEPHASE 3HIFT 3AMPLE T&#, T$00 #LOCK #,+ $ATA $) )NVALID $ATABITS  ENABLE %. )NVALID !CTIVE 0ASSIVE $ATASELECTIONBIT  .$"NUMBEROFACTIVEPHASEDATABITS  T$00LENGTHOFDATAFRAMEPASSIVEPHASE '!0'03 Table 60. Content of a data frame (transmitted LSB first) Bit Data selection bit Description 0 0-7 CONTR_REG1(LSB…MSB) 8-15 CONTR_REG2(LSB…MSB) 16-23 CONTR_REG3(LSB…MSB) 24-29 CONTR_REG4(LSB…MSB) Upstream communication The serial data output [DO] is the synchronous serial data signal of the upstream channel. The polarity for [DO] is ‚normal polarity'- i.e. a low level bit at [DO] is stored in the µC as a logic ‚0', and a high level bit at [DO] is stored in the µC as a logic ‚1'. The serial data output is single-ended. The frequency is derived from CL by an internal divider to typ. fSDO = CL/64. It can be adjusted via MSC to fSDO = CL/16... CL/128. The time for a bit is TSDO = fSDO. Each upstream frame consists of 16 bit: Note: 130/170  1 start bit, always '0'  4-bit-upstream address field (A[0..3] with LSB first)  8 bit data upstream data field (D[0..7] with LSB first)  1 upstream parity bit (with odd parity for the complete data frame)  2 fSDO stop bit, always '1'. External pull-up resistor on SDO pin is required. Its value depends on MSC SDO bit rate. DocID027452 Rev 5 L9779WD Functional description The commands that perform a read access to the L9779WD-data always initiate 4 registers to be sent by the L9779 to the µC. Within the execution of these read commands an upstream data frame is sent after the 2 stop bits of the prior upstream data frame and one additional inter-frame bit waiting time. If a new read command is received while the 4 registers up-stream communication is active, the 16 bit up-stream on-going is completed and after the inter-frame bit it is sent the new 4 register up-stream sequence requested. With the beginning of the upstream frame the latched flags contained in the register are cleared automatically. The time from the read command to the first upstream frame of the answer is less than 100µs. The end of the upstream frame is after 17 x 4 tUSC. Outside the upstream frame the DO output is high impedance. Figure 80. Upstream communication diagram BITUPSTREAMDATAF RAME BITADDRESS F IELD 3TART BIT ! ! ,3" BITDATAFIELD ! -3" ! $ ,3" $ $ $ $ $ $ $ 0ARITY -3" BIT 3TOP BIT 3TOP BIT T53# )NTERF RAME BIT UPSTREAMDATAFRAME $ $ $ 0ARITY -3" BIT 3TOP BIT .EXTUPSTREAMDATAFRAME 3TOP BIT @ 3TART BIT ! ,3" ! ! '!0'03 Timing characteristics Figure 81. Timing diagram T&#, #LOCK #,+ TSETUP THOLD TSWITCH T%.SETUP $ATA $) ENABLE %. T%.HOLD !CTIVEPHASE 0ASSIVEPHASE !CTIVEPHASE T3$/DELAY $/ '!0'03 DocID027452 Rev 5 131/170 169 Functional description L9779WD Table 61. Timing characteristics Symbol Min. Typ. Max. Unit Cycle time 25 - - ns tsetup Data setup time 5 - - ns thold Data hold time 5 - - ns tswitch Switching time Switching time for CL, EN and SI measured between 0.1*VVDD3 and 0.9*VVDD3 - - 3 ns tCLlow CL low time 10 - - ns tCLhigh CL high time 10 - - ns tENsetup (1) EN setup time (i.e. time between falling edge of EN and next falling edge of CL) 5 - - ns tENhold (1) EN hold time (i.e. time between falling edge of CL and next rising edge of EN) 5 - - ns tSDO /tCL data out cycle time CL_CONF1=’1’,CL_CONF0=’1’ CL_CONF1=’1’,CL_CONF0=’0’ CL_CONF1=’0’,CL_CONF0=’1’ CL_CONF1=’0’,CL_CONF0=’0’ +25% - tCL fCL - Parameter 128 64 32 16 -25% Clock range at CL L9779WD is fully functional incl. all timings as long as there is a clock at pins CLP, CLN: CL - - 40 MHz tSDOdelay - - 160 ns 1. Enable setup time and enable hold time are validated with characterization. Figure 82. Time circuit $RIVER , ) CONST TYP M!  $) 0$) . #,0#,.  : TYP M6 RECEIVER  '!0'03 132/170 DocID027452 Rev 5 L9779WD Functional description Figure 83. Cycle time diagram #,0$) 0 6 6 6 #,.$) . 6 6 6 #,#,0 #,. $) $) 0 $) . M6  M6 M6 M6  '!0'03 Table 62. Time electrical characteristics Pin CLP, CLN Symbol Parameter Test condition VCLP, VCLN Input voltage range VCLdiff Differential input voltage VCLdiff =|VCLP-VCLN| VCLdiff Input voltage offset VCLdiff =0.5*(VCLP+VCLN) Rcl Not to be tested. It is an application note. EXTERNAL Resistor between CLP and CLN Min Typ Max Unit 0.8 - 1.6 V 150 - 450 mV 1 - 1.4 V - 100 -  Rpu_N Internal pull-up resistor - 100 200 400 k Rpd_P Internal pull-down resistor - 100 200 400 k 100 mV Differential input high detection VCL_high level VCL_high= VCLP_high - VCLN_high DocID027452 Rev 5 133/170 169 Functional description L9779WD Table 62. Time electrical characteristics (continued) Pin Symbol CLP, CLN VCL_low Test condition Differential input low detection level VCL_low= VCLP_low- VCLN_low VDIP, VDIN Input voltage range VDIdiff Differential input voltage VDIdiff =|VDIP-VDIN| VDIdiff Input voltage offset VDIdiff =0.5*(VCLP+VCLN) Rcl DIP, DIN Parameter EN Typ Max Unit -100 - - mV 0.8 - 1.6 V 150 - 450 mV 1 - 1.4 V - 100 - Ω Rpu_N Internal pull-up resistor - 100 200 400 kΩ Rpd_P Internal pull-down resistor - 100 200 400 kΩ - - - 100 mV -100 - - mV - - 0.5 V VDD_IO -0.5 - - V VDI_low Differential input low detection level VDI_low= VDIP_low- VDIN_low - VDO_L DO output low level VDD_IO = 5 V or 3.3 V Isink current = 2 mA VDO_H DO output high level VSUP = 5 V or 3.3 V Isource current=2mA fDO Maximum frequency Tested by SCAN fCL/ 128 fCL/ 64 fCL/ 16 MHz ENL Low input level - -0.3 - 1.1 V ENH High input level - 2.3 - VDD 5+0.3 V Hysteresis - 0.1 - - V Input current - - - 5 µA Pull-up resistor - 50 - 250 kΩ VHYST IIN RPU 134/170 Not to be tested. It is an application note. Resistor between DIP and DIN Differential input high detection VDI_high level VDI_high= VDIP_high- VDIN_high DO - Min DocID027452 Rev 5 L9779WD Functional description 6.18.2 Commands MSC-commands are encoded with 6 bits with a Hamming distance at least of 2. Table 63. Commands # Command Command bit MSB ... LSB Description 1 RD_DATA1 000011 Read CONFIG_REG1…4 (Upstream Block 1) 2 RD_DATA2 000101 Read CONFIG_REG5, 6, 7 (Upstream Block 2) 3 RD_DATA3 000110 Read DIA_REG1...4 (Upstream Block 3) 4 RD_DATA4 001001 Read DIA_REG5...8 (Upstream Block 4) 5 RD_DATA5 001010 Read DIA_REG9…11, IDENT_REG (Upstream Block 5) 6 RD_DATA6 001100 Read WDA_QUERY, 00h, STEP_CNT (Upstream Block 6) 7 WR_CONFIG1 001111 Write CONFIG_REG1 8 WR_CONFIG2 010001 Write CONFIG_REG2 9 WR_CONFIG3 010010 Write CONFIG_REG3 10 WR_CONFIG4 010100 Write CONFIG_REG4 11 WR_CONFIG5 010111 Write CONFIG_REG5 12 WR_CONFIG6 011000 Write CONFIG_REG6 13 WR_CONFIG7 011011 Write CONFIG_REG7 14 LOCK 011101 Disable writing of all configuration bit 15 UNLOCK 011110 Enable writing of all configuration bit 16 SW_RST 100001 Software reset 17 START 100010 Enable power stages 18 RD_SINGLE 101000 Read one byte at a time on each access (see addresses table) 19 STOP 101011 Disable power stage 20 RD_DATA7 101101 Read DIA_REG12, DIA_REG12, RESP, MSC_RESPTIME (Upstream block 7) 21 RD_DATA8 101110 Read WDA_RESPTIME, REQULO, REQUHI, RST_AB1_CNT 22 WR_RESP 100100 Write RESP register 23 WR_RESPTIME 110000 Write RESPTIME register 24 WR_CPS 110011 Write CPS parallel configuration (if CPS mode enabled) 25 MRD_REACT 100111 Main relay reactivation after OVC switch off DocID027452 Rev 5 135/170 169 Functional description Note: L9779WD Pay attention to the fact that the LSB is always transmitted first. RD_DATA1, 2, 3, 4, 5, 6, 7 and 8 Table 64. RD_DATA1, 2, 3, 4, 5, 6, 7 and 8 Command CSB C(5..0) CD(7..0) RD_DATA1 1 000011 XXXXXXXX RD_DATA2 1 000101 XXXXXXXX RD_DATA3 1 000110 XXXXXXXX RD_DATA4 1 001001 XXXXXXXX RD_DATA5 1 001010 XXXXXXXX RD_DATA6 1 001100 XXXXXXXX RD_DATA7 1 101101 XXXXXXXX RD_DATA8 1 101110 XXXXXXXX CSB : command selection bit - always '1' C(5...0) : command bit CD(7...0): command data bit READ_DATA1 initiates 4 upstream communications that transfer data block 1 that consists of the registers CONFIG_REG1, CONFIG_REG2, CONFIG_REG3 and CONFIG_REG4, transmitted exactly in this order. READ_DATA2 initiates 4 upstream communications that transfer data block 2 that consists of the registers CONFIG_REG5, CONFIG_REG6, CONFIG_REG7, not used, transmitted exactly in this order. READ_DATA3 initiates 4 upstream communications that transfer data block 3 that consists of the registers DIA_REG1, DIA_REG2, DIA_REG3 and DIA_REG4, transmitted exactly in this order. READ_DATA4 initiates 4 upstream communications that transfer data block 4 that consists of the registers DIA_REG5, DIA_REG6, DIA_REG7 and DIA_REG8, transmitted exactly in this order. READ_DATA5 initiates 4 upstream communications that transfer data block 5 that consists of the registers DIA_REG9, DIA_REG10, DIA_REG11 and IDENT_REG, transmitted exactly in this order. READ_DATA6 initiates 4 upstream communications that transfer data block 6 that consists of the registers WDA_QUERY, not used, STEP_CTN_H and STEP_CTN_L. READ_DATA7 initiates 4 upstream communications that transfer data block 7 that consists of the registers DIA_REG12, DIA_REG12, RESP, and WDA_RESPTIME. READ_DAT8 initiates 4 upstream communications that transfer data block 7 that consists of the registers WDA_RESPTIME, REQULO, REQUHI, RST_AB1_CNT. The command has no relevant data as command data bit - they may be set to '1' or '0'. 136/170 DocID027452 Rev 5 L9779WD Functional description If a new read command is received while the current 4 up-stream communication is active, the 16 bit up-stream on-going is completed and after the inter-frame bit it is sent the new 4 register up-stream sequence requested. WR_CONFIG1, 2, 3, 4, 5, 6, 7, WR_RESP, WR_RESPTIME Table 65. WR_CONFIG1, 2, 3, 4, 5, 6, 7, WR_RESP, WR_RESPTIME Command CSB C(5..0) CD(7..0) WR_CONFIG1 1 001111 CONFIG1(7:0) WR_CONFIG2 1 010001 CONFIG2(7:0) WR_CONFIG3 1 010010 CONFIG3(7:0) WR_CONFIG4 1 010100 CONFIG4(7:0) WR_CONFIG5 1 010111 CONFIG5(7:0) WR_CONFIG6 1 011000 CONFIG6(7:0) WR_CONFIG7 1 011011 CONFIG7(7:0) WR_RESP 1 100100 RESP WR_RESPTIME 1 110000 WDA_RESPTIME WR_CPS 1 110011 CPS CSB : command selection bit - always '1' C(5...0) : command bit CD(7...0): command data bit Writes the register CONFIG_REG1, 2, 3, 4, 5, 6, 7 Lock, unlock Table 66. Lock, unlock Command CSB C(5..0) CD(7..0) Lock 1 011101 XXXXXXXX Unlock 1 011110 XXXXXXXX CSB : command selection bit - always '1' C(5...0) : command bit CD(7...0): command data bit This command disables ("lock") writing of all configuration registers. The commands have no relevant data as command data bit - they may be set to '1' or '0'. The registers RESP and RESPTIME are not affected by LOCK command (i.e. they cannot be locked) Default state is configuration registers not locked. The content of a lockable bit is valid both if the bit is locked or if it is unlocked. Writing data to the bit is possible if the bit is unlocked; the new values become valid during execution of the write command. DocID027452 Rev 5 137/170 169 Functional description L9779WD SW_RST Table 67. SW_RST Command CSB C(5..0) CD(7..0) SW_RST 1 100001 XXXXXXXX CSB : command selection bit - always '1' C(5...0) : command bit CD(7...0): command data bit With CD(7..0) = X X X X X X X X This command generates a L9779WD internal reset initiated by the µC's software ("software reset") that clears all the configuration and diagnostic registers and switches-off all the drivers. The command has no relevant data as command data bit - they may be set to '1' or '0'. Start, Stop Table 68. Start, Stop Command CSB C(5..0) CD(7..0) Start 1 100010 XXXXXXXX Stop 1 101011 XXXXXXXX CSB : command selection bit - always '1' C(5...0) : command bit CD(7...0): command data bit The command START sets the bit to '0'. With = '0' the outputs [OUT1...OUT9] [OUT13…OUT28] and [IGN1...IGN4] can be activated using control registers. After a reset (default state) the bit is ='1' and the outputs are disabled (so any MSC data frame writing control registers is ignored and the power stages are all switched off). The command STOP sets the bit to '1' disabling the outputs. These commands have no relevant data as command data bit - they may be set to '1' or '0'. 138/170 DocID027452 Rev 5 L9779WD Functional description MRD_REACT Table 69. MRD_REACT Command CSB C(5..0) CD(7..0) MRD_REACT 1 100111 XXXXXXXX CSB : command selection bit - always '1' C(5...0) : command bit CD(7...0): command data bit This command allows to the uC to turn on the MRD if it was switched off due to over current. RD_SINGLE Table 70. RD_SINGLE Command CSB C(5..0) CD(7..0) RD_SINGLE 1 101000 0 0 CD(5..0) CSB : command selection bit - always '1' C(5...0) : command bit CD(7...0): command data bit to select the register to be read. NB: CD(7..6) must be 0. This command allows to read one register at a time. The register to be read is specified through the command data field and is encoded with a Hamming distance at least of 2 according to the following table: Table 71. Register through the command data field # CD(5:0) Register Description 1 000011 R CONFIG_REG1 MRD_OT_DIS, OUT8 short to VB filter time and threshold 2 000101 R CONFIG_REG2 LS_IGN_OFF, OUT9 short to VB filter time and threshold 3 000110 R CONFIG_REG3 VRS edge and feedback position selection 4 001001 R CONFIG_REG4 lock status/slew-rate/upstream clock ratio/off state diagnosis/power latch mode config 5 001010 R CONFIG_REG5 VRS config/MSC monitoring status/OUT21-28 config 6 001100 R CONFIG_REG6 PSOFF/power latch mode enable flag/reset generation flag/can error enable flag 7 001111 R CONFIG_REG7 low battery setting status to OUT 13,14,24,25/TD mask type/IGN diagnosis type 8 111001 R CONFIG_REG8 WDA RESP 9 111010 R CONFIG_REG9 RESPTIME 10 111100 R CONFIG_REG10 CPS CONF 11 010001 R DIA_REG1 diagnosis bit of OUT 1,2,3,4 DocID027452 Rev 5 139/170 169 Functional description L9779WD Table 71. Register through the command data field (continued) # CD(5:0) Register Description 12 010010 R DIA_REG2 diagnosis bit of OUT 5,6,7,8 13 010100 R DIA_REG3 diagnosis bit of OUT 9,10,13,14 14 010111 R DIA_REG4 diagnosis bit of OUT 15,16,17,18 15 011000 R DIA_REG5 diagnosis bit of OUT 19,20 16 011011 R DIA_REG6 diagnosis bit of OUT 21,22,23,24 17 011101 R DIA_REG7 diagnosis bit of OUT 25,26,27,28 18 011110 R DIA_REG8 diagnosis bit of IGN 1,2,3,4 19 100001 R DIA_REG9 VTRK diag bit/VRS diag bit/MRD status /KEY_ON_STATUS (not filtered) 20 100010 R DIA_REG10 OV_RST/OUT_DIS/V3V3_UV/general diag in OUT 2128/CRK_RST/ general diag in OUT 1-10,13-20,IGN 14/TNL_RST 21 100100 R DIA_REG11 MSC error flag/CAN error flag/VDD reset flag/ over temperature flag 22 100111 ZERO_REG 23 101000 R STP_CNT_H stepper counts high 24 101011 R STP_CNT_L stepper counts low 25 101110 R IDENT_REG chip id, revision information 26 101101 R DIA_REG12 Key on status filtered 27 110000 RESPTIME WDA Response Time 28 110011 REQULO WDA request low byte 29 110101 REQUHI WDA request high byte 30 110110 RST_AB1_CNT Returns all zeros WDA AB1 counter In case of RD_SINGLE command the upstream consists of 16 bits as described in Figure 80. The association between the registers and the "4 bit address field" is the following: Table 72. Association between the registers and the "4 bit address field # 140/170 Register Content of “4 bit address field” in the upstream 1 CONFIG_REG1 0000 2 CONFIG_REG2 0100 3 CONFIG_REG3 1000 4 CONFIG_REG4 1100 5 CONFIG_REG5 0000 6 CONFIG_REG6 0100 7 CONFIG_REG7 1000 DocID027452 Rev 5 L9779WD Functional description Table 72. Association between the registers and the "4 bit address field (continued) # Register Content of “4 bit address field” in the upstream 8 RESP (CONFIG_REG8) 1100 9 RESPTIME (CONFIG_REG9) 0000 10 CPS (CONFIG_REG10) 0100 11 DIA_REG1 0001 12 DIA_REG 2 0101 13 DIA_REG 3 1001 14 DIA_REG 4 1101 15 DIA_REG 5 0010 16 DIA_REG 6 0110 17 DIA_REG 7 1010 18 DIA_REG 8 1110 19 DIA_REG 9 0011 20 DIA_REG 10 0111 21 DIA_REG 11 1011 22 ZERO_REG 0100 23 STEP_H 1000 24 STEP_L 1100 25 R IDENT_REG 0000 26 DIA_REG 12 0000 27 RESPTIME 0001 28 REQULO 0101 29 REQUHI 1001 30 RST_AB1_CNT 1101 DocID027452 Rev 5 141/170 169 Functional description 6.18.3 L9779WD Registers (Upstream blocks) Table 73. Registers Register Address Description Written by Read by Upstream read block 1 CONFIG_REG1 0000b Configuration register 1 WR_CONFIG1 RD_DATA1 CONFIG_REG2 0100b Configuration register 2 WR_CONFIG2 RD_DATA1 CONFIG_REG3 1000b Configuration register 3 WR_CONFIG3 RD_DATA1 CONFIG_REG4 1100b Configuration register 4 WR_CONFIG4 RD_DATA1 CONFIG_REG5 0000b Configuration register 5 WR_CONFIG5 RD_DATA2 CONFIG_REG6 0100b Configuration register 6 WR_CONFIG6 RD_DATA2 CONFIG_REG7 1000b Configuration register 7 WR_CONFIG7 RD_DATA2 0x0000 1100b - - RD_DATA2 DIA_REG1 0001b Diagnostic register1 - RD_DATA3 DIA_REG2 0101b Diagnostic register2 - RD_DATA3 DIA_REG3 1001b Diagnostic register3 - RD_DATA3 DIA_REG4 1101b Diagnostic register4 - RD_DATA3 DIA_REG5 0010b Diagnostic register5 - RD_DATA4 DIA_REG6 0110b Diagnostic register6 - RD_DATA4 DIA_REG7 1010b Diagnostic register7 - RD_DATA4 DIA_REG8 1110b Diagnostic register8 - RD_DATA4 DIA_REG9 0011b Diagnostic register9 - RD_DATA5 DIA_REG10 0111b Diagnostic register10 - RD_DATA5 DIA_REG11 1011b Diagnostic register11 - RD_DATA5 IDENT_REG 1111b Identifier - RD_DATA5 WD_QUERY 0000b WDA Query - RD_DATA6 0x0000 0100b Not used - RD_DATA6 STEP_CNT_H 1000b - - RD_DATA6 STEP_CNT_L 1100b - - RD_DATA6 Upstream read block 2 Upstream read block 3 Upstream read block 4 Upstream read block 5 Upstream read block 6 142/170 DocID027452 Rev 5 L9779WD Functional description Table 73. Registers (continued) Register Address Description Written by Read by Upstream read block 7 DIA_REG12 0000b Diagnostic register 12 - RD_DATA7 DIA_REG12 0100b Diagnostic register 12 - RD_DATA7 RESP 1000b Response to WDA register - RD_DATA7 RESPTIME 1100b MSC RESPTIME register - RD_DATA7 RESPTIME 0001b - - RD_DATA8 REQULO 0101b - - RD_DATA8 REQUHI 1001b - - RD_DATA8 AB1_COUNTER 1101b - - RD_DATA8 CONTR_REG1 - Data frame --- CONTR_REG2 - Data frame --- CONTR_REG3 - Data frame --- CONTR_REG4 - Data frame --- Upstream read block 8 Command for OUTn, IGNn See Control Registers CONTR_REG1 to 4 STEP_CNT_H STEPPER COUNTER HIGH 7 6 5 LINEUP2 LINEUP1 RESERVED 4 3 2 1 0 CNT[9:5] R Address: 1000b Type: R Reset: 0000 0000 [7] LINEUP2: used to assure the alignment of high and low part of the counter [6] LINEUP1: used to assure the alignment of high and low part of the counter [5] RESERVED: not used [4:0] CNT[9:5]: high part of steps count DocID027452 Rev 5 143/170 169 Functional description L9779WD STEP_CNT_L STEPPER COUNTER LOW 7 6 5 LINEUP2 LINEUP1 RESERVED 4 3 2 1 0 CNT[4:0] R Address: 1100b Type: R Reset: 0000 0000 [7] LINEUP2: used to assure the alignment of high and low part of the counter [6] LINEUP1: used to assure the alignment of high and low part of the counter [5] RESERVED: not used [4:0] CNT[4:0]: low part of steps count IDENT_REG 7 Identity register 6 5 4 3 IDENT[2:0] MCR[2:0] R Address: 1111b Type: R Reset: 0000_0000 [7:5] IDENT[2:0]: chip identifier 000: L9779WD 001 010 011 [4:2] MCR[2:0]: chip revision corresponding to: metal change 000: AA version 001: AB version 010: AC version 110: AD version [1:0] MSR[1:0]: chip revision corresponding to: full mask set 144/170 DocID027452 Rev 5 2 1 0 MSR[1:0] L9779WD Functional description Configuration register 1, 2, 3 CONFIG_REG1 7 Configuration register 1 6 5 4 F_TH_SEL_8[2:0] 3 2 F_TM_SEL_8[2:0] R/W Address: 0000b Type: R/W (write access: WRITE_CONFIG1) Reset: 0000 1000 1 0 VRS mode MRD_OT_DID R/W R/W [7:5] F_TH_SEL_8: OUT8 short fault to VB threshold voltage selection. 000: 0.55 V (default) 001: 1 V 010: 1.5 V 011: 2 V 100: 2.5 V 101: 0.172 V 110: 0.3 V 111: 0.45 V [4:2] F_TM_SEL_8: OUT8 short fault to VB filter time selection. 000: 1.3 µs 001: 2.6 µs 010: 5.2 µs (default) 011: 10 µs 100: 21 µs 101: 42 µs 110: 84 µs 111: 170 µs [1] VRS mode: 0 = limited adaptive (default) 1 = full adaptive [0] MRD_OT_DIS: disables OT switch_off for MRD: 0 = MRD OT switches off the driver 1 = MRD OT does NOT switch off the driver DocID027452 Rev 5 145/170 169 Functional description L9779WD CONFIG_REG2 7 6 Configuration register 2 5 4 F_TH_SEL_9[2:0] 3 2 F_TM_SEL_9[2:0] 1 0 Charge pump OFF LS_IGN_OFF R R/W R/W Address: 0100b Type: R/W (write access: WRITE_CONFIG2) Reset: 0000 1000 [7:5] F_TH_SEL_9[2:0]: OUT9 short fault to VB threshold voltage selection. 000: 0.55 V (default) 001: 1 V 010: 1.5 V 011: 2 V 100: 2.5 V 101: 0.150 V 110: 0.3 V 111: 0.45 V [4:2] F_TM_SEL_9[2:0]: OUT9 short fault to VB filter time selection. 000: 1.3 µs 001: 2.6 µs 010: 5.2 µs (default) 011: 10 µs 100: 21 µs 101: 42 µs 110: 84 µs 111: 170 µs [1] Charge pump OFF 0= ON (default) 1= OFF [0] LS_IGN_OFF Control LS stage of IGN driver 0 = normal behaviour 1 = LS of IGN driver always OFF 146/170 DocID027452 Rev 5 L9779WD Functional description CONFIG_REG3 7 6 Configuration register 3 5 4 3 2 RESERVED 1 0 EN_FALLING_FILT HYS_FB_SEL R/W Address: 1000b Type: R/W (write access: WRITE_CONFIG3) Reset: 0000 1000 [7:2] RESERVED: not used [1] EN_FALLING_FILT: 0 = Falling edge filter disabled 1 = Falling edge filter enabled [0] HYS_FB_SEL: 0 = VRS hyst. Feedback connected before adaptative filter 1 = VRS hyst. Feedback connected after adaptative filter DocID027452 Rev 5 147/170 169 Functional description L9779WD CONFIG_REG4 7 6 PWL_TIMEOUT_CONF[2:0] Configuration register 4 5 4 3 OFF_LCDR 2 FDO_SEL[1:0] 1 0 ISO_SRC LOCK R/W Address: 1100b Type: R/W (write access: WRITE_CONFIG4) Reset: 0000_0010 [7:5] PWL_TIMEOUT_CONF[2:0]: Power latch mode time-out configuration. 000: Disabled (default) 001: 4.7 minutes ±5% 010: 9 minutes ±5% 011: 19 minutes ±5% 100: 28 minutes ±5% 101: 37 minutes ±5% 110: 75 minutes ±5% 111: 470 ms ±5% [4] OFF_LCDR: Off state diagnosis for Low-current drive 1 = Off state diagnosis and the bias current of OUT19, OUT20 is active 0 = Off state diagnosis and the bias current of OUT19, OUT20 is disabled [3:2] F_DO_SEL[1:0]: Upstream clock ratio selection. 00: fDO= fCL/ 64(default) 01: fDO= fCL/ 16 10: fDO= fCL/ 32 11: fDO= fCL/ 128 [1] ISO_SRC: Slew-rate control for the ISO9141 serial interface (K-Line) 0 = No slew rate limitation 1 = Slew-rate limitation active [0] LOCK: Lock bit status. Set by LOCK command and cleared with UNLOCK command 1 = ALL configuration registers are locked and cannot be changed 0 = all configuration registers can be changed 148/170 DocID027452 Rev 5 L9779WD Functional description CONFIG_REG5 7 RESERVED Configuration register 5 6 5 4 3 2 1 0 MSC_ACT_EN VRS_DIAG/ MIN_HYST VRS_MODE1 VRS_MODE0 VRS_HYST2 VRS_HYST1 VRS_HYST0 R/W Address: 0000b Type: R/W (write access: WRITE_CONFIG5) Reset: - Note: 1101_1000 [7] RESERVED: not used [6] MSC_ACT_EN: MSC activity monitoring enable 1: MSC activity monitoring function is enabled 0: MSC activity monitoring function is disabled [5] If fully adaptive mode selected: VRS diag: VRS diagnosis enable 1: diagnosis function is enabled 0: diagnosis function is disabled If limited adaptive mode selected: Forces VRS minimum hysteresis (5 µA) 1: minimum hysteresis forced 0: normal operation as per VRS_HYST configuration [4:3] VRS_MODE 00: internal auto-adaptive filter time OFF, Internal auto-adaptive hysteresis OFF 01: internal auto-adaptive filter time OFF, Internal auto-adaptive hysteresis ON 10: Iinternal auto-adaptive filter time ON, Internal auto-adaptive hysteresis OFF 11: internal auto-adaptive filter time ON, Internal auto-adaptive hysteresis ON [2:0] VRS_HYST 000: Hys current = 17 µA (Hys VRS = 347 mV with 10 k ext resistors) [default] 001: Hys current = 5 µA (Hys VRS=100mV with 10 k ext resistors) 010: Hys current = 10 µA (Hys VRS=200mV with 10 k ext resistors) 011: Hys current = 17 µA (Hys VRS=347mV with 10 k ext resistors) 100: Hys current = 32 µA (Hys VRS=644mV with 10 k ext resistors) 101: Hys current = 51 µA (Hys VRS=967mV with 10 k ext resistors) 110: Hys current = 17 µA (Hys VRS=347mV with 10 k ext resistors) 111: Hys current = 0 µA (used only for test purpose) Note: When VRS limited amplitude adaptive mode is set, VRS_HYST limits the minimum hysteresis to the set value. When VRS limited mode is set, filter time must be enabled at operation start, and shall never be disabled afterwards. When VRS limited mode is set, VRS diagnostic function is not available. DocID027452 Rev 5 149/170 169 Functional description L9779WD CONFIG_REG6 Configuration register 6 7 6 5 4 3 2 1 0 CAN_ERR_EN NL_RST PWL_EN_N/ SEO_EN_N PSOFF VDD5_UV mask VDD5 under voltage on SDO WDA time base setting (RESPTIME) PWL/SEO timeout R/W Address: 0100b Type: R/W (write access: WRITE_CONFIG6) Reset: 0010 0010 [7] CAN_ERR_EN: CAN error handling 1: CAN error handling enabled 0: CAN error handling disabled [6] NL_RST: Reset generation during Power latch mode when KEY_ON 0 --> 1 1: reset generated 0: reset not generated [5] PWL_EN_N: Power latch mode enable PWL_EN_N/SEO_EN_N: Power latch/secure engine off mode enable 1: power latch mode function is disabled (default) 0: power latch mode function is enabled [4] PSOFF: Power supply off (VDD5, VTRK1, VTRK2, Charge-pump, internal supply) when KEY_ON = 0 and PWL_EN_N = 1 0: switch off power supply and switch off MRD 1: do not switch off power supply and switch off MRD [3] VDD5_UV mask 1: mask VDD5_UV 0: mask removed (default) Note: if VDD5_UV is masked, OUTx are not automatically switched off. [2] VDD5 under voltage on SDO 1: VDD5 under voltage event forces SDO to constantly send Low logic values whenever SDO output is enabled, till VDD5 under voltage monitor remains active 0: this function disabled (default) Note: as SDO gets stuck to Low upon VDD5_UV event, before any further readings, it is recommended that this function is disabled. [1] WDA time base setting This bit selects the RESPTIME time base 1: (default) sets time base to 1/64 kHz 0: sets time base to 1/39 kHz [0] PWL/SEO timeout 0: PWL timeout counter has priority over SEO (default) 1: SEO timeout counter has priority over PW Note: if this bit is set, bit4 and bit5 of same register have no effects 150/170 DocID027452 Rev 5 L9779WD Functional description Table 74. CONFIG_REG6 power off source TIMEOUT (REG4 bit7..5) WATCHDOG Power off source Reg6bit0 1 0 1 1 X (X) 0 0 X (X) 0 1 X (X) KEY OFF Reg6bit5 SEO (OUT1…4 OUT13/ OUT14) X Description Direct switch-off at KEY_ON=0(default) Switch-off in case of Watch-dog error X X Switch-off at expiration of PWL timer SEO enabled for OUT1-4, OUT13,14 X Switch-off in case of Watchdog error SEO enabled for OUT1-4, OUT13,14 DocID027452 Rev 5 151/170 169 Functional description L9779WD CONFIG_REG7 7 Configuration register 7 6 IGN_DIA_MODE IGN_DIA_SGEN 5 4 TD_MASK_X2 RESERVED 3 2 1 0 OUT25_EN_LB OUT21_EN_LB OUT14_EN_LB OUT13_EN_LB R/W Address: 1000b Type: R/W (write access: WRITE_CONFIG7) Reset: 0101 0000 [7] IGN_DIA_MODE: IGN diagnosis mode for short to battery: 1: latch mode 0: no latch mode [6] IGN_DIA_SGEN: IGN diagnosis enable for short to ground: 1: Current diagnosis enabled 0: Voltage diagnosis enabled [5] TD_MASK_X2: 0: Td_mask as specified in respective tables for OUT13 to OUT28 1: Td_mask doubled for OUT13 to OUT28 [4] RESERVED: not used [3] OUT25_EN_LB: Low battery function enable 1: LB function is enabled for OUT25 0: LB function is disabled for OUT25 [2] OUT21_EN_LB: Low battery function enable 1: LB function is enabled for OUT21 0: LB function is disabled for OUT21 [1] OUT14_EN_LB: Low battery function enable 1: LB function is enabled for OUT14 0: LB function is disabled for OUT14 [0] OUT13_EN_LB: Low battery function enable 1: LB function is enabled for OUT13 0: LB function is disabled for OUT13 Note: The bit OUT21,25_EN_LB has priority over the CPS_CONFx bit, this means that if one of OUT21,25_EN_LB is set to 1 the OUT21…28 become independent power stages. 152/170 DocID027452 Rev 5 L9779WD Functional description CONFIG_REG10 (CPS Configuration register) 7 6 5 4 Configuration register 10 3 2 1 0 see Table 39 and 40 CPS_CONF - Address: - Type: WR_CPS Reset: 0000 0001 [7:1] See Table 39 and 40 [0] CPS_CONF 1: OUT21...OUT28 are configured as 2 full-bridge for stepper motor driving (default) 0: OUT21...OUT24 are configured as single power stages DIA_REG[1:5] Diagnostic register 1, 2, 3, 4, 5 7 DIA_REG1 6 5 OUT4_DIAG 4 DIA_REG2 OUT8_DIAG OUT7_DIAG DIA_REG3 OUT14_DIAG OUT13_DIAG DIA_REG4 OUT18_DIAG DIA_REG5 3 OUT3_DIAG OUT6_DIAG WDA_STATUS OUT17_DIAG RESERVED Address: 0001b, 0101b, 1001b, 1101b, 0010b Type: R (Read only) 2 OUT2_DIAG RESERVED 1 0 OUT1_DIAG OUT5_DIAG OUT9_DIAG OUT16_DIAG OUT15_DIAG OUT20_DIAG OUT19_DIAG Reset: DIA_REG1:[7:6] OUT4_DIAG: Diagnosis bit of power stage OUT4 00: Short-circuit to ground (SCG) 01: Open load (OL) 10: Short-circuit to BAT (SCB) 11: Power stage OK NO FAIL DIA_REG1:[5:4] OUT3_DIAG: Diagnosis bit of power stage OUT3 00: Short-circuit to ground (SCG) 01: Open load (OL) 10: Short-circuit to BAT (SCB) 11: Power stage OK NO FAIL DIA_REG1:[3:2] OUT2_DIAG: Diagnosis bit of power stage OUT2 00: Short-circuit to ground (SCG) 01: Open load (OL) 10: Short-circuit to BAT (SCB) 11: Power stage OK NO FAIL DocID027452 Rev 5 153/170 169 Functional description L9779WD DIA_REG1:[1:0] OUT1_DIAG: Diagnosis bit of power stage OUT1 00: Short-circuit to ground (SCG) 01: Open load (OL) 10: Short-circuit to BAT (SCB) 11: Power stage OK NO FAIL DIA_REG2:[7:6] OUT8_DIAG: Diagnosis bit of power stage OUT8 00: Short-circuit to ground (SCG) 01: Open load (OL) 10: Short-circuit to BAT (SCB) 11: Power stage OK NO FAIL DIA_REG2:[5:4] OUT7_DIAG: Diagnosis bit of power stage OUT7 00: Short-circuit to ground (SCG) 01: Open load (OL) 10: Short-circuit to BAT (SCB) 11: Power stage OK NO FAIL DIA_REG2:[3:2] OUT6_DIAG: Diagnosis bit of power stage OUT6 00: Short-circuit to ground (SCG) 01: Open load (OL) 10: Short-circuit to BAT (SCB) 11: Power stage OK NO FAIL DIA_REG2:[1:0] OUT5_DIAG: Diagnosis bit of power stage OUT5 00: Short-circuit to ground (SCG) 01: Open load (OL) 10: Short-circuit to BAT (SCB) 11: Power stage OK NO FAIL DIA_REG3:[7:6] OUT14_DIAG: Diagnosis bit of power stage OUT14 00: Short-circuit to ground (SCG) 01: Open load (OL) 10: Short-circuit to BAT (SCB) 11: Power stage OK NO FAIL DIA_REG3:[5:4] OUT13_DIAG: Diagnosis bit of power stage OUT13 00: Short-circuit to ground (SCG) 01: Open load (OL) 10: Short-circuit to BAT (SCB) 11: Power stage OK NO FAIL DIA_REG3:[3] ]WDA STATUS: status of WDA pin, not latched DIA_REG3:[2] RESERVED: not used DIA_REG3:[1:0] OUT9_DIAG: Diagnosis bit of power stage OUT9 00: Short-circuit to ground (SCG) 01: Open load (OL) 10: Short-circuit to BAT (SCB) 11: Power stage OK NO FAIL 154/170 DocID027452 Rev 5 L9779WD Functional description DIA_REG4:[7-6] OUT18_DIAG: Diagnosis bit of power stage OUT18 00: Short-circuit to ground (SCG) 01: Open load (OL) 10: Short-circuit to BAT (SCB) 11: Power stage OK NO FAIL DIA_REG4:[5-4] OUT17_DIAG: Diagnosis bit of power stage OUT17 00: Short-circuit to ground (SCG) 01: Open load (OL) 10: Short-circuit to BAT (SCB) 11: Power stage OK NO FAIL DIA_REG4:[3-2] OUT16_DIAG: Diagnosis bit of power stage OUT16 00: Short-circuit to ground (SCG) 01: Open load (OL) 10: Short-circuit to BAT (SCB) 11: Power stage OK NO FAIL DIA_REG4:[1-0] OUT15_DIAG: Diagnosis bit of power stage OUT15 00: Short-circuit to ground (SCG) 01: Open load (OL) 10: Short-circuit to BAT (SCB) 11: Power stage OK NO FAIL DIA_REG5:[7:4] RESERVED: All bit read 1 DIA_REG5:[3-2] OUT20_DIAG: Diagnosis bit of power stage OUT20 00: Short-circuit to ground (SCG) 01: Open load (OL) 10: Short-circuit to BAT (SCB) 11: Power stage OK NO FAIL DIA_REG5:[1-0] OUT19_DIAG: Diagnosis bit of power stage OUT19 00: Short-circuit to ground (SCG) 01: Open load (OL) 10: Short-circuit to BAT (SCB) 11: Power stage OK NO FAIL Note: All diagnosis bit (including OT1, F1, OT2, F2) will be cleared automatically by reading – i.e. if a diagnosis bits indicates a fault this fault has occurred after the last read access to this register. DocID027452 Rev 5 155/170 169 Functional description L9779WD Diagnostic register 6 and 7 DIA_REG6 Diagnostic register 6 7 Configured as single power stages 6 OUT24_DIAG 5 4 3 OUT23_DIAG Configured as H bridge OUT22_DIAG H1_DIAG Address: 0110b Type: R (Read only) Reset: Configured as single power stages [7-6] OUT24_diag[1:0]: Diagnosis bit of OUT24 00: Short-circuit to ground 01: Open load (OL) 10: Short-circuit to BAT (SCB) 11: Power stage OK NO FAIL [5-4] OUT23_diag[1:0]: Diagnosis bit of OUT23 00: Short-circuit to VB 01: Open load (OL) 10: Short-circuit to GND 11: Power stage OK NO FAIL [3-2] OUT22_diag[1:0]: Diagnosis bit of OUT22 00: Short-circuit to ground 01: Open load (OL) 10: Short-circuit to BAT (SCB) 11: Power stage OK NO FAIL [1-0] OUT21_diag[1:0]: Diagnosis bit of OUT21 00: Short-circuit to VB 01: Open load (OL) 10: Short-circuit to GND 11: Power stage OK NO FAIL Configured as H bridge [7-0] H1_diag[7:0]: Diagnosis bit of H1 bridge 00000001: Short to Ground (OFF) 00000101: Short to VBAT (OFF) 00000100: Open Load (OFF) 00000010: Open Load (ON) 00000011: Over current (ON) 00000111: Fault detection running (ON) 11111111: Power stages OK NO FAULT All other combinations: NOT USED 156/170 2 DocID027452 Rev 5 1 0 OUT21_DIAG L9779WD Functional description DIA_REG7 Diagnostic register 7 7 Configured as single power stages 6 OUT28_DIAG 5 4 3 OUT27_DIAG Configured as H bridge 2 OUT26_DIAG 1 0 OUT25_DIAG H2_DIAG Address: 1010b Type: R (Read only) Reset: Configured as single power stages [7-6] OUT28_DIAG[1:0]: Diagnosis bit of OUT28 00: Short-circuit to ground 01: Open load (OL) 10: Short-circuit to BAT (SCB) 11: Power stage OK NO FAIL [5-4] OUT27_DIAG[1:0]: Diagnosis bit of OUT27 00: Short-circuit to ground 01: Open load (OL) 10: Short-circuit to BAT (SCB) 11: Power stage OK NO FAIL [3-2] OUT26_DIAG[1:0]: Diagnosis bit of OUT26 00: Short-circuit to VB 01: Open load (OL) 10: Short-circuit to GND 11: Power stage OK NO FAIL [1-0] OUT25_DIAG[1:0]: Diagnosis bit of OUT25 00: Short-circuit to VB 01: Open load (OL) 10: Short-circuit to GND 11: Power stage OK NO FAIL Configured as H bridge [7-0] H2_diag[7:0]: Diagnosis bit of H2 bridge 00000001: Short to Ground (OFF) 00000101: Short to VBAT (OFF) 00000100: Open Load (OFF) 00000010: Open Load (ON) 00000011: Over current (ON) 00000111: Fault detection running (ON) 11111111: Power stages OK NO FAULT All other combinations: NOT USED DocID027452 Rev 5 157/170 169 Functional description L9779WD DIA_REG8 7 Diagnostic register 8 6 IGN4_DIAG[1:0] Address: 5 4 IGN3_DIAG[1:0] 3 2 IGN2_DIAG[1:0] 1110b Type: Reset: [7:6] IGN4_DIAG[1:0]: Diagnosis bit of IGN4 00: Short-circuit to ground (SCG) 01: Open load (OL) 10: Short-circuit to BAT (SCB) 11: Power stage ok NO FAIL [5:4] IGN3_DIAG[1:0]: Diagnosis bit of IGN3 00: Short-circuit to ground (SCG) 01: Open load (OL) 10: Short-circuit to BAT (SCB) 11: Power stage ok NO FAIL [3:2] IGN2_DIAG[1:0]: Diagnosis bit of IGN2 00: Short-circuit to ground (SCG) 01: Open load (OL) 10: Short-circuit to BAT (SCB) 11: Power stage ok NO FAIL [1:0] IGN1_DIAG[1:0]: Diagnosis bit of IGN1 00: Short-circuit to ground (SCG) 01: Open load (OL) 10: Short-circuit to BAT (SCB) 11: Power stage ok NO FAIL 158/170 DocID027452 Rev 5 1 0 IGN1_DIAG[1:0] L9779WD Functional description DIA_REG9 Diagnostic register 9 7 6 5 4 KEY_ON_ STATUS MRD_OVC VRS_STAT VRS_DIAG 3 2 VTRK2_DIAG[1:0] 1 0 VTRK1_DIAG[1:0] R/W Address: 0011b Type: Reset: [7] KEY_ON_STATUS 1: KEY_ON voltage above KEY_ON_H 0: KEY_ON voltage below KEY_ON_L [6] MRD_OVC 1: Current MRD status is OFF due to previous Over current 0: Current MRD status is ON (no OVC detected) [5] VRS_STAT 1: Diag ON 0: Diag OFF [4] VRS_DIAG 0: No Fault 1: Generic fault detected This function is only available if VRS is set to fully adaptive mode. When limited adaptive mode is set, VRS_DIAG always returns 0. [3-2] VTRK2_DIAG[1:0]: Diagnosis bit of VTRK2 00: Not used 01: Overload condition/out of regulation 10: Overvoltage (OV) or over temperature (OT) (Lower priority respect to Overload condition) 11: Sensor supply VTRK ok NO FAIL [1-0] VTRK1_DIAG[1:0]: Diagnosis bit of VTRK1 00: Not used 01: Overload condition/out of regulation 10: Overvoltage (OV) or over temperature (OT) (Lower priority respect to overload condition) 11: Sensor supply VTRK OK NO FAIL DocID027452 Rev 5 159/170 169 Functional description L9779WD DIA_REG10 Diagnostic register 10 7 6 5 4 3 2 1 0 TNL_RST F1 CRK_RST F2 VDD5_OV V3V3_UV OUT_DIS OV_RST Address: 0111b Type: Reset: [7] TNL_RST 0: No reset generated 1: Reset generated by TNL [6] F1 0: No fault 1: any fault occurred in OUT1...10, OUT13...20, IGN1…4 [5] CRK_RST 0: No reset generated 1: Reset generated by VDD_UV (tTHOLD) Note: if VDD5_UV is masked, the VDD5_UV event is anyhow latched. [2] CAN_ERROR 0: No fault 1: fault present (one of the 4 possible error on CAN) [1] TRANS_L 0: No fault 1: data frame length incorrect [0] TRANS_F 0: No fault 1= no data stream within time-out DocID027452 Rev 5 161/170 169 Functional description L9779WD 7 6 5 4 3 WDG_RST (latched) SEO OUT1-4 SEO OUT13-14 WDG_RST (latched) Diagnostic register 12 VDDIO_UNDERVOLTAGE DIA_REG12 Address: 2 1 RESERVED 0 KEY_ON_FLT 0000b Type: Reset: [7] VDDIO_UNDERVOLTAGE: It goes to 1, if VDDIO undervoltage longer than 225 ms [6] WDG_RST latched: 1: WDA has generated a RST event 0: no event [5] SEO event when the OUT1-4 are switched off after 225 ms [4] SEO event when the OUT13-14 after 600ms when KEY is OFF [3] WDG_RST not latched: 1: WDA has generated a RST event 0: no event [2:1] RESERVED: not used [0] KEY_ON_FLT: Key on after filter Note: the DIA_REG12 is read by READ_DATA 7 but reset by READ_DATA5. Bit4 and bit5 are usable when power-latch enable bit in CONF6 Bit 5 is set to 0. SEO Flags are set to 1 after delay if KEY_ON is low or if a WDA event occurs with CONF6 Bit 5 already set to 0. In the latter case the KEY_ON may be high but SEO bits are nevertheless set. 162/170 DocID027452 Rev 5 L9779WD Functional description Control registers CONTR1 to 4 Control registers are written with the data frame. (Remember: D1 is the second least bit of the data frame - the LSB D0 is the "data selection bit" with D0='0'. The bit D0 is the first bit received by the L9779WD on the downstream channel in a data frame!). They control the output stages OUT1…10, OUT13…20, OUT21…28 and IGNn. CMD = 1 OUTPUT ONCMD = 0 OUTPUT OFF CONTR_REG1 Control register 1 7 6 5 4 3 2 1 0 CMD_OUT1 CMD_OUT2 CMD_OUT3 CMD_OUT4 CMD_OUT5 CMD_OUT20 CMD_OUT8 CMD_OUT19 R/W Address: Type: Reset: Via DATA frame 0000 0000 (ALL outputs switched OFF) [7] CMD_OUT1 1: OUT1 - Power stage switched ON 0: OUT1 - Power stage switched OFF [6] CMD_OUT2 1: OUT2 - Power stage switched ON 0: OUT2 - Power stage switched OFF [5] CMD_OUT3 1: OUT3 - Power stage switched ON 0: OUT3 - Power stage switched OFF [4] CMD_OUT4 1: OUT4 - Power stage switched ON 0: OUT4 - Power stage switched OFF [3] CMD_OUT5 1: OUT5 - Power stage switched ON 0: OUT5 - Power stage switched OFF [2] CMD_OUT20 1: OUT20 - Power stage switched ON 0: OUT20 - Power stage switched OFF [1] CMD_OUT8 1: OUT8 - Power stage switched ON 0: OUT8 - Power stage switched OFF [0] CMD_OUT19 1: OUT19 - Power stage switched ON 0: OUT19 - Power stage switched OFF DocID027452 Rev 5 163/170 169 Functional description L9779WD CONTR_REG2 Control register 2 7 6 5 4 3 2 1 0 CMD_OUT15 CMD_OUT14 DON'T CARE CMD_OUT9 CMD_IGN1 CMD_IGN2 CMD_IGN3 CMD_IGN4 Address: Type: Via DATA frame Reset: 0000 0000 (ALL outputs switched OFF) [7] CMD_OUT15 1: OUT15 - Power stage switched ON 0: OUT15 - Power stage switched OFF [6] CMD_OUT14 1: OUT14 - Power stage switched ON 0: OUT14 - Power stage switched OFF [5] DON'T CARE [3] CMD_OUT9 1: OUT9 - Power stage switched ON 0: OUT9 - Power stage switched OFF [4] CMD_IGN1 1: IGN1 - Power stage switched ON 0: IGN1 - Power stage switched OFF [2] CMD_IGN2 1: IGN2 - Power stage switched ON 0: IGN2 - Power stage switched OFF [1] CMD_IGN3 1: IGN3 - Power stage switched ON 0: IGN3 - Power stage switched OFF [0] CMD_IGN4 1: IGN4 - Power stage switched ON 0: IGN4 - Power stage switched OFF 164/170 DocID027452 Rev 5 L9779WD Functional description CONTR_REG3 Control register 3 7 6 CPS_CONF = 0 CMD_OUT22 CPS_CONF = 1 DIR CMD_OUT21 ENABLE 5 4 3 2 1 0 CMD_OUT16 CMD_OUT13 CMD_OUT17 CMD_OUT18 CMD_OUT7 CMD_OUT6 Address: Type: Reset: Via DATA frame 0000 0000 (ALL outputs switched OFF) 0 CMD_OUT6 1: OUT6 - Power stage switched ON 0: OUT6 - Power stage switched OFF 1 CMD_OUT7 1: OUT7 - Power stage switched ON 0: OUT7 - Power stage switched OFF 2 CMD_OUT18 1: OUT18 - Power stage switched ON 0: OUT18 - Power stage switched OFF 3 CMD_OUT17 1: OUT17 - Power stage switched ON 0: OUT17 - Power stage switched OFF 4 CMD_OUT13 1: OUT13 - Power stage switched ON 0: OUT13 - Power stage switched OFF 5 CMD_OUT16 1: OUT16 - Power stage switched ON 0: OUT16 - Power stage switched OFF 6 CMD_OUT21 1: OUT21 - Power stage switched ON (High side driver) 0: OUT21 - Power stage switched OFF Note: If CPS_CONF=0 (single power stages configuration) ENABLE 0: stepper motor driver disabled 1: stepper motor driver enabled Note: If CPS_CONF=1(stepper motor driving configuration) 7 CMD_OUT22 1: OUT22 - Power stage switched ON Note: If CPS_CONF=0 (single power stages configuration) 0: OUT22 - Power stage switched OFF DIR 0: forward direction 1: backward direction Note: if CPS_CONF=1(stepper motor driving configuration) Note: The meaning of some CONTR_REG3 bit depends on the configuration of bit CPS_CONF of CONF_REG1. DocID027452 Rev 5 165/170 169 Functional description L9779WD CONTR_REG4 Control register 4 7 CPS_CONF = 0 CPS_CONF = 1 6 RESERVED 5 4 3 2 1 CMD_OUT28 CMD_OUT27 CMD_OUT26 CMD_OUT25 CMD_OUT24 0 CMD_OUT23 Address: Type: Reset: 0000 0000 (ALL outputs switched OFF) [6-7] RESERVED: NOT used [5] CMD_OUT28 1: OUT28 Power stage switched ON 0: OUT28 Power stage switched OFF [4] CMD_OUT27 1: OUT27 Power stage switched ON 0: OUT27 Power stage switched OFF [3] CMD_OUT26 1: OUT26 - Power stage switched ON (High side driver) 0: OUT26 - Power stage switched OFF [2] CMD_OUT25 1: OUT25 - Power stage switched ON (High side driver) 0: OUT25 - Power stage switched OFF [1] CMD_OUT24 1: OUT24 - Power stage switched ON 0: OUT24 - Power stage switched OFF [0] If CPS_CONF=0 (single power stages configuration) CMD_OUT23 1: OUT23 Power stage switched ON 0: OUT23 Power stage switched OFF if CPS_CONF=1(stepper motor driving configuration) PWM 1 0: no step change in the driving sequence 0 1: step change in the driving sequence (next step applied) Note: The meaning of some CONTR_REG4 bit depends on the configuration of bit CPS_CONF of CONF_REG1. 166/170 DocID027452 Rev 5 PWM L9779WD 7 Package information Package information In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK® packages, depending on their level of environmental compliance. ECOPACK® specifications, grade definitions and product status are available at: www.st.com. ECOPACK® is an ST trademark. HiQUAD-64 package information Figure 84. HiQUAD-64 package outline 1 F $ $ ( 1 $ E ) 0 $ % H ( %277209,(: % VOXJWRSYLHZ '  ( ( ( 7.1 *$8*(3/$1( F VOXJ ERWWRPVLGH $ 6 /  VHDWLQJSODQH  & &RSODQDULW\  (VOXJOHQJKW $ ' ' *$3*36 B)B0 DocID027452 Rev 5 167/170 169 Package information L9779WD Table 75. HiQUAD-64 package mechanical data Dimensions Ref Inches(1) Millimeters Min. Typ. Max. Min. Typ. Max. A - - 3.15 - - 0.1240 A1 0 - 0.25 0 - 0.0098 A2 2.50 - 2.90 0.0984 - 0.1142 A3 0 - 0.10 0 - 0.0039 b 0.22 - 0.38 0.0087 - 0.0150 c 0.23 - 0.32 0.0091 - 0.0126 (2) D 17.00 - 17.40 0.6693 - 0.6850 D1 13.90 14.00 14.10 0.5472 0.5512 0.5551 D2 2.65 2.80 2.95 0.1043 0.1102 0.1161 E 17.00 - 17.40 0.6693 - 0.6850 13.90 14.00 14.10 0.5472 0.5512 0.5551 E2 2.35 - 2.65 0.0925 - 0.1043 E3 9.30 9.50 9.70 0.3661 0.3740 0.3819 E4 13.30 13.50 13.70 0.5236 0.5315 0.5394 e - 0.65 - - 0.0256 - F - 0.12 - - 0.0047 - G - 0.10 - - 0.0039 - L 0.80 - 1.10 0.0315 - 0.0433 N - - 10° - - 10° s 0° - 7° 0° - 7° (1) E1 1. Values in inches are converted from mm and rounded to 4 decimal digits. 2. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.15mm (.006inc.). 168/170 DocID027452 Rev 5 L9779WD 8 Revision history Revision history ; Table 76. Document revision history Date Revision Changes 3-Feb-2015 1 Initial release. 19-Mar-2015 2 Removed reference to L9779WDM from document. Updated: Table 4: ESD protection on page 19; In Table 42: CAN transceiver electrical characteristics the values of the VCANHL,CM parameter. 08-Apr-2015 3 Modified on Table 34 page 84 for “Diagnostic high threshold” parameter the max. value in 3 V. 20-May-2015 4 Updated Table 63 on page 135 and Table 71 on page 139. 14-Sep-2015 5 Updated: Table 35 on page 87 and Table 36 on page 88. DocID027452 Rev 5 169/170 169 L9779WD IMPORTANT NOTICE – PLEASE READ CAREFULLY STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on ST products before placing orders. ST products are sold pursuant to ST’s terms and conditions of sale in place at the time of order acknowledgement. Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or the design of Purchasers’ products. No license, express or implied, to any intellectual property right is granted by ST herein. Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product. ST and the ST logo are trademarks of ST. All other product or service names are the property of their respective owners. Information in this document supersedes and replaces information previously supplied in any prior versions of this document. © 2015 STMicroelectronics – All rights reserved 170/170 DocID027452 Rev 5