L9822EPD

L 9822E OCTAL SERIAL SOLENOID DRIVER . . . . . . . . . ADVANCE DATA EIGHT LOW RDSon DMOS OUTPUTS (0.5Ω AT I O = 1A @ 25°C VCC = 5V± 5%) 8 BIT SERIAL INPUT DATA (SPI) 8 BIT SERIAL DIAGNOSTIC OUTPUT FOR OVERLOADAND OPENCIRCUIT CONDITIONS OUTPUT SHORT CIRCUIT PROTECTION CHIP ENABLESELECTFUNCTION (active low) INTERNAL 36V CLAMPING FOR EACH OUTPUT CASCADABLE WITH ANOTHER OCTAL DRIVER LOW QUIESCENT CURRENT (10mA MAX.) PACKAGE MULTIWATT15, PowerSO20 AND SO20L MULTIPOWER BCD TECHNOLOGY PowerSO20 SO20L (16+2+2) Multiwatt15 ORDERING NUMBERS: L9822E (Multiwatt15) L9822EPD (Power SO20) L9822ED (SO20L ) DESCRIPTION The L9822E is an octal low side solenoid driver rea lized in Multipower-BCD technology particularly suited for driving lamps, relays and solenoids in auBLOCK DIAGRAM tomotive environment. The DMOS outpts L9822E has a very low power consumption. Data is transmitted serially to the device using the Serial Peripheral Interface (SPI) protocol. The L9822E features the outputs status monitoring function. September 1994 This is advanced information on a new product now in development or undergoing evaluation. Details are subject to change without notice. 1/11 L9822E PIN CONNECTIONS (top view) GND SO VDD RESET OUT7 OUT6 OUT5 OUT4 N.C. GND 1 2 3 4 5 6 7 8 9 10 D94AT119 20 19 18 17 16 15 14 13 12 11 GND SI SCLK CE OUT0 OUT1 OUT2 OUT3 N.C. GND OUT6 OUT5 OUT4 N.C. GND GND N.C. OUT3 OUT2 OUT1 1 2 3 4 5 6 7 8 9 10 D94AT118 20 19 18 17 16 15 14 13 12 11 OUT7 RESET VDD SO GND GND SI SLCK CE OUT0 PowerSO20 SO20L Multiwatt15 ABSOLUTE MAXIMUM RATINGS Symbol VCC VO II DC Logic Supply Output Voltage Input Transient Current (CE, SI, SCLK, RESET, SO) : Duration Time t = 1s, VI < 0 VI > VCC Continous Output Current (for each output) Junction and Storage Temperature Range Parameter – 0.7 – 0.7 Value 7 40 Unit V V – 25 + 25 Int. Limited – 40 150 mA mA A °C IOdc Tj, Tstg THERMAL DATA Symbol R th j-case R th j-amb Parameter Thermal Resistance Junction-Case Thermal Resistance Junction-Ambient Max. Max. Multiwatt15 2 35 SO20L 25 70 PowerSO20 Unit 1.5 60 °C/W °C/W 2/11 L9822E PIN DESCRIPTION VCC Logic supply voltage - nominally 5V GROUND Device Ground.This groundapplies for the logic circuits as well as the power output stages. RESET Asynchronousreset for the outputstages,the parallel latch and the shift register inside the L9822ESP. This pin is active low and it must not be left floating. A power on clear function may be implementedconnecting this pin to VCC with an external resistor and to ground with an external capacitor. CE Chip Enable. Data is transferred from the shift registers to the outputs on the rising edge of this signal. The falling edge of this signal sets the shift register with the output voltage sense bits coming from the output stages. The output driver for the SO pin is enabled when this pin is low. SO Serial Output. This pin is the serial output from the shift register and it is tri-stated when CE is high. A high for a data bit on this pin indicates that the particular output is high. A low on this pin for a data bit indicates that the output is low. Comparing the serial output bits with the previous serial input bits the external microcontroller implements the diagnostic data supplied by the L9822. SI Serial Input. This pin is the serial data input. A high on thispin will programa particularoutputto be OFF, while a low will turn it ON. SCLK Serial Clock. This pin clocks the shift register. New SO data will appear on every rising edge of this pin and new SI data will be latched on every SCLK’s falling edge into the shift register. OUTPUTS 00-07 Power output pins. The input and outputbits correspondingto 07 are sent and received first via the SPI bus and 00is the last. The outputsare provided with current limiting and voltage sense functions for fault indication and protection. The nominal load current for these outputs is 500mA, but the current limiting is set to a minimum of 1.05A.The outputsalso have on board clamps set at about 36V for recirculation of inductive load current. ELECTRICAL CHARACTERISTICS (VCC = 5V ± 5%. Tj = – 40 to 125°C ; unless otherwise speciifed) Symbol VOC EOC IOleak R DSon Parameter Output Clamping Volt. Out. Clamping Energy Out. Leakage Current On Resistance Test Conditions IO = 0.5A, Output Programmed OFF IO = 0.5A, When ON VO = 24V, Output Progr. OFF Output Progr. ON IO = 0.5A IO = 0.8A IO = 1A With Fault Reset Disabled Output Progr. ON IO = 500mA No Reactive Load IO = 500mA No Reactive Load Output Progr. OFF Fault detected if VO > VOREF See fig. 3 1.6 75 1.05 10 10 2 250 0.55 0.55 0.55 Min. 30 20 1 1 1 1 Typ. Max. 40 Unit V mJ mA Ω Ω Ω A µs µs V µs IOL tPHL tP VOREF tUD Out. Self Limiting Current Turn-on Delay Turn-off Delay Fault Refer. Voltage Fault Reset Delay (after CE L to H transition) Output OFF Voltage VOFF Output Pin Floating.cOutput Progr. OFF, 1.0 V 3/11 L9822E ELECTRICAL CHARACTERISTICS (Continued) Symbol Parameter Test Conditions Min. Typ. Max. Unit INPUT BUFFER (SI, CE, SCLK and RESET pins) V T– Threshold Voltage at Falling Edge SCLK only Threshold Voltage at Rising Edge SCLK only Hysteresis Voltage Input Current Input Capacitance VCC = 5V ± 10% 0.2VCC 0.6 VCC = 5V ± 10% 0.7VCC 4.15 VT+ – VT– VCC = 5.50V, 0 < VI < VCC 0 < VI < VCC 0.85 – 10 2.5 + 10 20 V V V V V µA nF V T+ VH II CI OUTPUT BUFFER (SO pin) VSOL VSOH ISOtl C SO ICC Output LOW Voltage Output HIGH Voltage Output Tristate Leakage Current Output Capacitance Quiescent Supply Current at VCC Pin IO = 1.6mA IO = 0.8mA 0 < VO < VCC, CE Pin Held High, VCC = 5.25V 0 < VO < VCC CE Pin Held High All Outputs Progr. ON. IO = 0.5A per Output Simultaneously VCC – 1.3V – 20 20 20 10 0.4 V V µA pF mA SERIAL PERIPHERAL INTERFACE (see fig. 2, timing diagram) fop tlead tlag twSCKH twSCKL tsu tH tEN tDIS tV trSO tfSO trSI tfSI tho Operating Frequency Enable Lead Time Enable Lag Time Clock HIGH Time Clock LOW Time Data Setup Time Data Hold Time Enable Time Disable Time Data Valid Time Rise Time (SO output) Fall Time (SO output) Rise Time SPI Inputs (SCK, SI, CE) Fall Time SPI Inputs (SCLK, SI, CE) Output Data Hold Time VCC = 20 to 70% CL = 200pF VCC = 70 to 20% CL = 200pF VCC = 20 to 70% CL = 200pF VCC = 70 to 20% CL = 200pF 200 200 0 D.C. 250 250 200 200 75 75 250 250 100 50 50 2 MHz ns ns ns ns ns ns ns ns ns ns ns ns ns µs 4/11 L9822E FUNCTIONAL DESCRIPTION The L9822ESP DMOS output is a low operating power device featu-ring,eight 1Ω RDSON DMOSdrivers with transient protection circuits in output stages. Each channel is independentlycontrolled by an output latch and a common RESET line which disables all eight outputs. The driver has low saturation and shortcircuit protectionand candrive inductiveandresistive loads such as solenoids, lamps and relais. Datais transmittedtothe deviceseriallyusingtheSerialPeripheral Interface(SPI) protocol. The circuit receives 8 bit serial data by means of the serial input (SI) which is stored in an internal register to control the output drivers. The serial output (SO) provides 8 bit of diagnostic data representing the voltage level at the driver output. This allows the microprocessor to diagnosethe condition of the output drivers. The output saturation voltage is monitored by a comparator for an out of saturation condition and is able to unlatch the particular driver through the fault reset line. This circuit is also cascadable with another octal driver in order to jam 8 bit multiple data. The device is selected when the chip enable (CE) line is low. Additionally the (SO) is placed in a tri-state mode when the device is deselected. The negative edge of the (CE) transfers the voltage level of the drivers to the shift registerand the positive edge of the (CE) latchesthe new datafrom the shift registerto the drivers. When CE is Low, data bit contained into the shift register is transferred to SO output at every SCLK positive transition while data bit present at SI input is latched into the shift register on every SCLK negative transition. Internal Blocks Description The internal architecture of the device is based on the three internal major blocks : the octal shift register for talking to the SPI bus, the octal latch for holding control bits written into the device and the octal load driver array. Shift Register The shift register has both serial and parallel inputs and serial and parallel outputs. The serial input accepts data from the SPI bus and the serial output simultaneously sends data into the SPI bus. The parallel outputs are latched into the parallel latch inside the L9822ESPat the end of adata transfer. The parallel inputs jam diagnostic data into the shift register at the beginning of a data transfer cycle. Parallel Latch The parallel latch holds the input data from the shift register. This data then actuates the output stages. Individual registers in the latch may be cleared by fault conditions in order to protect the overloaded output stages. The entire latch may also be cleared by the RESET signal. Output Stages The output stagesprovide an active low drive signal suitable for 0.75A continuous loads. Each output has a current limit circuit which limits the maximum output current to at least 1.05A to allow for high inrush currents. Additionally,the outputshaveinternal zeners set to 36 volts to clamp inductive transients at turn-off. Each output also has a voltage comparator observing the outputnode. If the voltage exceeds 1.8V on an ON output pin, a fault condition is assumed and the latch driving this particular stage is reset, turning the output OFF to protect it. The timing of this action is described below. These comparators also provide diagnostic feedback data to the shift register. Additionally, the comparatorscontainan internalpulldowncurrentwhich will causethe cell to indicate a low output voltage if the output is programmedOFF and the output pin is open circuited. TIMING DATA TRANSFER Figure #2 shows the overall timing diagram from a byte transfer to and from the L9822ESP using the SPI bus. CE High to Low Transition The action begins when the Chip Enable(CE) pin is pulledlow. The tri-state Serial Output(SO)pin driver will be enabledentire time that CE is low. At the falling edge of the CE pin, the diagnostic data from the voltage comparatorsin the output stages will be latched into the shift register. If a particular output is high, a logic one will be jammed into that bit in the shift register. If the output is low, a logic zero will be loadedthere. The most significant bit (07) shouldbe presented at the Serial Input (SI) pin. A zero at this pin will program an output ON, while a one will program the output OFF. SCLK Transitions The Serial Clock (SCLK) pin should then be pulled high. At thispoint the diagnostic bit from the most significantoutput(07) will appearat the SO pin.A high here indicates that the 07 pin is higher than 1.8V. The SCLK pin shouldthen be toggledlow then high. New SO data will appearfollowingevery rising edge of SCLK and new SI data will be latched into the L9822ESPshift register on the falling edges. An unlimited amount of data may be shifted through the 5/11 L9822E device shift register (into the SI pin and out the SO pin), allowing the other SPI devices to be cascaded in a daisy chain with the L9822ESP. CE Low to High Transition Once the last data bit has been shifted into the L9822ESP,the CE pin should be pulled high. At the rising edge of CE the shift register data is latched intothe parallel latch and the outputstageswill be actuated by the new data. An internal 160µs delay timer will also be started at this rising edge (see tUD). During the 160µs period, the outputs will be protected only by the analog current limiting circuits since the resetting of the parallel latches by faults conditionswill be inhibitedduringthis period.This allows the part to overcome any high inrush currents that may flow immediately after turn on. Once the delay period has elapsed, the output voltages are sensed by the comparators and any output with voltageshigher than 1.8V arelatched OFF. It shouldbe noted that the SCLK pin should be low at both tranFigure 1 : Byte Timing with Asynchronous Reset. sitions of the CE pin to avoid any false clocking of theshift register. TheSCLK input is gatedby the CE pin, so that the SCLK pin is ignored whenever the CE pin is high. FAULT CONDITIONS CHECK Checking for fault conditions may be done in the following way. Clock in a new control byte. Wait 160 microseconds or so to allow the outputs to settle. Clock in thesame controlbyte and observethe diagnostic data that comes out of the device. The diagnostic bits should be identical to the bits that were first clockedin. Any differenceswould point to a fault on that output.If the outputwas programmed ON by clocking in a zero, and a one came back as the diagnosticbit forthat output,the outputpinwasstill high and a short circuit or overload condition exists. If the output was programmed OFF by clocking in a one, and a zero came back as the diagnostic bit for that output, nothing had pulled the output pin high and it 6/11 L9822E Figure 2 : Timing Diagram. Figure 3 : Typical Application Circuit. 7/11 L9822E MULTIWATT15 PACKAGE MECHANICAL DATA DIM. A B C D E F G G1 H1 H2 L L1 L2 L3 L4 L7 M M1 S S1 Dia1 MIN. mm TYP. MAX. 5 2.65 1.6 0.55 0.75 1.52 18.03 20.2 22.5 22.5 18.1 17.75 10.9 2.9 4.85 5.53 2.6 2.6 3.85 MIN. inch TYP. MAX. 0.197 0.104 0.063 0.022 0.030 0.060 0.710 0.795 0.886 0.886 0.713 0.699 0.429 0.114 0.191 0.218 0.102 0.102 0.152 1 0.49 0.66 1.02 17.53 19.6 21.9 21.7 17.65 17.25 10.3 2.65 4.25 4.63 1.9 1.9 3.65 0.019 0.026 0.040 0.690 0.772 0.862 0.854 0.695 0.679 0.406 0.104 0.167 0.182 0.075 0.075 0.144 0.039 1.27 17.78 0.050 0.700 22.2 22.1 17.5 10.7 4.55 5.08 0.874 0.870 0.689 0.421 0.179 0.200 8/11 L9822E PowerSO20 PACKAGE MECHANICAL DATA DIM. MIN. A a1 a2 a3 b c D (1) E e e3 E1 (1) E2 G h L N S T 10.0 0.80 0 10.90 0 0.40 0.23 15.80 13.90 1.27 11.43 11.10 2.90 0.10 1.10 1.10 8° (max.) 0.3937 0.0314 10° (max.) 0 0.4291 0.10 mm TYP. MAX. 3.60 0.30 3.30 0.10 0.53 0.32 16.00 14.50 0 0.0157 0.009 0.6220 0.5472 0.050 0.450 0.437 0.1141 0.0039 0.0433 0.0433 0.0039 MIN. inch TYP. MAX. 0.1417 0.0118 0.1299 0.0039 0.0209 0.0126 0.6299 0.570 (1) ”D and F” do not include mold flash or protrusions - Mold flash or protrusions shall not exceed 0.15mm (0.006”) N N a2 b e e3 A R c DETAIL B a1 E DETAIL A D lead 20 11 DETAIL A a3 DETAIL B E2 T E1 Gage Plan e 0.35 slug -C- S L SEA TING PLANE G C 1 10 (COPLANARITY) h x 45 ° PSO20MEC 9/11 L9822E SO20 PACKAGE MECHANICAL DATA DIM. MIN A a1 a2 b b1 C c1 D E e e3 F G L M S 8.8 0.5 10 1.27 11.43 1 7.4 9.15 1.27 0.75 8° (max.) 0.346 0.020 1 12.6 10.65 0.394 0.050 0.450 0.039 0.291 0.360 0.050 0.030 0.35 0.23 0.5 45° (typ.) 0.039 0.496 0.419 0.1 mm TYP MAX 2.65 0.2 2.45 0.49 0.32 0.014 0.009 0.020 0.004 MIN inch TYP MAX 0.104 0.008 0.096 0.019 0.013 10/11 L9822E Information furnished is believed to be accurate and reliable. However, SGS-THOMSON Microelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of SGS-THOMSON Microelectronics. Specification mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. SGS-THOMSON Microelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of SGS-THOMSON Microelectronics. © 1996 SGS-THOMSON Microelectronics – Printed in Italy – All Rights Reserved MULTIWATT® is a Registered Trademark of SGS-THOMSON Microelectronics PowerSO-20™ is a Trademark of SGS-THOMSON Microelectronics SGS-THOMSON Microelectronics GROUP OF COMPANIES Australia - Brazil - Canada - China - France - Germany - Hong Kong - Italy - Japan - Korea - Malaysia - Malta - Morocco The Netherlands - Singapore - Spain - Sweden - Switzerland - Taiwan - Thailand - United Kingdom - U.S.A. 11/11