L9822N_03

® L9822N OCTAL SERIAL SOLENOID DRIVER . . . . . . . . . EIGHT LOW RDSon DMOS OUTPUTS (0.5Ω AT IO = 1A @ 25°C VCC = 5V± 5%) 8 BIT SERIAL INPUT DATA (SPI) 8 BIT SERIAL DIAGNOSTIC OUTPUT FOR OVERLOAD AND OPEN CIRCUIT CONDITIONS OUTPUT SHORT CIRCUIT PROTECTION CHIP ENABLE SELECT FUNCTION (active low) INTERNAL 35V CLAMPING FOR EACH OUTPUT CASCADABLE WITH ANOTHER OCTAL DRIVER LOW QUIESCENT CURRENT (10mA MAX.) PACKAGE Power SO20 MULTIPOWER BCD TECHNOLOGY PowerSO20 ORDERING NUMBER: L9822N DESCRIPTION The L9822N is an octal low side solenoid driver rea lized in Multipower-BCD technology particularly suited for driving lamps, relays and solenoids in BLOCK DIAGRAM automotive environment. The DMOS outpts L9822N has a very low power consumption. Data is transmitted serially to the device using the Serial Peripheral Interface (SPI) protocol. The L9822N features the outputs status monitoring function. October 2003 1/9 L9822N PIN CONNECTIONS (top view) GND SO VCC RESET OUT7 OUT6 OUT5 OUT4 N.C. GND 1 2 3 4 5 6 7 8 9 10 D94AT119A 20 19 18 17 16 15 14 13 12 11 GND SI SCLK CE OUT0 OUT1 OUT2 OUT3 N.C. GND ABSOLUTE MAXIMUM RATINGS Symbol VCC VO II Parameter DC Logic Supply Output Voltage Input Transient Current (CE, SI, SCLK, RESET, SO) : Duration Time t = 1s, VI < 0 VI > VCC Junction and Storage Temperature Range – 0.7 – 0.7 Value 7 40 Unit V V – 25 + 25 – 40 150 mA mA °C Tj, Tstg THERMAL DATA Symbol Rth j-case Rth j-amb Parameter Thermal Resistance Junction-Case Thermal Resistance Junction-Ambient Max. Max. Value 1.5 60 Unit °C/W °C/W 2/9 L9822N PIN DESCRIPTION VCC Logic supply voltage - nominally 5V GROUND Device Ground. This ground applies for the logic circuits as well as the power output stages. RESET Asynchronous reset for the output stages, the parallel latch and the shift register inside the L9822NSP. This pin is active low and it must not be left floating. A power on clear function may be implemented connecting this pin to VCC with an external resistor and to ground with an external capacitor. CE Chip Enable. Data is transferred from the shift registers to the outputs on the rising edge of this signal. The falling edge of this signal sets the shift register with the output voltage sense bits coming from the output stages. The output driver for the SO pin is enabled when this pin is low. SO Serial Output. This pin is the serial output from the shift register and it is tri-stated when CE is high. A high for a data bit on this pin indicates that the particular output is high. A low on this pin for a data bit indicates that the output is low. Comparing the serial output bits with the previous serial input bits the external microcontroller implements the diagnostic data supplied by the L9822. SI Serial Input. This pin is the serial data input. A high on this pin will program a particular output to be OFF, while a low will turn it ON. SCLK Serial Clock. This pin clocks the shift register. New SO data will appear on every rising edge of this pin and new SI data will be latched on every SCLK’s falling edge into the shift register. OUTPUTS 00-07 Power output pins. The input and output bits corresponding to 07 are sent and received first via the SPI bus and 00 is the last. The outputs are provided with current limiting and voltage sense functions for fault indication and protection. The nominal load current for these outputs is 500mA. The outputs also have on board clamps set at about 36V for recirculation of inductive load current. ELECTRICAL CHARACTERISTICS (VCC = 5V ± 5%. Tj = – 40 to 125°C ; unless otherwise speciifed) Symbol VOC EOC IOFF RDSon Parameter Output Clamping Volt. Out. Clamping Energy Out. Leakage Current On Resistance Test Conditions IO = 0.5A, Output Programmed OFF IO = 0.5A, When ON VO = 24V, Output Progr. OFF Output Progr. ON IO = 0.5A IO = 0.75A IO = 1A With Fault Reset Disabled IO = 500mA No Reactive Load IO = 500mA No Reactive Load Output Progr. OFF Fault detected if VO > VOREF See fig. 3 1.6 75 Min. 30 20 Typ. 35 Max. 40 1 0.53 0.53 0.53 1 1 1 10 10 2 250 Unit V mJ mA Ω Ω Ω µs µs V µs tPHL tP VOREF tUD Turn-on Delay Turn-off Delay Fault Refer. Voltage Fault Reset Delay (after CE L to H transition) Output OFF Voltage VOFF Output Pin Floating.cOutput Progr. OFF, 1.0 V 3/9 L9822N ELECTRICAL CHARACTERISTICS (Continued) Symbol Parameter Test Conditions Min. Typ. Max. Unit INPUT BUFFER (SI, CE, SCLK and RESET pins) VT– VT+ VH II CI Threshold Voltage at Falling Edge Threshold Voltage at Rising Edge Hysteresis Voltage Input Current Input Capacitance VT+ – VT– VCC = 5.25V, 0 < VI < VCC 0 < VI < VCC 1.45 – 10 + 10 20 0.2VCC 0.7VCC V V V µA pF OUTPUT BUFFER (SO pin) VSOL VSOH ISOtl CSO ICC Output LOW Voltage Output HIGH Voltage Output Tristate Leakage Current Output Capacitance Quiescent Supply Current at VCC Pin IO = 1.6mA IO = 0.8mA 0 < VO < VCC, CE Pin Held High, VCC = 5.25V 0 < VO < VCC CE Pin Held High All Outputs Progr. ON. IO = 0.5A per Output Simultaneously 0.4 VCC – 1.3V – 10 10 20 10 V V µA pF mA SERIAL PERIPHERAL INTERFACE (see fig. 2, timing diagram) fop tlead tlag twSCKH twSCKL tsu tH tEN tDIS tV trSO tfSO trSI tfSI tho Operating Frequency Enable Lead Time Enable Lag Time Clock HIGH Time Clock LOW Time Data Setup Time Data Hold Time Enable Time Disable Time Data Valid Time Rise Time (SO output) Fall Time (SO output) Rise Time SPI Inputs (SCK, SI, CE) Fall Time SPI Inputs (SCLK, SI, CE) Output Data Hold Time VCC = 20 to 70% CL = 200pF VCC = 70 to 20% CL = 200pF VCC = 20 to 70% CL = 200pF VCC = 70 to 20% CL = 200pF 0 D.C. 250 250 200 200 75 75 250 250 100 50 50 200 200 2 MHz ns ns ns ns ns ns ns ns ns ns ns ns ns ns 4/9 L9822N FUNCTIONAL DESCRIPTION The L9822N DMOS output is a low operating power device featu-ring, eight 1Ω RDSON DMOS drivers with transient protection circuits in output stages. Each channel is independently controlled by an output latch and a common RESET line which disables all eight outputs. The driver has low saturation and short circuit protection and can drive inductive and resistive loads such as solenoids, lamps and relais. Data is transmitted to the device serially using the Serial Peripheral Interface (SPI) protocol. The circuit receives 8 bit serial data by means of the serial input (SI) which is stored in an internal register to control the output drivers. The serial output (SO) provides 8 bit of diagnostic data representing the voltage level at the driver output. This allows the microprocessor to diagnose the condition of the output drivers. The output saturation voltage is monitored by a comparator for an out of saturation condition and is able to unlatch the particular driver through the fault reset line. This circuit is also cascadable with another octal driver in order to jam 8 bit multiple data. The device is selected when the chip enable (CE) line is low. Additionally the (SO) is placed in a tri-state mode when the device is deselected. The negative edge of the (CE) transfers the voltage level of the drivers to the shift register and the positive edge of the (CE) latches the new data from the shift register to the drivers. When CE is Low, data bit contained into the shift register is transferred to SO output at every SCLK positive transition while data bit present at SI input is latched into the shift register on every SCLK negative transition. Internal Blocks Description The internal architecture of the device is based on the three internal major blocks : the octal shift register for talking to the SPI bus, the octal latch for holding control bits written into the device and the octal load driver array. Shift Register The shift register has both serial and parallel inputs and serial and parallel outputs. The serial input accepts data from the SPI bus and the serial output simultaneously sends data into the SPI bus. The parallel outputs are latched into the parallel latch inside the L9822N at the end of a data transfer. The parallel inputs jam diagnostic data into the shift register at the beginning of a data transfer cycle. Parallel Latch The parallel latch holds the input data from the shift register. This data then actuates the output stages. Individual registers in the latch may be cleared by fault conditions in order to protect the overloaded output stages. The entire latch may also be cleared by the RESET signal. Output Stages The output stages provide an active low drive signal suitable for 0.75A continuous loads. The outputs have internal zeners set to 36 volts to clamp inductive transients at turn-off. Each output also has a voltage comparator observing the output node. If the voltage exceeds 1.8V on an ON output pin, a fault condition is assumed and the latch driving this particular stage is reset, turning the output OFF to protect it. The timing of this action is described below. These comparators also provide diagnostic feedback data to the shift register. Additionally, the comparators contain an internal pulldown current which will cause the cell to indicate a low output voltage if the output is programmed OFF and the output pin is open circuited. TIMING DATA TRANSFER Figure #2 shows the overall timing diagram from a byte transfer to and from the L9822NSP using the SPI bus. CE High to Low Transition The action begins when the Chip Enable (CE) pin is pulled low. The tri-state Serial Output (SO) pin driver will be enabled entire time that CE is low. At the falling edge of the CE pin, the diagnostic data from the voltage comparators in the output stages will be latched into the shift register. If a particular output is high, a logic one will be jammed into that bit in the shift register. If the output is low, a logic zero will be loaded there. The most significant bit (07) should be presented at the Serial Input (SI) pin. A zero at this pin will program an output ON, while a one will program the output OFF. SCLK Transitions The Serial Clock (SCLK) pin should then be pulled high. At this point the diagnostic bit from the most significant output (07) will appear at the SO pin. A high here indicates that the 07 pin is higher than 1.8V. The SCLK pin should then be toggled low then high. New SO data will appear following every rising edge of SCLK and new SI data will be latched into the L9822N shift register on the falling edges. An unlimited amount of data may be shifted through the device shift register (into the SI pin and out the SO pin), allowing the other SPI devices to be cascaded in a daisy chain with the L9822N. 5/9 L9822N CE Low to High Transition Once the last data bit has been shifted into the L9822NSP, the CE pin should be pulled high. At the rising edge of CE the shift register data is latched into the parallel latch and the output stages will be actuated by the new data. An internal 160µs delay timer will also be started at this rising edge (see tUD). During the 160µs period, the outputs will be protected only by the analog current limiting circuits since the resetting of the parallel latches by faults conditions will be inhibited during this period. This allows the part to overcome any high inrush currents that may flow immediately after turn on. Once the delay period has elapsed, the output voltages are sensed by the comparators and any output with voltages higher than 1.8V are latched OFF. It should be noted that the SCLK pin should be low at both transitions of the CE pin to avoid any false clocking of the shift register. The SCLK input is gated by the CE pin, so that the SCLK pin is ignored whenever the CE pin is high. FAULT CONDITIONS CHECK Checking for fault conditions may be done in the following way. Clock in a new control byte. Wait 160 microseconds or so to allow the outputs to settle. Clock in the same control byte and observe the diagnostic data that comes out of the device. The diagnostic bits should be identical to the bits that were first clocked in. Any differences would point to a fault on that output. If the output was programmed ON by clocking in a zero, and a one came back as the diagnostic bit for that output, the output pin was still high and a short circuit or overload condition exists. If the output was programmed OFF by clocking in a one, and a zero came back as the diagnostic bit for that output, nothing had pulled the output pin high and it must be floating, so an open circuit condition exists for that output. Figure 1 : Byte Timing with Asynchronous Reset. 6/9 L9822N Figure 2 : Timing Diagram. Figure 3 : Typical Application Circuit. N 7/9 L9822N mm DIM. MIN. A A1 B C D (1) E e H h L k ddd 10.0 0.25 0.40 2.35 0.10 0.33 0.23 12.60 7.40 1.27 10.65 0.75 1.27 0.394 0.010 0.016 TYP. MAX. 2.65 0.30 0.51 0.32 13.00 7.60 MIN. 0.093 0.004 0.013 0.009 0.496 0.291 0.050 0.419 0.030 0.050 TYP. MAX. 0.104 0.012 0.200 0.013 0.512 0.299 inch OUTLINE AND MECHANICAL DATA 0˚ (min.), 8˚ (max.) 0.10 0.004 (1) “D” dimension does not include mold flash, protusions or gate burrs. Mold flash, protusions or gate burrs shall not exceed 0.15mm per side. SO20 0016022 D 8/9 L 9822N Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is a registered trademark of STMicroelectronics. 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